Define some predicates that are used for node matching. More...

Namespaces
namespace	EHABI

namespace	WinEH

Classes
struct	ArchNames

struct	CpuNames

struct	ExtName

struct	FPUName

struct	ParsedBranchProtection

Enumerations
enum	ArchExtKind : uint64_t { AEK_INVALID = 0 , AEK_NONE = 1 , AEK_CRC = 1 << 1 , AEK_CRYPTO = 1 << 2 , AEK_FP = 1 << 3 , AEK_HWDIVTHUMB = 1 << 4 , AEK_HWDIVARM = 1 << 5 , AEK_MP = 1 << 6 , AEK_SIMD = 1 << 7 , AEK_SEC = 1 << 8 , AEK_VIRT = 1 << 9 , AEK_DSP = 1 << 10 , AEK_FP16 = 1 << 11 , AEK_RAS = 1 << 12 , AEK_DOTPROD = 1 << 13 , AEK_SHA2 = 1 << 14 , AEK_AES = 1 << 15 , AEK_FP16FML = 1 << 16 , AEK_SB = 1 << 17 , AEK_FP_DP = 1 << 18 , AEK_LOB = 1 << 19 , AEK_BF16 = 1 << 20 , AEK_I8MM = 1 << 21 , AEK_CDECP0 = 1 << 22 , AEK_CDECP1 = 1 << 23 , AEK_CDECP2 = 1 << 24 , AEK_CDECP3 = 1 << 25 , AEK_CDECP4 = 1 << 26 , AEK_CDECP5 = 1 << 27 , AEK_CDECP6 = 1 << 28 , AEK_CDECP7 = 1 << 29 , AEK_PACBTI = 1 << 30 , AEK_OS = 1ULL << 59 , AEK_IWMMXT = 1ULL << 60 , AEK_IWMMXT2 = 1ULL << 61 , AEK_MAVERICK = 1ULL << 62 , AEK_XSCALE = 1ULL << 63 }

enum class	ArchKind { ARM_ARCH }

enum	FPUKind { FK_LAST }

enum class	FPUVersion { NONE , VFPV2 , VFPV3 , VFPV3_FP16 , VFPV4 , VFPV5 , VFPV5_FULLFP16 }

enum class	FPURestriction { None = 0 , D16 , SP_D16 }

enum class	NeonSupportLevel { None = 0 , Neon , Crypto }

enum class	ProfileKind { INVALID = 0 , A , R , M }

enum class	ISAKind { INVALID = 0 , ARM , THUMB , AARCH64 }

enum class	EndianKind { INVALID = 0 , LITTLE , BIG }

enum	DW_ISA { DW_ISA_ARM_thumb = 1 , DW_ISA_ARM_arm = 2 }

enum	Rounding { RN = 0 , RP = 1 , RM = 2 , RZ = 3 , rmMask = 3 }
	Possible values of current rounding mode, which is specified in bits 23:22 of FPSCR. More...

enum	PartialMappingIdx { PMI_GPR , PMI_SPR , PMI_DPR , PMI_Min = PMI_GPR }

enum	ValueMappingIdx { InvalidIdx = 0 , GPR3OpsIdx = 1 , SPR3OpsIdx = 4 , DPR3OpsIdx = 7 }

enum	Fixups { fixup_arm_ldst_pcrel_12 = FirstTargetFixupKind , fixup_t2_ldst_pcrel_12 , fixup_arm_pcrel_10_unscaled , fixup_arm_pcrel_10 , fixup_t2_pcrel_10 , fixup_arm_pcrel_9 , fixup_t2_pcrel_9 , fixup_arm_ldst_abs_12 , fixup_thumb_adr_pcrel_10 , fixup_arm_adr_pcrel_12 , fixup_t2_adr_pcrel_12 , fixup_arm_condbranch , fixup_arm_uncondbranch , fixup_t2_condbranch , fixup_t2_uncondbranch , fixup_arm_thumb_br , fixup_arm_uncondbl , fixup_arm_condbl , fixup_arm_blx , fixup_arm_thumb_bl , fixup_arm_thumb_blx , fixup_arm_thumb_cb , fixup_arm_thumb_cp , fixup_arm_thumb_bcc , fixup_arm_movt_hi16 , fixup_arm_movw_lo16 , fixup_t2_movt_hi16 , fixup_t2_movw_lo16 , fixup_arm_thumb_upper_8_15 , fixup_arm_thumb_upper_0_7 , fixup_arm_thumb_lower_8_15 , fixup_arm_thumb_lower_0_7 , fixup_arm_mod_imm , fixup_t2_so_imm , fixup_bf_branch , fixup_bf_target , fixup_bfl_target , fixup_bfc_target , fixup_bfcsel_else_target , fixup_wls , fixup_le , LastTargetFixupKind , NumTargetFixupKinds = LastTargetFixupKind - FirstTargetFixupKind }

enum	OperandType { OPERAND_VPRED_R = MCOI::OPERAND_FIRST_TARGET , OPERAND_VPRED_N }

enum class	PredBlockMask { T = 0b1000 , TT = 0b0100 , TE = 0b1100 , TTT = 0b0010 , TTE = 0b0110 , TEE = 0b1110 , TET = 0b1010 , TTTT = 0b0001 , TTTE = 0b0011 , TTEE = 0b0111 , TTET = 0b0101 , TEEE = 0b1111 , TEET = 0b1101 , TETT = 0b1001 , TETE = 0b1011 }
	Mask values for IT and VPT Blocks, to be used by MCOperands. More...

Functions
bool	isDoublePrecision (const FPURestriction restriction)

bool	has32Regs (const FPURestriction restriction)

ArchKind &	operator-- (ArchKind &Kind)

StringRef	getFPUName (FPUKind FPUKind)

FPUVersion	getFPUVersion (FPUKind FPUKind)

NeonSupportLevel	getFPUNeonSupportLevel (FPUKind FPUKind)

FPURestriction	getFPURestriction (FPUKind FPUKind)

bool	getFPUFeatures (FPUKind FPUKind, std::vector< StringRef > &Features)

bool	getHWDivFeatures (uint64_t HWDivKind, std::vector< StringRef > &Features)

bool	getExtensionFeatures (uint64_t Extensions, std::vector< StringRef > &Features)

StringRef	getArchName (ArchKind AK)

unsigned	getArchAttr (ArchKind AK)

StringRef	getCPUAttr (ArchKind AK)

StringRef	getSubArch (ArchKind AK)

StringRef	getArchExtName (uint64_t ArchExtKind)

StringRef	getArchExtFeature (StringRef ArchExt)

bool	appendArchExtFeatures (StringRef CPU, ARM::ArchKind AK, StringRef ArchExt, std::vector< StringRef > &Features, FPUKind &ArgFPUKind)

ArchKind	convertV9toV8 (ArchKind AK)

FPUKind	getDefaultFPU (StringRef CPU, ArchKind AK)

uint64_t	getDefaultExtensions (StringRef CPU, ArchKind AK)

StringRef	getDefaultCPU (StringRef Arch)

StringRef	getCanonicalArchName (StringRef Arch)
	MArch is expected to be of the form (arm\|thumb)?(eb)?(v.

StringRef	getFPUSynonym (StringRef FPU)

uint64_t	parseHWDiv (StringRef HWDiv)

FPUKind	parseFPU (StringRef FPU)

ArchKind	parseArch (StringRef Arch)

uint64_t	parseArchExt (StringRef ArchExt)

ArchKind	parseCPUArch (StringRef CPU)

ProfileKind	parseArchProfile (StringRef Arch)

unsigned	parseArchVersion (StringRef Arch)

void	fillValidCPUArchList (SmallVectorImpl< StringRef > &Values)

StringRef	computeDefaultTargetABI (const Triple &TT, StringRef CPU)

StringRef	getARMCPUForArch (const llvm::Triple &Triple, StringRef MArch={})
	Get the (LLVM) name of the minimum ARM CPU for the arch we are targeting.

void	PrintSupportedExtensions (StringMap< StringRef > DescMap)

StringRef	getArchSynonym (StringRef Arch)
	Converts e.g. "armv8" -> "armv8-a".

ISAKind	parseArchISA (StringRef Arch)

EndianKind	parseArchEndian (StringRef Arch)

bool	parseBranchProtection (StringRef Spec, ParsedBranchProtection &PBP, StringRef &Err, bool EnablePAuthLR=false)

bool	isBitFieldInvertedMask (unsigned v)

FastISel *	createFastISel (FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo)

static bool	checkPartMapping (const RegisterBankInfo::PartialMapping &PM, unsigned Start, unsigned Length, unsigned RegBankID)

static void	checkPartialMappings ()

static bool	checkValueMapping (const RegisterBankInfo::ValueMapping &VM, const RegisterBankInfo::PartialMapping *BreakDown)

static void	checkValueMappings ()

bool	isVpred (OperandType op)

bool	isVpred (uint8_t op)

bool	isCDECoproc (size_t Coproc, const MCSubtargetInfo &STI)

Variables
const ExtName	ARCHExtNames []

struct {
StringRef llvm::ARM::Name

uint64_t llvm::ARM::ID

}	HWDivNames []

const CpuNames	CPUNames []

static const FPUName	FPUNames []

static const ArchNames	ARMArchNames []

const unsigned	RoundingBitsPos = 22

const unsigned	FPStatusBits = 0xf800009f

const unsigned	FPReservedBits = 0x00006060

const RegisterBankInfo::PartialMapping	PartMappings []

const RegisterBankInfo::ValueMapping	ValueMappings []

Detailed Description

Define some predicates that are used for node matching.

Enumeration Type Documentation

◆ ArchExtKind

enum llvm::ARM::ArchExtKind : uint64_t

Enumerator
AEK_INVALID
AEK_NONE
AEK_CRC
AEK_CRYPTO
AEK_FP
AEK_HWDIVTHUMB
AEK_HWDIVARM
AEK_MP
AEK_SIMD
AEK_SEC
AEK_VIRT
AEK_DSP
AEK_FP16
AEK_RAS
AEK_DOTPROD
AEK_SHA2
AEK_AES
AEK_FP16FML
AEK_SB
AEK_FP_DP
AEK_LOB
AEK_BF16
AEK_I8MM
AEK_CDECP0
AEK_CDECP1
AEK_CDECP2
AEK_CDECP3
AEK_CDECP4
AEK_CDECP5
AEK_CDECP6
AEK_CDECP7
AEK_PACBTI
AEK_OS
AEK_IWMMXT
AEK_IWMMXT2
AEK_MAVERICK
AEK_XSCALE

Definition at line 31 of file ARMTargetParser.h.

◆ ArchKind

enum class llvm::ARM::ArchKind

strong

Enumerator
ARM_ARCH

Definition at line 97 of file ARMTargetParser.h.

◆ DW_ISA

enum llvm::ARM::DW_ISA

Enumerator
DW_ISA_ARM_thumb
DW_ISA_ARM_arm

Definition at line 25 of file ARMAsmPrinter.h.

◆ EndianKind

enum class llvm::ARM::EndianKind

strong

Enumerator
INVALID
LITTLE
BIG

Definition at line 23 of file ARMTargetParserCommon.h.

◆ Fixups

enum llvm::ARM::Fixups

Enumerator
fixup_arm_ldst_pcrel_12
fixup_t2_ldst_pcrel_12
fixup_arm_pcrel_10_unscaled
fixup_arm_pcrel_10
fixup_t2_pcrel_10
fixup_arm_pcrel_9
fixup_t2_pcrel_9
fixup_arm_ldst_abs_12
fixup_thumb_adr_pcrel_10
fixup_arm_adr_pcrel_12
fixup_t2_adr_pcrel_12
fixup_arm_condbranch
fixup_arm_uncondbranch
fixup_t2_condbranch
fixup_t2_uncondbranch
fixup_arm_thumb_br
fixup_arm_uncondbl
fixup_arm_condbl
fixup_arm_blx
fixup_arm_thumb_bl
fixup_arm_thumb_blx
fixup_arm_thumb_cb
fixup_arm_thumb_cp
fixup_arm_thumb_bcc
fixup_arm_movt_hi16
fixup_arm_movw_lo16
fixup_t2_movt_hi16
fixup_t2_movw_lo16
fixup_arm_thumb_upper_8_15
fixup_arm_thumb_upper_0_7
fixup_arm_thumb_lower_8_15
fixup_arm_thumb_lower_0_7
fixup_arm_mod_imm
fixup_t2_so_imm
fixup_bf_branch
fixup_bf_target
fixup_bfl_target
fixup_bfc_target
fixup_bfcsel_else_target
fixup_wls
fixup_le
LastTargetFixupKind
NumTargetFixupKinds

Definition at line 16 of file ARMFixupKinds.h.

◆ FPUKind

enum llvm::ARM::FPUKind

Enumerator
FK_LAST

Definition at line 122 of file ARMTargetParser.h.

◆ FPURestriction

enum class llvm::ARM::FPURestriction

strong

Enumerator
None	No restriction.
D16	Only 16 D registers.
SP_D16	Only single-precision instructions, with 16 D registers.

Definition at line 140 of file ARMTargetParser.h.

◆ FPUVersion

enum class llvm::ARM::FPUVersion

strong

Enumerator
NONE
VFPV2
VFPV3
VFPV3_FP16
VFPV4
VFPV5
VFPV5_FULLFP16

Definition at line 129 of file ARMTargetParser.h.

◆ ISAKind

enum class llvm::ARM::ISAKind

strong

Enumerator
INVALID
ARM
THUMB
AARCH64

Definition at line 21 of file ARMTargetParserCommon.h.

◆ NeonSupportLevel

enum class llvm::ARM::NeonSupportLevel

strong

Enumerator
None	No Neon.
Neon	Neon.
Crypto	Neon with Crypto.

Definition at line 155 of file ARMTargetParser.h.

◆ OperandType

enum llvm::ARM::OperandType

Enumerator
OPERAND_VPRED_R
OPERAND_VPRED_N

Definition at line 113 of file ARMMCTargetDesc.h.

◆ PartialMappingIdx

enum llvm::ARM::PartialMappingIdx

Enumerator
PMI_GPR
PMI_SPR
PMI_DPR
PMI_Min

Definition at line 31 of file ARMRegisterBankInfo.cpp.

◆ PredBlockMask

enum class llvm::ARM::PredBlockMask

strong

Mask values for IT and VPT Blocks, to be used by MCOperands.

Note that this is different from the "real" encoding used by the instructions. In this encoding, the lowest set bit indicates the end of the encoding, and above that, "1" indicates an else, while "0" indicates a then. Tx = x100 Txy = xy10 Txyz = xyz1

Enumerator
T
TT
TE
TTT
TTE
TEE
TET
TTTT
TTTE
TTEE
TTET
TEEE
TEET
TETT
TETE

Definition at line 105 of file ARMBaseInfo.h.

◆ ProfileKind

enum class llvm::ARM::ProfileKind

strong

Enumerator
INVALID
A
R
M

Definition at line 162 of file ARMTargetParser.h.

◆ Rounding

enum llvm::ARM::Rounding

Possible values of current rounding mode, which is specified in bits 23:22 of FPSCR.

Enumerator
RN
RP
RM
RZ
rmMask

Definition at line 367 of file ARMISelLowering.h.

◆ ValueMappingIdx

enum llvm::ARM::ValueMappingIdx

Enumerator
InvalidIdx
GPR3OpsIdx
SPR3OpsIdx
DPR3OpsIdx

Definition at line 68 of file ARMRegisterBankInfo.cpp.

Function Documentation

◆ appendArchExtFeatures()

bool llvm::ARM::appendArchExtFeatures	(	StringRef	CPU,
		ARM::ArchKind	AK,
		StringRef	ArchExt,
		std::vector< StringRef > &	Features,
		ARM::FPUKind &	ArgFPUKind
	)

Definition at line 422 of file ARMTargetParser.cpp.

References AEK_INVALID, ARCHExtNames, findDoublePrecisionFPU(), findSinglePrecisionFPU(), getDefaultFPU(), getFPURestriction(), isDoublePrecision(), parseArchExt(), and stripNegationPrefix().

◆ checkPartialMappings()

static void llvm::ARM::checkPartialMappings ( )

static

Definition at line 55 of file ARMRegisterBankInfo.cpp.

References assert(), checkPartMapping(), PartMappings, PMI_DPR, PMI_GPR, PMI_Min, and PMI_SPR.

Referenced by llvm::ARMRegisterBankInfo::ARMRegisterBankInfo().

◆ checkPartMapping()

static bool llvm::ARM::checkPartMapping	(	const RegisterBankInfo::PartialMapping &	PM,
		unsigned	Start,
		unsigned	Length,
		unsigned	RegBankID
	)

static

Definition at line 48 of file ARMRegisterBankInfo.cpp.

References llvm::RegisterBank::getID(), llvm::RegisterBankInfo::PartialMapping::Length, llvm::Length, llvm::RegisterBankInfo::PartialMapping::RegBank, and llvm::RegisterBankInfo::PartialMapping::StartIdx.

Referenced by checkPartialMappings().

◆ checkValueMapping()

static bool llvm::ARM::checkValueMapping	(	const RegisterBankInfo::ValueMapping &	VM,
		const RegisterBankInfo::PartialMapping *	BreakDown
	)

static

Definition at line 93 of file ARMRegisterBankInfo.cpp.

References llvm::RegisterBankInfo::ValueMapping::BreakDown, and llvm::RegisterBankInfo::ValueMapping::NumBreakDowns.

Referenced by checkValueMappings().

◆ checkValueMappings()

static void llvm::ARM::checkValueMappings ( )

static

Definition at line 98 of file ARMRegisterBankInfo.cpp.

References assert(), checkValueMapping(), DPR3OpsIdx, GPR3OpsIdx, PartMappings, PMI_DPR, PMI_GPR, PMI_Min, PMI_SPR, SPR3OpsIdx, and ValueMappings.

Referenced by llvm::ARMRegisterBankInfo::ARMRegisterBankInfo().

◆ computeDefaultTargetABI()

StringRef llvm::ARM::computeDefaultTargetABI	(	const Triple &	TT,
		StringRef	CPU
	)

Definition at line 539 of file ARMTargetParser.cpp.

References llvm::Triple::Android, llvm::Triple::EABI, llvm::Triple::EABIHF, llvm::StringRef::empty(), getArchName(), llvm::Triple::GNUEABI, llvm::Triple::GNUEABIHF, llvm::Triple::GNUEABIHFT64, llvm::Triple::GNUEABIT64, llvm::Triple::MuslEABI, llvm::Triple::MuslEABIHF, llvm::Triple::OpenHOS, parseArchProfile(), parseCPUArch(), TT, and llvm::Triple::UnknownOS.

Referenced by computeTargetABI().

◆ convertV9toV8()

ARM::ArchKind llvm::ARM::convertV9toV8 ( ARM::ArchKind AK )

Definition at line 481 of file ARMTargetParser.cpp.

References getProfileKind().

◆ createFastISel()

FastISel * llvm::ARM::createFastISel	(	FunctionLoweringInfo &	funcInfo,
		const TargetLibraryInfo *	libInfo
	)

Definition at line 3079 of file ARMFastISel.cpp.

References llvm::MachineFunction::getSubtarget(), llvm::FunctionLoweringInfo::MF, and llvm::ARMSubtarget::useFastISel().

Referenced by llvm::ARMTargetLowering::createFastISel().

◆ fillValidCPUArchList()

void llvm::ARM::fillValidCPUArchList ( SmallVectorImpl< StringRef > & Values )

Definition at line 532 of file ARMTargetParser.cpp.

References CPUNames, and llvm::SmallVectorTemplateBase< T, bool >::push_back().

◆ getArchAttr()

unsigned llvm::ARM::getArchAttr ( ARM::ArchKind AK )

Definition at line 342 of file ARMTargetParser.cpp.

Referenced by llvm::jitlink::createLinkGraphFromELFObject_aarch32().

◆ getArchExtFeature()

StringRef llvm::ARM::getArchExtFeature ( StringRef ArchExt )

Definition at line 358 of file ARMTargetParser.cpp.

References ARCHExtNames, and stripNegationPrefix().

◆ getArchExtName()

StringRef llvm::ARM::getArchExtName ( uint64_t ArchExtKind )

Definition at line 346 of file ARMTargetParser.cpp.

References ARCHExtNames.

◆ getArchName()

StringRef llvm::ARM::getArchName ( ARM::ArchKind AK )

Definition at line 330 of file ARMTargetParser.cpp.

References Name.

Referenced by computeDefaultTargetABI(), and llvm::ARM_MC::ParseARMTriple().

◆ getArchSynonym()

StringRef llvm::ARM::getArchSynonym ( StringRef Arch )

Converts e.g. "armv8" -> "armv8-a".

Definition at line 19 of file ARMTargetParserCommon.cpp.

References llvm::StringSwitch< T, R >::Case(), llvm::StringSwitch< T, R >::Cases(), and llvm::StringSwitch< T, R >::Default().

Referenced by llvm::AArch64::parseArch(), and parseArch().

◆ getARMCPUForArch()

StringRef llvm::ARM::getARMCPUForArch	(	const llvm::Triple &	Triple,
		StringRef	MArch = `{}`
	)

Get the (LLVM) name of the minimum ARM CPU for the arch we are targeting.

Parameters

Arch	the architecture name (e.g., "armv7s"). If it is an empty string then the triple's arch name is used.

Definition at line 579 of file ARMTargetParser.cpp.

References llvm::Triple::DriverKit, llvm::Triple::EABI, llvm::Triple::EABIHF, llvm::StringRef::empty(), llvm::Triple::FreeBSD, llvm::Triple::getArchName(), getCanonicalArchName(), getDefaultCPU(), llvm::Triple::getEnvironment(), llvm::Triple::getOS(), llvm::Triple::GNUEABI, llvm::Triple::GNUEABIHF, llvm::Triple::GNUEABIHFT64, llvm::Triple::Haiku, llvm::Triple::IOS, llvm_unreachable, llvm::Triple::MacOSX, llvm::Triple::MuslEABIHF, llvm::Triple::NaCl, llvm::Triple::NetBSD, llvm::Triple::OpenBSD, parseArchVersion(), llvm::Triple::TvOS, llvm::Triple::WatchOS, llvm::Triple::Win32, and llvm::Triple::XROS.

◆ getCanonicalArchName()

StringRef llvm::ARM::getCanonicalArchName ( StringRef Arch )

MArch is expected to be of the form (arm|thumb)?(eb)?(v.

+)?(eb)?, but (iwmmxt|xscale)(eb)? is also permitted. If the former, return "v.+", if the latter, return unmodified string, minus 'eb'. If invalid, return empty string.

Definition at line 55 of file ARMTargetParserCommon.cpp.

References A, and llvm::StringRef::npos.

Referenced by getARMCPUForArch(), llvm::AArch64::parseArch(), parseArch(), parseArchProfile(), parseArchVersion(), parseARMArch(), and parseSubArch().

◆ getCPUAttr()

StringRef llvm::ARM::getCPUAttr ( ARM::ArchKind AK )

Definition at line 334 of file ARMTargetParser.cpp.

◆ getDefaultCPU()

StringRef llvm::ARM::getDefaultCPU ( StringRef Arch )

Definition at line 492 of file ARMTargetParser.cpp.

References CPUNames, and parseArch().

Referenced by getARMCPUForArch().

◆ getDefaultExtensions()

uint64_t llvm::ARM::getDefaultExtensions	(	StringRef	CPU,
		ARM::ArchKind	AK
	)

Definition at line 282 of file ARMTargetParser.cpp.

References AEK_INVALID, ARMArchNames, and llvm::StringSwitch< T, R >::Default().

◆ getDefaultFPU()

ARM::FPUKind llvm::ARM::getDefaultFPU	(	StringRef	CPU,
		ARM::ArchKind	AK
	)

Definition at line 271 of file ARMTargetParser.cpp.

References ARMArchNames, and llvm::StringSwitch< T, R >::Default().

Referenced by appendArchExtFeatures().

◆ getExtensionFeatures()

bool llvm::ARM::getExtensionFeatures	(	uint64_t	Extensions,
		std::vector< StringRef > &	Features
	)

Definition at line 314 of file ARMTargetParser.cpp.

References AEK_INVALID, ARCHExtNames, Extensions, and getHWDivFeatures().

◆ getFPUFeatures()

bool llvm::ARM::getFPUFeatures	(	ARM::FPUKind	FPUKind,
		std::vector< StringRef > &	Features
	)

Definition at line 156 of file ARMTargetParser.cpp.

References FK_LAST, and Info.

◆ getFPUName()

StringRef llvm::ARM::getFPUName ( ARM::FPUKind FPUKind )

Definition at line 253 of file ARMTargetParser.cpp.

References FK_LAST.

◆ getFPUNeonSupportLevel()

ARM::NeonSupportLevel llvm::ARM::getFPUNeonSupportLevel ( ARM::FPUKind FPUKind )

Definition at line 230 of file ARMTargetParser.cpp.

References FK_LAST.

◆ getFPURestriction()

ARM::FPURestriction llvm::ARM::getFPURestriction ( ARM::FPUKind FPUKind )

Definition at line 265 of file ARMTargetParser.cpp.

References FK_LAST.

Referenced by appendArchExtFeatures().

◆ getFPUSynonym()

StringRef llvm::ARM::getFPUSynonym ( StringRef FPU )

Definition at line 236 of file ARMTargetParser.cpp.

References llvm::StringSwitch< T, R >::Case(), llvm::StringSwitch< T, R >::Cases(), and llvm::StringSwitch< T, R >::Default().

Referenced by parseFPU().

◆ getFPUVersion()

ARM::FPUVersion llvm::ARM::getFPUVersion ( ARM::FPUKind FPUKind )

Definition at line 259 of file ARMTargetParser.cpp.

References FK_LAST.

◆ getHWDivFeatures()

bool llvm::ARM::getHWDivFeatures	(	uint64_t	HWDivKind,
		std::vector< StringRef > &	Features
	)

Definition at line 295 of file ARMTargetParser.cpp.

References AEK_HWDIVARM, AEK_HWDIVTHUMB, and AEK_INVALID.

Referenced by getExtensionFeatures().

◆ getSubArch()

StringRef llvm::ARM::getSubArch ( ARM::ArchKind AK )

Definition at line 338 of file ARMTargetParser.cpp.

References getSubArch().

Referenced by getSubArch().

◆ has32Regs()

bool llvm::ARM::has32Regs ( const FPURestriction restriction )

inline

Definition at line 150 of file ARMTargetParser.h.

References None.

Referenced by findDoublePrecisionFPU(), and findSinglePrecisionFPU().

◆ isBitFieldInvertedMask()

bool llvm::ARM::isBitFieldInvertedMask ( unsigned v )

Definition at line 20888 of file ARMISelLowering.cpp.

References llvm::isShiftedMask_32().

Referenced by PerformORCombineToBFI().

◆ isCDECoproc()

bool llvm::ARM::isCDECoproc	(	size_t	Coproc,
		const MCSubtargetInfo &	STI
	)

Definition at line 628 of file ARMMCTargetDesc.cpp.

References llvm::MCSubtargetInfo::getFeatureBits().

◆ isDoublePrecision()

bool llvm::ARM::isDoublePrecision ( const FPURestriction restriction )

inline

Definition at line 146 of file ARMTargetParser.h.

References SP_D16.

Referenced by appendArchExtFeatures(), findDoublePrecisionFPU(), and findSinglePrecisionFPU().

◆ isVpred() [1/2]

bool llvm::ARM::isVpred ( OperandType op )

inline

Definition at line 117 of file ARMMCTargetDesc.h.

References op, OPERAND_VPRED_N, and OPERAND_VPRED_R.

Referenced by findFirstVectorPredOperandIdx(), llvm::findFirstVPTPredOperandIdx(), and isVpred().

◆ isVpred() [2/2]

bool llvm::ARM::isVpred ( uint8_t op )

inline

Definition at line 120 of file ARMMCTargetDesc.h.

References isVpred(), and op.

◆ operator--()

ArchKind & llvm::ARM::operator-- ( ArchKind & Kind )

inline

Definition at line 210 of file ARMTargetParser.h.

References assert().

◆ parseArch()

ARM::ArchKind llvm::ARM::parseArch ( StringRef Arch )

Definition at line 31 of file ARMTargetParser.cpp.

References A, getArchSynonym(), and getCanonicalArchName().

Referenced by llvm::jitlink::createLinkGraphFromELFObject_aarch32(), getARMSubType(), llvm::ARM_MC::ParseARMTriple(), and parseSubArch().

◆ parseArchEndian()

ARM::EndianKind llvm::ARM::parseArchEndian ( StringRef Arch )

Definition at line 119 of file ARMTargetParserCommon.cpp.

References llvm::StringRef::ends_with(), and llvm::StringRef::starts_with().

Referenced by parseARMArch().

◆ parseArchExt()

uint64_t llvm::ARM::parseArchExt ( StringRef ArchExt )

Definition at line 516 of file ARMTargetParser.cpp.

References A, AEK_INVALID, and ARCHExtNames.

Referenced by appendArchExtFeatures().

◆ parseArchISA()

ARM::ISAKind llvm::ARM::parseArchISA ( StringRef Arch )

Definition at line 110 of file ARMTargetParserCommon.cpp.

References llvm::StringSwitch< T, R >::Default(), and llvm::StringSwitch< T, R >::StartsWith().

Referenced by parseARMArch().

◆ parseArchProfile()

ARM::ProfileKind llvm::ARM::parseArchProfile ( StringRef Arch )

Definition at line 151 of file ARMTargetParser.cpp.

References getCanonicalArchName(), getProfileKind(), and parseArch().

Referenced by computeDefaultTargetABI(), and parseARMArch().

◆ parseArchVersion()

unsigned llvm::ARM::parseArchVersion ( StringRef Arch )

Definition at line 42 of file ARMTargetParser.cpp.

References getCanonicalArchName(), llvm_unreachable, and parseArch().

Referenced by getARMCPUForArch(), and parseARMArch().

◆ parseBranchProtection()

bool llvm::ARM::parseBranchProtection	(	StringRef	Spec,
		ParsedBranchProtection &	PBP,
		StringRef &	Err,
		bool	EnablePAuthLR = `false`
	)

Definition at line 142 of file ARMTargetParserCommon.cpp.

References llvm::ARM::ParsedBranchProtection::BranchProtectionPAuthLR, llvm::ARM::ParsedBranchProtection::BranchTargetEnforcement, llvm::ARM::ParsedBranchProtection::GuardedControlStack, I, llvm::ARM::ParsedBranchProtection::Key, llvm::ARM::ParsedBranchProtection::Scope, and llvm::SmallVectorBase< Size_T >::size().

◆ parseCPUArch()

ARM::ArchKind llvm::ARM::parseCPUArch ( StringRef CPU )

Definition at line 524 of file ARMTargetParser.cpp.

References llvm::CallingConv::C, and CPUNames.

Referenced by computeDefaultTargetABI().

◆ parseFPU()

ARM::FPUKind llvm::ARM::parseFPU ( StringRef FPU )

Definition at line 221 of file ARMTargetParser.cpp.

References F, and getFPUSynonym().

◆ parseHWDiv()

uint64_t llvm::ARM::parseHWDiv ( StringRef HWDiv )

Definition at line 507 of file ARMTargetParser.cpp.

References AEK_INVALID, D, getHWDivSynonym(), and HWDivNames.

◆ PrintSupportedExtensions()

void llvm::ARM::PrintSupportedExtensions ( StringMap< StringRef > DescMap )

Definition at line 653 of file ARMTargetParser.cpp.

References ARCHExtNames, llvm::StringMapImpl::empty(), llvm::format(), llvm::left_justify(), and llvm::outs().

Variable Documentation

◆ ARCHExtNames

const ExtName llvm::ARM::ARCHExtNames[]

Initial value:

= {
#define ARM_ARCH_EXT_NAME(NAME, ID, FEATURE, NEGFEATURE)                       
                                  
}

Definition at line 80 of file ARMTargetParser.h.

Referenced by appendArchExtFeatures(), getArchExtFeature(), getArchExtName(), getExtensionFeatures(), parseArchExt(), and PrintSupportedExtensions().

◆ ARMArchNames

const ArchNames llvm::ARM::ARMArchNames[]

static

Initial value:

= {
#define ARM_ARCH(NAME, ID, CPU_ATTR, ARCH_FEATURE, ARCH_ATTR, ARCH_FPU,        ARCH_BASE_EXT)                                                
                                                                               
}

Definition at line 202 of file ARMTargetParser.h.

Referenced by getDefaultExtensions(), and getDefaultFPU().

◆ CPUNames

const CpuNames llvm::ARM::CPUNames[]

Initial value:

= {
#define ARM_CPU_NAME(NAME, ID, DEFAULT_FPU, IS_DEFAULT, DEFAULT_EXT)           
                                                     
}

Definition at line 115 of file ARMTargetParser.h.

Referenced by fillValidCPUArchList(), getDefaultCPU(), and parseCPUArch().

◆ FPReservedBits

const unsigned llvm::ARM::FPReservedBits = 0x00006060

Definition at line 384 of file ARMISelLowering.h.

Referenced by llvm::ARMLegalizerInfo::legalizeCustom().

◆ FPStatusBits

const unsigned llvm::ARM::FPStatusBits = 0xf800009f

Definition at line 380 of file ARMISelLowering.h.

Referenced by llvm::ARMLegalizerInfo::legalizeCustom().

◆ FPUNames

const FPUName llvm::ARM::FPUNames[]

static

Initial value:

= {
#define ARM_FPU(NAME, KIND, VERSION, NEON_SUPPORT, RESTRICTION)                
                                                   
 
}

Definition at line 176 of file ARMTargetParser.h.

Referenced by findDoublePrecisionFPU(), and findSinglePrecisionFPU().

◆

const struct { ... } llvm::ARM::HWDivNames[]

Initial value:

= {
#define ARM_HW_DIV_NAME(NAME, ID)            
}

Referenced by parseHWDiv().

◆ ID

uint64_t llvm::ARM::ID

Definition at line 90 of file ARMTargetParser.h.

◆ Name

StringRef llvm::ARM::Name

Definition at line 89 of file ARMTargetParser.h.

◆ PartMappings

const RegisterBankInfo::PartialMapping llvm::ARM::PartMappings[]

Initial value:

{
    
    {0, 32, GPRRegBank},
    
    {0, 32, FPRRegBank},
    
    {0, 64, FPRRegBank},
}

Definition at line 38 of file ARMRegisterBankInfo.cpp.

Referenced by checkPartialMappings(), and checkValueMappings().

◆ RoundingBitsPos

const unsigned llvm::ARM::RoundingBitsPos = 22

Definition at line 376 of file ARMISelLowering.h.

◆ ValueMappings

const RegisterBankInfo::ValueMapping llvm::ARM::ValueMappings[]

Initial value:

= {
    
    {nullptr, 0},
    
    {&PartMappings[PMI_GPR - PMI_Min], 1},
    {&PartMappings[PMI_GPR - PMI_Min], 1},
    {&PartMappings[PMI_GPR - PMI_Min], 1},
    
    {&PartMappings[PMI_SPR - PMI_Min], 1},
    {&PartMappings[PMI_SPR - PMI_Min], 1},
    {&PartMappings[PMI_SPR - PMI_Min], 1},
    
    {&PartMappings[PMI_DPR - PMI_Min], 1},
    {&PartMappings[PMI_DPR - PMI_Min], 1},
    {&PartMappings[PMI_DPR - PMI_Min], 1}}

Definition at line 75 of file ARMRegisterBankInfo.cpp.

Referenced by checkValueMappings(), and llvm::ARMRegisterBankInfo::getInstrMapping().

Namespaces

Classes

Enumerations

Functions

Variables

Detailed Description

Enumeration Type Documentation

◆ ArchExtKind

◆ ArchKind

◆ DW_ISA

◆ EndianKind

◆ Fixups

◆ FPUKind

◆ FPURestriction

◆ FPUVersion

◆ ISAKind

◆ NeonSupportLevel

◆ OperandType

◆ PartialMappingIdx

◆ PredBlockMask

◆ ProfileKind

◆ Rounding

◆ ValueMappingIdx

Function Documentation

◆ appendArchExtFeatures()

◆ checkPartialMappings()

◆ checkPartMapping()

◆ checkValueMapping()

◆ checkValueMappings()

◆ computeDefaultTargetABI()

◆ convertV9toV8()

◆ createFastISel()

◆ fillValidCPUArchList()

◆ getArchAttr()

◆ getArchExtFeature()

◆ getArchExtName()

◆ getArchName()

◆ getArchSynonym()

◆ getARMCPUForArch()

◆ getCanonicalArchName()

◆ getCPUAttr()

◆ getDefaultCPU()

◆ getDefaultExtensions()

◆ getDefaultFPU()

◆ getExtensionFeatures()

◆ getFPUFeatures()

◆ getFPUName()

◆ getFPUNeonSupportLevel()

◆ getFPURestriction()

◆ getFPUSynonym()

◆ getFPUVersion()

◆ getHWDivFeatures()

◆ getSubArch()

◆ has32Regs()

◆ isBitFieldInvertedMask()

◆ isCDECoproc()

◆ isDoublePrecision()

◆ isVpred() [1/2]

◆ isVpred() [2/2]

◆ operator--()

◆ parseArch()

◆ parseArchEndian()

◆ parseArchExt()

◆ parseArchISA()

◆ parseArchProfile()

◆ parseArchVersion()

◆ parseBranchProtection()

◆ parseCPUArch()

◆ parseFPU()

◆ parseHWDiv()

◆ PrintSupportedExtensions()

Variable Documentation

◆ ARCHExtNames

◆ ARMArchNames

◆ CPUNames

◆ FPReservedBits

◆ FPStatusBits

◆ FPUNames

◆

◆ ID