50#define DEBUG_TYPE "asm-printer"
53 std::unique_ptr<MCStreamer> Streamer)
55 MCP(nullptr), InConstantPool(
false), OptimizationGoals(-1) {}
66 InConstantPool =
false;
73 if (AFI->isThumbFunction()) {
81 if (AFI->isCmseNSEntryFunction()) {
93 assert(
Size &&
"C++ constructor pointer had zero size!");
96 assert(GV &&
"C++ constructor pointer was not a GlobalValue!");
106 if (PromotedGlobals.count(GV))
117 MCP =
MF.getConstantPool();
127 PromotedGlobals.insert_range(AFI->getGlobalsPromotedToConstantPool());
130 unsigned OptimizationGoal;
133 OptimizationGoal = 6;
134 else if (
F.hasMinSize())
136 OptimizationGoal = 4;
137 else if (
F.hasOptSize())
139 OptimizationGoal = 3;
142 OptimizationGoal = 2;
145 OptimizationGoal = 1;
148 OptimizationGoal = 5;
151 if (OptimizationGoals == -1)
152 OptimizationGoals = OptimizationGoal;
153 else if (OptimizationGoals != (
int)OptimizationGoal)
154 OptimizationGoals = 0;
156 if (Subtarget->isTargetCOFF()) {
157 bool Local =
F.hasLocalLinkage();
177 if (! ThumbIndirectPads.empty()) {
182 for (std::pair<unsigned, MCSymbol *> &TIP : ThumbIndirectPads) {
190 ThumbIndirectPads.clear();
228 if(ARM::GPRPairRegClass.
contains(Reg)) {
231 Reg =
TRI->getSubReg(Reg, ARM::gsub_0);
262 if (Subtarget->genExecuteOnly())
281GetARMJTIPICJumpTableLabel(
unsigned uid)
const {
292 if (ExtraCode && ExtraCode[0]) {
293 if (ExtraCode[1] != 0)
return true;
295 switch (ExtraCode[0]) {
304 if (
MI->getOperand(OpNum).isReg()) {
305 MCRegister Reg =
MI->getOperand(OpNum).getReg().asMCReg();
312 bool Lane0 =
TRI->getSubReg(SR, ARM::ssub_0) == Reg;
319 if (!
MI->getOperand(OpNum).isImm())
321 O << ~(
MI->getOperand(OpNum).
getImm());
324 if (!
MI->getOperand(OpNum).isImm())
326 O << (
MI->getOperand(OpNum).
getImm() & 0xffff);
329 if (!
MI->getOperand(OpNum).isReg())
337 if (ARM::GPRPairRegClass.
contains(RegBegin)) {
339 Register Reg0 =
TRI->getSubReg(RegBegin, ARM::gsub_0);
341 RegBegin =
TRI->getSubReg(RegBegin, ARM::gsub_1);
349 unsigned RegOps = OpNum + 1;
350 while (
MI->getOperand(RegOps).isReg()) {
365 if (!FlagsOP.
isImm())
373 if (
F.isUseOperandTiedToDef(TiedIdx)) {
375 unsigned OpFlags =
MI->getOperand(OpNum).getImm();
377 OpNum +=
F.getNumOperandRegisters() + 1;
386 const unsigned NumVals =
F.getNumOperandRegisters();
395 if (ExtraCode[0] ==
'Q')
401 if (
F.hasRegClassConstraint(RC) &&
402 ARM::GPRPairRegClass.hasSubClassEq(
TRI->getRegClass(RC))) {
410 TRI->getSubReg(MO.
getReg(), FirstHalf ? ARM::gsub_0 : ARM::gsub_1);
416 unsigned RegOp = FirstHalf ? OpNum : OpNum + 1;
417 if (RegOp >=
MI->getNumOperands())
429 if (!
MI->getOperand(OpNum).isReg())
431 Register Reg =
MI->getOperand(OpNum).getReg();
432 if (!ARM::QPRRegClass.
contains(Reg))
436 TRI->getSubReg(Reg, ExtraCode[0] ==
'e' ? ARM::dsub_0 : ARM::dsub_1);
451 if(!ARM::GPRPairRegClass.
contains(Reg))
453 Reg =
TRI->getSubReg(Reg, ARM::gsub_1);
465 unsigned OpNum,
const char *ExtraCode,
468 if (ExtraCode && ExtraCode[0]) {
469 if (ExtraCode[1] != 0)
return true;
471 switch (ExtraCode[0]) {
473 default:
return true;
475 if (!
MI->getOperand(OpNum).isReg())
483 assert(MO.
isReg() &&
"unexpected inline asm memory operand");
496 const bool WasThumb =
isThumb(StartInfo);
497 if (!EndInfo || WasThumb !=
isThumb(*EndInfo)) {
508 const Triple &TT =
TM.getTargetTriple();
515 if (TT.isOSBinFormatELF())
520 if (!M.getModuleInlineAsm().empty() && TT.isThumb())
549 const Triple &TT =
TM.getTargetTriple();
550 if (TT.isOSBinFormatMachO()) {
560 if (!Stubs.empty()) {
565 for (
auto &Stub : Stubs)
573 if (!Stubs.empty()) {
578 for (
auto &Stub : Stubs)
597 if (OptimizationGoals > 0 &&
598 (Subtarget->isTargetAEABI() || Subtarget->isTargetGNUAEABI() ||
599 Subtarget->isTargetMuslAEABI()))
601 OptimizationGoals = -1;
618 if (
F.isDeclaration())
620 return F.getFnAttribute(Attr).getValueAsString() !=
Value;
628 if (
F.isDeclaration())
630 StringRef AttrVal =
F.getFnAttribute(Attr).getValueAsString();
637 auto F = M.functions().begin();
638 auto E = M.functions().end();
644 return !
F.isDeclaration() &&
F.getDenormalModeRaw() !=
Value;
648void ARMAsmPrinter::emitAttributes() {
649 MCTargetStreamer &TS = *
OutStreamer->getTargetStreamer();
650 ARMTargetStreamer &ATS =
static_cast<ARMTargetStreamer &
>(TS);
661 const Triple &
TT =
TM.getTargetTriple();
662 StringRef CPU =
TM.getTargetCPU();
663 StringRef
FS =
TM.getTargetFeatureString();
667 ArchFS = (Twine(ArchFS) +
"," +
FS).str();
669 ArchFS = std::string(FS);
671 const ARMBaseTargetMachine &ATM =
672 static_cast<const ARMBaseTargetMachine &
>(
TM);
673 const ARMSubtarget STI(TT, std::string(CPU), ArchFS, ATM,
683 }
else if (STI.isRWPI()) {
720 if (!STI.hasVFP2Base()) {
730 }
else if (STI.hasVFP3Base()) {
747 "no-trapping-math",
"true") ||
748 TM.Options.NoTrappingFPMath)
756 if (
TM.Options.HonorSignDependentRoundingFPMathOption)
762 if (
TM.Options.NoInfsFPMath &&
TM.Options.NoNaNsFPMath)
785 if (
const Module *SourceModule =
MMI->getModule()) {
789 SourceModule->getModuleFlag(
"wchar_size"))) {
790 int WCharWidth = WCharWidthValue->getZExtValue();
791 assert((WCharWidth == 2 || WCharWidth == 4) &&
792 "wchar_t width must be 2 or 4 bytes");
800 SourceModule->getModuleFlag(
"min_enum_size"))) {
801 int EnumWidth = EnumWidthValue->getZExtValue();
802 assert((EnumWidth == 1 || EnumWidth == 4) &&
803 "Minimum enum width must be 1 or 4 bytes");
804 int EnumBuildAttr = EnumWidth == 1 ? 1 : 2;
809 SourceModule->getModuleFlag(
"sign-return-address"));
810 if (PACValue && PACValue->isOne()) {
814 if (!STI.hasPACBTI()) {
822 SourceModule->getModuleFlag(
"branch-target-enforcement"));
823 if (BTIValue && BTIValue->isOne()) {
827 if (!STI.hasPACBTI()) {
839 else if (STI.isR9Reserved())
853 +
"BF" +
Twine(FunctionNumber) +
"_" +
Twine(LabelId));
861 +
"PC" +
Twine(FunctionNumber) +
"_" +
Twine(LabelId));
886 unsigned char TargetFlags) {
887 if (Subtarget->isTargetMachO()) {
896 MachineModuleInfoMachO &MMIMachO =
897 MMI->getObjFileInfo<MachineModuleInfoMachO>();
902 if (!StubSym.getPointer())
906 }
else if (Subtarget->isTargetCOFF()) {
907 assert(Subtarget->isTargetWindows() &&
908 "Windows is the only supported COFF target");
915 SmallString<128>
Name;
925 MachineModuleInfoCOFF &MMICOFF =
926 MMI->getObjFileInfo<MachineModuleInfoCOFF>();
930 if (!StubSym.getPointer())
935 }
else if (Subtarget->isTargetELF()) {
959 for (
const auto *GV : ACPC->promotedGlobals()) {
960 if (!EmittedPromotedGlobalLabels.count(GV)) {
963 EmittedPromotedGlobalLabels.insert(GV);
982 MCSym = GetARMGVSymbol(GV, TF);
985 MCSym =
MBB->getSymbol();
1028 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel(JTI);
1036 const std::vector<MachineJumpTableEntry> &JT = MJTI->
getJumpTables();
1037 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
1056 else if (AFI->isThumbFunction())
1074 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel(JTI);
1079 const std::vector<MachineJumpTableEntry> &JT = MJTI->
getJumpTables();
1080 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
1087 .addExpr(MBBSymbolExpr)
1094 unsigned OffsetWidth) {
1095 assert((OffsetWidth == 1 || OffsetWidth == 2) &&
"invalid tbb/tbh width");
1099 if (Subtarget->isThumb1Only())
1102 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel(JTI);
1107 const std::vector<MachineJumpTableEntry> &JT = MJTI->
getJumpTables();
1108 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
1114 for (
auto *
MBB : JTBBs) {
1150 const MCSymbol *BranchLabel)
const {
1160 BaseLabel = GetARMJTIPICJumpTableLabel(JTI);
1167 BaseLabel = BranchLabel;
1175 BaseLabel = BranchLabel;
1180 BaseLabel =
nullptr;
1187 return std::make_tuple(BaseLabel, BaseOffset, BranchLabel, EntrySize);
1190void ARMAsmPrinter::EmitUnwindingInstruction(
const MachineInstr *
MI) {
1192 "Only instruction which are involved into frame setup code are allowed");
1202 unsigned Opc =
MI->getOpcode();
1203 unsigned SrcReg, DstReg;
1208 SrcReg = DstReg = ARM::SP;
1212 case ARM::t2MOVTi16:
1233 DstReg =
MI->getOperand(0).getReg();
1236 SrcReg = ARM::FPSCR;
1237 DstReg =
MI->getOperand(0).getReg();
1239 case ARM::VMRS_FPEXC:
1240 SrcReg = ARM::FPEXC;
1241 DstReg =
MI->getOperand(0).getReg();
1244 SrcReg =
MI->getOperand(1).getReg();
1245 DstReg =
MI->getOperand(0).getReg();
1250 if (
MI->mayStore()) {
1252 assert(DstReg == ARM::SP &&
1253 "Only stack pointer as a destination reg is supported");
1257 unsigned StartOp = 2 + 2;
1259 unsigned NumOffset = 0;
1262 unsigned PadBefore = 0;
1265 unsigned PadAfter = 0;
1273 StartOp = 2; NumOffset = 2;
1275 case ARM::STMDB_UPD:
1276 case ARM::t2STMDB_UPD:
1277 case ARM::VSTMDDB_UPD:
1278 assert(SrcReg == ARM::SP &&
1279 "Only stack pointer as a source reg is supported");
1280 for (
unsigned i = StartOp,
NumOps =
MI->getNumOperands() - NumOffset;
1293 "Pad registers must come before restored ones");
1302 if (
unsigned RemappedReg = AFI->EHPrologueRemappedRegs.lookup(
Reg))
1307 case ARM::STR_PRE_IMM:
1308 case ARM::STR_PRE_REG:
1309 case ARM::t2STR_PRE:
1310 assert(
MI->getOperand(2).getReg() == ARM::SP &&
1311 "Only stack pointer as a source reg is supported");
1312 if (
unsigned RemappedReg = AFI->EHPrologueRemappedRegs.lookup(SrcReg))
1313 SrcReg = RemappedReg;
1317 case ARM::t2STRD_PRE:
1318 assert(
MI->getOperand(3).getReg() == ARM::SP &&
1319 "Only stack pointer as a source reg is supported");
1320 SrcReg =
MI->getOperand(1).getReg();
1321 if (
unsigned RemappedReg = AFI->EHPrologueRemappedRegs.lookup(SrcReg))
1322 SrcReg = RemappedReg;
1324 SrcReg =
MI->getOperand(2).getReg();
1325 if (
unsigned RemappedReg = AFI->EHPrologueRemappedRegs.lookup(SrcReg))
1326 SrcReg = RemappedReg;
1328 PadBefore = -
MI->getOperand(4).getImm() - 8;
1341 if (SrcReg == ARM::SP) {
1357 case ARM::t2ADDri12:
1358 case ARM::t2ADDspImm:
1359 case ARM::t2ADDspImm12:
1360 Offset = -
MI->getOperand(2).getImm();
1364 case ARM::t2SUBri12:
1365 case ARM::t2SUBspImm:
1366 case ARM::t2SUBspImm12:
1367 Offset =
MI->getOperand(2).getImm();
1370 Offset =
MI->getOperand(2).getImm()*4;
1374 Offset = -
MI->getOperand(2).getImm()*4;
1378 -AFI->EHPrologueOffsetInRegs.lookup(
MI->getOperand(2).getReg());
1387 else if (DstReg == ARM::SP) {
1397 }
else if (DstReg == ARM::SP) {
1407 AFI->EHPrologueRemappedRegs[DstReg] = SrcReg;
1410 case ARM::VMRS_FPEXC:
1417 case ARM::tLDRpci: {
1420 unsigned CPI =
MI->getOperand(1).getIndex();
1421 const MachineConstantPool *MCP =
MF.getConstantPool();
1422 if (CPI >= MCP->getConstants().size())
1423 CPI = AFI->getOriginalCPIdx(CPI);
1424 assert(CPI != -1U &&
"Invalid constpool index");
1427 const MachineConstantPoolEntry &CPE = MCP->getConstants()[CPI];
1430 AFI->EHPrologueOffsetInRegs[DstReg] =
Offset;
1434 Offset =
MI->getOperand(1).getImm();
1435 AFI->EHPrologueOffsetInRegs[DstReg] =
Offset;
1437 case ARM::t2MOVTi16:
1438 Offset =
MI->getOperand(2).getImm();
1439 AFI->EHPrologueOffsetInRegs[DstReg] |= (
Offset << 16);
1442 Offset =
MI->getOperand(2).getImm();
1443 AFI->EHPrologueOffsetInRegs[DstReg] =
Offset;
1446 assert(
MI->getOperand(3).getImm() == 8 &&
1447 "The shift amount is not equal to 8");
1448 assert(
MI->getOperand(2).getReg() ==
MI->getOperand(0).getReg() &&
1449 "The source register is not equal to the destination register");
1450 AFI->EHPrologueOffsetInRegs[DstReg] <<= 8;
1453 assert(
MI->getOperand(2).getReg() ==
MI->getOperand(0).getReg() &&
1454 "The source register is not equal to the destination register");
1455 Offset =
MI->getOperand(3).getImm();
1456 AFI->EHPrologueOffsetInRegs[DstReg] +=
Offset;
1460 AFI->EHPrologueRemappedRegs[ARM::R12] = ARM::RA_AUTH_CODE;
1472#include "ARMGenMCPseudoLowering.inc"
1475 ARM_MC::verifyInstructionPredicates(
MI->getOpcode(),
1483 if (InConstantPool &&
MI->getOpcode() != ARM::CONSTPOOL_ENTRY) {
1485 InConstantPool =
false;
1489 if (Subtarget->isTargetEHABICompatible() &&
1491 EmitUnwindingInstruction(
MI);
1494 if (
MCInst OutInst; lowerPseudoInstExpansion(
MI, OutInst)) {
1500 "Pseudo flag setting opcode should be expanded early");
1503 unsigned Opc =
MI->getOpcode();
1505 case ARM::t2MOVi32imm:
llvm_unreachable(
"Should be lowered by thumb2it pass");
1506 case ARM::DBG_VALUE:
llvm_unreachable(
"Should be handled by generic printing");
1508 case ARM::tLEApcrel:
1509 case ARM::t2LEApcrel: {
1513 ARM::t2LEApcrel ? ARM::t2ADR
1514 : (
MI->getOpcode() == ARM::tLEApcrel ? ARM::tADR
1516 .
addReg(
MI->getOperand(0).getReg())
1519 .
addImm(
MI->getOperand(2).getImm())
1520 .
addReg(
MI->getOperand(3).getReg()));
1523 case ARM::LEApcrelJT:
1524 case ARM::tLEApcrelJT:
1525 case ARM::t2LEApcrelJT: {
1527 GetARMJTIPICJumpTableLabel(
MI->getOperand(1).getIndex());
1529 ARM::t2LEApcrelJT ? ARM::t2ADR
1530 : (
MI->getOpcode() == ARM::tLEApcrelJT ? ARM::tADR
1532 .
addReg(
MI->getOperand(0).getReg())
1535 .
addImm(
MI->getOperand(2).getImm())
1536 .
addReg(
MI->getOperand(3).getReg()));
1541 case ARM::BX_CALL: {
1551 assert(Subtarget->hasV4TOps());
1553 .addReg(
MI->getOperand(0).getReg()));
1556 case ARM::tBX_CALL: {
1557 if (Subtarget->hasV5TOps())
1568 for (std::pair<unsigned, MCSymbol *> &TIP : ThumbIndirectPads) {
1569 if (TIP.first == TReg) {
1570 TRegSym = TIP.second;
1577 ThumbIndirectPads.push_back(std::make_pair(TReg, TRegSym));
1587 case ARM::BMOVPCRX_CALL: {
1599 .addReg(
MI->getOperand(0).getReg())
1607 case ARM::BMOVPCB_CALL: {
1619 const unsigned TF =
Op.getTargetFlags();
1620 MCSymbol *GVSym = GetARMGVSymbol(GV, TF);
1629 case ARM::MOVi16_ga_pcrel:
1630 case ARM::t2MOVi16_ga_pcrel: {
1632 TmpInst.
setOpcode(
Opc == ARM::MOVi16_ga_pcrel? ARM::MOVi16 : ARM::t2MOVi16);
1635 unsigned TF =
MI->getOperand(1).getTargetFlags();
1637 MCSymbol *GVSym = GetARMGVSymbol(GV, TF);
1644 unsigned PCAdj = (
Opc == ARM::MOVi16_ga_pcrel) ? 8 : 4;
1663 case ARM::MOVTi16_ga_pcrel:
1664 case ARM::t2MOVTi16_ga_pcrel: {
1667 ? ARM::MOVTi16 : ARM::t2MOVTi16);
1671 unsigned TF =
MI->getOperand(2).getTargetFlags();
1673 MCSymbol *GVSym = GetARMGVSymbol(GV, TF);
1680 unsigned PCAdj = (
Opc == ARM::MOVTi16_ga_pcrel) ? 8 : 4;
1711 if (
MI->getOperand(1).isReg()) {
1713 MCInst.addReg(
MI->getOperand(1).getReg());
1716 const MCExpr *BranchTarget;
1717 if (
MI->getOperand(1).isMBB())
1720 else if (
MI->getOperand(1).isGlobal()) {
1723 GetARMGVSymbol(GV,
MI->getOperand(1).getTargetFlags()),
OutContext);
1724 }
else if (
MI->getOperand(1).isSymbol()) {
1731 MCInst.addExpr(BranchTarget);
1734 if (
Opc == ARM::t2BFic) {
1739 MCInst.addExpr(ElseLabel);
1740 MCInst.addImm(
MI->getOperand(3).getImm());
1742 MCInst.addImm(
MI->getOperand(2).getImm())
1743 .addReg(
MI->getOperand(3).getReg());
1749 case ARM::t2BF_LabelPseudo: {
1758 case ARM::tPICADD: {
1771 .addReg(
MI->getOperand(0).getReg())
1772 .
addReg(
MI->getOperand(0).getReg())
1792 .addReg(
MI->getOperand(0).getReg())
1794 .
addReg(
MI->getOperand(1).getReg())
1796 .
addImm(
MI->getOperand(3).getImm())
1797 .
addReg(
MI->getOperand(4).getReg())
1809 case ARM::PICLDRSH: {
1823 switch (
MI->getOpcode()) {
1826 case ARM::PICSTR: Opcode = ARM::STRrs;
break;
1827 case ARM::PICSTRB: Opcode = ARM::STRBrs;
break;
1828 case ARM::PICSTRH: Opcode = ARM::STRH;
break;
1829 case ARM::PICLDR: Opcode = ARM::LDRrs;
break;
1830 case ARM::PICLDRB: Opcode = ARM::LDRBrs;
break;
1831 case ARM::PICLDRH: Opcode = ARM::LDRH;
break;
1832 case ARM::PICLDRSB: Opcode = ARM::LDRSB;
break;
1833 case ARM::PICLDRSH: Opcode = ARM::LDRSH;
break;
1836 .addReg(
MI->getOperand(0).getReg())
1838 .
addReg(
MI->getOperand(1).getReg())
1841 .
addImm(
MI->getOperand(3).getImm())
1842 .
addReg(
MI->getOperand(4).getReg()));
1846 case ARM::CONSTPOOL_ENTRY: {
1847 if (Subtarget->genExecuteOnly())
1855 unsigned LabelId = (
unsigned)
MI->getOperand(0).getImm();
1856 unsigned CPIdx = (
unsigned)
MI->getOperand(1).getIndex();
1859 if (!InConstantPool) {
1861 InConstantPool =
true;
1873 case ARM::JUMPTABLE_ADDRS:
1876 case ARM::JUMPTABLE_INSTS:
1879 case ARM::JUMPTABLE_TBB:
1880 case ARM::JUMPTABLE_TBH:
1883 case ARM::t2BR_JT: {
1886 .addReg(
MI->getOperand(0).getReg())
1893 case ARM::t2TBH_JT: {
1894 unsigned Opc =
MI->getOpcode() == ARM::t2TBB_JT ? ARM::t2TBB : ARM::t2TBH;
1898 .addReg(
MI->getOperand(0).getReg())
1899 .
addReg(
MI->getOperand(1).getReg())
1906 case ARM::tTBH_JT: {
1908 bool Is8Bit =
MI->getOpcode() == ARM::tTBB_JT;
1911 assert(
MI->getOperand(1).isKill() &&
"We need the index register as scratch!");
1924 if (
Base == ARM::PC) {
1947 unsigned Opc = Is8Bit ? ARM::tLDRBi : ARM::tLDRHi;
1951 .addImm(Is8Bit ? 4 : 2)
1961 unsigned Opc = Is8Bit ? ARM::tLDRBr : ARM::tLDRHr;
1994 unsigned Opc =
MI->getOpcode() == ARM::BR_JTr ?
1995 ARM::MOVr : ARM::tMOVr;
2003 if (
Opc == ARM::MOVr)
2008 case ARM::BR_JTm_i12: {
2021 case ARM::BR_JTm_rs: {
2035 case ARM::BR_JTadd: {
2039 .addReg(
MI->getOperand(0).getReg())
2040 .
addReg(
MI->getOperand(1).getReg())
2054 if (!Subtarget->isTargetMachO()) {
2065 if (!Subtarget->isTargetMachO()) {
2073 case ARM::t2Int_eh_sjlj_setjmp:
2074 case ARM::t2Int_eh_sjlj_setjmp_nofp:
2075 case ARM::tInt_eh_sjlj_setjmp: {
2084 Register SrcReg =
MI->getOperand(0).getReg();
2085 Register ValReg =
MI->getOperand(1).getReg();
2125 .addExpr(SymbolExpr)
2142 case ARM::Int_eh_sjlj_setjmp_nofp:
2143 case ARM::Int_eh_sjlj_setjmp: {
2150 Register SrcReg =
MI->getOperand(0).getReg();
2151 Register ValReg =
MI->getOperand(1).getReg();
2202 case ARM::Int_eh_sjlj_longjmp: {
2207 Register SrcReg =
MI->getOperand(0).getReg();
2208 Register ScratchReg =
MI->getOperand(1).getReg();
2256 assert(Subtarget->hasV4TOps());
2264 case ARM::tInt_eh_sjlj_longjmp: {
2270 Register SrcReg =
MI->getOperand(0).getReg();
2271 Register ScratchReg =
MI->getOperand(1).getReg();
2336 case ARM::tInt_WIN_eh_sjlj_longjmp: {
2341 Register SrcReg =
MI->getOperand(0).getReg();
2366 case ARM::PATCHABLE_FUNCTION_ENTER:
2369 case ARM::PATCHABLE_FUNCTION_EXIT:
2372 case ARM::PATCHABLE_TAIL_CALL:
2375 case ARM::SpeculationBarrierISBDSBEndBB: {
2387 case ARM::t2SpeculationBarrierISBDSBEndBB: {
2403 case ARM::SpeculationBarrierSBEndBB: {
2410 case ARM::t2SpeculationBarrierSBEndBB: {
2418 case ARM::SEH_StackAlloc:
2420 MI->getOperand(1).getImm());
2423 case ARM::SEH_SaveRegs:
2424 case ARM::SEH_SaveRegs_Ret:
2426 MI->getOperand(1).getImm());
2429 case ARM::SEH_SaveSP:
2433 case ARM::SEH_SaveFRegs:
2435 MI->getOperand(1).getImm());
2438 case ARM::SEH_SaveLR:
2443 case ARM::SEH_Nop_Ret:
2447 case ARM::SEH_PrologEnd:
2451 case ARM::SEH_EpilogStart:
2455 case ARM::SEH_EpilogEnd:
2477LLVMInitializeARMAsmPrinter() {
assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")
static void emitNonLazySymbolPointer(MCStreamer &OutStreamer, MCSymbol *StubLabel, MachineModuleInfoImpl::StubValueTy &MCSym)
static uint8_t getModifierSpecifier(ARMCP::ARMCPModifier Modifier)
static MCSymbol * getPICLabel(StringRef Prefix, unsigned FunctionNumber, unsigned LabelId, MCContext &Ctx)
static bool checkDenormalAttributeInconsistency(const Module &M)
static bool checkFunctionsAttributeConsistency(const Module &M, StringRef Attr, StringRef Value)
static bool isThumb(const MCSubtargetInfo &STI)
static MCSymbol * getBFLabel(StringRef Prefix, unsigned FunctionNumber, unsigned LabelId, MCContext &Ctx)
static bool checkDenormalAttributeConsistency(const Module &M, StringRef Attr, DenormalMode Value)
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
#define LLVM_EXTERNAL_VISIBILITY
This file contains the declarations for the subclasses of Constant, which represent the different fla...
Module.h This file contains the declarations for the Module class.
const size_t AbstractManglingParser< Derived, Alloc >::NumOps
Machine Check Debug Module
Register const TargetRegisterInfo * TRI
Promote Memory to Register
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
static bool contains(SmallPtrSetImpl< ConstantExpr * > &Cache, ConstantExpr *Expr, Constant *C)
This file defines the SmallString class.
static TableGen::Emitter::Opt Y("gen-skeleton-entry", EmitSkeleton, "Generate example skeleton entry")
static TableGen::Emitter::OptClass< SkeletonEmitter > X("gen-skeleton-class", "Generate example skeleton class")
static const unsigned FramePtr
void emitJumpTableAddrs(const MachineInstr *MI)
void emitJumpTableTBInst(const MachineInstr *MI, unsigned OffsetWidth)
void emitFunctionBodyEnd() override
Targets can override this to emit stuff after the last basic block in the function.
bool runOnMachineFunction(MachineFunction &F) override
runOnMachineFunction - This uses the emitInstruction() method to print assembly for each instruction.
MCSymbol * GetCPISymbol(unsigned CPID) const override
Return the symbol for the specified constant pool entry.
void printOperand(const MachineInstr *MI, int OpNum, raw_ostream &O)
void emitStartOfAsmFile(Module &M) override
This virtual method can be overridden by targets that want to emit something at the start of their fi...
ARMAsmPrinter(TargetMachine &TM, std::unique_ptr< MCStreamer > Streamer)
void emitFunctionEntryLabel() override
EmitFunctionEntryLabel - Emit the label that is the entrypoint for the function.
void emitInlineAsmEnd(const MCSubtargetInfo &StartInfo, const MCSubtargetInfo *EndInfo) const override
Let the target do anything it needs to do after emitting inlineasm.
void LowerPATCHABLE_FUNCTION_EXIT(const MachineInstr &MI)
void emitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) override
EmitMachineConstantPoolValue - Print a machine constantpool value to the .s file.
bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNum, const char *ExtraCode, raw_ostream &O) override
Print the specified operand of MI, an INLINEASM instruction, using the specified assembler variant.
void emitXXStructor(const DataLayout &DL, const Constant *CV) override
Targets can override this to change how global constants that are part of a C++ static/global constru...
void LowerPATCHABLE_FUNCTION_ENTER(const MachineInstr &MI)
void LowerPATCHABLE_TAIL_CALL(const MachineInstr &MI)
void emitEndOfAsmFile(Module &M) override
This virtual method can be overridden by targets that want to emit something at the end of their file...
std::tuple< const MCSymbol *, uint64_t, const MCSymbol *, codeview::JumpTableEntrySize > getCodeViewJumpTableInfo(int JTI, const MachineInstr *BranchInstr, const MCSymbol *BranchLabel) const override
Gets information required to create a CodeView debug symbol for a jump table.
void emitJumpTableInsts(const MachineInstr *MI)
const ARMBaseTargetMachine & getTM() const
void emitGlobalVariable(const GlobalVariable *GV) override
Emit the specified global variable to the .s file.
bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum, const char *ExtraCode, raw_ostream &O) override
Print the specified operand of MI, an INLINEASM instruction, using the specified assembler variant as...
void emitInstruction(const MachineInstr *MI) override
Targets should implement this to emit instructions.
void PrintSymbolOperand(const MachineOperand &MO, raw_ostream &O) override
Print the MachineOperand as a symbol.
bool isLittleEndian() const
ARMConstantPoolValue - ARM specific constantpool value.
bool isPromotedGlobal() const
unsigned char getPCAdjustment() const
bool isMachineBasicBlock() const
bool isGlobalValue() const
ARMCP::ARMCPModifier getModifier() const
bool mustAddCurrentAddress() const
unsigned getLabelId() const
bool isBlockAddress() const
ARMFunctionInfo - This class is derived from MachineFunctionInfo and contains private ARM-specific in...
static const char * getRegisterName(MCRegister Reg, unsigned AltIdx=ARM::NoRegAltName)
MCPhysReg getFramePointerReg() const
bool isTargetWindows() const
bool isTargetDarwin() const
void emitTargetAttributes(const MCSubtargetInfo &STI)
Emit the build attributes that only depend on the hardware that we expect.
virtual void emitSetFP(MCRegister FpReg, MCRegister SpReg, int64_t Offset=0)
virtual void finishAttributeSection()
virtual void emitMovSP(MCRegister Reg, int64_t Offset=0)
virtual void emitARMWinCFISaveSP(unsigned Reg)
virtual void emitInst(uint32_t Inst, char Suffix='\0')
virtual void emitARMWinCFISaveLR(unsigned Offset)
virtual void emitTextAttribute(unsigned Attribute, StringRef String)
virtual void emitARMWinCFIAllocStack(unsigned Size, bool Wide)
virtual void emitARMWinCFISaveRegMask(unsigned Mask, bool Wide)
virtual void emitRegSave(const SmallVectorImpl< MCRegister > &RegList, bool isVector)
virtual void emitARMWinCFIEpilogEnd()
virtual void emitARMWinCFIPrologEnd(bool Fragment)
virtual void switchVendor(StringRef Vendor)
virtual void emitCode16()
virtual void emitARMWinCFISaveFRegs(unsigned First, unsigned Last)
virtual void emitSyntaxUnified()
virtual void emitARMWinCFIEpilogStart(unsigned Condition)
virtual void emitPad(int64_t Offset)
virtual void emitAttribute(unsigned Attribute, unsigned Value)
virtual void emitARMWinCFINop(bool Wide)
const TargetLoweringObjectFile & getObjFileLowering() const
Return information about object file lowering.
MCSymbol * getSymbolWithGlobalValueBase(const GlobalValue *GV, StringRef Suffix) const
Return the MCSymbol for a private symbol with global value name as its base, with the specified suffi...
MCSymbol * getSymbol(const GlobalValue *GV) const
void EmitToStreamer(MCStreamer &S, const MCInst &Inst)
virtual void emitGlobalVariable(const GlobalVariable *GV)
Emit the specified global variable to the .s file.
TargetMachine & TM
Target machine description.
void emitXRayTable()
Emit a table with all XRay instrumentation points.
MCSymbol * getMBBExceptionSym(const MachineBasicBlock &MBB)
const MCAsmInfo * MAI
Target Asm Printer information.
MachineFunction * MF
The current machine function.
virtual void SetupMachineFunction(MachineFunction &MF)
This should be called when a new MachineFunction is being processed from runOnMachineFunction.
void emitFunctionBody()
This method emits the body and trailer for a function.
virtual void emitLinkage(const GlobalValue *GV, MCSymbol *GVSym) const
This emits linkage information about GVSym based on GV, if this is supported by the target.
unsigned getFunctionNumber() const
Return a unique ID for the current function.
AsmPrinter(TargetMachine &TM, std::unique_ptr< MCStreamer > Streamer, char &ID=AsmPrinter::ID)
void printOffset(int64_t Offset, raw_ostream &OS) const
This is just convenient handler for printing offsets.
void emitGlobalConstant(const DataLayout &DL, const Constant *CV, AliasMapTy *AliasList=nullptr)
EmitGlobalConstant - Print a general LLVM constant to the .s file.
MCSymbol * getSymbolPreferLocal(const GlobalValue &GV) const
Similar to getSymbol() but preferred for references.
MCSymbol * CurrentFnSym
The symbol for the current function.
MachineModuleInfo * MMI
This is a pointer to the current MachineModuleInfo.
void emitAlignment(Align Alignment, const GlobalObject *GV=nullptr, unsigned MaxBytesToEmit=0) const
Emit an alignment directive to the specified power of two boundary.
MCContext & OutContext
This is the context for the output file that we are streaming.
bool isPositionIndependent() const
std::unique_ptr< MCStreamer > OutStreamer
This is the MCStreamer object for the file we are generating.
void getNameWithPrefix(SmallVectorImpl< char > &Name, const GlobalValue *GV) const
MCSymbol * GetBlockAddressSymbol(const BlockAddress *BA) const
Return the MCSymbol used to satisfy BlockAddress uses of the specified basic block.
const DataLayout & getDataLayout() const
Return information about data layout.
virtual void emitFunctionEntryLabel()
EmitFunctionEntryLabel - Emit the label that is the entrypoint for the function.
MCSymbol * GetExternalSymbolSymbol(const Twine &Sym) const
Return the MCSymbol for the specified ExternalSymbol.
const MCSubtargetInfo & getSubtargetInfo() const
Return information about subtarget.
virtual bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, const char *ExtraCode, raw_ostream &OS)
Print the specified operand of MI, an INLINEASM instruction, using the specified assembler variant.
The address of a basic block.
This is an important base class in LLVM.
const Constant * stripPointerCasts() const
A parsed version of the target data layout string in and methods for querying it.
TypeSize getTypeAllocSize(Type *Ty) const
Returns the offset in bytes between successive objects of the specified type, including alignment pad...
bool isThreadLocal() const
If the value is "Thread Local", its value isn't shared by the threads.
bool hasInternalLinkage() const
static const MCBinaryExpr * createAdd(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx, SMLoc Loc=SMLoc())
static const MCBinaryExpr * createDiv(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
static const MCBinaryExpr * createSub(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
static LLVM_ABI const MCConstantExpr * create(int64_t Value, MCContext &Ctx, bool PrintInHex=false, unsigned SizeInBytes=0)
Context object for machine code objects.
LLVM_ABI MCSymbol * getOrCreateSymbol(const Twine &Name)
Lookup the symbol inside with the specified Name.
Base class for the full range of assembler expressions which are needed for parsing.
MCInstBuilder & addReg(MCRegister Reg)
Add a new register operand.
MCInstBuilder & addImm(int64_t Val)
Add a new integer immediate operand.
MCInstBuilder & addExpr(const MCExpr *Val)
Add a new MCExpr operand.
Instances of this class represent a single low-level machine instruction.
void addOperand(const MCOperand Op)
void setOpcode(unsigned Op)
MCSection * getThreadLocalPointerSection() const
MCSection * getNonLazySymbolPointerSection() const
static MCOperand createExpr(const MCExpr *Val)
static MCOperand createReg(MCRegister Reg)
static MCOperand createImm(int64_t Val)
Wrapper class representing physical registers. Should be passed by value.
Streaming machine code generation interface.
virtual bool emitSymbolAttribute(MCSymbol *Symbol, MCSymbolAttr Attribute)=0
Add the given Attribute to Symbol.
MCContext & getContext() const
void emitValue(const MCExpr *Value, unsigned Size, SMLoc Loc=SMLoc())
virtual void emitLabel(MCSymbol *Symbol, SMLoc Loc=SMLoc())
Emit a label for Symbol into the current section.
virtual void emitIntValue(uint64_t Value, unsigned Size)
Special case of EmitValue that avoids the client having to pass in a MCExpr for constant integers.
Generic base class for all target subtargets.
bool hasFeature(unsigned Feature) const
static const MCSymbolRefExpr * create(const MCSymbol *Symbol, MCContext &Ctx, SMLoc Loc=SMLoc())
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
LLVM_ABI void print(raw_ostream &OS, const MCAsmInfo *MAI) const
print - Print the value to the stream OS.
Target specific streamer interface.
LLVM_ABI MCSymbol * getSymbol() const
Return the MCSymbol for this basic block.
This class is a data container for one entry in a MachineConstantPool.
union llvm::MachineConstantPoolEntry::@004270020304201266316354007027341142157160323045 Val
The constant itself.
bool isMachineConstantPoolEntry() const
isMachineConstantPoolEntry - Return true if the MachineConstantPoolEntry is indeed a target specific ...
MachineConstantPoolValue * MachineCPVal
const Constant * ConstVal
Abstract base class for all machine specific constantpool value subclasses.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Representation of each machine instruction.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
const MachineOperand & getOperand(unsigned i) const
const std::vector< MachineJumpTableEntry > & getJumpTables() const
StubValueTy & getGVStubEntry(MCSymbol *Sym)
std::vector< std::pair< MCSymbol *, StubValueTy > > SymbolListTy
PointerIntPair< MCSymbol *, 1, bool > StubValueTy
MachineModuleInfoMachO - This is a MachineModuleInfoImpl implementation for MachO targets.
SymbolListTy GetThreadLocalGVStubList()
StubValueTy & getGVStubEntry(MCSymbol *Sym)
StubValueTy & getThreadLocalGVStubEntry(MCSymbol *Sym)
SymbolListTy GetGVStubList()
Accessor methods to return the set of stubs in sorted order.
MachineOperand class - Representation of each machine instruction operand.
unsigned getSubReg() const
const GlobalValue * getGlobal() const
bool isReg() const
isReg - Tests if this is a MO_Register operand.
MachineBasicBlock * getMBB() const
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
unsigned getTargetFlags() const
bool isGlobal() const
isGlobal - Tests if this is a MO_GlobalAddress operand.
MachineOperandType getType() const
getType - Returns the MachineOperandType for this operand.
Register getReg() const
getReg - Returns the register number.
@ MO_Immediate
Immediate operand.
@ MO_ConstantPoolIndex
Address of indexed Constant in Constant Pool.
@ MO_GlobalAddress
Address of a global value.
@ MO_MachineBasicBlock
MachineBasicBlock reference.
@ MO_Register
Register operand.
int64_t getOffset() const
Return the offset from the symbol in this operand.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
A Module instance is used to store all the information related to an LLVM module.
virtual void print(raw_ostream &OS, const Module *M) const
print - Print out the internal state of the pass.
PointerTy getPointer() const
Wrapper class representing virtual and physical registers.
SmallString - A SmallString is just a SmallVector with methods and accessors that make it work better...
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
StringRef - Represent a constant reference to a string, i.e.
Primary interface to the complete machine description for the target machine.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
TypeSize getRegSizeInBits(const TargetRegisterClass &RC) const
Return the size in bits of a register from class RC.
virtual Register getFrameRegister(const MachineFunction &MF) const =0
Debug information queries.
virtual const TargetRegisterInfo * getRegisterInfo() const =0
Return the target's register information.
Triple - Helper class for working with autoconf configuration names.
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
The instances of the Type class are immutable: once they are created, they are never changed.
LLVM Value Representation.
Type * getType() const
All values are typed, get the type of this value.
This class implements an extremely fast bulk output stream that can only output to a stream.
A raw_ostream that writes to an SmallVector or SmallString.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ SECREL
Thread Pointer Offset.
@ GOT_PREL
Thread Local Storage (General Dynamic Mode)
@ SBREL
Section Relative (Windows TLS)
@ GOTTPOFF
Global Offset Table, PC Relative.
@ TPOFF
Global Offset Table, Thread Pointer Offset.
@ MO_LO16
MO_LO16 - On a symbol operand, this represents a relocation containing lower 16 bit of the address.
@ MO_LO_0_7
MO_LO_0_7 - On a symbol operand, this represents a relocation containing bits 0 through 7 of the addr...
@ MO_LO_8_15
MO_LO_8_15 - On a symbol operand, this represents a relocation containing bits 8 through 15 of the ad...
@ MO_NONLAZY
MO_NONLAZY - This is an independent flag, on a symbol operand "FOO" it represents a symbol which,...
@ MO_HI_8_15
MO_HI_8_15 - On a symbol operand, this represents a relocation containing bits 24 through 31 of the a...
@ MO_HI16
MO_HI16 - On a symbol operand, this represents a relocation containing higher 16 bit of the address.
@ MO_DLLIMPORT
MO_DLLIMPORT - On a symbol operand, this represents that the reference to the symbol is for an import...
@ MO_HI_0_7
MO_HI_0_7 - On a symbol operand, this represents a relocation containing bits 16 through 23 of the ad...
@ MO_COFFSTUB
MO_COFFSTUB - On a symbol operand "FOO", this indicates that the reference is actually to the "....
std::string ParseARMTriple(const Triple &TT, StringRef CPU)
const MCSpecifierExpr * createLower16(const MCExpr *Expr, MCContext &Ctx)
const MCSpecifierExpr * createUpper16(const MCExpr *Expr, MCContext &Ctx)
SymbolStorageClass
Storage class tells where and what the symbol represents.
@ IMAGE_SYM_CLASS_EXTERNAL
External symbol.
@ IMAGE_SYM_CLASS_STATIC
Static.
@ IMAGE_SYM_DTYPE_FUNCTION
A function that returns a base type.
@ SCT_COMPLEX_TYPE_SHIFT
Type is formed as (base + (derived << SCT_COMPLEX_TYPE_SHIFT))
std::enable_if_t< detail::IsValidPointer< X, Y >::value, X * > extract_or_null(Y &&MD)
Extract a Value from Metadata, allowing null.
This is an optimization pass for GlobalISel generic memory operations.
decltype(auto) dyn_cast(const From &Val)
dyn_cast<X> - Return the argument parameter cast to the specified type.
Target & getTheThumbBETarget()
@ MCDR_DataRegionEnd
.end_data_region
@ MCDR_DataRegion
.data_region
@ MCDR_DataRegionJT8
.data_region jt8
@ MCDR_DataRegionJT32
.data_region jt32
@ MCDR_DataRegionJT16
.data_region jt16
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
MachineInstr * getImm(const MachineOperand &MO, const MachineRegisterInfo *MRI)
LLVM_ABI raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.
void LowerARMMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI, ARMAsmPrinter &AP)
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
DWARFExpression::Operation Op
OutputIt move(R &&Range, OutputIt Out)
Provide wrappers to std::move which take ranges instead of having to pass begin/end explicitly.
DenormalMode parseDenormalFPAttribute(StringRef Str)
Returns the denormal mode to use for inputs and outputs.
decltype(auto) cast(const From &Val)
cast<X> - Return the argument parameter cast to the specified type.
Target & getTheARMLETarget()
unsigned convertAddSubFlagsOpcode(unsigned OldOpc)
Map pseudo instructions that imply an 'S' bit onto real opcodes.
@ MCSA_IndirectSymbol
.indirect_symbol (MachO)
@ MCSA_ELF_TypeFunction
.type _foo, STT_FUNC # aka @function
Target & getTheARMBETarget()
Target & getTheThumbLETarget()
Implement std::hash so that hash_code can be used in STL containers.
This struct is a compact representation of a valid (non-zero power of two) alignment.
Represent subnormal handling kind for floating point instruction inputs and outputs.
static constexpr DenormalMode getPositiveZero()
static constexpr DenormalMode getPreserveSign()
static constexpr DenormalMode getIEEE()
RegisterAsmPrinter - Helper template for registering a target specific assembly printer,...