LLVM 22.0.0git
ARMAsmPrinter.cpp
Go to the documentation of this file.
1//===-- ARMAsmPrinter.cpp - Print machine code to an ARM .s file ----------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains a printer that converts from our internal representation
10// of machine-dependent LLVM code to GAS-format ARM assembly language.
11//
12//===----------------------------------------------------------------------===//
13
14#include "ARMAsmPrinter.h"
15#include "ARM.h"
18#include "ARMTargetMachine.h"
19#include "ARMTargetObjectFile.h"
27#include "llvm/IR/Constants.h"
28#include "llvm/IR/DataLayout.h"
29#include "llvm/IR/Mangler.h"
30#include "llvm/IR/Module.h"
31#include "llvm/IR/Type.h"
32#include "llvm/MC/MCAsmInfo.h"
33#include "llvm/MC/MCAssembler.h"
34#include "llvm/MC/MCContext.h"
36#include "llvm/MC/MCInst.h"
39#include "llvm/MC/MCStreamer.h"
40#include "llvm/MC/MCSymbol.h"
44#include "llvm/Support/Debug.h"
48using namespace llvm;
49
50#define DEBUG_TYPE "asm-printer"
51
53 std::unique_ptr<MCStreamer> Streamer)
54 : AsmPrinter(TM, std::move(Streamer), ID), Subtarget(nullptr), AFI(nullptr),
55 MCP(nullptr), InConstantPool(false), OptimizationGoals(-1) {}
56
58 return static_cast<const ARMBaseTargetMachine &>(TM);
59}
60
62 // Make sure to terminate any constant pools that were at the end
63 // of the function.
64 if (!InConstantPool)
65 return;
66 InConstantPool = false;
67 OutStreamer->emitDataRegion(MCDR_DataRegionEnd);
68}
69
71 auto &TS =
72 static_cast<ARMTargetStreamer &>(*OutStreamer->getTargetStreamer());
73 if (AFI->isThumbFunction()) {
74 TS.emitCode16();
75 TS.emitThumbFunc(CurrentFnSym);
76 } else {
77 TS.emitCode32();
78 }
79
80 // Emit symbol for CMSE non-secure entry point
81 if (AFI->isCmseNSEntryFunction()) {
82 MCSymbol *S =
83 OutContext.getOrCreateSymbol("__acle_se_" + CurrentFnSym->getName());
84 emitLinkage(&MF->getFunction(), S);
85 OutStreamer->emitSymbolAttribute(S, MCSA_ELF_TypeFunction);
86 OutStreamer->emitLabel(S);
87 }
89}
90
93 assert(Size && "C++ constructor pointer had zero size!");
94
96 assert(GV && "C++ constructor pointer was not a GlobalValue!");
97
99 GetARMGVSymbol(GV, ARMII::MO_NO_FLAG),
100 (Subtarget->isTargetELF() ? ARM::S_TARGET1 : ARM::S_None), OutContext);
101
102 OutStreamer->emitValue(E, Size);
103}
104
106 if (PromotedGlobals.count(GV))
107 // The global was promoted into a constant pool. It should not be emitted.
108 return;
110}
111
112/// runOnMachineFunction - This uses the emitInstruction()
113/// method to print assembly for each instruction.
114///
116 AFI = MF.getInfo<ARMFunctionInfo>();
117 MCP = MF.getConstantPool();
118 Subtarget = &MF.getSubtarget<ARMSubtarget>();
119
121 const Function &F = MF.getFunction();
122 const TargetMachine& TM = MF.getTarget();
123
124 // Collect all globals that had their storage promoted to a constant pool.
125 // Functions are emitted before variables, so this accumulates promoted
126 // globals from all functions in PromotedGlobals.
127 PromotedGlobals.insert_range(AFI->getGlobalsPromotedToConstantPool());
128
129 // Calculate this function's optimization goal.
130 unsigned OptimizationGoal;
131 if (F.hasOptNone())
132 // For best debugging illusion, speed and small size sacrificed
133 OptimizationGoal = 6;
134 else if (F.hasMinSize())
135 // Aggressively for small size, speed and debug illusion sacrificed
136 OptimizationGoal = 4;
137 else if (F.hasOptSize())
138 // For small size, but speed and debugging illusion preserved
139 OptimizationGoal = 3;
140 else if (TM.getOptLevel() == CodeGenOptLevel::Aggressive)
141 // Aggressively for speed, small size and debug illusion sacrificed
142 OptimizationGoal = 2;
143 else if (TM.getOptLevel() > CodeGenOptLevel::None)
144 // For speed, but small size and good debug illusion preserved
145 OptimizationGoal = 1;
146 else // TM.getOptLevel() == CodeGenOptLevel::None
147 // For good debugging, but speed and small size preserved
148 OptimizationGoal = 5;
149
150 // Combine a new optimization goal with existing ones.
151 if (OptimizationGoals == -1) // uninitialized goals
152 OptimizationGoals = OptimizationGoal;
153 else if (OptimizationGoals != (int)OptimizationGoal) // conflicting goals
154 OptimizationGoals = 0;
155
156 if (Subtarget->isTargetCOFF()) {
157 bool Local = F.hasLocalLinkage();
161
162 OutStreamer->beginCOFFSymbolDef(CurrentFnSym);
163 OutStreamer->emitCOFFSymbolStorageClass(Scl);
164 OutStreamer->emitCOFFSymbolType(Type);
165 OutStreamer->endCOFFSymbolDef();
166 }
167
168 // Emit the rest of the function body.
170
171 // Emit the XRay table for this function.
173
174 // If we need V4T thumb mode Register Indirect Jump pads, emit them.
175 // These are created per function, rather than per TU, since it's
176 // relatively easy to exceed the thumb branch range within a TU.
177 if (! ThumbIndirectPads.empty()) {
178 auto &TS =
179 static_cast<ARMTargetStreamer &>(*OutStreamer->getTargetStreamer());
180 TS.emitCode16();
182 for (std::pair<unsigned, MCSymbol *> &TIP : ThumbIndirectPads) {
183 OutStreamer->emitLabel(TIP.second);
185 .addReg(TIP.first)
186 // Add predicate operands.
188 .addReg(0));
189 }
190 ThumbIndirectPads.clear();
191 }
192
193 // We didn't modify anything.
194 return false;
195}
196
198 raw_ostream &O) {
199 assert(MO.isGlobal() && "caller should check MO.isGlobal");
200 unsigned TF = MO.getTargetFlags();
201 if (TF & ARMII::MO_LO16)
202 O << ":lower16:";
203 else if (TF & ARMII::MO_HI16)
204 O << ":upper16:";
205 else if (TF & ARMII::MO_LO_0_7)
206 O << ":lower0_7:";
207 else if (TF & ARMII::MO_LO_8_15)
208 O << ":lower8_15:";
209 else if (TF & ARMII::MO_HI_0_7)
210 O << ":upper0_7:";
211 else if (TF & ARMII::MO_HI_8_15)
212 O << ":upper8_15:";
213
214 GetARMGVSymbol(MO.getGlobal(), TF)->print(O, MAI);
215 printOffset(MO.getOffset(), O);
216}
217
219 raw_ostream &O) {
220 const MachineOperand &MO = MI->getOperand(OpNum);
221
222 switch (MO.getType()) {
223 default: llvm_unreachable("<unknown operand type>");
225 Register Reg = MO.getReg();
226 assert(Reg.isPhysical());
227 assert(!MO.getSubReg() && "Subregs should be eliminated!");
228 if(ARM::GPRPairRegClass.contains(Reg)) {
229 const MachineFunction &MF = *MI->getParent()->getParent();
230 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
231 Reg = TRI->getSubReg(Reg, ARM::gsub_0);
232 }
234 break;
235 }
237 O << '#';
238 unsigned TF = MO.getTargetFlags();
239 if (TF == ARMII::MO_LO16)
240 O << ":lower16:";
241 else if (TF == ARMII::MO_HI16)
242 O << ":upper16:";
243 else if (TF == ARMII::MO_LO_0_7)
244 O << ":lower0_7:";
245 else if (TF == ARMII::MO_LO_8_15)
246 O << ":lower8_15:";
247 else if (TF == ARMII::MO_HI_0_7)
248 O << ":upper0_7:";
249 else if (TF == ARMII::MO_HI_8_15)
250 O << ":upper8_15:";
251 O << MO.getImm();
252 break;
253 }
255 MO.getMBB()->getSymbol()->print(O, MAI);
256 return;
258 PrintSymbolOperand(MO, O);
259 break;
260 }
262 if (Subtarget->genExecuteOnly())
263 llvm_unreachable("execute-only should not generate constant pools");
264 GetCPISymbol(MO.getIndex())->print(O, MAI);
265 break;
266 }
267}
268
270 // The AsmPrinter::GetCPISymbol superclass method tries to use CPID as
271 // indexes in MachineConstantPool, which isn't in sync with indexes used here.
272 const DataLayout &DL = getDataLayout();
273 return OutContext.getOrCreateSymbol(Twine(DL.getPrivateGlobalPrefix()) +
274 "CPI" + Twine(getFunctionNumber()) + "_" +
275 Twine(CPID));
276}
277
278//===--------------------------------------------------------------------===//
279
280MCSymbol *ARMAsmPrinter::
281GetARMJTIPICJumpTableLabel(unsigned uid) const {
282 const DataLayout &DL = getDataLayout();
283 SmallString<60> Name;
284 raw_svector_ostream(Name) << DL.getPrivateGlobalPrefix() << "JTI"
285 << getFunctionNumber() << '_' << uid;
286 return OutContext.getOrCreateSymbol(Name);
287}
288
290 const char *ExtraCode, raw_ostream &O) {
291 // Does this asm operand have a single letter operand modifier?
292 if (ExtraCode && ExtraCode[0]) {
293 if (ExtraCode[1] != 0) return true; // Unknown modifier.
294
295 switch (ExtraCode[0]) {
296 default:
297 // See if this is a generic print operand
298 return AsmPrinter::PrintAsmOperand(MI, OpNum, ExtraCode, O);
299 case 'P': // Print a VFP double precision register.
300 case 'q': // Print a NEON quad precision register.
301 printOperand(MI, OpNum, O);
302 return false;
303 case 'y': // Print a VFP single precision register as indexed double.
304 if (MI->getOperand(OpNum).isReg()) {
305 MCRegister Reg = MI->getOperand(OpNum).getReg().asMCReg();
306 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
307 // Find the 'd' register that has this 's' register as a sub-register,
308 // and determine the lane number.
309 for (MCPhysReg SR : TRI->superregs(Reg)) {
310 if (!ARM::DPRRegClass.contains(SR))
311 continue;
312 bool Lane0 = TRI->getSubReg(SR, ARM::ssub_0) == Reg;
313 O << ARMInstPrinter::getRegisterName(SR) << (Lane0 ? "[0]" : "[1]");
314 return false;
315 }
316 }
317 return true;
318 case 'B': // Bitwise inverse of integer or symbol without a preceding #.
319 if (!MI->getOperand(OpNum).isImm())
320 return true;
321 O << ~(MI->getOperand(OpNum).getImm());
322 return false;
323 case 'L': // The low 16 bits of an immediate constant.
324 if (!MI->getOperand(OpNum).isImm())
325 return true;
326 O << (MI->getOperand(OpNum).getImm() & 0xffff);
327 return false;
328 case 'M': { // A register range suitable for LDM/STM.
329 if (!MI->getOperand(OpNum).isReg())
330 return true;
331 const MachineOperand &MO = MI->getOperand(OpNum);
332 Register RegBegin = MO.getReg();
333 // This takes advantage of the 2 operand-ness of ldm/stm and that we've
334 // already got the operands in registers that are operands to the
335 // inline asm statement.
336 O << "{";
337 if (ARM::GPRPairRegClass.contains(RegBegin)) {
338 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
339 Register Reg0 = TRI->getSubReg(RegBegin, ARM::gsub_0);
340 O << ARMInstPrinter::getRegisterName(Reg0) << ", ";
341 RegBegin = TRI->getSubReg(RegBegin, ARM::gsub_1);
342 }
343 O << ARMInstPrinter::getRegisterName(RegBegin);
344
345 // FIXME: The register allocator not only may not have given us the
346 // registers in sequence, but may not be in ascending registers. This
347 // will require changes in the register allocator that'll need to be
348 // propagated down here if the operands change.
349 unsigned RegOps = OpNum + 1;
350 while (MI->getOperand(RegOps).isReg()) {
351 O << ", "
352 << ARMInstPrinter::getRegisterName(MI->getOperand(RegOps).getReg());
353 RegOps++;
354 }
355
356 O << "}";
357
358 return false;
359 }
360 case 'R': // The most significant register of a pair.
361 case 'Q': { // The least significant register of a pair.
362 if (OpNum == 0)
363 return true;
364 const MachineOperand &FlagsOP = MI->getOperand(OpNum - 1);
365 if (!FlagsOP.isImm())
366 return true;
367 InlineAsm::Flag F(FlagsOP.getImm());
368
369 // This operand may not be the one that actually provides the register. If
370 // it's tied to a previous one then we should refer instead to that one
371 // for registers and their classes.
372 unsigned TiedIdx;
373 if (F.isUseOperandTiedToDef(TiedIdx)) {
374 for (OpNum = InlineAsm::MIOp_FirstOperand; TiedIdx; --TiedIdx) {
375 unsigned OpFlags = MI->getOperand(OpNum).getImm();
376 const InlineAsm::Flag F(OpFlags);
377 OpNum += F.getNumOperandRegisters() + 1;
378 }
379 F = InlineAsm::Flag(MI->getOperand(OpNum).getImm());
380
381 // Later code expects OpNum to be pointing at the register rather than
382 // the flags.
383 OpNum += 1;
384 }
385
386 const unsigned NumVals = F.getNumOperandRegisters();
387 unsigned RC;
388 bool FirstHalf;
389 const ARMBaseTargetMachine &ATM =
390 static_cast<const ARMBaseTargetMachine &>(TM);
391
392 // 'Q' should correspond to the low order register and 'R' to the high
393 // order register. Whether this corresponds to the upper or lower half
394 // depends on the endianess mode.
395 if (ExtraCode[0] == 'Q')
396 FirstHalf = ATM.isLittleEndian();
397 else
398 // ExtraCode[0] == 'R'.
399 FirstHalf = !ATM.isLittleEndian();
400 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
401 if (F.hasRegClassConstraint(RC) &&
402 ARM::GPRPairRegClass.hasSubClassEq(TRI->getRegClass(RC))) {
403 if (NumVals != 1)
404 return true;
405 const MachineOperand &MO = MI->getOperand(OpNum);
406 if (!MO.isReg())
407 return true;
408 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
409 Register Reg =
410 TRI->getSubReg(MO.getReg(), FirstHalf ? ARM::gsub_0 : ARM::gsub_1);
412 return false;
413 }
414 if (NumVals != 2)
415 return true;
416 unsigned RegOp = FirstHalf ? OpNum : OpNum + 1;
417 if (RegOp >= MI->getNumOperands())
418 return true;
419 const MachineOperand &MO = MI->getOperand(RegOp);
420 if (!MO.isReg())
421 return true;
422 Register Reg = MO.getReg();
424 return false;
425 }
426
427 case 'e': // The low doubleword register of a NEON quad register.
428 case 'f': { // The high doubleword register of a NEON quad register.
429 if (!MI->getOperand(OpNum).isReg())
430 return true;
431 Register Reg = MI->getOperand(OpNum).getReg();
432 if (!ARM::QPRRegClass.contains(Reg))
433 return true;
434 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
436 TRI->getSubReg(Reg, ExtraCode[0] == 'e' ? ARM::dsub_0 : ARM::dsub_1);
438 return false;
439 }
440
441 // This modifier is not yet supported.
442 case 'h': // A range of VFP/NEON registers suitable for VLD1/VST1.
443 return true;
444 case 'H': { // The highest-numbered register of a pair.
445 const MachineOperand &MO = MI->getOperand(OpNum);
446 if (!MO.isReg())
447 return true;
448 const MachineFunction &MF = *MI->getParent()->getParent();
449 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
450 Register Reg = MO.getReg();
451 if(!ARM::GPRPairRegClass.contains(Reg))
452 return false;
453 Reg = TRI->getSubReg(Reg, ARM::gsub_1);
455 return false;
456 }
457 }
458 }
459
460 printOperand(MI, OpNum, O);
461 return false;
462}
463
465 unsigned OpNum, const char *ExtraCode,
466 raw_ostream &O) {
467 // Does this asm operand have a single letter operand modifier?
468 if (ExtraCode && ExtraCode[0]) {
469 if (ExtraCode[1] != 0) return true; // Unknown modifier.
470
471 switch (ExtraCode[0]) {
472 case 'A': // A memory operand for a VLD1/VST1 instruction.
473 default: return true; // Unknown modifier.
474 case 'm': // The base register of a memory operand.
475 if (!MI->getOperand(OpNum).isReg())
476 return true;
477 O << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg());
478 return false;
479 }
480 }
481
482 const MachineOperand &MO = MI->getOperand(OpNum);
483 assert(MO.isReg() && "unexpected inline asm memory operand");
484 O << "[" << ARMInstPrinter::getRegisterName(MO.getReg()) << "]";
485 return false;
486}
487
488static bool isThumb(const MCSubtargetInfo& STI) {
489 return STI.hasFeature(ARM::ModeThumb);
490}
491
493 const MCSubtargetInfo *EndInfo) const {
494 // If either end mode is unknown (EndInfo == NULL) or different than
495 // the start mode, then restore the start mode.
496 const bool WasThumb = isThumb(StartInfo);
497 if (!EndInfo || WasThumb != isThumb(*EndInfo)) {
498 auto &TS =
499 static_cast<ARMTargetStreamer &>(*OutStreamer->getTargetStreamer());
500 if (WasThumb)
501 TS.emitCode16();
502 else
503 TS.emitCode32();
504 }
505}
506
508 const Triple &TT = TM.getTargetTriple();
509 auto &TS =
510 static_cast<ARMTargetStreamer &>(*OutStreamer->getTargetStreamer());
511 // Use unified assembler syntax.
513
514 // Emit ARM Build Attributes
515 if (TT.isOSBinFormatELF())
516 emitAttributes();
517
518 // Use the triple's architecture and subarchitecture to determine
519 // if we're thumb for the purposes of the top level code16 state.
520 if (!M.getModuleInlineAsm().empty() && TT.isThumb())
521 TS.emitCode16();
522}
523
524static void
527 // L_foo$stub:
528 OutStreamer.emitLabel(StubLabel);
529 // .indirect_symbol _foo
531
532 if (MCSym.getInt())
533 // External to current translation unit.
534 OutStreamer.emitIntValue(0, 4/*size*/);
535 else
536 // Internal to current translation unit.
537 //
538 // When we place the LSDA into the TEXT section, the type info
539 // pointers need to be indirect and pc-rel. We accomplish this by
540 // using NLPs; however, sometimes the types are local to the file.
541 // We need to fill in the value for the NLP in those cases.
542 OutStreamer.emitValue(
543 MCSymbolRefExpr::create(MCSym.getPointer(), OutStreamer.getContext()),
544 4 /*size*/);
545}
546
547
549 const Triple &TT = TM.getTargetTriple();
550 if (TT.isOSBinFormatMachO()) {
551 // All darwin targets use mach-o.
552 const TargetLoweringObjectFileMachO &TLOFMacho =
554 MachineModuleInfoMachO &MMIMacho =
555 MMI->getObjFileInfo<MachineModuleInfoMachO>();
556
557 // Output non-lazy-pointers for external and common global variables.
559
560 if (!Stubs.empty()) {
561 // Switch with ".non_lazy_symbol_pointer" directive.
562 OutStreamer->switchSection(TLOFMacho.getNonLazySymbolPointerSection());
564
565 for (auto &Stub : Stubs)
566 emitNonLazySymbolPointer(*OutStreamer, Stub.first, Stub.second);
567
568 Stubs.clear();
569 OutStreamer->addBlankLine();
570 }
571
572 Stubs = MMIMacho.GetThreadLocalGVStubList();
573 if (!Stubs.empty()) {
574 // Switch with ".non_lazy_symbol_pointer" directive.
575 OutStreamer->switchSection(TLOFMacho.getThreadLocalPointerSection());
577
578 for (auto &Stub : Stubs)
579 emitNonLazySymbolPointer(*OutStreamer, Stub.first, Stub.second);
580
581 Stubs.clear();
582 OutStreamer->addBlankLine();
583 }
584
585 // Funny Darwin hack: This flag tells the linker that no global symbols
586 // contain code that falls through to other global symbols (e.g. the obvious
587 // implementation of multiple entry points). If this doesn't occur, the
588 // linker can safely perform dead code stripping. Since LLVM never
589 // generates code that does this, it is always safe to set.
590 OutStreamer->emitSubsectionsViaSymbols();
591 }
592
593 // The last attribute to be emitted is ABI_optimization_goals
594 MCTargetStreamer &TS = *OutStreamer->getTargetStreamer();
595 ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
596
597 if (OptimizationGoals > 0 &&
598 (Subtarget->isTargetAEABI() || Subtarget->isTargetGNUAEABI() ||
599 Subtarget->isTargetMuslAEABI()))
601 OptimizationGoals = -1;
602
604}
605
606//===----------------------------------------------------------------------===//
607// Helper routines for emitStartOfAsmFile() and emitEndOfAsmFile()
608// FIXME:
609// The following seem like one-off assembler flags, but they actually need
610// to appear in the .ARM.attributes section in ELF.
611// Instead of subclassing the MCELFStreamer, we do the work here.
612
613// Returns true if all function definitions have the same function attribute
614// value. It also returns true when the module has no functions.
617 return !any_of(M, [&](const Function &F) {
618 if (F.isDeclaration())
619 return false;
620 return F.getFnAttribute(Attr).getValueAsString() != Value;
621 });
622}
623// Returns true if all functions definitions have the same denormal mode.
624// It also returns true when the module has no functions.
627 return !any_of(M, [&](const Function &F) {
628 if (F.isDeclaration())
629 return false;
630 StringRef AttrVal = F.getFnAttribute(Attr).getValueAsString();
631 return parseDenormalFPAttribute(AttrVal) != Value;
632 });
633}
634
635// Returns true if all functions have different denormal modes.
637 auto F = M.functions().begin();
638 auto E = M.functions().end();
639 if (F == E)
640 return false;
641 DenormalMode Value = F->getDenormalModeRaw();
642 ++F;
643 return std::any_of(F, E, [&](const Function &F) {
644 return !F.isDeclaration() && F.getDenormalModeRaw() != Value;
645 });
646}
647
648void ARMAsmPrinter::emitAttributes() {
649 MCTargetStreamer &TS = *OutStreamer->getTargetStreamer();
650 ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
651
653
654 ATS.switchVendor("aeabi");
655
656 // Compute ARM ELF Attributes based on the default subtarget that
657 // we'd have constructed. The existing ARM behavior isn't LTO clean
658 // anyhow.
659 // FIXME: For ifunc related functions we could iterate over and look
660 // for a feature string that doesn't match the default one.
661 const Triple &TT = TM.getTargetTriple();
662 StringRef CPU = TM.getTargetCPU();
663 StringRef FS = TM.getTargetFeatureString();
664 std::string ArchFS = ARM_MC::ParseARMTriple(TT, CPU);
665 if (!FS.empty()) {
666 if (!ArchFS.empty())
667 ArchFS = (Twine(ArchFS) + "," + FS).str();
668 else
669 ArchFS = std::string(FS);
670 }
671 const ARMBaseTargetMachine &ATM =
672 static_cast<const ARMBaseTargetMachine &>(TM);
673 const ARMSubtarget STI(TT, std::string(CPU), ArchFS, ATM,
674 ATM.isLittleEndian());
675
676 // Emit build attributes for the available hardware.
677 ATS.emitTargetAttributes(STI);
678
679 // RW data addressing.
680 if (isPositionIndependent()) {
683 } else if (STI.isRWPI()) {
684 // RWPI specific attributes.
687 }
688
689 // RO data addressing.
690 if (isPositionIndependent() || STI.isROPI()) {
693 }
694
695 // GOT use.
696 if (isPositionIndependent()) {
699 } else {
702 }
703
704 // Set FP Denormals.
705 if (checkDenormalAttributeConsistency(*MMI->getModule(), "denormal-fp-math",
709 else if (checkDenormalAttributeConsistency(*MMI->getModule(),
710 "denormal-fp-math",
714 else if (checkDenormalAttributeInconsistency(*MMI->getModule()) ||
716 *MMI->getModule(), "denormal-fp-math", DenormalMode::getIEEE()))
719 else {
720 if (!STI.hasVFP2Base()) {
721 // When the target doesn't have an FPU (by design or
722 // intention), the assumptions made on the software support
723 // mirror that of the equivalent hardware support *if it
724 // existed*. For v7 and better we indicate that denormals are
725 // flushed preserving sign, and for V6 we indicate that
726 // denormals are flushed to positive zero.
727 if (STI.hasV7Ops())
730 } else if (STI.hasVFP3Base()) {
731 // In VFPv4, VFPv4U, VFPv3, or VFPv3U, it is preserved. That is,
732 // the sign bit of the zero matches the sign bit of the input or
733 // result that is being flushed to zero.
736 }
737 // For VFPv2 implementations it is implementation defined as
738 // to whether denormals are flushed to positive zero or to
739 // whatever the sign of zero is (ARM v7AR ARM 2.7.5). Historically
740 // LLVM has chosen to flush this to positive zero (most likely for
741 // GCC compatibility), so that's the chosen value here (the
742 // absence of its emission implies zero).
743 }
744
745 // Set FP exceptions and rounding
746 if (checkFunctionsAttributeConsistency(*MMI->getModule(),
747 "no-trapping-math", "true") ||
748 TM.Options.NoTrappingFPMath)
751 else {
753
754 // If the user has permitted this code to choose the IEEE 754
755 // rounding at run-time, emit the rounding attribute.
756 if (TM.Options.HonorSignDependentRoundingFPMathOption)
758 }
759
760 // TM.Options.NoInfsFPMath && TM.Options.NoNaNsFPMath is the
761 // equivalent of GCC's -ffinite-math-only flag.
762 if (TM.Options.NoInfsFPMath && TM.Options.NoNaNsFPMath)
765 else
768
769 // FIXME: add more flags to ARMBuildAttributes.h
770 // 8-bytes alignment stuff.
773
774 // Hard float. Use both S and D registers and conform to AAPCS-VFP.
775 if (getTM().isAAPCS_ABI() && TM.Options.FloatABIType == FloatABI::Hard)
777
778 // FIXME: To support emitting this build attribute as GCC does, the
779 // -mfp16-format option and associated plumbing must be
780 // supported. For now the __fp16 type is exposed by default, so this
781 // attribute should be emitted with value 1.
784
785 if (const Module *SourceModule = MMI->getModule()) {
786 // ABI_PCS_wchar_t to indicate wchar_t width
787 // FIXME: There is no way to emit value 0 (wchar_t prohibited).
788 if (auto WCharWidthValue = mdconst::extract_or_null<ConstantInt>(
789 SourceModule->getModuleFlag("wchar_size"))) {
790 int WCharWidth = WCharWidthValue->getZExtValue();
791 assert((WCharWidth == 2 || WCharWidth == 4) &&
792 "wchar_t width must be 2 or 4 bytes");
794 }
795
796 // ABI_enum_size to indicate enum width
797 // FIXME: There is no way to emit value 0 (enums prohibited) or value 3
798 // (all enums contain a value needing 32 bits to encode).
799 if (auto EnumWidthValue = mdconst::extract_or_null<ConstantInt>(
800 SourceModule->getModuleFlag("min_enum_size"))) {
801 int EnumWidth = EnumWidthValue->getZExtValue();
802 assert((EnumWidth == 1 || EnumWidth == 4) &&
803 "Minimum enum width must be 1 or 4 bytes");
804 int EnumBuildAttr = EnumWidth == 1 ? 1 : 2;
806 }
807
809 SourceModule->getModuleFlag("sign-return-address"));
810 if (PACValue && PACValue->isOne()) {
811 // If "+pacbti" is used as an architecture extension,
812 // Tag_PAC_extension is emitted in
813 // ARMTargetStreamer::emitTargetAttributes().
814 if (!STI.hasPACBTI()) {
817 }
819 }
820
822 SourceModule->getModuleFlag("branch-target-enforcement"));
823 if (BTIValue && BTIValue->isOne()) {
824 // If "+pacbti" is used as an architecture extension,
825 // Tag_BTI_extension is emitted in
826 // ARMTargetStreamer::emitTargetAttributes().
827 if (!STI.hasPACBTI()) {
830 }
832 }
833 }
834
835 // We currently do not support using R9 as the TLS pointer.
836 if (STI.isRWPI())
839 else if (STI.isR9Reserved())
842 else
845}
846
847//===----------------------------------------------------------------------===//
848
849static MCSymbol *getBFLabel(StringRef Prefix, unsigned FunctionNumber,
850 unsigned LabelId, MCContext &Ctx) {
851
852 MCSymbol *Label = Ctx.getOrCreateSymbol(Twine(Prefix)
853 + "BF" + Twine(FunctionNumber) + "_" + Twine(LabelId));
854 return Label;
855}
856
857static MCSymbol *getPICLabel(StringRef Prefix, unsigned FunctionNumber,
858 unsigned LabelId, MCContext &Ctx) {
859
860 MCSymbol *Label = Ctx.getOrCreateSymbol(Twine(Prefix)
861 + "PC" + Twine(FunctionNumber) + "_" + Twine(LabelId));
862 return Label;
863}
864
866 switch (Modifier) {
868 return ARM::S_None;
869 case ARMCP::TLSGD:
870 return ARM::S_TLSGD;
871 case ARMCP::TPOFF:
872 return ARM::S_TPOFF;
873 case ARMCP::GOTTPOFF:
874 return ARM::S_GOTTPOFF;
875 case ARMCP::SBREL:
876 return ARM::S_SBREL;
877 case ARMCP::GOT_PREL:
878 return ARM::S_GOT_PREL;
879 case ARMCP::SECREL:
880 return ARM::S_COFF_SECREL;
881 }
882 llvm_unreachable("Invalid ARMCPModifier!");
883}
884
885MCSymbol *ARMAsmPrinter::GetARMGVSymbol(const GlobalValue *GV,
886 unsigned char TargetFlags) {
887 if (Subtarget->isTargetMachO()) {
888 bool IsIndirect =
889 (TargetFlags & ARMII::MO_NONLAZY) && Subtarget->isGVIndirectSymbol(GV);
890
891 if (!IsIndirect)
892 return getSymbol(GV);
893
894 // FIXME: Remove this when Darwin transition to @GOT like syntax.
895 MCSymbol *MCSym = getSymbolWithGlobalValueBase(GV, "$non_lazy_ptr");
896 MachineModuleInfoMachO &MMIMachO =
897 MMI->getObjFileInfo<MachineModuleInfoMachO>();
899 GV->isThreadLocal() ? MMIMachO.getThreadLocalGVStubEntry(MCSym)
900 : MMIMachO.getGVStubEntry(MCSym);
901
902 if (!StubSym.getPointer())
904 !GV->hasInternalLinkage());
905 return MCSym;
906 } else if (Subtarget->isTargetCOFF()) {
907 assert(Subtarget->isTargetWindows() &&
908 "Windows is the only supported COFF target");
909
910 bool IsIndirect =
911 (TargetFlags & (ARMII::MO_DLLIMPORT | ARMII::MO_COFFSTUB));
912 if (!IsIndirect)
913 return getSymbol(GV);
914
915 SmallString<128> Name;
916 if (TargetFlags & ARMII::MO_DLLIMPORT)
917 Name = "__imp_";
918 else if (TargetFlags & ARMII::MO_COFFSTUB)
919 Name = ".refptr.";
920 getNameWithPrefix(Name, GV);
921
922 MCSymbol *MCSym = OutContext.getOrCreateSymbol(Name);
923
924 if (TargetFlags & ARMII::MO_COFFSTUB) {
925 MachineModuleInfoCOFF &MMICOFF =
926 MMI->getObjFileInfo<MachineModuleInfoCOFF>();
928 MMICOFF.getGVStubEntry(MCSym);
929
930 if (!StubSym.getPointer())
932 }
933
934 return MCSym;
935 } else if (Subtarget->isTargetELF()) {
936 return getSymbolPreferLocal(*GV);
937 }
938 llvm_unreachable("unexpected target");
939}
940
943 const DataLayout &DL = getDataLayout();
944 int Size = DL.getTypeAllocSize(MCPV->getType());
945
946 ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV);
947
948 if (ACPV->isPromotedGlobal()) {
949 // This constant pool entry is actually a global whose storage has been
950 // promoted into the constant pool. This global may be referenced still
951 // by debug information, and due to the way AsmPrinter is set up, the debug
952 // info is immutable by the time we decide to promote globals to constant
953 // pools. Because of this, we need to ensure we emit a symbol for the global
954 // with private linkage (the default) so debug info can refer to it.
955 //
956 // However, if this global is promoted into several functions we must ensure
957 // we don't try and emit duplicate symbols!
958 auto *ACPC = cast<ARMConstantPoolConstant>(ACPV);
959 for (const auto *GV : ACPC->promotedGlobals()) {
960 if (!EmittedPromotedGlobalLabels.count(GV)) {
961 MCSymbol *GVSym = getSymbol(GV);
962 OutStreamer->emitLabel(GVSym);
963 EmittedPromotedGlobalLabels.insert(GV);
964 }
965 }
966 return emitGlobalConstant(DL, ACPC->getPromotedGlobalInit());
967 }
968
969 MCSymbol *MCSym;
970 if (ACPV->isLSDA()) {
971 MCSym = getMBBExceptionSym(MF->front());
972 } else if (ACPV->isBlockAddress()) {
973 const BlockAddress *BA =
974 cast<ARMConstantPoolConstant>(ACPV)->getBlockAddress();
975 MCSym = GetBlockAddressSymbol(BA);
976 } else if (ACPV->isGlobalValue()) {
977 const GlobalValue *GV = cast<ARMConstantPoolConstant>(ACPV)->getGV();
978
979 // On Darwin, const-pool entries may get the "FOO$non_lazy_ptr" mangling, so
980 // flag the global as MO_NONLAZY.
981 unsigned char TF = Subtarget->isTargetMachO() ? ARMII::MO_NONLAZY : 0;
982 MCSym = GetARMGVSymbol(GV, TF);
983 } else if (ACPV->isMachineBasicBlock()) {
984 const MachineBasicBlock *MBB = cast<ARMConstantPoolMBB>(ACPV)->getMBB();
985 MCSym = MBB->getSymbol();
986 } else {
987 assert(ACPV->isExtSymbol() && "unrecognized constant pool value");
988 auto Sym = cast<ARMConstantPoolSymbol>(ACPV)->getSymbol();
989 MCSym = GetExternalSymbolSymbol(Sym);
990 }
991
992 // Create an MCSymbol for the reference.
993 const MCExpr *Expr = MCSymbolRefExpr::create(
995
996 if (ACPV->getPCAdjustment()) {
997 MCSymbol *PCLabel =
998 getPICLabel(DL.getPrivateGlobalPrefix(), getFunctionNumber(),
999 ACPV->getLabelId(), OutContext);
1000 const MCExpr *PCRelExpr = MCSymbolRefExpr::create(PCLabel, OutContext);
1001 PCRelExpr =
1002 MCBinaryExpr::createAdd(PCRelExpr,
1004 OutContext),
1005 OutContext);
1006 if (ACPV->mustAddCurrentAddress()) {
1007 // We want "(<expr> - .)", but MC doesn't have a concept of the '.'
1008 // label, so just emit a local label end reference that instead.
1009 MCSymbol *DotSym = OutContext.createTempSymbol();
1010 OutStreamer->emitLabel(DotSym);
1011 const MCExpr *DotExpr = MCSymbolRefExpr::create(DotSym, OutContext);
1012 PCRelExpr = MCBinaryExpr::createSub(PCRelExpr, DotExpr, OutContext);
1013 }
1014 Expr = MCBinaryExpr::createSub(Expr, PCRelExpr, OutContext);
1015 }
1016 OutStreamer->emitValue(Expr, Size);
1017}
1018
1020 const MachineOperand &MO1 = MI->getOperand(1);
1021 unsigned JTI = MO1.getIndex();
1022
1023 // Make sure the Thumb jump table is 4-byte aligned. This will be a nop for
1024 // ARM mode tables.
1025 emitAlignment(Align(4));
1026
1027 // Emit a label for the jump table.
1028 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel(JTI);
1029 OutStreamer->emitLabel(JTISymbol);
1030
1031 // Mark the jump table as data-in-code.
1032 OutStreamer->emitDataRegion(MCDR_DataRegionJT32);
1033
1034 // Emit each entry of the table.
1035 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
1036 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
1037 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
1038
1039 for (MachineBasicBlock *MBB : JTBBs) {
1040 // Construct an MCExpr for the entry. We want a value of the form:
1041 // (BasicBlockAddr - TableBeginAddr)
1042 //
1043 // For example, a table with entries jumping to basic blocks BB0 and BB1
1044 // would look like:
1045 // LJTI_0_0:
1046 // .word (LBB0 - LJTI_0_0)
1047 // .word (LBB1 - LJTI_0_0)
1048 const MCExpr *Expr = MCSymbolRefExpr::create(MBB->getSymbol(), OutContext);
1049
1050 if (isPositionIndependent() || Subtarget->isROPI())
1051 Expr = MCBinaryExpr::createSub(Expr, MCSymbolRefExpr::create(JTISymbol,
1052 OutContext),
1053 OutContext);
1054 // If we're generating a table of Thumb addresses in static relocation
1055 // model, we need to add one to keep interworking correctly.
1056 else if (AFI->isThumbFunction())
1058 OutContext);
1059 OutStreamer->emitValue(Expr, 4);
1060 }
1061 // Mark the end of jump table data-in-code region.
1062 OutStreamer->emitDataRegion(MCDR_DataRegionEnd);
1063}
1064
1066 const MachineOperand &MO1 = MI->getOperand(1);
1067 unsigned JTI = MO1.getIndex();
1068
1069 // Make sure the Thumb jump table is 4-byte aligned. This will be a nop for
1070 // ARM mode tables.
1071 emitAlignment(Align(4));
1072
1073 // Emit a label for the jump table.
1074 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel(JTI);
1075 OutStreamer->emitLabel(JTISymbol);
1076
1077 // Emit each entry of the table.
1078 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
1079 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
1080 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
1081
1082 for (MachineBasicBlock *MBB : JTBBs) {
1083 const MCExpr *MBBSymbolExpr = MCSymbolRefExpr::create(MBB->getSymbol(),
1084 OutContext);
1085 // If this isn't a TBB or TBH, the entries are direct branch instructions.
1087 .addExpr(MBBSymbolExpr)
1088 .addImm(ARMCC::AL)
1089 .addReg(0));
1090 }
1091}
1092
1094 unsigned OffsetWidth) {
1095 assert((OffsetWidth == 1 || OffsetWidth == 2) && "invalid tbb/tbh width");
1096 const MachineOperand &MO1 = MI->getOperand(1);
1097 unsigned JTI = MO1.getIndex();
1098
1099 if (Subtarget->isThumb1Only())
1100 emitAlignment(Align(4));
1101
1102 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel(JTI);
1103 OutStreamer->emitLabel(JTISymbol);
1104
1105 // Emit each entry of the table.
1106 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
1107 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
1108 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
1109
1110 // Mark the jump table as data-in-code.
1111 OutStreamer->emitDataRegion(OffsetWidth == 1 ? MCDR_DataRegionJT8
1113
1114 for (auto *MBB : JTBBs) {
1115 const MCExpr *MBBSymbolExpr = MCSymbolRefExpr::create(MBB->getSymbol(),
1116 OutContext);
1117 // Otherwise it's an offset from the dispatch instruction. Construct an
1118 // MCExpr for the entry. We want a value of the form:
1119 // (BasicBlockAddr - TBBInstAddr + 4) / 2
1120 //
1121 // For example, a TBB table with entries jumping to basic blocks BB0 and BB1
1122 // would look like:
1123 // LJTI_0_0:
1124 // .byte (LBB0 - (LCPI0_0 + 4)) / 2
1125 // .byte (LBB1 - (LCPI0_0 + 4)) / 2
1126 // where LCPI0_0 is a label defined just before the TBB instruction using
1127 // this table.
1128 MCSymbol *TBInstPC = GetCPISymbol(MI->getOperand(0).getImm());
1129 const MCExpr *Expr = MCBinaryExpr::createAdd(
1132 Expr = MCBinaryExpr::createSub(MBBSymbolExpr, Expr, OutContext);
1134 OutContext);
1135 OutStreamer->emitValue(Expr, OffsetWidth);
1136 }
1137 // Mark the end of jump table data-in-code region. 32-bit offsets use
1138 // actual branch instructions here, so we don't mark those as a data-region
1139 // at all.
1140 OutStreamer->emitDataRegion(MCDR_DataRegionEnd);
1141
1142 // Make sure the next instruction is 2-byte aligned.
1143 emitAlignment(Align(2));
1144}
1145
1146std::tuple<const MCSymbol *, uint64_t, const MCSymbol *,
1149 const MachineInstr *BranchInstr,
1150 const MCSymbol *BranchLabel) const {
1152 const MCSymbol *BaseLabel;
1153 uint64_t BaseOffset = 0;
1154 switch (BranchInstr->getOpcode()) {
1155 case ARM::BR_JTadd:
1156 case ARM::BR_JTr:
1157 case ARM::tBR_JTr:
1158 // Word relative to the jump table address.
1160 BaseLabel = GetARMJTIPICJumpTableLabel(JTI);
1161 break;
1162 case ARM::tTBH_JT:
1163 case ARM::t2TBH_JT:
1164 // half-word shifted left, relative to *after* the branch instruction.
1166 BranchLabel = GetCPISymbol(BranchInstr->getOperand(3).getImm());
1167 BaseLabel = BranchLabel;
1168 BaseOffset = 4;
1169 break;
1170 case ARM::tTBB_JT:
1171 case ARM::t2TBB_JT:
1172 // byte shifted left, relative to *after* the branch instruction.
1174 BranchLabel = GetCPISymbol(BranchInstr->getOperand(3).getImm());
1175 BaseLabel = BranchLabel;
1176 BaseOffset = 4;
1177 break;
1178 case ARM::t2BR_JT:
1179 // Direct jump.
1180 BaseLabel = nullptr;
1182 break;
1183 default:
1184 llvm_unreachable("Unknown jump table instruction");
1185 }
1186
1187 return std::make_tuple(BaseLabel, BaseOffset, BranchLabel, EntrySize);
1188}
1189
1190void ARMAsmPrinter::EmitUnwindingInstruction(const MachineInstr *MI) {
1192 "Only instruction which are involved into frame setup code are allowed");
1193
1194 MCTargetStreamer &TS = *OutStreamer->getTargetStreamer();
1195 ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
1196 const MachineFunction &MF = *MI->getParent()->getParent();
1197 const TargetRegisterInfo *TargetRegInfo =
1199 const MachineRegisterInfo &MachineRegInfo = MF.getRegInfo();
1200
1201 Register FramePtr = TargetRegInfo->getFrameRegister(MF);
1202 unsigned Opc = MI->getOpcode();
1203 unsigned SrcReg, DstReg;
1204
1205 switch (Opc) {
1206 case ARM::tPUSH:
1207 // special case: tPUSH does not have src/dst regs.
1208 SrcReg = DstReg = ARM::SP;
1209 break;
1210 case ARM::tLDRpci:
1211 case ARM::t2MOVi16:
1212 case ARM::t2MOVTi16:
1213 case ARM::tMOVi8:
1214 case ARM::tADDi8:
1215 case ARM::tLSLri:
1216 // special cases:
1217 // 1) for Thumb1 code we sometimes materialize the constant via constpool
1218 // load.
1219 // 2) for Thumb1 execute only code we materialize the constant via the
1220 // following pattern:
1221 // movs r3, #:upper8_15:<const>
1222 // lsls r3, #8
1223 // adds r3, #:upper0_7:<const>
1224 // lsls r3, #8
1225 // adds r3, #:lower8_15:<const>
1226 // lsls r3, #8
1227 // adds r3, #:lower0_7:<const>
1228 // So we need to special-case MOVS, ADDS and LSLS, and keep track of
1229 // where we are in the sequence with the simplest of state machines.
1230 // 3) for Thumb2 execute only code we materialize the constant via
1231 // immediate constants in 2 separate instructions (MOVW/MOVT).
1232 SrcReg = ~0U;
1233 DstReg = MI->getOperand(0).getReg();
1234 break;
1235 case ARM::VMRS:
1236 SrcReg = ARM::FPSCR;
1237 DstReg = MI->getOperand(0).getReg();
1238 break;
1239 case ARM::VMRS_FPEXC:
1240 SrcReg = ARM::FPEXC;
1241 DstReg = MI->getOperand(0).getReg();
1242 break;
1243 default:
1244 SrcReg = MI->getOperand(1).getReg();
1245 DstReg = MI->getOperand(0).getReg();
1246 break;
1247 }
1248
1249 // Try to figure out the unwinding opcode out of src / dst regs.
1250 if (MI->mayStore()) {
1251 // Register saves.
1252 assert(DstReg == ARM::SP &&
1253 "Only stack pointer as a destination reg is supported");
1254
1256 // Skip src & dst reg, and pred ops.
1257 unsigned StartOp = 2 + 2;
1258 // Use all the operands.
1259 unsigned NumOffset = 0;
1260 // Amount of SP adjustment folded into a push, before the
1261 // registers are stored (pad at higher addresses).
1262 unsigned PadBefore = 0;
1263 // Amount of SP adjustment folded into a push, after the
1264 // registers are stored (pad at lower addresses).
1265 unsigned PadAfter = 0;
1266
1267 switch (Opc) {
1268 default:
1269 MI->print(errs());
1270 llvm_unreachable("Unsupported opcode for unwinding information");
1271 case ARM::tPUSH:
1272 // Special case here: no src & dst reg, but two extra imp ops.
1273 StartOp = 2; NumOffset = 2;
1274 [[fallthrough]];
1275 case ARM::STMDB_UPD:
1276 case ARM::t2STMDB_UPD:
1277 case ARM::VSTMDDB_UPD:
1278 assert(SrcReg == ARM::SP &&
1279 "Only stack pointer as a source reg is supported");
1280 for (unsigned i = StartOp, NumOps = MI->getNumOperands() - NumOffset;
1281 i != NumOps; ++i) {
1282 const MachineOperand &MO = MI->getOperand(i);
1283 // Actually, there should never be any impdef stuff here. Skip it
1284 // temporary to workaround PR11902.
1285 if (MO.isImplicit())
1286 continue;
1287 // Registers, pushed as a part of folding an SP update into the
1288 // push instruction are marked as undef and should not be
1289 // restored when unwinding, because the function can modify the
1290 // corresponding stack slots.
1291 if (MO.isUndef()) {
1292 assert(RegList.empty() &&
1293 "Pad registers must come before restored ones");
1294 unsigned Width =
1295 TargetRegInfo->getRegSizeInBits(MO.getReg(), MachineRegInfo) / 8;
1296 PadAfter += Width;
1297 continue;
1298 }
1299 // Check for registers that are remapped (for a Thumb1 prologue that
1300 // saves high registers).
1301 Register Reg = MO.getReg();
1302 if (unsigned RemappedReg = AFI->EHPrologueRemappedRegs.lookup(Reg))
1303 Reg = RemappedReg;
1304 RegList.push_back(Reg);
1305 }
1306 break;
1307 case ARM::STR_PRE_IMM:
1308 case ARM::STR_PRE_REG:
1309 case ARM::t2STR_PRE:
1310 assert(MI->getOperand(2).getReg() == ARM::SP &&
1311 "Only stack pointer as a source reg is supported");
1312 if (unsigned RemappedReg = AFI->EHPrologueRemappedRegs.lookup(SrcReg))
1313 SrcReg = RemappedReg;
1314
1315 RegList.push_back(SrcReg);
1316 break;
1317 case ARM::t2STRD_PRE:
1318 assert(MI->getOperand(3).getReg() == ARM::SP &&
1319 "Only stack pointer as a source reg is supported");
1320 SrcReg = MI->getOperand(1).getReg();
1321 if (unsigned RemappedReg = AFI->EHPrologueRemappedRegs.lookup(SrcReg))
1322 SrcReg = RemappedReg;
1323 RegList.push_back(SrcReg);
1324 SrcReg = MI->getOperand(2).getReg();
1325 if (unsigned RemappedReg = AFI->EHPrologueRemappedRegs.lookup(SrcReg))
1326 SrcReg = RemappedReg;
1327 RegList.push_back(SrcReg);
1328 PadBefore = -MI->getOperand(4).getImm() - 8;
1329 break;
1330 }
1331 if (MAI->getExceptionHandlingType() == ExceptionHandling::ARM) {
1332 if (PadBefore)
1333 ATS.emitPad(PadBefore);
1334 ATS.emitRegSave(RegList, Opc == ARM::VSTMDDB_UPD);
1335 // Account for the SP adjustment, folded into the push.
1336 if (PadAfter)
1337 ATS.emitPad(PadAfter);
1338 }
1339 } else {
1340 // Changes of stack / frame pointer.
1341 if (SrcReg == ARM::SP) {
1342 int64_t Offset = 0;
1343 switch (Opc) {
1344 default:
1345 MI->print(errs());
1346 llvm_unreachable("Unsupported opcode for unwinding information");
1347 case ARM::tLDRspi:
1348 // Used to restore LR in a prologue which uses it as a temporary, has
1349 // no effect on unwind tables.
1350 return;
1351 case ARM::MOVr:
1352 case ARM::tMOVr:
1353 Offset = 0;
1354 break;
1355 case ARM::ADDri:
1356 case ARM::t2ADDri:
1357 case ARM::t2ADDri12:
1358 case ARM::t2ADDspImm:
1359 case ARM::t2ADDspImm12:
1360 Offset = -MI->getOperand(2).getImm();
1361 break;
1362 case ARM::SUBri:
1363 case ARM::t2SUBri:
1364 case ARM::t2SUBri12:
1365 case ARM::t2SUBspImm:
1366 case ARM::t2SUBspImm12:
1367 Offset = MI->getOperand(2).getImm();
1368 break;
1369 case ARM::tSUBspi:
1370 Offset = MI->getOperand(2).getImm()*4;
1371 break;
1372 case ARM::tADDspi:
1373 case ARM::tADDrSPi:
1374 Offset = -MI->getOperand(2).getImm()*4;
1375 break;
1376 case ARM::tADDhirr:
1377 Offset =
1378 -AFI->EHPrologueOffsetInRegs.lookup(MI->getOperand(2).getReg());
1379 break;
1380 }
1381
1382 if (MAI->getExceptionHandlingType() == ExceptionHandling::ARM) {
1383 if (DstReg == FramePtr && FramePtr != ARM::SP)
1384 // Set-up of the frame pointer. Positive values correspond to "add"
1385 // instruction.
1386 ATS.emitSetFP(FramePtr, ARM::SP, -Offset);
1387 else if (DstReg == ARM::SP) {
1388 // Change of SP by an offset. Positive values correspond to "sub"
1389 // instruction.
1390 ATS.emitPad(Offset);
1391 } else {
1392 // Move of SP to a register. Positive values correspond to an "add"
1393 // instruction.
1394 ATS.emitMovSP(DstReg, -Offset);
1395 }
1396 }
1397 } else if (DstReg == ARM::SP) {
1398 MI->print(errs());
1399 llvm_unreachable("Unsupported opcode for unwinding information");
1400 } else {
1401 int64_t Offset = 0;
1402 switch (Opc) {
1403 case ARM::tMOVr:
1404 // If a Thumb1 function spills r8-r11, we copy the values to low
1405 // registers before pushing them. Record the copy so we can emit the
1406 // correct ".save" later.
1407 AFI->EHPrologueRemappedRegs[DstReg] = SrcReg;
1408 break;
1409 case ARM::VMRS:
1410 case ARM::VMRS_FPEXC:
1411 // If a function spills FPSCR or FPEXC, we copy the values to low
1412 // registers before pushing them. However, we can't issue annotations
1413 // for FP status registers because ".save" requires GPR registers, and
1414 // ".vsave" requires DPR registers, so don't record the copy and simply
1415 // emit annotations for the source registers used for the store.
1416 break;
1417 case ARM::tLDRpci: {
1418 // Grab the constpool index and check, whether it corresponds to
1419 // original or cloned constpool entry.
1420 unsigned CPI = MI->getOperand(1).getIndex();
1421 const MachineConstantPool *MCP = MF.getConstantPool();
1422 if (CPI >= MCP->getConstants().size())
1423 CPI = AFI->getOriginalCPIdx(CPI);
1424 assert(CPI != -1U && "Invalid constpool index");
1425
1426 // Derive the actual offset.
1427 const MachineConstantPoolEntry &CPE = MCP->getConstants()[CPI];
1428 assert(!CPE.isMachineConstantPoolEntry() && "Invalid constpool entry");
1429 Offset = cast<ConstantInt>(CPE.Val.ConstVal)->getSExtValue();
1430 AFI->EHPrologueOffsetInRegs[DstReg] = Offset;
1431 break;
1432 }
1433 case ARM::t2MOVi16:
1434 Offset = MI->getOperand(1).getImm();
1435 AFI->EHPrologueOffsetInRegs[DstReg] = Offset;
1436 break;
1437 case ARM::t2MOVTi16:
1438 Offset = MI->getOperand(2).getImm();
1439 AFI->EHPrologueOffsetInRegs[DstReg] |= (Offset << 16);
1440 break;
1441 case ARM::tMOVi8:
1442 Offset = MI->getOperand(2).getImm();
1443 AFI->EHPrologueOffsetInRegs[DstReg] = Offset;
1444 break;
1445 case ARM::tLSLri:
1446 assert(MI->getOperand(3).getImm() == 8 &&
1447 "The shift amount is not equal to 8");
1448 assert(MI->getOperand(2).getReg() == MI->getOperand(0).getReg() &&
1449 "The source register is not equal to the destination register");
1450 AFI->EHPrologueOffsetInRegs[DstReg] <<= 8;
1451 break;
1452 case ARM::tADDi8:
1453 assert(MI->getOperand(2).getReg() == MI->getOperand(0).getReg() &&
1454 "The source register is not equal to the destination register");
1455 Offset = MI->getOperand(3).getImm();
1456 AFI->EHPrologueOffsetInRegs[DstReg] += Offset;
1457 break;
1458 case ARM::t2PAC:
1459 case ARM::t2PACBTI:
1460 AFI->EHPrologueRemappedRegs[ARM::R12] = ARM::RA_AUTH_CODE;
1461 break;
1462 default:
1463 MI->print(errs());
1464 llvm_unreachable("Unsupported opcode for unwinding information");
1465 }
1466 }
1467 }
1468}
1469
1470// Simple pseudo-instructions have their lowering (with expansion to real
1471// instructions) auto-generated.
1472#include "ARMGenMCPseudoLowering.inc"
1473
1475 ARM_MC::verifyInstructionPredicates(MI->getOpcode(),
1476 getSubtargetInfo().getFeatureBits());
1477
1478 const DataLayout &DL = getDataLayout();
1479 MCTargetStreamer &TS = *OutStreamer->getTargetStreamer();
1480 ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
1481
1482 // If we just ended a constant pool, mark it as such.
1483 if (InConstantPool && MI->getOpcode() != ARM::CONSTPOOL_ENTRY) {
1484 OutStreamer->emitDataRegion(MCDR_DataRegionEnd);
1485 InConstantPool = false;
1486 }
1487
1488 // Emit unwinding stuff for frame-related instructions
1489 if (Subtarget->isTargetEHABICompatible() &&
1490 MI->getFlag(MachineInstr::FrameSetup))
1491 EmitUnwindingInstruction(MI);
1492
1493 // Do any auto-generated pseudo lowerings.
1494 if (MCInst OutInst; lowerPseudoInstExpansion(MI, OutInst)) {
1495 EmitToStreamer(*OutStreamer, OutInst);
1496 return;
1497 }
1498
1499 assert(!convertAddSubFlagsOpcode(MI->getOpcode()) &&
1500 "Pseudo flag setting opcode should be expanded early");
1501
1502 // Check for manual lowerings.
1503 unsigned Opc = MI->getOpcode();
1504 switch (Opc) {
1505 case ARM::t2MOVi32imm: llvm_unreachable("Should be lowered by thumb2it pass");
1506 case ARM::DBG_VALUE: llvm_unreachable("Should be handled by generic printing");
1507 case ARM::LEApcrel:
1508 case ARM::tLEApcrel:
1509 case ARM::t2LEApcrel: {
1510 // FIXME: Need to also handle globals and externals
1511 MCSymbol *CPISymbol = GetCPISymbol(MI->getOperand(1).getIndex());
1512 EmitToStreamer(*OutStreamer, MCInstBuilder(MI->getOpcode() ==
1513 ARM::t2LEApcrel ? ARM::t2ADR
1514 : (MI->getOpcode() == ARM::tLEApcrel ? ARM::tADR
1515 : ARM::ADR))
1516 .addReg(MI->getOperand(0).getReg())
1518 // Add predicate operands.
1519 .addImm(MI->getOperand(2).getImm())
1520 .addReg(MI->getOperand(3).getReg()));
1521 return;
1522 }
1523 case ARM::LEApcrelJT:
1524 case ARM::tLEApcrelJT:
1525 case ARM::t2LEApcrelJT: {
1526 MCSymbol *JTIPICSymbol =
1527 GetARMJTIPICJumpTableLabel(MI->getOperand(1).getIndex());
1528 EmitToStreamer(*OutStreamer, MCInstBuilder(MI->getOpcode() ==
1529 ARM::t2LEApcrelJT ? ARM::t2ADR
1530 : (MI->getOpcode() == ARM::tLEApcrelJT ? ARM::tADR
1531 : ARM::ADR))
1532 .addReg(MI->getOperand(0).getReg())
1534 // Add predicate operands.
1535 .addImm(MI->getOperand(2).getImm())
1536 .addReg(MI->getOperand(3).getReg()));
1537 return;
1538 }
1539 // Darwin call instructions are just normal call instructions with different
1540 // clobber semantics (they clobber R9).
1541 case ARM::BX_CALL: {
1543 .addReg(ARM::LR)
1544 .addReg(ARM::PC)
1545 // Add predicate operands.
1546 .addImm(ARMCC::AL)
1547 .addReg(0)
1548 // Add 's' bit operand (always reg0 for this)
1549 .addReg(0));
1550
1551 assert(Subtarget->hasV4TOps());
1553 .addReg(MI->getOperand(0).getReg()));
1554 return;
1555 }
1556 case ARM::tBX_CALL: {
1557 if (Subtarget->hasV5TOps())
1558 llvm_unreachable("Expected BLX to be selected for v5t+");
1559
1560 // On ARM v4t, when doing a call from thumb mode, we need to ensure
1561 // that the saved lr has its LSB set correctly (the arch doesn't
1562 // have blx).
1563 // So here we generate a bl to a small jump pad that does bx rN.
1564 // The jump pads are emitted after the function body.
1565
1566 Register TReg = MI->getOperand(0).getReg();
1567 MCSymbol *TRegSym = nullptr;
1568 for (std::pair<unsigned, MCSymbol *> &TIP : ThumbIndirectPads) {
1569 if (TIP.first == TReg) {
1570 TRegSym = TIP.second;
1571 break;
1572 }
1573 }
1574
1575 if (!TRegSym) {
1576 TRegSym = OutContext.createTempSymbol();
1577 ThumbIndirectPads.push_back(std::make_pair(TReg, TRegSym));
1578 }
1579
1580 // Create a link-saving branch to the Reg Indirect Jump Pad.
1582 // Predicate comes first here.
1583 .addImm(ARMCC::AL).addReg(0)
1584 .addExpr(MCSymbolRefExpr::create(TRegSym, OutContext)));
1585 return;
1586 }
1587 case ARM::BMOVPCRX_CALL: {
1589 .addReg(ARM::LR)
1590 .addReg(ARM::PC)
1591 // Add predicate operands.
1592 .addImm(ARMCC::AL)
1593 .addReg(0)
1594 // Add 's' bit operand (always reg0 for this)
1595 .addReg(0));
1596
1598 .addReg(ARM::PC)
1599 .addReg(MI->getOperand(0).getReg())
1600 // Add predicate operands.
1602 .addReg(0)
1603 // Add 's' bit operand (always reg0 for this)
1604 .addReg(0));
1605 return;
1606 }
1607 case ARM::BMOVPCB_CALL: {
1609 .addReg(ARM::LR)
1610 .addReg(ARM::PC)
1611 // Add predicate operands.
1612 .addImm(ARMCC::AL)
1613 .addReg(0)
1614 // Add 's' bit operand (always reg0 for this)
1615 .addReg(0));
1616
1617 const MachineOperand &Op = MI->getOperand(0);
1618 const GlobalValue *GV = Op.getGlobal();
1619 const unsigned TF = Op.getTargetFlags();
1620 MCSymbol *GVSym = GetARMGVSymbol(GV, TF);
1621 const MCExpr *GVSymExpr = MCSymbolRefExpr::create(GVSym, OutContext);
1623 .addExpr(GVSymExpr)
1624 // Add predicate operands.
1625 .addImm(ARMCC::AL)
1626 .addReg(0));
1627 return;
1628 }
1629 case ARM::MOVi16_ga_pcrel:
1630 case ARM::t2MOVi16_ga_pcrel: {
1631 MCInst TmpInst;
1632 TmpInst.setOpcode(Opc == ARM::MOVi16_ga_pcrel? ARM::MOVi16 : ARM::t2MOVi16);
1633 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
1634
1635 unsigned TF = MI->getOperand(1).getTargetFlags();
1636 const GlobalValue *GV = MI->getOperand(1).getGlobal();
1637 MCSymbol *GVSym = GetARMGVSymbol(GV, TF);
1638 const MCExpr *GVSymExpr = MCSymbolRefExpr::create(GVSym, OutContext);
1639
1640 MCSymbol *LabelSym =
1641 getPICLabel(DL.getPrivateGlobalPrefix(), getFunctionNumber(),
1642 MI->getOperand(2).getImm(), OutContext);
1643 const MCExpr *LabelSymExpr= MCSymbolRefExpr::create(LabelSym, OutContext);
1644 unsigned PCAdj = (Opc == ARM::MOVi16_ga_pcrel) ? 8 : 4;
1645 const MCExpr *PCRelExpr = ARM::createLower16(
1647 GVSymExpr,
1648 MCBinaryExpr::createAdd(LabelSymExpr,
1650 OutContext),
1651 OutContext),
1652 OutContext);
1653 TmpInst.addOperand(MCOperand::createExpr(PCRelExpr));
1654
1655 // Add predicate operands.
1657 TmpInst.addOperand(MCOperand::createReg(0));
1658 // Add 's' bit operand (always reg0 for this)
1659 TmpInst.addOperand(MCOperand::createReg(0));
1660 EmitToStreamer(*OutStreamer, TmpInst);
1661 return;
1662 }
1663 case ARM::MOVTi16_ga_pcrel:
1664 case ARM::t2MOVTi16_ga_pcrel: {
1665 MCInst TmpInst;
1666 TmpInst.setOpcode(Opc == ARM::MOVTi16_ga_pcrel
1667 ? ARM::MOVTi16 : ARM::t2MOVTi16);
1668 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
1669 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(1).getReg()));
1670
1671 unsigned TF = MI->getOperand(2).getTargetFlags();
1672 const GlobalValue *GV = MI->getOperand(2).getGlobal();
1673 MCSymbol *GVSym = GetARMGVSymbol(GV, TF);
1674 const MCExpr *GVSymExpr = MCSymbolRefExpr::create(GVSym, OutContext);
1675
1676 MCSymbol *LabelSym =
1677 getPICLabel(DL.getPrivateGlobalPrefix(), getFunctionNumber(),
1678 MI->getOperand(3).getImm(), OutContext);
1679 const MCExpr *LabelSymExpr= MCSymbolRefExpr::create(LabelSym, OutContext);
1680 unsigned PCAdj = (Opc == ARM::MOVTi16_ga_pcrel) ? 8 : 4;
1681 const MCExpr *PCRelExpr = ARM::createUpper16(
1683 GVSymExpr,
1684 MCBinaryExpr::createAdd(LabelSymExpr,
1686 OutContext),
1687 OutContext),
1688 OutContext);
1689 TmpInst.addOperand(MCOperand::createExpr(PCRelExpr));
1690 // Add predicate operands.
1692 TmpInst.addOperand(MCOperand::createReg(0));
1693 // Add 's' bit operand (always reg0 for this)
1694 TmpInst.addOperand(MCOperand::createReg(0));
1695 EmitToStreamer(*OutStreamer, TmpInst);
1696 return;
1697 }
1698 case ARM::t2BFi:
1699 case ARM::t2BFic:
1700 case ARM::t2BFLi:
1701 case ARM::t2BFr:
1702 case ARM::t2BFLr: {
1703 // This is a Branch Future instruction.
1704
1705 const MCExpr *BranchLabel = MCSymbolRefExpr::create(
1706 getBFLabel(DL.getPrivateGlobalPrefix(), getFunctionNumber(),
1707 MI->getOperand(0).getIndex(), OutContext),
1708 OutContext);
1709
1710 auto MCInst = MCInstBuilder(Opc).addExpr(BranchLabel);
1711 if (MI->getOperand(1).isReg()) {
1712 // For BFr/BFLr
1713 MCInst.addReg(MI->getOperand(1).getReg());
1714 } else {
1715 // For BFi/BFLi/BFic
1716 const MCExpr *BranchTarget;
1717 if (MI->getOperand(1).isMBB())
1718 BranchTarget = MCSymbolRefExpr::create(
1719 MI->getOperand(1).getMBB()->getSymbol(), OutContext);
1720 else if (MI->getOperand(1).isGlobal()) {
1721 const GlobalValue *GV = MI->getOperand(1).getGlobal();
1722 BranchTarget = MCSymbolRefExpr::create(
1723 GetARMGVSymbol(GV, MI->getOperand(1).getTargetFlags()), OutContext);
1724 } else if (MI->getOperand(1).isSymbol()) {
1725 BranchTarget = MCSymbolRefExpr::create(
1726 GetExternalSymbolSymbol(MI->getOperand(1).getSymbolName()),
1727 OutContext);
1728 } else
1729 llvm_unreachable("Unhandled operand kind in Branch Future instruction");
1730
1731 MCInst.addExpr(BranchTarget);
1732 }
1733
1734 if (Opc == ARM::t2BFic) {
1735 const MCExpr *ElseLabel = MCSymbolRefExpr::create(
1736 getBFLabel(DL.getPrivateGlobalPrefix(), getFunctionNumber(),
1737 MI->getOperand(2).getIndex(), OutContext),
1738 OutContext);
1739 MCInst.addExpr(ElseLabel);
1740 MCInst.addImm(MI->getOperand(3).getImm());
1741 } else {
1742 MCInst.addImm(MI->getOperand(2).getImm())
1743 .addReg(MI->getOperand(3).getReg());
1744 }
1745
1747 return;
1748 }
1749 case ARM::t2BF_LabelPseudo: {
1750 // This is a pseudo op for a label used by a branch future instruction
1751
1752 // Emit the label.
1753 OutStreamer->emitLabel(getBFLabel(DL.getPrivateGlobalPrefix(),
1755 MI->getOperand(0).getIndex(), OutContext));
1756 return;
1757 }
1758 case ARM::tPICADD: {
1759 // This is a pseudo op for a label + instruction sequence, which looks like:
1760 // LPC0:
1761 // add r0, pc
1762 // This adds the address of LPC0 to r0.
1763
1764 // Emit the label.
1765 OutStreamer->emitLabel(getPICLabel(DL.getPrivateGlobalPrefix(),
1767 MI->getOperand(2).getImm(), OutContext));
1768
1769 // Form and emit the add.
1771 .addReg(MI->getOperand(0).getReg())
1772 .addReg(MI->getOperand(0).getReg())
1773 .addReg(ARM::PC)
1774 // Add predicate operands.
1776 .addReg(0));
1777 return;
1778 }
1779 case ARM::PICADD: {
1780 // This is a pseudo op for a label + instruction sequence, which looks like:
1781 // LPC0:
1782 // add r0, pc, r0
1783 // This adds the address of LPC0 to r0.
1784
1785 // Emit the label.
1786 OutStreamer->emitLabel(getPICLabel(DL.getPrivateGlobalPrefix(),
1788 MI->getOperand(2).getImm(), OutContext));
1789
1790 // Form and emit the add.
1792 .addReg(MI->getOperand(0).getReg())
1793 .addReg(ARM::PC)
1794 .addReg(MI->getOperand(1).getReg())
1795 // Add predicate operands.
1796 .addImm(MI->getOperand(3).getImm())
1797 .addReg(MI->getOperand(4).getReg())
1798 // Add 's' bit operand (always reg0 for this)
1799 .addReg(0));
1800 return;
1801 }
1802 case ARM::PICSTR:
1803 case ARM::PICSTRB:
1804 case ARM::PICSTRH:
1805 case ARM::PICLDR:
1806 case ARM::PICLDRB:
1807 case ARM::PICLDRH:
1808 case ARM::PICLDRSB:
1809 case ARM::PICLDRSH: {
1810 // This is a pseudo op for a label + instruction sequence, which looks like:
1811 // LPC0:
1812 // OP r0, [pc, r0]
1813 // The LCP0 label is referenced by a constant pool entry in order to get
1814 // a PC-relative address at the ldr instruction.
1815
1816 // Emit the label.
1817 OutStreamer->emitLabel(getPICLabel(DL.getPrivateGlobalPrefix(),
1819 MI->getOperand(2).getImm(), OutContext));
1820
1821 // Form and emit the load
1822 unsigned Opcode;
1823 switch (MI->getOpcode()) {
1824 default:
1825 llvm_unreachable("Unexpected opcode!");
1826 case ARM::PICSTR: Opcode = ARM::STRrs; break;
1827 case ARM::PICSTRB: Opcode = ARM::STRBrs; break;
1828 case ARM::PICSTRH: Opcode = ARM::STRH; break;
1829 case ARM::PICLDR: Opcode = ARM::LDRrs; break;
1830 case ARM::PICLDRB: Opcode = ARM::LDRBrs; break;
1831 case ARM::PICLDRH: Opcode = ARM::LDRH; break;
1832 case ARM::PICLDRSB: Opcode = ARM::LDRSB; break;
1833 case ARM::PICLDRSH: Opcode = ARM::LDRSH; break;
1834 }
1836 .addReg(MI->getOperand(0).getReg())
1837 .addReg(ARM::PC)
1838 .addReg(MI->getOperand(1).getReg())
1839 .addImm(0)
1840 // Add predicate operands.
1841 .addImm(MI->getOperand(3).getImm())
1842 .addReg(MI->getOperand(4).getReg()));
1843
1844 return;
1845 }
1846 case ARM::CONSTPOOL_ENTRY: {
1847 if (Subtarget->genExecuteOnly())
1848 llvm_unreachable("execute-only should not generate constant pools");
1849
1850 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool
1851 /// in the function. The first operand is the ID# for this instruction, the
1852 /// second is the index into the MachineConstantPool that this is, the third
1853 /// is the size in bytes of this constant pool entry.
1854 /// The required alignment is specified on the basic block holding this MI.
1855 unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
1856 unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex();
1857
1858 // If this is the first entry of the pool, mark it.
1859 if (!InConstantPool) {
1860 OutStreamer->emitDataRegion(MCDR_DataRegion);
1861 InConstantPool = true;
1862 }
1863
1864 OutStreamer->emitLabel(GetCPISymbol(LabelId));
1865
1866 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
1867 if (MCPE.isMachineConstantPoolEntry())
1869 else
1871 return;
1872 }
1873 case ARM::JUMPTABLE_ADDRS:
1875 return;
1876 case ARM::JUMPTABLE_INSTS:
1878 return;
1879 case ARM::JUMPTABLE_TBB:
1880 case ARM::JUMPTABLE_TBH:
1881 emitJumpTableTBInst(MI, MI->getOpcode() == ARM::JUMPTABLE_TBB ? 1 : 2);
1882 return;
1883 case ARM::t2BR_JT: {
1885 .addReg(ARM::PC)
1886 .addReg(MI->getOperand(0).getReg())
1887 // Add predicate operands.
1889 .addReg(0));
1890 return;
1891 }
1892 case ARM::t2TBB_JT:
1893 case ARM::t2TBH_JT: {
1894 unsigned Opc = MI->getOpcode() == ARM::t2TBB_JT ? ARM::t2TBB : ARM::t2TBH;
1895 // Lower and emit the PC label, then the instruction itself.
1896 OutStreamer->emitLabel(GetCPISymbol(MI->getOperand(3).getImm()));
1898 .addReg(MI->getOperand(0).getReg())
1899 .addReg(MI->getOperand(1).getReg())
1900 // Add predicate operands.
1902 .addReg(0));
1903 return;
1904 }
1905 case ARM::tTBB_JT:
1906 case ARM::tTBH_JT: {
1907
1908 bool Is8Bit = MI->getOpcode() == ARM::tTBB_JT;
1909 Register Base = MI->getOperand(0).getReg();
1910 Register Idx = MI->getOperand(1).getReg();
1911 assert(MI->getOperand(1).isKill() && "We need the index register as scratch!");
1912
1913 // Multiply up idx if necessary.
1914 if (!Is8Bit)
1916 .addReg(Idx)
1917 .addReg(ARM::CPSR)
1918 .addReg(Idx)
1919 .addImm(1)
1920 // Add predicate operands.
1921 .addImm(ARMCC::AL)
1922 .addReg(0));
1923
1924 if (Base == ARM::PC) {
1925 // TBB [base, idx] =
1926 // ADDS idx, idx, base
1927 // LDRB idx, [idx, #4] ; or LDRH if TBH
1928 // LSLS idx, #1
1929 // ADDS pc, pc, idx
1930
1931 // When using PC as the base, it's important that there is no padding
1932 // between the last ADDS and the start of the jump table. The jump table
1933 // is 4-byte aligned, so we ensure we're 4 byte aligned here too.
1934 //
1935 // FIXME: Ideally we could vary the LDRB index based on the padding
1936 // between the sequence and jump table, however that relies on MCExprs
1937 // for load indexes which are currently not supported.
1938 OutStreamer->emitCodeAlignment(Align(4), &getSubtargetInfo());
1940 .addReg(Idx)
1941 .addReg(Idx)
1942 .addReg(Base)
1943 // Add predicate operands.
1944 .addImm(ARMCC::AL)
1945 .addReg(0));
1946
1947 unsigned Opc = Is8Bit ? ARM::tLDRBi : ARM::tLDRHi;
1949 .addReg(Idx)
1950 .addReg(Idx)
1951 .addImm(Is8Bit ? 4 : 2)
1952 // Add predicate operands.
1953 .addImm(ARMCC::AL)
1954 .addReg(0));
1955 } else {
1956 // TBB [base, idx] =
1957 // LDRB idx, [base, idx] ; or LDRH if TBH
1958 // LSLS idx, #1
1959 // ADDS pc, pc, idx
1960
1961 unsigned Opc = Is8Bit ? ARM::tLDRBr : ARM::tLDRHr;
1963 .addReg(Idx)
1964 .addReg(Base)
1965 .addReg(Idx)
1966 // Add predicate operands.
1967 .addImm(ARMCC::AL)
1968 .addReg(0));
1969 }
1970
1972 .addReg(Idx)
1973 .addReg(ARM::CPSR)
1974 .addReg(Idx)
1975 .addImm(1)
1976 // Add predicate operands.
1977 .addImm(ARMCC::AL)
1978 .addReg(0));
1979
1980 OutStreamer->emitLabel(GetCPISymbol(MI->getOperand(3).getImm()));
1982 .addReg(ARM::PC)
1983 .addReg(ARM::PC)
1984 .addReg(Idx)
1985 // Add predicate operands.
1986 .addImm(ARMCC::AL)
1987 .addReg(0));
1988 return;
1989 }
1990 case ARM::tBR_JTr:
1991 case ARM::BR_JTr: {
1992 // mov pc, target
1993 MCInst TmpInst;
1994 unsigned Opc = MI->getOpcode() == ARM::BR_JTr ?
1995 ARM::MOVr : ARM::tMOVr;
1996 TmpInst.setOpcode(Opc);
1997 TmpInst.addOperand(MCOperand::createReg(ARM::PC));
1998 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
1999 // Add predicate operands.
2001 TmpInst.addOperand(MCOperand::createReg(0));
2002 // Add 's' bit operand (always reg0 for this)
2003 if (Opc == ARM::MOVr)
2004 TmpInst.addOperand(MCOperand::createReg(0));
2005 EmitToStreamer(*OutStreamer, TmpInst);
2006 return;
2007 }
2008 case ARM::BR_JTm_i12: {
2009 // ldr pc, target
2010 MCInst TmpInst;
2011 TmpInst.setOpcode(ARM::LDRi12);
2012 TmpInst.addOperand(MCOperand::createReg(ARM::PC));
2013 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
2014 TmpInst.addOperand(MCOperand::createImm(MI->getOperand(2).getImm()));
2015 // Add predicate operands.
2017 TmpInst.addOperand(MCOperand::createReg(0));
2018 EmitToStreamer(*OutStreamer, TmpInst);
2019 return;
2020 }
2021 case ARM::BR_JTm_rs: {
2022 // ldr pc, target
2023 MCInst TmpInst;
2024 TmpInst.setOpcode(ARM::LDRrs);
2025 TmpInst.addOperand(MCOperand::createReg(ARM::PC));
2026 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
2027 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(1).getReg()));
2028 TmpInst.addOperand(MCOperand::createImm(MI->getOperand(2).getImm()));
2029 // Add predicate operands.
2031 TmpInst.addOperand(MCOperand::createReg(0));
2032 EmitToStreamer(*OutStreamer, TmpInst);
2033 return;
2034 }
2035 case ARM::BR_JTadd: {
2036 // add pc, target, idx
2038 .addReg(ARM::PC)
2039 .addReg(MI->getOperand(0).getReg())
2040 .addReg(MI->getOperand(1).getReg())
2041 // Add predicate operands.
2043 .addReg(0)
2044 // Add 's' bit operand (always reg0 for this)
2045 .addReg(0));
2046 return;
2047 }
2048 case ARM::SPACE:
2049 OutStreamer->emitZeros(MI->getOperand(1).getImm());
2050 return;
2051 case ARM::TRAP: {
2052 // Non-Darwin binutils don't yet support the "trap" mnemonic.
2053 // FIXME: Remove this special case when they do.
2054 if (!Subtarget->isTargetMachO()) {
2055 uint32_t Val = 0xe7ffdefeUL;
2056 OutStreamer->AddComment("trap");
2057 ATS.emitInst(Val);
2058 return;
2059 }
2060 break;
2061 }
2062 case ARM::tTRAP: {
2063 // Non-Darwin binutils don't yet support the "trap" mnemonic.
2064 // FIXME: Remove this special case when they do.
2065 if (!Subtarget->isTargetMachO()) {
2066 uint16_t Val = 0xdefe;
2067 OutStreamer->AddComment("trap");
2068 ATS.emitInst(Val, 'n');
2069 return;
2070 }
2071 break;
2072 }
2073 case ARM::t2Int_eh_sjlj_setjmp:
2074 case ARM::t2Int_eh_sjlj_setjmp_nofp:
2075 case ARM::tInt_eh_sjlj_setjmp: {
2076 // Two incoming args: GPR:$src, GPR:$val
2077 // mov $val, pc
2078 // adds $val, #7
2079 // str $val, [$src, #4]
2080 // movs r0, #0
2081 // b LSJLJEH
2082 // movs r0, #1
2083 // LSJLJEH:
2084 Register SrcReg = MI->getOperand(0).getReg();
2085 Register ValReg = MI->getOperand(1).getReg();
2086 MCSymbol *Label = OutContext.createTempSymbol("SJLJEH");
2087 OutStreamer->AddComment("eh_setjmp begin");
2089 .addReg(ValReg)
2090 .addReg(ARM::PC)
2091 // Predicate.
2092 .addImm(ARMCC::AL)
2093 .addReg(0));
2094
2096 .addReg(ValReg)
2097 // 's' bit operand
2098 .addReg(ARM::CPSR)
2099 .addReg(ValReg)
2100 .addImm(7)
2101 // Predicate.
2102 .addImm(ARMCC::AL)
2103 .addReg(0));
2104
2106 .addReg(ValReg)
2107 .addReg(SrcReg)
2108 // The offset immediate is #4. The operand value is scaled by 4 for the
2109 // tSTR instruction.
2110 .addImm(1)
2111 // Predicate.
2112 .addImm(ARMCC::AL)
2113 .addReg(0));
2114
2116 .addReg(ARM::R0)
2117 .addReg(ARM::CPSR)
2118 .addImm(0)
2119 // Predicate.
2120 .addImm(ARMCC::AL)
2121 .addReg(0));
2122
2123 const MCExpr *SymbolExpr = MCSymbolRefExpr::create(Label, OutContext);
2125 .addExpr(SymbolExpr)
2126 .addImm(ARMCC::AL)
2127 .addReg(0));
2128
2129 OutStreamer->AddComment("eh_setjmp end");
2131 .addReg(ARM::R0)
2132 .addReg(ARM::CPSR)
2133 .addImm(1)
2134 // Predicate.
2135 .addImm(ARMCC::AL)
2136 .addReg(0));
2137
2138 OutStreamer->emitLabel(Label);
2139 return;
2140 }
2141
2142 case ARM::Int_eh_sjlj_setjmp_nofp:
2143 case ARM::Int_eh_sjlj_setjmp: {
2144 // Two incoming args: GPR:$src, GPR:$val
2145 // add $val, pc, #8
2146 // str $val, [$src, #+4]
2147 // mov r0, #0
2148 // add pc, pc, #0
2149 // mov r0, #1
2150 Register SrcReg = MI->getOperand(0).getReg();
2151 Register ValReg = MI->getOperand(1).getReg();
2152
2153 OutStreamer->AddComment("eh_setjmp begin");
2155 .addReg(ValReg)
2156 .addReg(ARM::PC)
2157 .addImm(8)
2158 // Predicate.
2159 .addImm(ARMCC::AL)
2160 .addReg(0)
2161 // 's' bit operand (always reg0 for this).
2162 .addReg(0));
2163
2165 .addReg(ValReg)
2166 .addReg(SrcReg)
2167 .addImm(4)
2168 // Predicate.
2169 .addImm(ARMCC::AL)
2170 .addReg(0));
2171
2173 .addReg(ARM::R0)
2174 .addImm(0)
2175 // Predicate.
2176 .addImm(ARMCC::AL)
2177 .addReg(0)
2178 // 's' bit operand (always reg0 for this).
2179 .addReg(0));
2180
2182 .addReg(ARM::PC)
2183 .addReg(ARM::PC)
2184 .addImm(0)
2185 // Predicate.
2186 .addImm(ARMCC::AL)
2187 .addReg(0)
2188 // 's' bit operand (always reg0 for this).
2189 .addReg(0));
2190
2191 OutStreamer->AddComment("eh_setjmp end");
2193 .addReg(ARM::R0)
2194 .addImm(1)
2195 // Predicate.
2196 .addImm(ARMCC::AL)
2197 .addReg(0)
2198 // 's' bit operand (always reg0 for this).
2199 .addReg(0));
2200 return;
2201 }
2202 case ARM::Int_eh_sjlj_longjmp: {
2203 // ldr sp, [$src, #8]
2204 // ldr $scratch, [$src, #4]
2205 // ldr r7, [$src]
2206 // bx $scratch
2207 Register SrcReg = MI->getOperand(0).getReg();
2208 Register ScratchReg = MI->getOperand(1).getReg();
2210 .addReg(ARM::SP)
2211 .addReg(SrcReg)
2212 .addImm(8)
2213 // Predicate.
2214 .addImm(ARMCC::AL)
2215 .addReg(0));
2216
2218 .addReg(ScratchReg)
2219 .addReg(SrcReg)
2220 .addImm(4)
2221 // Predicate.
2222 .addImm(ARMCC::AL)
2223 .addReg(0));
2224
2225 const MachineFunction &MF = *MI->getParent()->getParent();
2226 const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
2227
2228 if (STI.isTargetDarwin() || STI.isTargetWindows()) {
2229 // These platforms always use the same frame register
2231 .addReg(STI.getFramePointerReg())
2232 .addReg(SrcReg)
2233 .addImm(0)
2234 // Predicate.
2236 .addReg(0));
2237 } else {
2238 // If the calling code might use either R7 or R11 as
2239 // frame pointer register, restore it into both.
2241 .addReg(ARM::R7)
2242 .addReg(SrcReg)
2243 .addImm(0)
2244 // Predicate.
2245 .addImm(ARMCC::AL)
2246 .addReg(0));
2248 .addReg(ARM::R11)
2249 .addReg(SrcReg)
2250 .addImm(0)
2251 // Predicate.
2252 .addImm(ARMCC::AL)
2253 .addReg(0));
2254 }
2255
2256 assert(Subtarget->hasV4TOps());
2258 .addReg(ScratchReg)
2259 // Predicate.
2260 .addImm(ARMCC::AL)
2261 .addReg(0));
2262 return;
2263 }
2264 case ARM::tInt_eh_sjlj_longjmp: {
2265 // ldr $scratch, [$src, #8]
2266 // mov sp, $scratch
2267 // ldr $scratch, [$src, #4]
2268 // ldr r7, [$src]
2269 // bx $scratch
2270 Register SrcReg = MI->getOperand(0).getReg();
2271 Register ScratchReg = MI->getOperand(1).getReg();
2272
2273 const MachineFunction &MF = *MI->getParent()->getParent();
2274 const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
2275
2277 .addReg(ScratchReg)
2278 .addReg(SrcReg)
2279 // The offset immediate is #8. The operand value is scaled by 4 for the
2280 // tLDR instruction.
2281 .addImm(2)
2282 // Predicate.
2283 .addImm(ARMCC::AL)
2284 .addReg(0));
2285
2287 .addReg(ARM::SP)
2288 .addReg(ScratchReg)
2289 // Predicate.
2290 .addImm(ARMCC::AL)
2291 .addReg(0));
2292
2294 .addReg(ScratchReg)
2295 .addReg(SrcReg)
2296 .addImm(1)
2297 // Predicate.
2298 .addImm(ARMCC::AL)
2299 .addReg(0));
2300
2301 if (STI.isTargetDarwin() || STI.isTargetWindows()) {
2302 // These platforms always use the same frame register
2304 .addReg(STI.getFramePointerReg())
2305 .addReg(SrcReg)
2306 .addImm(0)
2307 // Predicate.
2309 .addReg(0));
2310 } else {
2311 // If the calling code might use either R7 or R11 as
2312 // frame pointer register, restore it into both.
2314 .addReg(ARM::R7)
2315 .addReg(SrcReg)
2316 .addImm(0)
2317 // Predicate.
2318 .addImm(ARMCC::AL)
2319 .addReg(0));
2321 .addReg(ARM::R11)
2322 .addReg(SrcReg)
2323 .addImm(0)
2324 // Predicate.
2325 .addImm(ARMCC::AL)
2326 .addReg(0));
2327 }
2328
2330 .addReg(ScratchReg)
2331 // Predicate.
2332 .addImm(ARMCC::AL)
2333 .addReg(0));
2334 return;
2335 }
2336 case ARM::tInt_WIN_eh_sjlj_longjmp: {
2337 // ldr.w r11, [$src, #0]
2338 // ldr.w sp, [$src, #8]
2339 // ldr.w pc, [$src, #4]
2340
2341 Register SrcReg = MI->getOperand(0).getReg();
2342
2344 .addReg(ARM::R11)
2345 .addReg(SrcReg)
2346 .addImm(0)
2347 // Predicate
2348 .addImm(ARMCC::AL)
2349 .addReg(0));
2351 .addReg(ARM::SP)
2352 .addReg(SrcReg)
2353 .addImm(8)
2354 // Predicate
2355 .addImm(ARMCC::AL)
2356 .addReg(0));
2358 .addReg(ARM::PC)
2359 .addReg(SrcReg)
2360 .addImm(4)
2361 // Predicate
2362 .addImm(ARMCC::AL)
2363 .addReg(0));
2364 return;
2365 }
2366 case ARM::PATCHABLE_FUNCTION_ENTER:
2368 return;
2369 case ARM::PATCHABLE_FUNCTION_EXIT:
2371 return;
2372 case ARM::PATCHABLE_TAIL_CALL:
2374 return;
2375 case ARM::SpeculationBarrierISBDSBEndBB: {
2376 // Print DSB SYS + ISB
2377 MCInst TmpInstDSB;
2378 TmpInstDSB.setOpcode(ARM::DSB);
2379 TmpInstDSB.addOperand(MCOperand::createImm(0xf));
2380 EmitToStreamer(*OutStreamer, TmpInstDSB);
2381 MCInst TmpInstISB;
2382 TmpInstISB.setOpcode(ARM::ISB);
2383 TmpInstISB.addOperand(MCOperand::createImm(0xf));
2384 EmitToStreamer(*OutStreamer, TmpInstISB);
2385 return;
2386 }
2387 case ARM::t2SpeculationBarrierISBDSBEndBB: {
2388 // Print DSB SYS + ISB
2389 MCInst TmpInstDSB;
2390 TmpInstDSB.setOpcode(ARM::t2DSB);
2391 TmpInstDSB.addOperand(MCOperand::createImm(0xf));
2393 TmpInstDSB.addOperand(MCOperand::createReg(0));
2394 EmitToStreamer(*OutStreamer, TmpInstDSB);
2395 MCInst TmpInstISB;
2396 TmpInstISB.setOpcode(ARM::t2ISB);
2397 TmpInstISB.addOperand(MCOperand::createImm(0xf));
2399 TmpInstISB.addOperand(MCOperand::createReg(0));
2400 EmitToStreamer(*OutStreamer, TmpInstISB);
2401 return;
2402 }
2403 case ARM::SpeculationBarrierSBEndBB: {
2404 // Print SB
2405 MCInst TmpInstSB;
2406 TmpInstSB.setOpcode(ARM::SB);
2407 EmitToStreamer(*OutStreamer, TmpInstSB);
2408 return;
2409 }
2410 case ARM::t2SpeculationBarrierSBEndBB: {
2411 // Print SB
2412 MCInst TmpInstSB;
2413 TmpInstSB.setOpcode(ARM::t2SB);
2414 EmitToStreamer(*OutStreamer, TmpInstSB);
2415 return;
2416 }
2417
2418 case ARM::SEH_StackAlloc:
2419 ATS.emitARMWinCFIAllocStack(MI->getOperand(0).getImm(),
2420 MI->getOperand(1).getImm());
2421 return;
2422
2423 case ARM::SEH_SaveRegs:
2424 case ARM::SEH_SaveRegs_Ret:
2425 ATS.emitARMWinCFISaveRegMask(MI->getOperand(0).getImm(),
2426 MI->getOperand(1).getImm());
2427 return;
2428
2429 case ARM::SEH_SaveSP:
2430 ATS.emitARMWinCFISaveSP(MI->getOperand(0).getImm());
2431 return;
2432
2433 case ARM::SEH_SaveFRegs:
2434 ATS.emitARMWinCFISaveFRegs(MI->getOperand(0).getImm(),
2435 MI->getOperand(1).getImm());
2436 return;
2437
2438 case ARM::SEH_SaveLR:
2439 ATS.emitARMWinCFISaveLR(MI->getOperand(0).getImm());
2440 return;
2441
2442 case ARM::SEH_Nop:
2443 case ARM::SEH_Nop_Ret:
2444 ATS.emitARMWinCFINop(MI->getOperand(0).getImm());
2445 return;
2446
2447 case ARM::SEH_PrologEnd:
2448 ATS.emitARMWinCFIPrologEnd(/*Fragment=*/false);
2449 return;
2450
2451 case ARM::SEH_EpilogStart:
2453 return;
2454
2455 case ARM::SEH_EpilogEnd:
2457 return;
2458 }
2459
2460 MCInst TmpInst;
2461 LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
2462
2463 EmitToStreamer(*OutStreamer, TmpInst);
2464}
2465
2466char ARMAsmPrinter::ID = 0;
2467
2468INITIALIZE_PASS(ARMAsmPrinter, "arm-asm-printer", "ARM Assembly Printer", false,
2469 false)
2470
2471//===----------------------------------------------------------------------===//
2472// Target Registry Stuff
2473//===----------------------------------------------------------------------===//
2474
2475// Force static initialization.
2476extern "C" LLVM_ABI LLVM_EXTERNAL_VISIBILITY void
2477LLVMInitializeARMAsmPrinter() {
2482}
unsigned SubReg
assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")
static void emitNonLazySymbolPointer(MCStreamer &OutStreamer, MCSymbol *StubLabel, MachineModuleInfoImpl::StubValueTy &MCSym)
static uint8_t getModifierSpecifier(ARMCP::ARMCPModifier Modifier)
static MCSymbol * getPICLabel(StringRef Prefix, unsigned FunctionNumber, unsigned LabelId, MCContext &Ctx)
static bool checkDenormalAttributeInconsistency(const Module &M)
static bool checkFunctionsAttributeConsistency(const Module &M, StringRef Attr, StringRef Value)
static bool isThumb(const MCSubtargetInfo &STI)
static MCSymbol * getBFLabel(StringRef Prefix, unsigned FunctionNumber, unsigned LabelId, MCContext &Ctx)
static bool checkDenormalAttributeConsistency(const Module &M, StringRef Attr, DenormalMode Value)
MachineBasicBlock & MBB
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
#define LLVM_ABI
Definition Compiler.h:213
#define LLVM_EXTERNAL_VISIBILITY
Definition Compiler.h:132
This file contains the declarations for the subclasses of Constant, which represent the different fla...
IRTranslator LLVM IR MI
Module.h This file contains the declarations for the Module class.
const size_t AbstractManglingParser< Derived, Alloc >::NumOps
#define F(x, y, z)
Definition MD5.cpp:55
Machine Check Debug Module
Register Reg
Register const TargetRegisterInfo * TRI
Promote Memory to Register
Definition Mem2Reg.cpp:110
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
Definition PassSupport.h:56
static bool contains(SmallPtrSetImpl< ConstantExpr * > &Cache, ConstantExpr *Expr, Constant *C)
Definition Value.cpp:480
This file defines the SmallString class.
static TableGen::Emitter::Opt Y("gen-skeleton-entry", EmitSkeleton, "Generate example skeleton entry")
static TableGen::Emitter::OptClass< SkeletonEmitter > X("gen-skeleton-class", "Generate example skeleton class")
static const unsigned FramePtr
void emitJumpTableAddrs(const MachineInstr *MI)
void emitJumpTableTBInst(const MachineInstr *MI, unsigned OffsetWidth)
void emitFunctionBodyEnd() override
Targets can override this to emit stuff after the last basic block in the function.
bool runOnMachineFunction(MachineFunction &F) override
runOnMachineFunction - This uses the emitInstruction() method to print assembly for each instruction.
MCSymbol * GetCPISymbol(unsigned CPID) const override
Return the symbol for the specified constant pool entry.
void printOperand(const MachineInstr *MI, int OpNum, raw_ostream &O)
void emitStartOfAsmFile(Module &M) override
This virtual method can be overridden by targets that want to emit something at the start of their fi...
ARMAsmPrinter(TargetMachine &TM, std::unique_ptr< MCStreamer > Streamer)
void emitFunctionEntryLabel() override
EmitFunctionEntryLabel - Emit the label that is the entrypoint for the function.
void emitInlineAsmEnd(const MCSubtargetInfo &StartInfo, const MCSubtargetInfo *EndInfo) const override
Let the target do anything it needs to do after emitting inlineasm.
void LowerPATCHABLE_FUNCTION_EXIT(const MachineInstr &MI)
void emitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) override
EmitMachineConstantPoolValue - Print a machine constantpool value to the .s file.
bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNum, const char *ExtraCode, raw_ostream &O) override
Print the specified operand of MI, an INLINEASM instruction, using the specified assembler variant.
void emitXXStructor(const DataLayout &DL, const Constant *CV) override
Targets can override this to change how global constants that are part of a C++ static/global constru...
void LowerPATCHABLE_FUNCTION_ENTER(const MachineInstr &MI)
void LowerPATCHABLE_TAIL_CALL(const MachineInstr &MI)
void emitEndOfAsmFile(Module &M) override
This virtual method can be overridden by targets that want to emit something at the end of their file...
std::tuple< const MCSymbol *, uint64_t, const MCSymbol *, codeview::JumpTableEntrySize > getCodeViewJumpTableInfo(int JTI, const MachineInstr *BranchInstr, const MCSymbol *BranchLabel) const override
Gets information required to create a CodeView debug symbol for a jump table.
void emitJumpTableInsts(const MachineInstr *MI)
const ARMBaseTargetMachine & getTM() const
void emitGlobalVariable(const GlobalVariable *GV) override
Emit the specified global variable to the .s file.
bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum, const char *ExtraCode, raw_ostream &O) override
Print the specified operand of MI, an INLINEASM instruction, using the specified assembler variant as...
void emitInstruction(const MachineInstr *MI) override
Targets should implement this to emit instructions.
void PrintSymbolOperand(const MachineOperand &MO, raw_ostream &O) override
Print the MachineOperand as a symbol.
ARMConstantPoolValue - ARM specific constantpool value.
unsigned char getPCAdjustment() const
ARMCP::ARMCPModifier getModifier() const
ARMFunctionInfo - This class is derived from MachineFunctionInfo and contains private ARM-specific in...
static const char * getRegisterName(MCRegister Reg, unsigned AltIdx=ARM::NoRegAltName)
MCPhysReg getFramePointerReg() const
bool isTargetWindows() const
bool isTargetDarwin() const
void emitTargetAttributes(const MCSubtargetInfo &STI)
Emit the build attributes that only depend on the hardware that we expect.
virtual void emitSetFP(MCRegister FpReg, MCRegister SpReg, int64_t Offset=0)
virtual void finishAttributeSection()
virtual void emitMovSP(MCRegister Reg, int64_t Offset=0)
virtual void emitARMWinCFISaveSP(unsigned Reg)
virtual void emitInst(uint32_t Inst, char Suffix='\0')
virtual void emitARMWinCFISaveLR(unsigned Offset)
virtual void emitTextAttribute(unsigned Attribute, StringRef String)
virtual void emitARMWinCFIAllocStack(unsigned Size, bool Wide)
virtual void emitARMWinCFISaveRegMask(unsigned Mask, bool Wide)
virtual void emitRegSave(const SmallVectorImpl< MCRegister > &RegList, bool isVector)
virtual void emitARMWinCFIEpilogEnd()
virtual void emitARMWinCFIPrologEnd(bool Fragment)
virtual void switchVendor(StringRef Vendor)
virtual void emitARMWinCFISaveFRegs(unsigned First, unsigned Last)
virtual void emitARMWinCFIEpilogStart(unsigned Condition)
virtual void emitPad(int64_t Offset)
virtual void emitAttribute(unsigned Attribute, unsigned Value)
virtual void emitARMWinCFINop(bool Wide)
const TargetLoweringObjectFile & getObjFileLowering() const
Return information about object file lowering.
MCSymbol * getSymbolWithGlobalValueBase(const GlobalValue *GV, StringRef Suffix) const
Return the MCSymbol for a private symbol with global value name as its base, with the specified suffi...
MCSymbol * getSymbol(const GlobalValue *GV) const
void EmitToStreamer(MCStreamer &S, const MCInst &Inst)
virtual void emitGlobalVariable(const GlobalVariable *GV)
Emit the specified global variable to the .s file.
TargetMachine & TM
Target machine description.
Definition AsmPrinter.h:94
void emitXRayTable()
Emit a table with all XRay instrumentation points.
MCSymbol * getMBBExceptionSym(const MachineBasicBlock &MBB)
const MCAsmInfo * MAI
Target Asm Printer information.
Definition AsmPrinter.h:97
MachineFunction * MF
The current machine function.
Definition AsmPrinter.h:109
virtual void SetupMachineFunction(MachineFunction &MF)
This should be called when a new MachineFunction is being processed from runOnMachineFunction.
void emitFunctionBody()
This method emits the body and trailer for a function.
virtual void emitLinkage(const GlobalValue *GV, MCSymbol *GVSym) const
This emits linkage information about GVSym based on GV, if this is supported by the target.
unsigned getFunctionNumber() const
Return a unique ID for the current function.
AsmPrinter(TargetMachine &TM, std::unique_ptr< MCStreamer > Streamer, char &ID=AsmPrinter::ID)
void printOffset(int64_t Offset, raw_ostream &OS) const
This is just convenient handler for printing offsets.
void emitGlobalConstant(const DataLayout &DL, const Constant *CV, AliasMapTy *AliasList=nullptr)
EmitGlobalConstant - Print a general LLVM constant to the .s file.
MCSymbol * getSymbolPreferLocal(const GlobalValue &GV) const
Similar to getSymbol() but preferred for references.
MCSymbol * CurrentFnSym
The symbol for the current function.
Definition AsmPrinter.h:128
MachineModuleInfo * MMI
This is a pointer to the current MachineModuleInfo.
Definition AsmPrinter.h:112
void emitAlignment(Align Alignment, const GlobalObject *GV=nullptr, unsigned MaxBytesToEmit=0) const
Emit an alignment directive to the specified power of two boundary.
MCContext & OutContext
This is the context for the output file that we are streaming.
Definition AsmPrinter.h:101
bool isPositionIndependent() const
std::unique_ptr< MCStreamer > OutStreamer
This is the MCStreamer object for the file we are generating.
Definition AsmPrinter.h:106
void getNameWithPrefix(SmallVectorImpl< char > &Name, const GlobalValue *GV) const
MCSymbol * GetBlockAddressSymbol(const BlockAddress *BA) const
Return the MCSymbol used to satisfy BlockAddress uses of the specified basic block.
const DataLayout & getDataLayout() const
Return information about data layout.
virtual void emitFunctionEntryLabel()
EmitFunctionEntryLabel - Emit the label that is the entrypoint for the function.
MCSymbol * GetExternalSymbolSymbol(const Twine &Sym) const
Return the MCSymbol for the specified ExternalSymbol.
const MCSubtargetInfo & getSubtargetInfo() const
Return information about subtarget.
virtual bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, const char *ExtraCode, raw_ostream &OS)
Print the specified operand of MI, an INLINEASM instruction, using the specified assembler variant.
The address of a basic block.
Definition Constants.h:899
This is an important base class in LLVM.
Definition Constant.h:43
const Constant * stripPointerCasts() const
Definition Constant.h:219
A parsed version of the target data layout string in and methods for querying it.
Definition DataLayout.h:63
TypeSize getTypeAllocSize(Type *Ty) const
Returns the offset in bytes between successive objects of the specified type, including alignment pad...
bool isThreadLocal() const
If the value is "Thread Local", its value isn't shared by the threads.
bool hasInternalLinkage() const
static const MCBinaryExpr * createAdd(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx, SMLoc Loc=SMLoc())
Definition MCExpr.h:343
static const MCBinaryExpr * createDiv(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition MCExpr.h:353
static const MCBinaryExpr * createSub(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition MCExpr.h:428
static LLVM_ABI const MCConstantExpr * create(int64_t Value, MCContext &Ctx, bool PrintInHex=false, unsigned SizeInBytes=0)
Definition MCExpr.cpp:212
Context object for machine code objects.
Definition MCContext.h:83
LLVM_ABI MCSymbol * getOrCreateSymbol(const Twine &Name)
Lookup the symbol inside with the specified Name.
Base class for the full range of assembler expressions which are needed for parsing.
Definition MCExpr.h:34
MCInstBuilder & addReg(MCRegister Reg)
Add a new register operand.
MCInstBuilder & addImm(int64_t Val)
Add a new integer immediate operand.
MCInstBuilder & addExpr(const MCExpr *Val)
Add a new MCExpr operand.
Instances of this class represent a single low-level machine instruction.
Definition MCInst.h:188
void addOperand(const MCOperand Op)
Definition MCInst.h:215
void setOpcode(unsigned Op)
Definition MCInst.h:201
MCSection * getThreadLocalPointerSection() const
MCSection * getNonLazySymbolPointerSection() const
static MCOperand createExpr(const MCExpr *Val)
Definition MCInst.h:166
static MCOperand createReg(MCRegister Reg)
Definition MCInst.h:138
static MCOperand createImm(int64_t Val)
Definition MCInst.h:145
Wrapper class representing physical registers. Should be passed by value.
Definition MCRegister.h:33
Streaming machine code generation interface.
Definition MCStreamer.h:220
virtual bool emitSymbolAttribute(MCSymbol *Symbol, MCSymbolAttr Attribute)=0
Add the given Attribute to Symbol.
MCContext & getContext() const
Definition MCStreamer.h:314
void emitValue(const MCExpr *Value, unsigned Size, SMLoc Loc=SMLoc())
virtual void emitLabel(MCSymbol *Symbol, SMLoc Loc=SMLoc())
Emit a label for Symbol into the current section.
virtual void emitIntValue(uint64_t Value, unsigned Size)
Special case of EmitValue that avoids the client having to pass in a MCExpr for constant integers.
Generic base class for all target subtargets.
bool hasFeature(unsigned Feature) const
static const MCSymbolRefExpr * create(const MCSymbol *Symbol, MCContext &Ctx, SMLoc Loc=SMLoc())
Definition MCExpr.h:214
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition MCSymbol.h:42
LLVM_ABI void print(raw_ostream &OS, const MCAsmInfo *MAI) const
print - Print the value to the stream OS.
Definition MCSymbol.cpp:59
Target specific streamer interface.
Definition MCStreamer.h:93
LLVM_ABI MCSymbol * getSymbol() const
Return the MCSymbol for this basic block.
This class is a data container for one entry in a MachineConstantPool.
union llvm::MachineConstantPoolEntry::@004270020304201266316354007027341142157160323045 Val
The constant itself.
bool isMachineConstantPoolEntry() const
isMachineConstantPoolEntry - Return true if the MachineConstantPoolEntry is indeed a target specific ...
MachineConstantPoolValue * MachineCPVal
Abstract base class for all machine specific constantpool value subclasses.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Representation of each machine instruction.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
const MachineOperand & getOperand(unsigned i) const
const std::vector< MachineJumpTableEntry > & getJumpTables() const
StubValueTy & getGVStubEntry(MCSymbol *Sym)
std::vector< std::pair< MCSymbol *, StubValueTy > > SymbolListTy
PointerIntPair< MCSymbol *, 1, bool > StubValueTy
MachineModuleInfoMachO - This is a MachineModuleInfoImpl implementation for MachO targets.
StubValueTy & getGVStubEntry(MCSymbol *Sym)
StubValueTy & getThreadLocalGVStubEntry(MCSymbol *Sym)
SymbolListTy GetGVStubList()
Accessor methods to return the set of stubs in sorted order.
MachineOperand class - Representation of each machine instruction operand.
unsigned getSubReg() const
const GlobalValue * getGlobal() const
int64_t getImm() const
bool isReg() const
isReg - Tests if this is a MO_Register operand.
MachineBasicBlock * getMBB() const
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
unsigned getTargetFlags() const
bool isGlobal() const
isGlobal - Tests if this is a MO_GlobalAddress operand.
MachineOperandType getType() const
getType - Returns the MachineOperandType for this operand.
Register getReg() const
getReg - Returns the register number.
@ MO_Immediate
Immediate operand.
@ MO_ConstantPoolIndex
Address of indexed Constant in Constant Pool.
@ MO_GlobalAddress
Address of a global value.
@ MO_MachineBasicBlock
MachineBasicBlock reference.
@ MO_Register
Register operand.
int64_t getOffset() const
Return the offset from the symbol in this operand.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
A Module instance is used to store all the information related to an LLVM module.
Definition Module.h:67
virtual void print(raw_ostream &OS, const Module *M) const
print - Print out the internal state of the pass.
Definition Pass.cpp:140
IntType getInt() const
PointerTy getPointer() const
Wrapper class representing virtual and physical registers.
Definition Register.h:19
SmallString - A SmallString is just a SmallVector with methods and accessors that make it work better...
Definition SmallString.h:26
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
StringRef - Represent a constant reference to a string, i.e.
Definition StringRef.h:55
Primary interface to the complete machine description for the target machine.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
TypeSize getRegSizeInBits(const TargetRegisterClass &RC) const
Return the size in bits of a register from class RC.
virtual Register getFrameRegister(const MachineFunction &MF) const =0
Debug information queries.
virtual const TargetRegisterInfo * getRegisterInfo() const =0
Return the target's register information.
Triple - Helper class for working with autoconf configuration names.
Definition Triple.h:47
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition Twine.h:82
The instances of the Type class are immutable: once they are created, they are never changed.
Definition Type.h:45
LLVM Value Representation.
Definition Value.h:75
Type * getType() const
All values are typed, get the type of this value.
Definition Value.h:256
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition raw_ostream.h:53
A raw_ostream that writes to an SmallVector or SmallString.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ SECREL
Thread Pointer Offset.
@ GOT_PREL
Thread Local Storage (General Dynamic Mode)
@ SBREL
Section Relative (Windows TLS)
@ GOTTPOFF
Global Offset Table, PC Relative.
@ TPOFF
Global Offset Table, Thread Pointer Offset.
@ MO_LO16
MO_LO16 - On a symbol operand, this represents a relocation containing lower 16 bit of the address.
@ MO_LO_0_7
MO_LO_0_7 - On a symbol operand, this represents a relocation containing bits 0 through 7 of the addr...
@ MO_LO_8_15
MO_LO_8_15 - On a symbol operand, this represents a relocation containing bits 8 through 15 of the ad...
@ MO_NONLAZY
MO_NONLAZY - This is an independent flag, on a symbol operand "FOO" it represents a symbol which,...
@ MO_HI_8_15
MO_HI_8_15 - On a symbol operand, this represents a relocation containing bits 24 through 31 of the a...
@ MO_HI16
MO_HI16 - On a symbol operand, this represents a relocation containing higher 16 bit of the address.
@ MO_DLLIMPORT
MO_DLLIMPORT - On a symbol operand, this represents that the reference to the symbol is for an import...
@ MO_HI_0_7
MO_HI_0_7 - On a symbol operand, this represents a relocation containing bits 16 through 23 of the ad...
@ MO_COFFSTUB
MO_COFFSTUB - On a symbol operand "FOO", this indicates that the reference is actually to the "....
std::string ParseARMTriple(const Triple &TT, StringRef CPU)
const MCSpecifierExpr * createLower16(const MCExpr *Expr, MCContext &Ctx)
const MCSpecifierExpr * createUpper16(const MCExpr *Expr, MCContext &Ctx)
SymbolStorageClass
Storage class tells where and what the symbol represents.
Definition COFF.h:218
@ IMAGE_SYM_CLASS_EXTERNAL
External symbol.
Definition COFF.h:224
@ IMAGE_SYM_CLASS_STATIC
Static.
Definition COFF.h:225
@ IMAGE_SYM_DTYPE_FUNCTION
A function that returns a base type.
Definition COFF.h:276
@ SCT_COMPLEX_TYPE_SHIFT
Type is formed as (base + (derived << SCT_COMPLEX_TYPE_SHIFT))
Definition COFF.h:280
std::enable_if_t< detail::IsValidPointer< X, Y >::value, X * > extract_or_null(Y &&MD)
Extract a Value from Metadata, allowing null.
Definition Metadata.h:681
This is an optimization pass for GlobalISel generic memory operations.
@ Offset
Definition DWP.cpp:477
decltype(auto) dyn_cast(const From &Val)
dyn_cast<X> - Return the argument parameter cast to the specified type.
Definition Casting.h:649
Target & getTheThumbBETarget()
@ MCDR_DataRegionEnd
.end_data_region
@ MCDR_DataRegion
.data_region
@ MCDR_DataRegionJT8
.data_region jt8
@ MCDR_DataRegionJT32
.data_region jt32
@ MCDR_DataRegionJT16
.data_region jt16
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
Definition STLExtras.h:1712
MachineInstr * getImm(const MachineOperand &MO, const MachineRegisterInfo *MRI)
LLVM_ABI raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.
void LowerARMMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI, ARMAsmPrinter &AP)
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
Definition MCRegister.h:21
DWARFExpression::Operation Op
OutputIt move(R &&Range, OutputIt Out)
Provide wrappers to std::move which take ranges instead of having to pass begin/end explicitly.
Definition STLExtras.h:1847
DenormalMode parseDenormalFPAttribute(StringRef Str)
Returns the denormal mode to use for inputs and outputs.
decltype(auto) cast(const From &Val)
cast<X> - Return the argument parameter cast to the specified type.
Definition Casting.h:565
Target & getTheARMLETarget()
unsigned convertAddSubFlagsOpcode(unsigned OldOpc)
Map pseudo instructions that imply an 'S' bit onto real opcodes.
@ MCSA_IndirectSymbol
.indirect_symbol (MachO)
@ MCSA_ELF_TypeFunction
.type _foo, STT_FUNC # aka @function
Target & getTheARMBETarget()
Target & getTheThumbLETarget()
Implement std::hash so that hash_code can be used in STL containers.
Definition BitVector.h:870
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition Alignment.h:39
Represent subnormal handling kind for floating point instruction inputs and outputs.
static constexpr DenormalMode getPositiveZero()
static constexpr DenormalMode getPreserveSign()
static constexpr DenormalMode getIEEE()
RegisterAsmPrinter - Helper template for registering a target specific assembly printer,...