TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDesc objects that represent all of the machine registers that the target has. More...
#include "llvm/CodeGen/TargetRegisterInfo.h"
Classes | |
| struct | RegClassInfo |
| struct | SubRegCoveredBits |
| SubRegCoveredBits - Emitted by tablegen: bit range covered by a subreg index, -1 in any being invalid. More... | |
Public Types | |
| using | regclass_iterator = const TargetRegisterClass *const * |
| using | vt_iterator = const MVT::SimpleValueType * |
 Public Types inherited from llvm::MCRegisterInfo | |
| using | regclass_iterator = const MCRegisterClass * |
Public Member Functions | |
| virtual unsigned | getNumSupportedRegs (const MachineFunction &) const |
| Return the number of registers for the function. (may overestimate) | |
| TypeSize | getRegSizeInBits (const TargetRegisterClass &RC) const |
| Return the size in bits of a register from class RC. | |
| unsigned | getSpillSize (const TargetRegisterClass &RC) const |
| Return the size in bytes of the stack slot allocated to hold a spilled copy of a register from class RC. | |
| Align | getSpillAlign (const TargetRegisterClass &RC) const |
| Return the minimum required alignment in bytes for a spill slot for a register of this class. | |
| bool | isTypeLegalForClass (const TargetRegisterClass &RC, MVT T) const |
| Return true if the given TargetRegisterClass has the ValueType T. | |
| bool | isTypeLegalForClass (const TargetRegisterClass &RC, LLT T) const |
| Return true if the given TargetRegisterClass is compatible with LLT T. | |
| vt_iterator | legalclasstypes_begin (const TargetRegisterClass &RC) const |
| Loop over all of the value types that can be represented by values in the given register class. | |
| vt_iterator | legalclasstypes_end (const TargetRegisterClass &RC) const |
| const TargetRegisterClass * | getMinimalPhysRegClass (MCRegister Reg, MVT VT=MVT::Other) const |
| Returns the Register Class of a physical register of the given type, picking the most sub register class of the right type that contains this physreg. | |
| const TargetRegisterClass * | getMinimalPhysRegClassLLT (MCRegister Reg, LLT Ty=LLT()) const |
| Returns the Register Class of a physical register of the given type, picking the most sub register class of the right type that contains this physreg. | |
| const TargetRegisterClass * | getAllocatableClass (const TargetRegisterClass *RC) const |
| Return the maximal subclass of the given register class that is allocatable or NULL. | |
| BitVector | getAllocatableSet (const MachineFunction &MF, const TargetRegisterClass *RC=nullptr) const |
| Returns a bitset indexed by register number indicating if a register is allocatable or not. | |
| ArrayRef< uint8_t > | getRegisterCosts (const MachineFunction &MF) const |
| Get a list of cost values for all registers that correspond to the index returned by RegisterCostTableIndex. | |
| bool | isInAllocatableClass (MCRegister RegNo) const |
| Return true if the register is in the allocation of any register class. | |
| const char * | getSubRegIndexName (unsigned SubIdx) const |
| Return the human-readable symbolic target-specific name for the specified SubRegIndex. | |
| unsigned | getSubRegIdxSize (unsigned Idx) const |
| Get the size of the bit range covered by a sub-register index. | |
| unsigned | getSubRegIdxOffset (unsigned Idx) const |
| Get the offset of the bit range covered by a sub-register index. | |
| LaneBitmask | getSubRegIndexLaneMask (unsigned SubIdx) const |
| Return a bitmask representing the parts of a register that are covered by SubIdx. | |
| bool | getCoveringSubRegIndexes (const MachineRegisterInfo &MRI, const TargetRegisterClass *RC, LaneBitmask LaneMask, SmallVectorImpl< unsigned > &Indexes) const |
Try to find one or more subregister indexes to cover LaneMask. | |
| LaneBitmask | getCoveringLanes () const |
| The lane masks returned by getSubRegIndexLaneMask() above can only be used to determine if sub-registers overlap - they can't be used to determine if a set of sub-registers completely cover another sub-register. | |
| bool | regsOverlap (Register RegA, Register RegB) const |
| Returns true if the two registers are equal or alias each other. | |
| bool | hasRegUnit (MCRegister Reg, Register RegUnit) const |
| Returns true if Reg contains RegUnit. | |
| virtual Register | lookThruCopyLike (Register SrcReg, const MachineRegisterInfo *MRI) const |
| Returns the original SrcReg unless it is the target of a copy-like operation, in which case we chain backwards through all such operations to the ultimate source register. | |
| virtual Register | lookThruSingleUseCopyChain (Register SrcReg, const MachineRegisterInfo *MRI) const |
| Find the original SrcReg unless it is the target of a copy-like operation, in which case we chain backwards through all such operations to the ultimate source register. | |
| virtual const MCPhysReg * | getCalleeSavedRegs (const MachineFunction *MF) const =0 |
| Return a null-terminated list of all of the callee-saved registers on this target. | |
| virtual const MCPhysReg * | getIPRACSRegs (const MachineFunction *MF) const |
| Return a null-terminated list of all of the callee-saved registers on this target when IPRA is on. | |
| virtual const uint32_t * | getCallPreservedMask (const MachineFunction &MF, CallingConv::ID) const |
| Return a mask of call-preserved registers for the given calling convention on the current function. | |
| virtual const uint32_t * | getCustomEHPadPreservedMask (const MachineFunction &MF) const |
| Return a register mask for the registers preserved by the unwinder, or nullptr if no custom mask is needed. | |
| virtual const uint32_t * | getNoPreservedMask () const |
| Return a register mask that clobbers everything. | |
| virtual ArrayRef< MCPhysReg > | getIntraCallClobberedRegs (const MachineFunction *MF) const |
| Return a list of all of the registers which are clobbered "inside" a call to the given function. | |
| bool | regmaskSubsetEqual (const uint32_t *mask0, const uint32_t *mask1) const |
Return true if all bits that are set in mask mask0 are also set in mask1. | |
| virtual ArrayRef< const uint32_t * > | getRegMasks () const =0 |
| Return all the call-preserved register masks defined for this target. | |
| virtual ArrayRef< const char * > | getRegMaskNames () const =0 |
| virtual BitVector | getReservedRegs (const MachineFunction &MF) const =0 |
| Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times, e.g. | |
| virtual std::optional< std::string > | explainReservedReg (const MachineFunction &MF, MCRegister PhysReg) const |
| Returns either a string explaining why the given register is reserved for this function, or an empty optional if no explanation has been written. | |
| virtual bool | isAsmClobberable (const MachineFunction &MF, MCRegister PhysReg) const |
| Returns false if we can't guarantee that Physreg, specified as an IR asm clobber constraint, will be preserved across the statement. | |
| virtual bool | isInlineAsmReadOnlyReg (const MachineFunction &MF, unsigned PhysReg) const |
| Returns true if PhysReg cannot be written to in inline asm statements. | |
| virtual bool | isConstantPhysReg (MCRegister PhysReg) const |
| Returns true if PhysReg is unallocatable and constant throughout the function. | |
| virtual bool | isDivergentRegClass (const TargetRegisterClass *RC) const |
| Returns true if the register class is considered divergent. | |
| virtual bool | isUniformReg (const MachineRegisterInfo &MRI, const RegisterBankInfo &RBI, Register Reg) const |
| Returns true if the register is considered uniform. | |
| virtual bool | shouldAnalyzePhysregInMachineLoopInfo (MCRegister R) const |
| Returns true if MachineLoopInfo should analyze the given physreg for loop invariance. | |
| virtual bool | isCallerPreservedPhysReg (MCRegister PhysReg, const MachineFunction &MF) const |
| Physical registers that may be modified within a function but are guaranteed to be restored before any uses. | |
| virtual bool | isCalleeSavedPhysReg (MCRegister PhysReg, const MachineFunction &MF) const |
| This is a wrapper around getCallPreservedMask(). | |
| virtual bool | isArgumentRegister (const MachineFunction &MF, MCRegister PhysReg) const |
| Returns true if PhysReg can be used as an argument to a function. | |
| virtual bool | isFixedRegister (const MachineFunction &MF, MCRegister PhysReg) const |
| Returns true if PhysReg is a fixed register. | |
| virtual bool | isGeneralPurposeRegister (const MachineFunction &MF, MCRegister PhysReg) const |
| Returns true if PhysReg is a general purpose register. | |
| virtual bool | isGeneralPurposeRegisterClass (const TargetRegisterClass *RC) const |
| Returns true if RC is a class/subclass of general purpose register. | |
| virtual void | adjustStackMapLiveOutMask (uint32_t *Mask) const |
| Prior to adding the live-out mask to a stackmap or patchpoint instruction, provide the target the opportunity to adjust it (mainly to remove pseudo-registers that should be ignored). | |
| MCRegister | getMatchingSuperReg (MCRegister Reg, unsigned SubIdx, const TargetRegisterClass *RC) const |
| Return a super-register of the specified register Reg so its sub-register of index SubIdx is Reg. | |
| virtual const TargetRegisterClass * | getMatchingSuperRegClass (const TargetRegisterClass *A, const TargetRegisterClass *B, unsigned Idx) const |
| Return a subclass of the specified register class A so that each register in it has a sub-register of the specified sub-register index which is in the specified register class B. | |
| virtual bool | shouldRewriteCopySrc (const TargetRegisterClass *DefRC, unsigned DefSubReg, const TargetRegisterClass *SrcRC, unsigned SrcSubReg) const |
| virtual const TargetRegisterClass * | getSubClassWithSubReg (const TargetRegisterClass *RC, unsigned Idx) const |
| Returns the largest legal sub-class of RC that supports the sub-register index Idx. | |
| virtual const TargetRegisterClass * | getSubRegisterClass (const TargetRegisterClass *SuperRC, unsigned SubRegIdx) const |
Return a register class that can be used for a subregister copy from/into SuperRC at SubRegIdx. | |
| unsigned | composeSubRegIndices (unsigned a, unsigned b) const |
| Return the subregister index you get from composing two subregister indices. | |
| LaneBitmask | composeSubRegIndexLaneMask (unsigned IdxA, LaneBitmask Mask) const |
| Transforms a LaneMask computed for one subregister to the lanemask that would have been computed when composing the subsubregisters with IdxA first. | |
| LaneBitmask | reverseComposeSubRegIndexLaneMask (unsigned IdxA, LaneBitmask LaneMask) const |
Transform a lanemask given for a virtual register to the corresponding lanemask before using subregister with index IdxA. | |
| virtual const TargetRegisterClass * | getPhysRegBaseClass (MCRegister Reg) const |
| Return target defined base register class for a physical register. | |
| const TargetRegisterClass * | getCommonSuperRegClass (const TargetRegisterClass *RCA, unsigned SubA, const TargetRegisterClass *RCB, unsigned SubB, unsigned &PreA, unsigned &PreB) const |
| Find a common super-register class if it exists. | |
| regclass_iterator | regclass_begin () const |
| Register class iterators. | |
| regclass_iterator | regclass_end () const |
| iterator_range< regclass_iterator > | regclasses () const |
| unsigned | getNumRegClasses () const |
| const TargetRegisterClass * | getRegClass (unsigned i) const |
| Returns the register class associated with the enumeration value. | |
| const char * | getRegClassName (const TargetRegisterClass *Class) const |
| Returns the name of the register class. | |
| const TargetRegisterClass * | getCommonSubClass (const TargetRegisterClass *A, const TargetRegisterClass *B) const |
| Find the largest common subclass of A and B. | |
| virtual const TargetRegisterClass * | getPointerRegClass (const MachineFunction &MF, unsigned Kind=0) const |
| Returns a TargetRegisterClass used for pointer values. | |
| virtual const TargetRegisterClass * | getCrossCopyRegClass (const TargetRegisterClass *RC) const |
| Returns a legal register class to copy a register in the specified class to or from. | |
| virtual const TargetRegisterClass * | getLargestLegalSuperClass (const TargetRegisterClass *RC, const MachineFunction &) const |
| Returns the largest super class of RC that is legal to use in the current sub-target and has the same spill size. | |
| virtual unsigned | getRegPressureLimit (const TargetRegisterClass *RC, MachineFunction &MF) const |
| Return the register pressure "high water mark" for the specific register class. | |
| virtual unsigned | getRegPressureSetScore (const MachineFunction &MF, unsigned PSetID) const |
| Return a heuristic for the machine scheduler to compare the profitability of increasing one register pressure set versus another. | |
| virtual const RegClassWeight & | getRegClassWeight (const TargetRegisterClass *RC) const =0 |
| Get the weight in units of pressure for this register class. | |
| TypeSize | getRegSizeInBits (Register Reg, const MachineRegisterInfo &MRI) const |
| Returns size in bits of a phys/virtual/generic register. | |
| virtual unsigned | getRegUnitWeight (unsigned RegUnit) const =0 |
| Get the weight in units of pressure for this register unit. | |
| virtual unsigned | getNumRegPressureSets () const =0 |
| Get the number of dimensions of register pressure. | |
| virtual const char * | getRegPressureSetName (unsigned Idx) const =0 |
| Get the name of this register unit pressure set. | |
| virtual unsigned | getRegPressureSetLimit (const MachineFunction &MF, unsigned Idx) const =0 |
| Get the register unit pressure limit for this dimension. | |
| virtual const int * | getRegClassPressureSets (const TargetRegisterClass *RC) const =0 |
| Get the dimensions of register pressure impacted by this register class. | |
| virtual const int * | getRegUnitPressureSets (unsigned RegUnit) const =0 |
| Get the dimensions of register pressure impacted by this register unit. | |
| virtual bool | getRegAllocationHints (Register VirtReg, ArrayRef< MCPhysReg > Order, SmallVectorImpl< MCPhysReg > &Hints, const MachineFunction &MF, const VirtRegMap *VRM=nullptr, const LiveRegMatrix *Matrix=nullptr) const |
| Get a list of 'hint' registers that the register allocator should try first when allocating a physical register for the virtual register VirtReg. | |
| virtual void | updateRegAllocHint (Register Reg, Register NewReg, MachineFunction &MF) const |
| A callback to allow target a chance to update register allocation hints when a register is "changed" (e.g. | |
| virtual bool | reverseLocalAssignment () const |
| Allow the target to reverse allocation order of local live ranges. | |
| virtual unsigned | getCSRFirstUseCost () const |
| Allow the target to override the cost of using a callee-saved register for the first time. | |
| virtual bool | requiresRegisterScavenging (const MachineFunction &MF) const |
| Returns true if the target requires (and can make use of) the register scavenger. | |
| virtual bool | useFPForScavengingIndex (const MachineFunction &MF) const |
| Returns true if the target wants to use frame pointer based accesses to spill to the scavenger emergency spill slot. | |
| virtual bool | requiresFrameIndexScavenging (const MachineFunction &MF) const |
| Returns true if the target requires post PEI scavenging of registers for materializing frame index constants. | |
| virtual bool | requiresFrameIndexReplacementScavenging (const MachineFunction &MF) const |
| Returns true if the target requires using the RegScavenger directly for frame elimination despite using requiresFrameIndexScavenging. | |
| virtual bool | requiresVirtualBaseRegisters (const MachineFunction &MF) const |
| Returns true if the target wants the LocalStackAllocation pass to be run and virtual base registers used for more efficient stack access. | |
| virtual bool | hasReservedSpillSlot (const MachineFunction &MF, Register Reg, int &FrameIdx) const |
| Return true if target has reserved a spill slot in the stack frame of the given function for the specified register. | |
| virtual bool | trackLivenessAfterRegAlloc (const MachineFunction &MF) const |
| Returns true if the live-ins should be tracked after register allocation. | |
| virtual bool | canRealignStack (const MachineFunction &MF) const |
| True if the stack can be realigned for the target. | |
| virtual bool | shouldRealignStack (const MachineFunction &MF) const |
| True if storage within the function requires the stack pointer to be aligned more than the normal calling convention calls for. | |
| bool | hasStackRealignment (const MachineFunction &MF) const |
| True if stack realignment is required and still possible. | |
| virtual int64_t | getFrameIndexInstrOffset (const MachineInstr *MI, int Idx) const |
| Get the offset from the referenced frame index in the instruction, if there is one. | |
| virtual bool | needsFrameBaseReg (MachineInstr *MI, int64_t Offset) const |
| Returns true if the instruction's frame index reference would be better served by a base register other than FP or SP. | |
| virtual Register | materializeFrameBaseRegister (MachineBasicBlock *MBB, int FrameIdx, int64_t Offset) const |
| Insert defining instruction(s) for a pointer to FrameIdx before insertion point I. | |
| virtual void | resolveFrameIndex (MachineInstr &MI, Register BaseReg, int64_t Offset) const |
| Resolve a frame index operand of an instruction to reference the indicated base register plus offset instead. | |
| virtual bool | isFrameOffsetLegal (const MachineInstr *MI, Register BaseReg, int64_t Offset) const |
| Determine whether a given base register plus offset immediate is encodable to resolve a frame index. | |
| virtual void | getOffsetOpcodes (const StackOffset &Offset, SmallVectorImpl< uint64_t > &Ops) const |
Gets the DWARF expression opcodes for Offset. | |
| DIExpression * | prependOffsetExpression (const DIExpression *Expr, unsigned PrependFlags, const StackOffset &Offset) const |
Prepends a DWARF expression for Offset to DIExpression Expr. | |
| virtual bool | saveScavengerRegister (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, MachineBasicBlock::iterator &UseMI, const TargetRegisterClass *RC, Register Reg) const |
| Spill the register so it can be used by the register scavenger. | |
| virtual bool | eliminateFrameIndicesBackwards () const |
| Process frame indices in reverse block order. | |
| virtual bool | eliminateFrameIndex (MachineBasicBlock::iterator MI, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const =0 |
| This method must be overriden to eliminate abstract frame indices from instructions which may use them. | |
| virtual StringRef | getRegAsmName (MCRegister Reg) const |
Return the assembly name for Reg. | |
| virtual bool | shouldCoalesce (MachineInstr *MI, const TargetRegisterClass *SrcRC, unsigned SubReg, const TargetRegisterClass *DstRC, unsigned DstSubReg, const TargetRegisterClass *NewRC, LiveIntervals &LIS) const |
| Subtarget Hooks. | |
| virtual bool | shouldRegionSplitForVirtReg (const MachineFunction &MF, const LiveInterval &VirtReg) const |
| Region split has a high compile time cost especially for large live range. | |
| virtual bool | shouldUseLastChanceRecoloringForVirtReg (const MachineFunction &MF, const LiveInterval &VirtReg) const |
| Last chance recoloring has a high compile time cost especially for targets with a lot of registers. | |
| virtual bool | shouldUseDeferredSpillingForVirtReg (const MachineFunction &MF, const LiveInterval &VirtReg) const |
| Deferred spilling delays the spill insertion of a virtual register after every other allocation. | |
| virtual bool | regClassPriorityTrumpsGlobalness (const MachineFunction &MF) const |
| When prioritizing live ranges in register allocation, if this hook returns true then the AllocationPriority of the register class will be treated as more important than whether the range is local to a basic block or global. | |
| virtual Register | getFrameRegister (const MachineFunction &MF) const =0 |
| Debug information queries. | |
| void | markSuperRegs (BitVector &RegisterSet, MCRegister Reg) const |
| Mark a register and all its aliases as reserved in the given set. | |
| bool | checkAllSuperRegsMarked (const BitVector &RegisterSet, ArrayRef< MCPhysReg > Exceptions=ArrayRef< MCPhysReg >()) const |
| Returns true if for every register in the set all super registers are part of the set as well. | |
| virtual const TargetRegisterClass * | getConstrainedRegClassForOperand (const MachineOperand &MO, const MachineRegisterInfo &MRI) const |
| MCRegister | getSubReg (MCRegister Reg, unsigned Idx) const |
| Returns the physical register number of sub-register "Index" for physical register RegNo. | |
| virtual bool | isNonallocatableRegisterCalleeSave (MCRegister Reg) const |
| Some targets have non-allocatable registers that aren't technically part of the explicit callee saved register list, but should be handled as such in certain cases. | |
| virtual std::optional< uint8_t > | getVRegFlagValue (StringRef Name) const |
| virtual SmallVector< StringLiteral > | getVRegFlagsOfReg (Register Reg, const MachineFunction &MF) const |
| Public Member Functions inherited from llvm::MCRegisterInfo | |
| iterator_range< MCSubRegIterator > | subregs (MCRegister Reg) const |
Return an iterator range over all sub-registers of Reg, excluding Reg. | |
| iterator_range< MCSubRegIterator > | subregs_inclusive (MCRegister Reg) const |
Return an iterator range over all sub-registers of Reg, including Reg. | |
| iterator_range< MCSuperRegIterator > | superregs (MCRegister Reg) const |
Return an iterator range over all super-registers of Reg, excluding Reg. | |
| iterator_range< MCSuperRegIterator > | superregs_inclusive (MCRegister Reg) const |
Return an iterator range over all super-registers of Reg, including Reg. | |
| detail::concat_range< const MCPhysReg, iterator_range< MCSubRegIterator >, iterator_range< MCSuperRegIterator > > | sub_and_superregs_inclusive (MCRegister Reg) const |
Return an iterator range over all sub- and super-registers of Reg, including Reg. | |
| iterator_range< MCRegUnitIterator > | regunits (MCRegister Reg) const |
Returns an iterator range over all regunits for Reg. | |
| virtual | ~MCRegisterInfo () |
| void | InitMCRegisterInfo (const MCRegisterDesc *D, unsigned NR, unsigned RA, unsigned PC, const MCRegisterClass *C, unsigned NC, const MCPhysReg(*RURoots)[2], unsigned NRU, const int16_t *DL, const LaneBitmask *RUMS, const char *Strings, const char *ClassStrings, const uint16_t *SubIndices, unsigned NumIndices, const uint16_t *RET) |
| Initialize MCRegisterInfo, called by TableGen auto-generated routines. | |
| void | mapLLVMRegsToDwarfRegs (const DwarfLLVMRegPair *Map, unsigned Size, bool isEH) |
| Used to initialize LLVM register to Dwarf register number mapping. | |
| void | mapDwarfRegsToLLVMRegs (const DwarfLLVMRegPair *Map, unsigned Size, bool isEH) |
| Used to initialize Dwarf register to LLVM register number mapping. | |
| void | mapLLVMRegToSEHReg (MCRegister LLVMReg, int SEHReg) |
| mapLLVMRegToSEHReg - Used to initialize LLVM register to SEH register number mapping. | |
| void | mapLLVMRegToCVReg (MCRegister LLVMReg, int CVReg) |
| MCRegister | getRARegister () const |
| This method should return the register where the return address can be found. | |
| MCRegister | getProgramCounter () const |
| Return the register which is the program counter. | |
| const MCRegisterDesc & | operator[] (MCRegister Reg) const |
| const MCRegisterDesc & | get (MCRegister Reg) const |
| Provide a get method, equivalent to [], but more useful with a pointer to this object. | |
| MCRegister | getSubReg (MCRegister Reg, unsigned Idx) const |
| Returns the physical register number of sub-register "Index" for physical register RegNo. | |
| MCRegister | getMatchingSuperReg (MCRegister Reg, unsigned SubIdx, const MCRegisterClass *RC) const |
| Return a super-register of the specified register Reg so its sub-register of index SubIdx is Reg. | |
| unsigned | getSubRegIndex (MCRegister RegNo, MCRegister SubRegNo) const |
| For a given register pair, return the sub-register index if the second register is a sub-register of the first. | |
| const char * | getName (MCRegister RegNo) const |
| Return the human-readable symbolic target-specific name for the specified physical register. | |
| bool | isConstant (MCRegister RegNo) const |
| Returns true if the given register is constant. | |
| bool | isArtificial (MCRegister RegNo) const |
| Returns true if the given register is artificial, which means it represents a regunit that is not separately addressable but still needs to be modelled, such as the top 16-bits of a 32-bit GPR. | |
| bool | isArtificialRegUnit (MCRegUnit Unit) const |
| Returns true when the given register unit is considered artificial. | |
| unsigned | getNumRegs () const |
| Return the number of registers this target has (useful for sizing arrays holding per register information) | |
| unsigned | getNumSubRegIndices () const |
| Return the number of sub-register indices understood by the target. | |
| unsigned | getNumRegUnits () const |
| Return the number of (native) register units in the target. | |
| virtual int64_t | getDwarfRegNum (MCRegister RegNum, bool isEH) const |
| Map a target register to an equivalent dwarf register number. | |
| std::optional< MCRegister > | getLLVMRegNum (uint64_t RegNum, bool isEH) const |
| Map a dwarf register back to a target register. | |
| int64_t | getDwarfRegNumFromDwarfEHRegNum (uint64_t RegNum) const |
| Map a target EH register number to an equivalent DWARF register number. | |
| int | getSEHRegNum (MCRegister RegNum) const |
| Map a target register to an equivalent SEH register number. | |
| int | getCodeViewRegNum (MCRegister RegNum) const |
| Map a target register to an equivalent CodeView register number. | |
| regclass_iterator | regclass_begin () const |
| regclass_iterator | regclass_end () const |
| iterator_range< regclass_iterator > | regclasses () const |
| unsigned | getNumRegClasses () const |
| const MCRegisterClass & | getRegClass (unsigned i) const |
| Returns the register class associated with the enumeration value. | |
| const char * | getRegClassName (const MCRegisterClass *Class) const |
| uint16_t | getEncodingValue (MCRegister Reg) const |
| Returns the encoding for Reg. | |
| bool | isSubRegister (MCRegister RegA, MCRegister RegB) const |
| Returns true if RegB is a sub-register of RegA. | |
| bool | isSuperRegister (MCRegister RegA, MCRegister RegB) const |
| Returns true if RegB is a super-register of RegA. | |
| bool | isSubRegisterEq (MCRegister RegA, MCRegister RegB) const |
| Returns true if RegB is a sub-register of RegA or if RegB == RegA. | |
| bool | isSuperRegisterEq (MCRegister RegA, MCRegister RegB) const |
| Returns true if RegB is a super-register of RegA or if RegB == RegA. | |
| bool | isSuperOrSubRegisterEq (MCRegister RegA, MCRegister RegB) const |
| Returns true if RegB is a super-register or sub-register of RegA or if RegB == RegA. | |
| bool | regsOverlap (MCRegister RegA, MCRegister RegB) const |
| Returns true if the two registers are equal or alias each other. | |
Static Public Member Functions | |
| static void | dumpReg (Register Reg, unsigned SubRegIndex=0, const TargetRegisterInfo *TRI=nullptr) |
| Debugging helper: dump register in human readable form to dbgs() stream. | |
Protected Member Functions | |
| TargetRegisterInfo (const TargetRegisterInfoDesc *ID, regclass_iterator RCB, regclass_iterator RCE, const char *const *SRINames, const SubRegCoveredBits *SubIdxRanges, const LaneBitmask *SRILaneMasks, LaneBitmask CoveringLanes, const RegClassInfo *const RCIs, const MVT::SimpleValueType *const RCVTLists, unsigned Mode=0) | |
| virtual | ~TargetRegisterInfo () |
| virtual unsigned | composeSubRegIndicesImpl (unsigned, unsigned) const |
| Overridden by TableGen in targets that have sub-registers. | |
| virtual LaneBitmask | composeSubRegIndexLaneMaskImpl (unsigned, LaneBitmask) const |
| Overridden by TableGen in targets that have sub-registers. | |
| virtual LaneBitmask | reverseComposeSubRegIndexLaneMaskImpl (unsigned, LaneBitmask) const |
| virtual unsigned | getRegisterCostTableIndex (const MachineFunction &MF) const |
| Return the register cost table index. | |
| const RegClassInfo & | getRegClassInfo (const TargetRegisterClass &RC) const |
Detailed Description
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDesc objects that represent all of the machine registers that the target has.
As such, we simply have to track a pointer to this array so that we can turn register number into a register descriptor.
Definition at line 235 of file TargetRegisterInfo.h.
Member Typedef Documentation
◆ regclass_iterator
Definition at line 237 of file TargetRegisterInfo.h.
◆ vt_iterator
Definition at line 238 of file TargetRegisterInfo.h.
Constructor & Destructor Documentation
◆ TargetRegisterInfo()
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protected |
Definition at line 52 of file TargetRegisterInfo.cpp.
◆ ~TargetRegisterInfo()
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protectedvirtualdefault |
Member Function Documentation
◆ adjustStackMapLiveOutMask()
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inlinevirtual |
Prior to adding the live-out mask to a stackmap or patchpoint instruction, provide the target the opportunity to adjust it (mainly to remove pseudo-registers that should be ignored).
Definition at line 649 of file TargetRegisterInfo.h.
◆ canRealignStack()
|
virtual |
True if the stack can be realigned for the target.
Definition at line 478 of file TargetRegisterInfo.cpp.
References llvm::MachineFunction::getFrameInfo(), and llvm::MachineFrameInfo::isStackRealignable().
Referenced by llvm::ARMBaseRegisterInfo::canRealignStack(), llvm::LoongArchRegisterInfo::canRealignStack(), llvm::M68kRegisterInfo::canRealignStack(), llvm::MipsRegisterInfo::canRealignStack(), llvm::X86RegisterInfo::canRealignStack(), and hasStackRealignment().
◆ checkAllSuperRegsMarked()
| bool TargetRegisterInfo::checkAllSuperRegsMarked | ( | const BitVector & | RegisterSet, |
| ArrayRef< MCPhysReg > | Exceptions = ArrayRef<MCPhysReg>() |
||
| ) | const |
Returns true if for every register in the set all super registers are part of the set as well.
Definition at line 82 of file TargetRegisterInfo.cpp.
References llvm::dbgs(), llvm::MCRegisterInfo::getNumRegs(), llvm::is_contained(), llvm::printReg(), llvm::BitVector::set(), and llvm::MCRegisterInfo::superregs().
◆ composeSubRegIndexLaneMask()
|
inline |
Transforms a LaneMask computed for one subregister to the lanemask that would have been computed when composing the subsubregisters with IdxA first.
- See also
- composeSubRegIndices()
Definition at line 724 of file TargetRegisterInfo.h.
References composeSubRegIndexLaneMaskImpl().
Referenced by llvm::rdf::PhysicalRegisterInfo::mapTo(), llvm::DeadLaneDetector::transferDefinedLanes(), and llvm::DeadLaneDetector::transferUsedLanes().
◆ composeSubRegIndexLaneMaskImpl()
|
inlineprotectedvirtual |
Overridden by TableGen in targets that have sub-registers.
Definition at line 765 of file TargetRegisterInfo.h.
References llvm_unreachable.
Referenced by composeSubRegIndexLaneMask().
◆ composeSubRegIndices()
Return the subregister index you get from composing two subregister indices.
The special null sub-register index composes as the identity.
If R:a:b is the same register as R:c, then composeSubRegIndices(a, b) returns c. Note that composeSubRegIndices does not tell you about illegal compositions. If R does not have a subreg a, or R:a does not have a subreg b, composeSubRegIndices doesn't tell you.
The ARM register Q0 has two D subregs dsub_0:D0 and dsub_1:D1. It also has ssub_0:S0 - ssub_3:S3 subregs. If you compose subreg indices dsub_1, ssub_0 you get ssub_2.
Definition at line 715 of file TargetRegisterInfo.h.
References composeSubRegIndicesImpl().
Referenced by getCommonSuperRegClass().
◆ composeSubRegIndicesImpl()
|
inlineprotectedvirtual |
Overridden by TableGen in targets that have sub-registers.
Definition at line 759 of file TargetRegisterInfo.h.
References llvm_unreachable.
Referenced by composeSubRegIndices().
◆ dumpReg()
|
static |
Debugging helper: dump register in human readable form to dbgs() stream.
Definition at line 679 of file TargetRegisterInfo.cpp.
References llvm::dbgs(), llvm::printReg(), and TRI.
◆ eliminateFrameIndex()
|
pure virtual |
This method must be overriden to eliminate abstract frame indices from instructions which may use them.
The instruction referenced by the iterator contains an MO_FrameIndex operand which must be eliminated by this method. This method may modify or replace the specified instruction, as long as it keeps the iterator pointing at the finished product. SPAdj is the SP adjustment due to call frame setup instruction. FIOperandNum is the FI operand number. Returns true if the current instruction was removed and the iterator is not longer valid
◆ eliminateFrameIndicesBackwards()
|
inlinevirtual |
Process frame indices in reverse block order.
This changes the behavior of the RegScavenger passed to eliminateFrameIndex. If this is true targets should scavengeRegisterBackwards in eliminateFrameIndex. New targets should prefer reverse scavenging behavior. TODO: Remove this when all targets return true.
Definition at line 1096 of file TargetRegisterInfo.h.
◆ explainReservedReg()
|
inlinevirtual |
Returns either a string explaining why the given register is reserved for this function, or an empty optional if no explanation has been written.
The absence of an explanation does not mean that the register is not reserved (meaning, you should check that PhysReg is in fact reserved before calling this).
Definition at line 569 of file TargetRegisterInfo.h.
◆ getAllocatableClass()
| const TargetRegisterClass * TargetRegisterInfo::getAllocatableClass | ( | const TargetRegisterClass * | RC | ) | const |
Return the maximal subclass of the given register class that is allocatable or NULL.
getAllocatableClass - Return the maximal subclass of the given register class that is alloctable, or NULL.
Definition at line 191 of file TargetRegisterInfo.cpp.
References getRegClass(), llvm::TargetRegisterClass::getSubClassMask(), llvm::TargetRegisterClass::isAllocatable(), and llvm::BitMaskClassIterator::isValid().
Referenced by getAllocatableSet(), and llvm::SIInstrInfo::reMaterialize().
◆ getAllocatableSet()
| BitVector TargetRegisterInfo::getAllocatableSet | ( | const MachineFunction & | MF, |
| const TargetRegisterClass * | RC = nullptr |
||
| ) | const |
Returns a bitset indexed by register number indicating if a register is allocatable or not.
If a register class is specified, returns the subset for the class.
Definition at line 252 of file TargetRegisterInfo.cpp.
References llvm::CallingConv::C, getAllocatableClass(), getAllocatableSetForRC(), llvm::MCRegisterInfo::getNumRegs(), llvm::MachineFunction::getRegInfo(), MRI, regclasses(), llvm::Reserved, and llvm::BitVector::reset().
Referenced by addLiveInRegs(), llvm::AggressiveAntiDepBreaker::AggressiveAntiDepBreaker(), and llvm::Thumb1InstrInfo::copyPhysReg().
◆ getCalleeSavedRegs()
|
pure virtual |
Return a null-terminated list of all of the callee-saved registers on this target.
The register should be in the order of desired callee-save stack frame offset. The first register is closest to the incoming stack pointer if stack grows down, and vice versa. Notice: This function does not take into account disabled CSRs. In most cases you will want to use instead the function getCalleeSavedRegs that is implemented in MachineRegisterInfo.
Referenced by llvm::MachineRegisterInfo::getCalleeSavedRegs().
◆ getCallPreservedMask()
|
inlinevirtual |
Return a mask of call-preserved registers for the given calling convention on the current function.
The mask should include all call-preserved aliases. This is used by the register allocator to determine which registers can be live across a call.
The mask is an array containing (TRI::getNumRegs()+31)/32 entries. A set bit indicates that all bits of the corresponding register are preserved across the function call. The bit mask is expected to be sub-register complete, i.e. if A is preserved, so are all its sub-registers.
Bits are numbered from the LSB, so the bit for physical register Reg can be found as (Mask[Reg / 32] >> Reg % 32) & 1.
A NULL pointer means that no register mask will be used, and call instructions should use implicit-def operands to indicate call clobbered registers.
Definition at line 517 of file TargetRegisterInfo.h.
Referenced by isCalleeSavedPhysReg(), and llvm::FastISel::selectPatchpoint().
◆ getCommonSubClass()
| const TargetRegisterClass * TargetRegisterInfo::getCommonSubClass | ( | const TargetRegisterClass * | A, |
| const TargetRegisterClass * | B | ||
| ) | const |
Find the largest common subclass of A and B.
Return NULL if there is no common subclass.
Definition at line 285 of file TargetRegisterInfo.cpp.
References A, B, and firstCommonClass().
Referenced by llvm::LiveStacks::getOrCreateInterval().
◆ getCommonSuperRegClass()
| const TargetRegisterClass * TargetRegisterInfo::getCommonSuperRegClass | ( | const TargetRegisterClass * | RCA, |
| unsigned | SubA, | ||
| const TargetRegisterClass * | RCB, | ||
| unsigned | SubB, | ||
| unsigned & | PreA, | ||
| unsigned & | PreB | ||
| ) | const |
Find a common super-register class if it exists.
Find a register class, SuperRC and two sub-register indices, PreA and PreB, such that:
- PreA + SubA == PreB + SubB (using composeSubRegIndices()), and
- For all Reg in SuperRC: Reg:PreA in RCA and Reg:PreB in RCB, and
- SuperRC->getSize() >= max(RCA->getSize(), RCB->getSize()).
SuperRC will be chosen such that no super-class of SuperRC satisfies the requirements, and there is no register class with a smaller spill size that satisfies the requirements.
SubA and SubB must not be 0. Use getMatchingSuperRegClass() instead.
Either of the PreA and PreB sub-register indices may be returned as 0. In that case, the returned register class will be a sub-class of the corresponding argument register class.
The function returns NULL if no register class can be found.
Definition at line 314 of file TargetRegisterInfo.cpp.
References assert(), composeSubRegIndices(), firstCommonClass(), getRegSizeInBits(), and std::swap().
◆ getConstrainedRegClassForOperand()
|
inlinevirtual |
Definition at line 1195 of file TargetRegisterInfo.h.
◆ getCoveringLanes()
|
inline |
The lane masks returned by getSubRegIndexLaneMask() above can only be used to determine if sub-registers overlap - they can't be used to determine if a set of sub-registers completely cover another sub-register.
The X86 general purpose registers have two lanes corresponding to the sub_8bit and sub_8bit_hi sub-registers. Both sub_32bit and sub_16bit have lane masks '3', but the sub_16bit sub-register doesn't fully cover the sub_32bit sub-register.
On the other hand, the ARM NEON lanes fully cover their registers: The dsub_0 sub-register is completely covered by the ssub_0 and ssub_1 lanes. This is related to the CoveredBySubRegs property on register definitions.
This function returns a bit mask of lanes that completely cover their sub-registers. More precisely, given:
Covering = getCoveringLanes(); MaskA = getSubRegIndexLaneMask(SubA); MaskB = getSubRegIndexLaneMask(SubB);
If (MaskA & ~(MaskB & Covering)) == 0, then SubA is completely covered by SubB.
Definition at line 442 of file TargetRegisterInfo.h.
Referenced by readsLaneSubset().
◆ getCoveringSubRegIndexes()
| bool TargetRegisterInfo::getCoveringSubRegIndexes | ( | const MachineRegisterInfo & | MRI, |
| const TargetRegisterClass * | RC, | ||
| LaneBitmask | LaneMask, | ||
| SmallVectorImpl< unsigned > & | Indexes | ||
| ) | const |
Try to find one or more subregister indexes to cover LaneMask.
If this is possible, returns true and appends the best matching set of indexes to Indexes. If this is not possible, returns false.
Definition at line 517 of file TargetRegisterInfo.cpp.
References llvm::LaneBitmask::any(), llvm::LaneBitmask::getNumLanes(), llvm::MCRegisterInfo::getNumSubRegIndices(), getSubClassWithSubReg(), getSubRegIndexLaneMask(), Idx, and llvm::SmallVectorTemplateBase< T, bool >::push_back().
◆ getCrossCopyRegClass()
|
inlinevirtual |
Returns a legal register class to copy a register in the specified class to or from.
If it is possible to copy the register directly without using a cross register class copy, return the specified RC. Returns NULL if it is not possible to copy between two registers of the specified class.
Definition at line 860 of file TargetRegisterInfo.h.
◆ getCSRFirstUseCost()
|
inlinevirtual |
Allow the target to override the cost of using a callee-saved register for the first time.
Default value of 0 means we will use a callee-saved register if it is available.
Definition at line 971 of file TargetRegisterInfo.h.
◆ getCustomEHPadPreservedMask()
|
inlinevirtual |
Return a register mask for the registers preserved by the unwinder, or nullptr if no custom mask is needed.
Definition at line 526 of file TargetRegisterInfo.h.
◆ getFrameIndexInstrOffset()
|
inlinevirtual |
Get the offset from the referenced frame index in the instruction, if there is one.
Definition at line 1034 of file TargetRegisterInfo.h.
◆ getFrameRegister()
|
pure virtual |
Debug information queries.
getFrameRegister - This method should return the register used as a base for values allocated in the current stack frame.
Referenced by llvm::MipsAsmPrinter::emitFrameDirective(), llvm::TargetFrameLowering::getDwarfFrameBase(), llvm::X86FrameLowering::getDwarfFrameBase(), llvm::TargetFrameLowering::getFrameIndexReference(), llvm::LoongArchFrameLowering::getFrameIndexReference(), llvm::RISCVFrameLowering::getFrameIndexReference(), and TransferTracker::isEntryValueValue().
◆ getIntraCallClobberedRegs()
|
inlinevirtual |
Return a list of all of the registers which are clobbered "inside" a call to the given function.
For example, these might be needed for PLT sequences of long-branch veneers.
Definition at line 539 of file TargetRegisterInfo.h.
◆ getIPRACSRegs()
|
inlinevirtual |
Return a null-terminated list of all of the callee-saved registers on this target when IPRA is on.
The list should include any non-allocatable registers that the backend uses and assumes will be saved by all calling conventions. This is typically the ISA-standard frame pointer, but could include the thread pointer, TOC pointer, or base pointer for different targets.
Definition at line 495 of file TargetRegisterInfo.h.
◆ getLargestLegalSuperClass()
|
inlinevirtual |
Returns the largest super class of RC that is legal to use in the current sub-target and has the same spill size.
The returned register class can be used to create virtual registers which means that all its registers can be copied and spilled.
The default implementation is very conservative and doesn't allow the register allocator to inflate register classes.
Definition at line 869 of file TargetRegisterInfo.h.
Referenced by llvm::SIRegisterInfo::getLargestLegalSuperClass(), llvm::PPCRegisterInfo::getLargestLegalSuperClass(), and llvm::MachineRegisterInfo::recomputeRegClass().
◆ getMatchingSuperReg()
|
inline |
Return a super-register of the specified register Reg so its sub-register of index SubIdx is Reg.
Definition at line 653 of file TargetRegisterInfo.h.
References llvm::MCRegisterInfo::getMatchingSuperReg(), llvm::TargetRegisterClass::MC, and Reg.
◆ getMatchingSuperRegClass()
|
virtual |
Return a subclass of the specified register class A so that each register in it has a sub-register of the specified sub-register index which is in the specified register class B.
TableGen will synthesize missing A sub-classes.
Definition at line 299 of file TargetRegisterInfo.cpp.
References A, assert(), B, firstCommonClass(), Idx, and llvm::SuperRegClassIterator::isValid().
◆ getMinimalPhysRegClass()
| const TargetRegisterClass * TargetRegisterInfo::getMinimalPhysRegClass | ( | MCRegister | Reg, |
| MVT | VT = MVT::Other |
||
| ) | const |
Returns the Register Class of a physical register of the given type, picking the most sub register class of the right type that contains this physreg.
getMinimalPhysRegClass - Returns the Register Class of a physical register of the given type, picking the most sub register class of the right type that contains this physreg.
Definition at line 208 of file TargetRegisterInfo.cpp.
References assert(), llvm::TargetRegisterClass::hasSubClass(), llvm::Register::isPhysicalRegister(), isTypeLegalForClass(), and regclasses().
Referenced by llvm::AArch64FrameLowering::assignCalleeSavedSpillSlots(), llvm::RISCVFrameLowering::assignCalleeSavedSpillSlots(), llvm::BitTracker::MachineEvaluator::getPhysRegBitWidth(), llvm::HexagonEvaluator::getPhysRegBitWidth(), and getRegSizeInBits().
◆ getMinimalPhysRegClassLLT()
| const TargetRegisterClass * TargetRegisterInfo::getMinimalPhysRegClassLLT | ( | MCRegister | Reg, |
| LLT | Ty = LLT() |
||
| ) | const |
Returns the Register Class of a physical register of the given type, picking the most sub register class of the right type that contains this physreg.
If there is no register class compatible with the given type, returns nullptr.
Definition at line 226 of file TargetRegisterInfo.cpp.
References assert(), llvm::TargetRegisterClass::hasSubClass(), llvm::Register::isPhysicalRegister(), isTypeLegalForClass(), llvm::LLT::isValid(), and regclasses().
◆ getNoPreservedMask()
Return a register mask that clobbers everything.
Definition at line 531 of file TargetRegisterInfo.h.
References llvm_unreachable.
◆ getNumRegClasses()
|
inline |
Definition at line 825 of file TargetRegisterInfo.h.
References regclass_begin(), and regclass_end().
Referenced by getRegClass(), getRegClassInfo(), llvm::ResourcePriorityQueue::ResourcePriorityQueue(), and llvm::RegisterClassInfo::runOnMachineFunction().
◆ getNumRegPressureSets()
|
pure virtual |
Get the number of dimensions of register pressure.
Referenced by llvm::RegPressureTracker::init(), llvm::RegPressureTracker::initLiveThru(), and llvm::RegisterClassInfo::runOnMachineFunction().
◆ getNumSupportedRegs()
|
inlinevirtual |
Return the number of registers for the function. (may overestimate)
Definition at line 278 of file TargetRegisterInfo.h.
References llvm::MCRegisterInfo::getNumRegs().
◆ getOffsetOpcodes()
|
virtual |
Gets the DWARF expression opcodes for Offset.
Definition at line 652 of file TargetRegisterInfo.cpp.
References llvm::DIExpression::appendOffset(), assert(), and llvm::Offset.
Referenced by LiveDebugValues::MLocTracker::emitLoc(), and prependOffsetExpression().
◆ getPhysRegBaseClass()
|
inlinevirtual |
Return target defined base register class for a physical register.
This is the register class with the lowest BaseClassOrder containing the register. Will be nullptr if the register is not in any base register class.
Definition at line 753 of file TargetRegisterInfo.h.
◆ getPointerRegClass()
|
inlinevirtual |
Returns a TargetRegisterClass used for pointer values.
If a target supports multiple different pointer register classes, kind specifies which one is indicated.
Definition at line 851 of file TargetRegisterInfo.h.
References llvm_unreachable.
◆ getRegAllocationHints()
|
virtual |
Get a list of 'hint' registers that the register allocator should try first when allocating a physical register for the virtual register VirtReg.
These registers are effectively moved to the front of the allocation order. If true is returned, regalloc will try to only use hints to the greatest extent possible even if it means spilling.
The Order argument is the allocation order for VirtReg's register class as returned from RegisterClassInfo::getOrder(). The hint registers must come from Order, and they must not be reserved.
The default implementation of this function will only add target independent register allocation hints. Targets that override this function should typically call this default implementation as well and expect to see generic copy hints added.
Definition at line 418 of file TargetRegisterInfo.cpp.
References llvm::VirtRegMap::getPhys(), llvm::MachineFunction::getRegInfo(), llvm::SmallSet< T, N, C >::insert(), llvm::is_contained(), llvm::Register::isPhysical(), llvm::Register::isVirtual(), MRI, and llvm::SmallVectorTemplateBase< T, bool >::push_back().
Referenced by llvm::AArch64RegisterInfo::getRegAllocationHints(), llvm::ARMBaseRegisterInfo::getRegAllocationHints(), llvm::PPCRegisterInfo::getRegAllocationHints(), llvm::RISCVRegisterInfo::getRegAllocationHints(), llvm::SystemZRegisterInfo::getRegAllocationHints(), and llvm::X86RegisterInfo::getRegAllocationHints().
◆ getRegAsmName()
|
inlinevirtual |
Return the assembly name for Reg.
Definition at line 1112 of file TargetRegisterInfo.h.
References llvm::MCRegisterInfo::getName(), and Reg.
Referenced by llvm::RISCVRegisterInfo::getRegAsmName(), llvm::TargetLowering::getRegForInlineAsmConstraint(), and LiveDebugValues::MLocTracker::LocIdxToName().
◆ getRegClass()
|
inline |
Returns the register class associated with the enumeration value.
See class MCOperandInfo.
Definition at line 831 of file TargetRegisterInfo.h.
References assert(), and getNumRegClasses().
Referenced by llvm::Thumb1InstrInfo::copyPhysReg(), and getAllocatableClass().
◆ getRegClassInfo()
|
inlineprotected |
Definition at line 813 of file TargetRegisterInfo.h.
References llvm::TargetRegisterClass::getID(), and getNumRegClasses().
Referenced by getRegSizeInBits(), getSpillAlign(), getSpillSize(), and legalclasstypes_begin().
◆ getRegClassName()
|
inline |
Returns the name of the register class.
Definition at line 837 of file TargetRegisterInfo.h.
References llvm::MCRegisterInfo::getRegClassName().
Referenced by llvm::RegAllocBase::allocatePhysRegs(), llvm::RegAllocEvictionAdvisor::getOrderLimit(), llvm::HexagonEvaluator::mask(), llvm::LiveStacks::print(), llvm::VirtRegMap::print(), and llvm::ExecutionDomainFix::runOnMachineFunction().
◆ getRegClassPressureSets()
|
pure virtual |
Get the dimensions of register pressure impacted by this register class.
Returns a -1 terminated array of pressure set IDs.
Referenced by llvm::RegisterClassInfo::computePSetLimit().
◆ getRegClassWeight()
|
pure virtual |
Get the weight in units of pressure for this register class.
Referenced by llvm::RegisterClassInfo::computePSetLimit().
◆ getRegisterCosts()
|
inline |
Get a list of cost values for all registers that correspond to the index returned by RegisterCostTableIndex.
Definition at line 370 of file TargetRegisterInfo.h.
References assert(), llvm::TargetRegisterInfoDesc::CostPerUse, llvm::MCRegisterInfo::getNumRegs(), getRegisterCostTableIndex(), and Idx.
Referenced by llvm::RegisterClassInfo::runOnMachineFunction(), and llvm::RAGreedy::runOnMachineFunction().
◆ getRegisterCostTableIndex()
|
inlineprotectedvirtual |
Return the register cost table index.
This implementation is sufficient for most architectures and can be overriden by targets in case there are multiple cost values associated with each register.
Definition at line 777 of file TargetRegisterInfo.h.
Referenced by getRegisterCosts().
◆ getRegMaskNames()
◆ getRegMasks()
Return all the call-preserved register masks defined for this target.
Referenced by llvm::rdf::PhysicalRegisterInfo::PhysicalRegisterInfo().
◆ getRegPressureLimit()
|
inlinevirtual |
Return the register pressure "high water mark" for the specific register class.
The scheduler is in high register pressure mode (for the specific register class) if it goes over the limit.
Note: this is the old register pressure model that relies on a manually specified representative register class per value type.
Definition at line 882 of file TargetRegisterInfo.h.
Referenced by llvm::ResourcePriorityQueue::ResourcePriorityQueue().
◆ getRegPressureSetLimit()
|
pure virtual |
Get the register unit pressure limit for this dimension.
This limit must be adjusted dynamically for reserved registers.
Referenced by llvm::RegisterClassInfo::computePSetLimit().
◆ getRegPressureSetName()
|
pure virtual |
Get the name of this register unit pressure set.
Referenced by llvm::GenericScheduler::initCandidate(), llvm::ScheduleDAGMILive::initRegPressure(), llvm::ConvergingVLIWScheduler::traceCandidate(), llvm::GenericSchedulerBase::traceCandidate(), and llvm::ScheduleDAGMILive::updateScheduledPressure().
◆ getRegPressureSetScore()
|
inlinevirtual |
Return a heuristic for the machine scheduler to compare the profitability of increasing one register pressure set versus another.
The scheduler will prefer increasing the register pressure of the set which returns the largest value for this function.
Definition at line 891 of file TargetRegisterInfo.h.
◆ getRegSizeInBits() [1/2]
|
inline |
Return the size in bits of a register from class RC.
Definition at line 294 of file TargetRegisterInfo.h.
References llvm::TypeSize::getFixed(), getRegClassInfo(), and RegSize.
Referenced by getCommonSuperRegClass(), LiveDebugValues::MLocTracker::getLocSizeInBits(), llvm::BitTracker::MachineEvaluator::getPhysRegBitWidth(), llvm::HexagonEvaluator::getPhysRegBitWidth(), llvm::BitTracker::MachineEvaluator::getRegBitWidth(), getRegSizeInBits(), and LiveDebugValues::MLocTracker::MLocTracker().
◆ getRegSizeInBits() [2/2]
| TypeSize TargetRegisterInfo::getRegSizeInBits | ( | Register | Reg, |
| const MachineRegisterInfo & | MRI | ||
| ) | const |
Returns size in bits of a phys/virtual/generic register.
Definition at line 496 of file TargetRegisterInfo.cpp.
References assert(), getMinimalPhysRegClass(), getRegSizeInBits(), llvm::LLT::getSizeInBits(), llvm::LLT::isValid(), and MRI.
◆ getRegUnitPressureSets()
|
pure virtual |
Get the dimensions of register pressure impacted by this register unit.
Returns a -1 terminated array of pressure set IDs.
◆ getRegUnitWeight()
Get the weight in units of pressure for this register unit.
◆ getReservedRegs()
|
pure virtual |
Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times, e.g.
stack pointer, return address. A reserved register:
- is not allocatable
- is considered always live
- is ignored by liveness tracking It is often necessary to reserve the super registers of a reserved register as well, to avoid them getting allocated indirectly. You may use markSuperRegs() and checkAllSuperRegsMarked() in this case.
Referenced by llvm::MachineRegisterInfo::freezeReservedRegs().
◆ getSpillAlign()
|
inline |
Return the minimum required alignment in bytes for a spill slot for a register of this class.
Definition at line 306 of file TargetRegisterInfo.h.
References getRegClassInfo().
Referenced by llvm::AArch64FrameLowering::assignCalleeSavedSpillSlots(), llvm::RISCVFrameLowering::assignCalleeSavedSpillSlots(), and llvm::ARCFrameLowering::processFunctionBeforeFrameFinalized().
◆ getSpillSize()
|
inline |
Return the size in bytes of the stack slot allocated to hold a spilled copy of a register from class RC.
Definition at line 300 of file TargetRegisterInfo.h.
References getRegClassInfo(), and llvm::TargetRegisterInfo::RegClassInfo::SpillSize.
Referenced by llvm::AArch64FrameLowering::assignCalleeSavedSpillSlots(), llvm::RISCVFrameLowering::assignCalleeSavedSpillSlots(), and llvm::ARCFrameLowering::processFunctionBeforeFrameFinalized().
◆ getSubClassWithSubReg()
|
inlinevirtual |
Returns the largest legal sub-class of RC that supports the sub-register index Idx.
If no such sub-class exists, return NULL. If all registers in RC already have an Idx sub-register, return RC.
TableGen generates a version of this function that is good enough in most cases. Targets can override if they have constraints that TableGen doesn't understand. For example, the x86 sub_8bit sub-register index is supported by the full GR32 register class in 64-bit mode, but only by the GR32_ABCD regiister class in 32-bit mode.
TableGen will synthesize missing RC sub-classes.
Definition at line 689 of file TargetRegisterInfo.h.
Referenced by llvm::FastISel::fastEmitInst_extractsubreg(), and getCoveringSubRegIndexes().
◆ getSubReg()
|
inline |
Returns the physical register number of sub-register "Index" for physical register RegNo.
Return zero if the sub-register does not exist.
Definition at line 1203 of file TargetRegisterInfo.h.
References getSubReg(), Idx, and Reg.
Referenced by addSavedGPR(), llvm::BitTracker::MachineEvaluator::getRegBitWidth(), getSubReg(), llvm::rdf::DataFlowGraph::makeRegRef(), and llvm::MachineInstr::substituteRegister().
◆ getSubRegIdxOffset()
Get the offset of the bit range covered by a sub-register index.
If an Offset doesn't make sense (the index isn't continuous, or is used to access sub-registers at different offsets), return -1.
Definition at line 598 of file TargetRegisterInfo.cpp.
References assert(), llvm::MCRegisterInfo::getNumSubRegIndices(), Idx, and llvm::TargetRegisterInfo::SubRegCoveredBits::Offset.
Referenced by LiveDebugValues::MLocTracker::getLocID(), LiveDebugValues::MLocTracker::MLocTracker(), and llvm::SIInstrInfo::reMaterialize().
◆ getSubRegIdxSize()
Get the size of the bit range covered by a sub-register index.
If the index isn't continuous, return the sum of the sizes of its parts. If the index is used to access subregisters of different sizes, return -1.
Definition at line 592 of file TargetRegisterInfo.cpp.
References assert(), llvm::MCRegisterInfo::getNumSubRegIndices(), Idx, and llvm::TargetRegisterInfo::SubRegCoveredBits::Size.
Referenced by LiveDebugValues::MLocTracker::getLocID(), LiveDebugValues::MLocTracker::MLocTracker(), and llvm::SIInstrInfo::reMaterialize().
◆ getSubRegIndexLaneMask()
|
inline |
Return a bitmask representing the parts of a register that are covered by SubIdx.
- See also
- LaneBitmask.
SubIdx == 0 is allowed, it has the lane mask ~0u.
Definition at line 405 of file TargetRegisterInfo.h.
References assert(), and llvm::MCRegisterInfo::getNumSubRegIndices().
Referenced by llvm::LiveIntervals::addKillFlags(), getCoveringSubRegIndexes(), getInstReadLaneMask(), llvm::ScheduleDAGInstrs::getLaneMaskForMO(), llvm::rdf::Liveness::resetKills(), llvm::LiveIntervals::shrinkToUses(), and llvm::DeadLaneDetector::transferDefinedLanes().
◆ getSubRegIndexName()
Return the human-readable symbolic target-specific name for the specified SubRegIndex.
Definition at line 385 of file TargetRegisterInfo.h.
References assert(), and llvm::MCRegisterInfo::getNumSubRegIndices().
◆ getSubRegisterClass()
|
inlinevirtual |
Return a register class that can be used for a subregister copy from/into SuperRC at SubRegIdx.
Definition at line 697 of file TargetRegisterInfo.h.
◆ getVRegFlagsOfReg()
|
inlinevirtual |
Definition at line 1219 of file TargetRegisterInfo.h.
◆ getVRegFlagValue()
|
inlinevirtual |
Definition at line 1214 of file TargetRegisterInfo.h.
◆ hasRegUnit()
|
inline |
Returns true if Reg contains RegUnit.
Definition at line 455 of file TargetRegisterInfo.h.
References Reg, and llvm::MCRegisterInfo::regunits().
◆ hasReservedSpillSlot()
|
inlinevirtual |
Return true if target has reserved a spill slot in the stack frame of the given function for the specified register.
e.g. On x86, if the frame register is required, the first fixed stack object is reserved as its spill slot. This tells PEI not to create a new stack frame object for the given register. It should be called only after determineCalleeSaves().
Definition at line 1010 of file TargetRegisterInfo.h.
◆ hasStackRealignment()
|
inline |
True if stack realignment is required and still possible.
Definition at line 1028 of file TargetRegisterInfo.h.
References canRealignStack(), and shouldRealignStack().
Referenced by llvm::TargetFrameLowering::allocateScavengingFrameIndexesNearIncomingSP(), llvm::MachineFrameInfo::estimateStackSize(), llvm::CSKYFrameLowering::getFrameIndexReference(), llvm::LoongArchFrameLowering::getFrameIndexReference(), llvm::RISCVFrameLowering::getFrameIndexReference(), llvm::AArch64FrameLowering::getFrameIndexReferencePreferSP(), llvm::AArch64FrameLowering::hasFPImpl(), llvm::ARCFrameLowering::hasFPImpl(), llvm::ARMFrameLowering::hasFPImpl(), llvm::CSKYFrameLowering::hasFPImpl(), llvm::LoongArchFrameLowering::hasFPImpl(), llvm::RISCVFrameLowering::hasFPImpl(), and llvm::VEFrameLowering::hasFPImpl().
◆ isArgumentRegister()
|
inlinevirtual |
Returns true if PhysReg can be used as an argument to a function.
Definition at line 623 of file TargetRegisterInfo.h.
◆ isAsmClobberable()
|
inlinevirtual |
Returns false if we can't guarantee that Physreg, specified as an IR asm clobber constraint, will be preserved across the statement.
Definition at line 575 of file TargetRegisterInfo.h.
◆ isCalleeSavedPhysReg()
|
virtual |
This is a wrapper around getCallPreservedMask().
Return true if the register is preserved after the call.
Definition at line 464 of file TargetRegisterInfo.cpp.
References assert(), llvm::Function::getCallingConv(), getCallPreservedMask(), llvm::MachineFunction::getFunction(), and llvm::Register::isPhysicalRegister().
◆ isCallerPreservedPhysReg()
|
inlinevirtual |
Physical registers that may be modified within a function but are guaranteed to be restored before any uses.
This is useful for targets that have call sequences where a GOT register may be updated by the caller prior to a call and is guaranteed to be restored (also by the caller) after the call.
Definition at line 612 of file TargetRegisterInfo.h.
◆ isConstantPhysReg()
|
inlinevirtual |
Returns true if PhysReg is unallocatable and constant throughout the function.
Used by MachineRegisterInfo::isConstantPhysReg().
Definition at line 588 of file TargetRegisterInfo.h.
◆ isDivergentRegClass()
|
inlinevirtual |
Returns true if the register class is considered divergent.
Definition at line 591 of file TargetRegisterInfo.h.
◆ isFixedRegister()
|
inlinevirtual |
Returns true if PhysReg is a fixed register.
Definition at line 629 of file TargetRegisterInfo.h.
◆ isFrameOffsetLegal()
|
inlinevirtual |
Determine whether a given base register plus offset immediate is encodable to resolve a frame index.
Definition at line 1065 of file TargetRegisterInfo.h.
References llvm_unreachable.
◆ isGeneralPurposeRegister()
|
inlinevirtual |
Returns true if PhysReg is a general purpose register.
Definition at line 635 of file TargetRegisterInfo.h.
◆ isGeneralPurposeRegisterClass()
|
inlinevirtual |
Returns true if RC is a class/subclass of general purpose register.
Definition at line 642 of file TargetRegisterInfo.h.
◆ isInAllocatableClass()
|
inline |
Return true if the register is in the allocation of any register class.
Definition at line 379 of file TargetRegisterInfo.h.
References llvm::TargetRegisterInfoDesc::InAllocatableClass.
Referenced by llvm::MachineRegisterInfo::isAllocatable().
◆ isInlineAsmReadOnlyReg()
|
inlinevirtual |
Returns true if PhysReg cannot be written to in inline asm statements.
Definition at line 581 of file TargetRegisterInfo.h.
◆ isNonallocatableRegisterCalleeSave()
|
inlinevirtual |
Some targets have non-allocatable registers that aren't technically part of the explicit callee saved register list, but should be handled as such in certain cases.
Definition at line 1210 of file TargetRegisterInfo.h.
◆ isTypeLegalForClass() [1/2]
|
inline |
Return true if the given TargetRegisterClass is compatible with LLT T.
Definition at line 319 of file TargetRegisterInfo.h.
References I, and legalclasstypes_begin().
◆ isTypeLegalForClass() [2/2]
|
inline |
Return true if the given TargetRegisterClass has the ValueType T.
Definition at line 311 of file TargetRegisterInfo.h.
References I, and legalclasstypes_begin().
Referenced by getMinimalPhysRegClass(), getMinimalPhysRegClassLLT(), and llvm::TargetLowering::getRegForInlineAsmConstraint().
◆ isUniformReg()
|
inlinevirtual |
Returns true if the register is considered uniform.
Definition at line 596 of file TargetRegisterInfo.h.
◆ legalclasstypes_begin()
|
inline |
Loop over all of the value types that can be represented by values in the given register class.
Definition at line 333 of file TargetRegisterInfo.h.
References getRegClassInfo(), and llvm::TargetRegisterInfo::RegClassInfo::VTListOffset.
Referenced by isTypeLegalForClass(), and legalclasstypes_end().
◆ legalclasstypes_end()
|
inline |
Definition at line 337 of file TargetRegisterInfo.h.
References I, and legalclasstypes_begin().
◆ lookThruCopyLike()
|
virtual |
Returns the original SrcReg unless it is the target of a copy-like operation, in which case we chain backwards through all such operations to the ultimate source register.
If a physical register is encountered, we stop the search.
Definition at line 605 of file TargetRegisterInfo.cpp.
References assert(), llvm::Register::isVirtual(), MI, and MRI.
◆ lookThruSingleUseCopyChain()
|
virtual |
Find the original SrcReg unless it is the target of a copy-like operation, in which case we chain backwards through all such operations to the ultimate source register.
If a physical register is encountered, we stop the search. Return the original SrcReg if all the definitions in the chain only have one user and not a physical register.
Definition at line 627 of file TargetRegisterInfo.cpp.
References assert(), llvm::Register::isVirtual(), MI, and MRI.
◆ markSuperRegs()
| void TargetRegisterInfo::markSuperRegs | ( | BitVector & | RegisterSet, |
| MCRegister | Reg | ||
| ) | const |
Mark a register and all its aliases as reserved in the given set.
Definition at line 76 of file TargetRegisterInfo.cpp.
References llvm::MCRegisterInfo::superregs_inclusive().
◆ materializeFrameBaseRegister()
|
inlinevirtual |
Insert defining instruction(s) for a pointer to FrameIdx before insertion point I.
Return materialized frame pointer.
Definition at line 1049 of file TargetRegisterInfo.h.
References llvm_unreachable.
◆ needsFrameBaseReg()
|
inlinevirtual |
Returns true if the instruction's frame index reference would be better served by a base register other than FP or SP.
Used by LocalStackFrameAllocation to determine which frame index references it should create new base registers for.
Definition at line 1043 of file TargetRegisterInfo.h.
◆ prependOffsetExpression()
| DIExpression * TargetRegisterInfo::prependOffsetExpression | ( | const DIExpression * | Expr, |
| unsigned | PrependFlags, | ||
| const StackOffset & | Offset | ||
| ) | const |
Prepends a DWARF expression for Offset to DIExpression Expr.
Definition at line 659 of file TargetRegisterInfo.cpp.
References assert(), llvm::DIExpression::DerefAfter, llvm::DIExpression::DerefBefore, llvm::DIExpression::EntryValue, getOffsetOpcodes(), llvm::Offset, llvm::DIExpression::prependOpcodes(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), and llvm::DIExpression::StackValue.
◆ regclass_begin()
|
inline |
Register class iterators.
Definition at line 819 of file TargetRegisterInfo.h.
Referenced by getNumRegClasses(), and regclasses().
◆ regclass_end()
|
inline |
Definition at line 820 of file TargetRegisterInfo.h.
Referenced by getNumRegClasses(), and regclasses().
◆ regclasses()
|
inline |
Definition at line 821 of file TargetRegisterInfo.h.
References llvm::make_range(), regclass_begin(), and regclass_end().
Referenced by llvm::RegisterClassInfo::computePSetLimit(), getAllocatableSet(), getMinimalPhysRegClass(), getMinimalPhysRegClassLLT(), llvm::TargetLowering::getRegForInlineAsmConstraint(), llvm::HexagonBlockRanges::HexagonBlockRanges(), LiveDebugValues::MLocTracker::MLocTracker(), llvm::rdf::PhysicalRegisterInfo::PhysicalRegisterInfo(), llvm::ResourcePriorityQueue::regPressureDelta(), and llvm::ResourcePriorityQueue::ResourcePriorityQueue().
◆ regClassPriorityTrumpsGlobalness()
|
inlinevirtual |
When prioritizing live ranges in register allocation, if this hook returns true then the AllocationPriority of the register class will be treated as more important than whether the range is local to a basic block or global.
Definition at line 1175 of file TargetRegisterInfo.h.
Referenced by llvm::RAGreedy::runOnMachineFunction().
◆ regmaskSubsetEqual()
| bool TargetRegisterInfo::regmaskSubsetEqual | ( | const uint32_t * | mask0, |
| const uint32_t * | mask1 | ||
| ) | const |
Return true if all bits that are set in mask mask0 are also set in mask1.
Definition at line 486 of file TargetRegisterInfo.cpp.
References llvm::MCRegisterInfo::getNumRegs(), I, and N.
◆ regsOverlap()
Returns true if the two registers are equal or alias each other.
The registers may be virtual registers.
Definition at line 446 of file TargetRegisterInfo.h.
References llvm::Register::asMCReg(), llvm::Register::isPhysical(), and llvm::MCRegisterInfo::regsOverlap().
Referenced by assignedRegPartiallyOverlaps(), llvm::MachineInstr::clearRegisterKills(), llvm::CCState::IsShadowAllocatedReg(), and llvm::MachineRegisterInfo::updateDbgUsersToReg().
◆ requiresFrameIndexReplacementScavenging()
|
inlinevirtual |
Returns true if the target requires using the RegScavenger directly for frame elimination despite using requiresFrameIndexScavenging.
Definition at line 993 of file TargetRegisterInfo.h.
◆ requiresFrameIndexScavenging()
|
inlinevirtual |
Returns true if the target requires post PEI scavenging of registers for materializing frame index constants.
Definition at line 987 of file TargetRegisterInfo.h.
◆ requiresRegisterScavenging()
|
inlinevirtual |
Returns true if the target requires (and can make use of) the register scavenger.
Definition at line 975 of file TargetRegisterInfo.h.
◆ requiresVirtualBaseRegisters()
|
inlinevirtual |
Returns true if the target wants the LocalStackAllocation pass to be run and virtual base registers used for more efficient stack access.
Definition at line 1000 of file TargetRegisterInfo.h.
◆ resolveFrameIndex()
|
inlinevirtual |
Resolve a frame index operand of an instruction to reference the indicated base register plus offset instead.
Definition at line 1058 of file TargetRegisterInfo.h.
References llvm_unreachable.
◆ reverseComposeSubRegIndexLaneMask()
|
inline |
Transform a lanemask given for a virtual register to the corresponding lanemask before using subregister with index IdxA.
This is the reverse of composeSubRegIndexLaneMask(), assuming Mask is a valie lane mask (no invalid bits set) the following holds: X0 = composeSubRegIndexLaneMask(Idx, Mask) X1 = reverseComposeSubRegIndexLaneMask(Idx, X0) => X1 == Mask
Definition at line 738 of file TargetRegisterInfo.h.
References reverseComposeSubRegIndexLaneMaskImpl().
Referenced by llvm::rdf::PhysicalRegisterInfo::mapTo(), llvm::DeadLaneDetector::transferDefinedLanes(), and llvm::DeadLaneDetector::transferUsedLanes().
◆ reverseComposeSubRegIndexLaneMaskImpl()
|
inlineprotectedvirtual |
Definition at line 769 of file TargetRegisterInfo.h.
References llvm_unreachable.
Referenced by reverseComposeSubRegIndexLaneMask().
◆ reverseLocalAssignment()
|
inlinevirtual |
Allow the target to reverse allocation order of local live ranges.
This will generally allocate shorter local live ranges first. For targets with many registers, this could reduce regalloc compile time by a large factor. It is disabled by default for three reasons: (1) Top-down allocation is simpler and easier to debug for targets that don't benefit from reversing the order. (2) Bottom-up allocation could result in poor evicition decisions on some targets affecting the performance of compiled code. (3) Bottom-up allocation is no longer guaranteed to optimally color.
Definition at line 966 of file TargetRegisterInfo.h.
Referenced by llvm::RAGreedy::runOnMachineFunction().
◆ saveScavengerRegister()
|
inlinevirtual |
Spill the register so it can be used by the register scavenger.
Return true if the register was spilled, false otherwise. If this function does not spill the register, the scavenger will instead spill it to the emergency spill slot.
Definition at line 1083 of file TargetRegisterInfo.h.
◆ shouldAnalyzePhysregInMachineLoopInfo()
|
inlinevirtual |
Returns true if MachineLoopInfo should analyze the given physreg for loop invariance.
Definition at line 603 of file TargetRegisterInfo.h.
◆ shouldCoalesce()
|
inlinevirtual |
Subtarget Hooks.
SrcRC and DstRC will be morphed into NewRC if this returns true.
Definition at line 1126 of file TargetRegisterInfo.h.
Referenced by llvm::AVRRegisterInfo::shouldCoalesce().
◆ shouldRealignStack()
|
virtual |
True if storage within the function requires the stack pointer to be aligned more than the normal calling convention calls for.
Definition at line 482 of file TargetRegisterInfo.cpp.
References llvm::MachineFunction::getFrameInfo(), and llvm::MachineFrameInfo::shouldRealignStack().
Referenced by hasStackRealignment(), llvm::SIRegisterInfo::shouldRealignStack(), and llvm::X86RegisterInfo::shouldRealignStack().
◆ shouldRegionSplitForVirtReg()
|
virtual |
Region split has a high compile time cost especially for large live range.
This method is used to decide whether or not VirtReg should go through this expensive splitting heuristic.
Definition at line 65 of file TargetRegisterInfo.cpp.
References llvm::TargetSubtargetInfo::getInstrInfo(), llvm::MachineFunction::getRegInfo(), llvm::MachineFunction::getSubtarget(), HugeSizeForSplit, MI, MRI, llvm::LiveInterval::reg(), llvm::LiveRange::size(), and TII.
◆ shouldRewriteCopySrc()
|
virtual |
Definition at line 409 of file TargetRegisterInfo.cpp.
References shareSameRegisterFile().
Referenced by llvm::ARMBaseRegisterInfo::shouldRewriteCopySrc(), and llvm::X86RegisterInfo::shouldRewriteCopySrc().
◆ shouldUseDeferredSpillingForVirtReg()
|
inlinevirtual |
Deferred spilling delays the spill insertion of a virtual register after every other allocation.
By deferring the spilling, it is sometimes possible to eliminate that spilling altogether because something else could have been eliminated, thus leaving some space for the virtual register. However, this comes with a compile time impact because it adds one more stage to the greedy register allocator. This method is used to decide whether VirtReg should use the deferred spilling stage instead of being spilled right away.
Definition at line 1166 of file TargetRegisterInfo.h.
◆ shouldUseLastChanceRecoloringForVirtReg()
|
inlinevirtual |
Last chance recoloring has a high compile time cost especially for targets with a lot of registers.
This method is used to decide whether or not VirtReg should go through this expensive heuristic. When this target hook is hit, by returning false, there is a high chance that the register allocation will fail altogether (usually with "ran out of registers"). That said, this error usually points to another problem in the optimization pipeline.
Definition at line 1151 of file TargetRegisterInfo.h.
◆ trackLivenessAfterRegAlloc()
|
inlinevirtual |
Returns true if the live-ins should be tracked after register allocation.
Definition at line 1016 of file TargetRegisterInfo.h.
Referenced by llvm::BranchFolder::OptimizeFunction().
◆ updateRegAllocHint()
|
inlinevirtual |
A callback to allow target a chance to update register allocation hints when a register is "changed" (e.g.
coalesced) to another register. e.g. On ARM, some virtual registers should target register pairs, if one of pair is coalesced to another register, the allocation hint of the other half of the pair should be changed to point to the new register.
Definition at line 952 of file TargetRegisterInfo.h.
◆ useFPForScavengingIndex()
|
inlinevirtual |
Returns true if the target wants to use frame pointer based accesses to spill to the scavenger emergency spill slot.
Definition at line 981 of file TargetRegisterInfo.h.
Referenced by llvm::TargetFrameLowering::allocateScavengingFrameIndexesNearIncomingSP().
The documentation for this class was generated from the following files:
- include/llvm/CodeGen/TargetRegisterInfo.h
- lib/CodeGen/TargetRegisterInfo.cpp
