LLVM 22.0.0git
TargetRegisterInfo.h
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1//==- CodeGen/TargetRegisterInfo.h - Target Register Information -*- C++ -*-==//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file describes an abstract interface used to get information about a
10// target machines register file. This information is used for a variety of
11// purposed, especially register allocation.
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef LLVM_CODEGEN_TARGETREGISTERINFO_H
16#define LLVM_CODEGEN_TARGETREGISTERINFO_H
17
18#include "llvm/ADT/ArrayRef.h"
20#include "llvm/ADT/StringRef.h"
24#include "llvm/IR/CallingConv.h"
25#include "llvm/MC/LaneBitmask.h"
31#include <cassert>
32#include <cstdint>
33
34namespace llvm {
35
36class BitVector;
37class DIExpression;
38class LiveRegMatrix;
39class MachineFunction;
40class MachineInstr;
41class RegScavenger;
42class VirtRegMap;
43class LiveIntervals;
44class LiveInterval;
46public:
47 using iterator = const MCPhysReg *;
48 using const_iterator = const MCPhysReg *;
49
50 // Instance variables filled by tablegen, do not use!
55 /// Classes with a higher priority value are assigned first by register
56 /// allocators using a greedy heuristic. The value is in the range [0,31].
58
59 // Change allocation priority heuristic used by greedy.
60 const bool GlobalPriority;
61
62 /// Configurable target specific flags.
64 /// Whether the class supports two (or more) disjunct subregister indices.
66 /// Whether a combination of subregisters can cover every register in the
67 /// class. See also the CoveredBySubRegs description in Target.td.
68 const bool CoveredBySubRegs;
69 const unsigned *SuperClasses;
71 ArrayRef<MCPhysReg> (*OrderFunc)(const MachineFunction &, bool Rev);
72
73 /// Return the register class ID number.
74 unsigned getID() const { return MC->getID(); }
75
76 /// begin/end - Return all of the registers in this class.
77 ///
78 iterator begin() const { return MC->begin(); }
79 iterator end() const { return MC->end(); }
80
81 /// Return the number of registers in this class.
82 unsigned getNumRegs() const { return MC->getNumRegs(); }
83
85 return ArrayRef(begin(), getNumRegs());
86 }
87
88 /// Return the specified register in the class.
89 MCRegister getRegister(unsigned i) const {
90 return MC->getRegister(i);
91 }
92
93 /// Return true if the specified register is included in this register class.
94 /// This does not include virtual registers.
95 bool contains(Register Reg) const {
96 /// FIXME: Historically this function has returned false when given vregs
97 /// but it should probably only receive physical registers
98 if (!Reg.isPhysical())
99 return false;
100 return MC->contains(Reg.asMCReg());
101 }
102
103 /// Return true if both registers are in this class.
104 bool contains(Register Reg1, Register Reg2) const {
105 /// FIXME: Historically this function has returned false when given a vregs
106 /// but it should probably only receive physical registers
107 if (!Reg1.isPhysical() || !Reg2.isPhysical())
108 return false;
109 return MC->contains(Reg1.asMCReg(), Reg2.asMCReg());
110 }
111
112 /// Return the cost of copying a value between two registers in this class. If
113 /// this is the maximum value, the register may be impossible to copy.
114 uint8_t getCopyCost() const { return MC->getCopyCost(); }
115
116 /// \return true if register class is very expensive to copy e.g. status flag
117 /// register classes.
119 return MC->getCopyCost() == std::numeric_limits<uint8_t>::max();
120 }
121
122 /// Return true if this register class may be used to create virtual
123 /// registers.
124 bool isAllocatable() const { return MC->isAllocatable(); }
125
126 /// Return true if this register class has a defined BaseClassOrder.
127 bool isBaseClass() const { return MC->isBaseClass(); }
128
129 /// Return true if the specified TargetRegisterClass
130 /// is a proper sub-class of this TargetRegisterClass.
131 bool hasSubClass(const TargetRegisterClass *RC) const {
132 return RC != this && hasSubClassEq(RC);
133 }
134
135 /// Returns true if RC is a sub-class of or equal to this class.
136 bool hasSubClassEq(const TargetRegisterClass *RC) const {
137 unsigned ID = RC->getID();
138 return (SubClassMask[ID / 32] >> (ID % 32)) & 1;
139 }
140
141 /// Return true if the specified TargetRegisterClass is a
142 /// proper super-class of this TargetRegisterClass.
143 bool hasSuperClass(const TargetRegisterClass *RC) const {
144 return RC->hasSubClass(this);
145 }
146
147 /// Returns true if RC is a super-class of or equal to this class.
148 bool hasSuperClassEq(const TargetRegisterClass *RC) const {
149 return RC->hasSubClassEq(this);
150 }
151
152 /// Returns a bit vector of subclasses, including this one.
153 /// The vector is indexed by class IDs.
154 ///
155 /// To use it, consider the returned array as a chunk of memory that
156 /// contains an array of bits of size NumRegClasses. Each 32-bit chunk
157 /// contains a bitset of the ID of the subclasses in big-endian style.
158
159 /// I.e., the representation of the memory from left to right at the
160 /// bit level looks like:
161 /// [31 30 ... 1 0] [ 63 62 ... 33 32] ...
162 /// [ XXX NumRegClasses NumRegClasses - 1 ... ]
163 /// Where the number represents the class ID and XXX bits that
164 /// should be ignored.
165 ///
166 /// See the implementation of hasSubClassEq for an example of how it
167 /// can be used.
168 const uint32_t *getSubClassMask() const {
169 return SubClassMask;
170 }
171
172 /// Returns a 0-terminated list of sub-register indices that project some
173 /// super-register class into this register class. The list has an entry for
174 /// each Idx such that:
175 ///
176 /// There exists SuperRC where:
177 /// For all Reg in SuperRC:
178 /// this->contains(Reg:Idx)
180 return SuperRegIndices;
181 }
182
183 /// Returns a list of super-classes. The
184 /// classes are ordered by ID which is also a topological ordering from large
185 /// to small classes. The list does NOT include the current class.
189
190 /// Return true if this TargetRegisterClass is a subset
191 /// class of at least one other TargetRegisterClass.
192 bool isASubClass() const { return SuperClasses != nullptr; }
193
194 /// Returns the preferred order for allocating registers from this register
195 /// class in MF. The raw order comes directly from the .td file and may
196 /// include reserved registers that are not allocatable.
197 /// Register allocators should also make sure to allocate
198 /// callee-saved registers only after all the volatiles are used. The
199 /// RegisterClassInfo class provides filtered allocation orders with
200 /// callee-saved registers moved to the end.
201 ///
202 /// The MachineFunction argument can be used to tune the allocatable
203 /// registers based on the characteristics of the function, subtarget, or
204 /// other criteria.
205 ///
206 /// By default, this method returns all registers in the class.
208 bool Rev = false) const {
209 return OrderFunc ? OrderFunc(MF, Rev) : getRegisters();
210 }
211
212 /// Returns the combination of all lane masks of register in this class.
213 /// The lane masks of the registers are the combination of all lane masks
214 /// of their subregisters. Returns 1 if there are no subregisters.
216 return LaneMask;
217 }
218};
219
220/// Extra information, not in MCRegisterDesc, about registers.
221/// These are used by codegen, not by MC.
223 const uint8_t *CostPerUse; // Extra cost of instructions using register.
224 unsigned NumCosts; // Number of cost values associated with each register.
225 const bool
226 *InAllocatableClass; // Register belongs to an allocatable regclass.
227};
228
229/// Each TargetRegisterClass has a per register weight, and weight
230/// limit which must be less than the limits of its pressure sets.
232 unsigned RegWeight;
233 unsigned WeightLimit;
234};
235
236/// TargetRegisterInfo base class - We assume that the target defines a static
237/// array of TargetRegisterDesc objects that represent all of the machine
238/// registers that the target has. As such, we simply have to track a pointer
239/// to this array so that we can turn register number into a register
240/// descriptor.
241///
243public:
244 using regclass_iterator = const TargetRegisterClass * const *;
248 unsigned VTListOffset;
249 };
250
251 /// SubRegCoveredBits - Emitted by tablegen: bit range covered by a subreg
252 /// index, -1 in any being invalid.
257
258private:
259 const TargetRegisterInfoDesc *InfoDesc; // Extra desc array for codegen
260 const char *const *SubRegIndexNames; // Names of subreg indexes.
261 const SubRegCoveredBits *SubRegIdxRanges; // Pointer to the subreg covered
262 // bit ranges array.
263
264 // Pointer to array of lane masks, one per sub-reg index.
265 const LaneBitmask *SubRegIndexLaneMasks;
266
267 regclass_iterator RegClassBegin, RegClassEnd; // List of regclasses
268 LaneBitmask CoveringLanes;
269 const RegClassInfo *const RCInfos;
270 const MVT::SimpleValueType *const RCVTLists;
271 unsigned HwMode;
272
273protected:
275 regclass_iterator RCE, const char *const *SRINames,
276 const SubRegCoveredBits *SubIdxRanges,
277 const LaneBitmask *SRILaneMasks, LaneBitmask CoveringLanes,
278 const RegClassInfo *const RCIs,
279 const MVT::SimpleValueType *const RCVTLists,
280 unsigned Mode = 0);
281
282public:
284
285 /// Return the number of registers for the function. (may overestimate)
286 virtual unsigned getNumSupportedRegs(const MachineFunction &) const {
287 return getNumRegs();
288 }
289
290 // Register numbers can represent physical registers, virtual registers, and
291 // sometimes stack slots. The unsigned values are divided into these ranges:
292 //
293 // 0 Not a register, can be used as a sentinel.
294 // [1;2^30) Physical registers assigned by TableGen.
295 // [2^30;2^31) Stack slots. (Rarely used.)
296 // [2^31;2^32) Virtual registers assigned by MachineRegisterInfo.
297 //
298 // Further sentinels can be allocated from the small negative integers.
299 // DenseMapInfo<unsigned> uses -1u and -2u.
300
301 /// Return the size in bits of a register from class RC.
305
306 /// Return the size in bytes of the stack slot allocated to hold a spilled
307 /// copy of a register from class RC.
308 unsigned getSpillSize(const TargetRegisterClass &RC) const {
309 return getRegClassInfo(RC).SpillSize / 8;
310 }
311
312 /// Return the minimum required alignment in bytes for a spill slot for
313 /// a register of this class.
315 return Align(getRegClassInfo(RC).SpillAlignment / 8);
316 }
317
318 /// Return true if the given TargetRegisterClass has the ValueType T.
320 for (auto I = legalclasstypes_begin(RC); *I != MVT::Other; ++I)
321 if (MVT(*I) == T)
322 return true;
323 return false;
324 }
325
326 /// Return true if the given TargetRegisterClass is compatible with LLT T.
328 for (auto I = legalclasstypes_begin(RC); *I != MVT::Other; ++I) {
329 MVT VT(*I);
330 if (VT == MVT::Untyped)
331 return true;
332
333 if (LLT(VT) == T)
334 return true;
335 }
336 return false;
337 }
338
339 /// Loop over all of the value types that can be represented by values
340 /// in the given register class.
342 return &RCVTLists[getRegClassInfo(RC).VTListOffset];
343 }
344
347 while (*I != MVT::Other)
348 ++I;
349 return I;
350 }
351
352 /// Returns the Register Class of a physical register of the given type,
353 /// picking the most sub register class of the right type that contains this
354 /// physreg.
356 MVT VT = MVT::Other) const;
357
358 /// Returns the common Register Class of two physical registers of the given
359 /// type, picking the most sub register class of the right type that contains
360 /// these two physregs.
361 const TargetRegisterClass *
363 MVT VT = MVT::Other) const;
364
365 /// Returns the Register Class of a physical register of the given type,
366 /// picking the most sub register class of the right type that contains this
367 /// physreg. If there is no register class compatible with the given type,
368 /// returns nullptr.
369 const TargetRegisterClass *getMinimalPhysRegClassLLT(MCRegister Reg,
370 LLT Ty = LLT()) const;
371
372 /// Returns the common Register Class of two physical registers of the given
373 /// type, picking the most sub register class of the right type that contains
374 /// these two physregs. If there is no register class compatible with the
375 /// given type, returns nullptr.
376 const TargetRegisterClass *
377 getCommonMinimalPhysRegClassLLT(MCRegister Reg1, MCRegister Reg2,
378 LLT Ty = LLT()) const;
379
380 /// Return the maximal subclass of the given register class that is
381 /// allocatable or NULL.
382 const TargetRegisterClass *
383 getAllocatableClass(const TargetRegisterClass *RC) const;
384
385 /// Returns a bitset indexed by register number indicating if a register is
386 /// allocatable or not. If a register class is specified, returns the subset
387 /// for the class.
388 BitVector getAllocatableSet(const MachineFunction &MF,
389 const TargetRegisterClass *RC = nullptr) const;
390
391 /// Get a list of cost values for all registers that correspond to the index
392 /// returned by RegisterCostTableIndex.
394 unsigned Idx = getRegisterCostTableIndex(MF);
395 unsigned NumRegs = getNumRegs();
396 assert(Idx < InfoDesc->NumCosts && "CostPerUse index out of bounds");
397
398 return ArrayRef(&InfoDesc->CostPerUse[Idx * NumRegs], NumRegs);
399 }
400
401 /// Return true if the register is in the allocation of any register class.
403 return InfoDesc->InAllocatableClass[RegNo];
404 }
405
406 /// Return the human-readable symbolic target-specific
407 /// name for the specified SubRegIndex.
408 const char *getSubRegIndexName(unsigned SubIdx) const {
409 assert(SubIdx && SubIdx < getNumSubRegIndices() &&
410 "This is not a subregister index");
411 return SubRegIndexNames[SubIdx-1];
412 }
413
414 /// Get the size of the bit range covered by a sub-register index.
415 /// If the index isn't continuous, return the sum of the sizes of its parts.
416 /// If the index is used to access subregisters of different sizes, return -1.
417 unsigned getSubRegIdxSize(unsigned Idx) const;
418
419 /// Get the offset of the bit range covered by a sub-register index.
420 /// If an Offset doesn't make sense (the index isn't continuous, or is used to
421 /// access sub-registers at different offsets), return -1.
422 unsigned getSubRegIdxOffset(unsigned Idx) const;
423
424 /// Return a bitmask representing the parts of a register that are covered by
425 /// SubIdx \see LaneBitmask.
426 ///
427 /// SubIdx == 0 is allowed, it has the lane mask ~0u.
428 LaneBitmask getSubRegIndexLaneMask(unsigned SubIdx) const {
429 assert(SubIdx < getNumSubRegIndices() && "This is not a subregister index");
430 return SubRegIndexLaneMasks[SubIdx];
431 }
432
433 /// Try to find one or more subregister indexes to cover \p LaneMask.
434 ///
435 /// If this is possible, returns true and appends the best matching set of
436 /// indexes to \p Indexes. If this is not possible, returns false.
437 bool getCoveringSubRegIndexes(const TargetRegisterClass *RC,
438 LaneBitmask LaneMask,
439 SmallVectorImpl<unsigned> &Indexes) const;
440
441 /// The lane masks returned by getSubRegIndexLaneMask() above can only be
442 /// used to determine if sub-registers overlap - they can't be used to
443 /// determine if a set of sub-registers completely cover another
444 /// sub-register.
445 ///
446 /// The X86 general purpose registers have two lanes corresponding to the
447 /// sub_8bit and sub_8bit_hi sub-registers. Both sub_32bit and sub_16bit have
448 /// lane masks '3', but the sub_16bit sub-register doesn't fully cover the
449 /// sub_32bit sub-register.
450 ///
451 /// On the other hand, the ARM NEON lanes fully cover their registers: The
452 /// dsub_0 sub-register is completely covered by the ssub_0 and ssub_1 lanes.
453 /// This is related to the CoveredBySubRegs property on register definitions.
454 ///
455 /// This function returns a bit mask of lanes that completely cover their
456 /// sub-registers. More precisely, given:
457 ///
458 /// Covering = getCoveringLanes();
459 /// MaskA = getSubRegIndexLaneMask(SubA);
460 /// MaskB = getSubRegIndexLaneMask(SubB);
461 ///
462 /// If (MaskA & ~(MaskB & Covering)) == 0, then SubA is completely covered by
463 /// SubB.
464 LaneBitmask getCoveringLanes() const { return CoveringLanes; }
465
466 /// Returns true if the two registers are equal or alias each other.
467 /// The registers may be virtual registers.
468 bool regsOverlap(Register RegA, Register RegB) const {
469 if (RegA == RegB)
470 return true;
471 if (RegA.isPhysical() && RegB.isPhysical())
472 return MCRegisterInfo::regsOverlap(RegA.asMCReg(), RegB.asMCReg());
473 return false;
474 }
475
476 /// Returns true if Reg contains RegUnit.
477 bool hasRegUnit(MCRegister Reg, MCRegUnit RegUnit) const {
478 return llvm::is_contained(regunits(Reg), RegUnit);
479 }
480
481 /// Returns the original SrcReg unless it is the target of a copy-like
482 /// operation, in which case we chain backwards through all such operations
483 /// to the ultimate source register. If a physical register is encountered,
484 /// we stop the search.
485 virtual Register lookThruCopyLike(Register SrcReg,
486 const MachineRegisterInfo *MRI) const;
487
488 /// Find the original SrcReg unless it is the target of a copy-like operation,
489 /// in which case we chain backwards through all such operations to the
490 /// ultimate source register. If a physical register is encountered, we stop
491 /// the search.
492 /// Return the original SrcReg if all the definitions in the chain only have
493 /// one user and not a physical register.
494 virtual Register
495 lookThruSingleUseCopyChain(Register SrcReg,
496 const MachineRegisterInfo *MRI) const;
497
498 /// Return a null-terminated list of all of the callee-saved registers on
499 /// this target. The register should be in the order of desired callee-save
500 /// stack frame offset. The first register is closest to the incoming stack
501 /// pointer if stack grows down, and vice versa.
502 /// Notice: This function does not take into account disabled CSRs.
503 /// In most cases you will want to use instead the function
504 /// getCalleeSavedRegs that is implemented in MachineRegisterInfo.
505 virtual const MCPhysReg*
507
508 /// Return a null-terminated list of all of the callee-saved registers on
509 /// this target when IPRA is on. The list should include any non-allocatable
510 /// registers that the backend uses and assumes will be saved by all calling
511 /// conventions. This is typically the ISA-standard frame pointer, but could
512 /// include the thread pointer, TOC pointer, or base pointer for different
513 /// targets.
514 virtual const MCPhysReg *getIPRACSRegs(const MachineFunction *MF) const {
515 return nullptr;
516 }
517
518 /// Return a mask of call-preserved registers for the given calling convention
519 /// on the current function. The mask should include all call-preserved
520 /// aliases. This is used by the register allocator to determine which
521 /// registers can be live across a call.
522 ///
523 /// The mask is an array containing (TRI::getNumRegs()+31)/32 entries.
524 /// A set bit indicates that all bits of the corresponding register are
525 /// preserved across the function call. The bit mask is expected to be
526 /// sub-register complete, i.e. if A is preserved, so are all its
527 /// sub-registers.
528 ///
529 /// Bits are numbered from the LSB, so the bit for physical register Reg can
530 /// be found as (Mask[Reg / 32] >> Reg % 32) & 1.
531 ///
532 /// A NULL pointer means that no register mask will be used, and call
533 /// instructions should use implicit-def operands to indicate call clobbered
534 /// registers.
535 ///
537 CallingConv::ID) const {
538 // The default mask clobbers everything. All targets should override.
539 return nullptr;
540 }
541
542 /// Return a register mask for the registers preserved by the unwinder,
543 /// or nullptr if no custom mask is needed.
544 virtual const uint32_t *
546 return nullptr;
547 }
548
549 /// Return a register mask that clobbers everything.
550 virtual const uint32_t *getNoPreservedMask() const {
551 llvm_unreachable("target does not provide no preserved mask");
552 }
553
554 /// Return a list of all of the registers which are clobbered "inside" a call
555 /// to the given function. For example, these might be needed for PLT
556 /// sequences of long-branch veneers.
557 virtual ArrayRef<MCPhysReg>
559 return {};
560 }
561
562 /// Return true if all bits that are set in mask \p mask0 are also set in
563 /// \p mask1.
564 bool regmaskSubsetEqual(const uint32_t *mask0, const uint32_t *mask1) const;
565
566 /// Return all the call-preserved register masks defined for this target.
569
570 /// Returns a bitset indexed by physical register number indicating if a
571 /// register is a special register that has particular uses and should be
572 /// considered unavailable at all times, e.g. stack pointer, return address.
573 /// A reserved register:
574 /// - is not allocatable
575 /// - is considered always live
576 /// - is ignored by liveness tracking
577 /// It is often necessary to reserve the super registers of a reserved
578 /// register as well, to avoid them getting allocated indirectly. You may use
579 /// markSuperRegs() and checkAllSuperRegsMarked() in this case.
580 virtual BitVector getReservedRegs(const MachineFunction &MF) const = 0;
581
582 /// Returns either a string explaining why the given register is reserved for
583 /// this function, or an empty optional if no explanation has been written.
584 /// The absence of an explanation does not mean that the register is not
585 /// reserved (meaning, you should check that PhysReg is in fact reserved
586 /// before calling this).
587 virtual std::optional<std::string>
589 return {};
590 }
591
592 /// Returns false if we can't guarantee that Physreg, specified as an IR asm
593 /// clobber constraint, will be preserved across the statement.
594 virtual bool isAsmClobberable(const MachineFunction &MF,
595 MCRegister PhysReg) const {
596 return true;
597 }
598
599 /// Returns true if PhysReg cannot be written to in inline asm statements.
601 MCRegister PhysReg) const {
602 return false;
603 }
604
605 /// Returns true if PhysReg is unallocatable and constant throughout the
606 /// function. Used by MachineRegisterInfo::isConstantPhysReg().
607 virtual bool isConstantPhysReg(MCRegister PhysReg) const { return false; }
608
609 /// Returns true if the register class is considered divergent.
610 virtual bool isDivergentRegClass(const TargetRegisterClass *RC) const {
611 return false;
612 }
613
614 /// Returns true if the register is considered uniform.
616 const RegisterBankInfo &RBI, Register Reg) const {
617 return false;
618 }
619
620 /// Returns true if MachineLoopInfo should analyze the given physreg
621 /// for loop invariance.
623 return false;
624 }
625
626 /// Physical registers that may be modified within a function but are
627 /// guaranteed to be restored before any uses. This is useful for targets that
628 /// have call sequences where a GOT register may be updated by the caller
629 /// prior to a call and is guaranteed to be restored (also by the caller)
630 /// after the call.
632 const MachineFunction &MF) const {
633 return false;
634 }
635
636 /// This is a wrapper around getCallPreservedMask().
637 /// Return true if the register is preserved after the call.
638 virtual bool isCalleeSavedPhysReg(MCRegister PhysReg,
639 const MachineFunction &MF) const;
640
641 /// Returns true if PhysReg can be used as an argument to a function.
642 virtual bool isArgumentRegister(const MachineFunction &MF,
643 MCRegister PhysReg) const {
644 return false;
645 }
646
647 /// Returns true if PhysReg is a fixed register.
648 virtual bool isFixedRegister(const MachineFunction &MF,
649 MCRegister PhysReg) const {
650 return false;
651 }
652
653 /// Returns true if PhysReg is a general purpose register.
655 MCRegister PhysReg) const {
656 return false;
657 }
658
659 /// Returns true if RC is a class/subclass of general purpose register.
660 virtual bool
662 return false;
663 }
664
665 /// Prior to adding the live-out mask to a stackmap or patchpoint
666 /// instruction, provide the target the opportunity to adjust it (mainly to
667 /// remove pseudo-registers that should be ignored).
668 virtual void adjustStackMapLiveOutMask(uint32_t *Mask) const {}
669
670 /// Return a super-register of the specified register
671 /// Reg so its sub-register of index SubIdx is Reg.
673 const TargetRegisterClass *RC) const {
674 return MCRegisterInfo::getMatchingSuperReg(Reg, SubIdx, RC->MC);
675 }
676
677 /// Return a subclass of the specified register
678 /// class A so that each register in it has a sub-register of the
679 /// specified sub-register index which is in the specified register class B.
680 ///
681 /// TableGen will synthesize missing A sub-classes.
682 virtual const TargetRegisterClass *
683 getMatchingSuperRegClass(const TargetRegisterClass *A,
684 const TargetRegisterClass *B, unsigned Idx) const;
685
686 /// Find a common register class that can accomodate both the source and
687 /// destination operands of a copy-like instruction:
688 ///
689 /// DefRC:DefSubReg = COPY SrcRC:SrcSubReg
690 ///
691 /// This is a generalized form of getMatchingSuperRegClass,
692 /// getCommonSuperRegClass, and getCommonSubClass which handles 0, 1, or 2
693 /// subregister indexes. Those utilities should be preferred if the number of
694 /// non-0 subregister indexes is known.
695 const TargetRegisterClass *
696 findCommonRegClass(const TargetRegisterClass *DefRC, unsigned DefSubReg,
697 const TargetRegisterClass *SrcRC,
698 unsigned SrcSubReg) const;
699
700 // For a copy-like instruction that defines a register of class DefRC with
701 // subreg index DefSubReg, reading from another source with class SrcRC and
702 // subregister SrcSubReg return true if this is a preferable copy
703 // instruction or an earlier use should be used.
704 virtual bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC,
705 unsigned DefSubReg,
706 const TargetRegisterClass *SrcRC,
707 unsigned SrcSubReg) const {
708 // If this source does not incur a cross register bank copy, use it.
709 return findCommonRegClass(DefRC, DefSubReg, SrcRC, SrcSubReg) != nullptr;
710 }
711
712 /// Returns the largest legal sub-class of RC that
713 /// supports the sub-register index Idx.
714 /// If no such sub-class exists, return NULL.
715 /// If all registers in RC already have an Idx sub-register, return RC.
716 ///
717 /// TableGen generates a version of this function that is good enough in most
718 /// cases. Targets can override if they have constraints that TableGen
719 /// doesn't understand. For example, the x86 sub_8bit sub-register index is
720 /// supported by the full GR32 register class in 64-bit mode, but only by the
721 /// GR32_ABCD regiister class in 32-bit mode.
722 ///
723 /// TableGen will synthesize missing RC sub-classes.
724 virtual const TargetRegisterClass *
725 getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
726 assert(Idx == 0 && "Target has no sub-registers");
727 return RC;
728 }
729
730 /// Return a register class that can be used for a subregister copy from/into
731 /// \p SuperRC at \p SubRegIdx.
732 virtual const TargetRegisterClass *
734 unsigned SubRegIdx) const {
735 return nullptr;
736 }
737
738 /// Return the subregister index you get from composing
739 /// two subregister indices.
740 ///
741 /// The special null sub-register index composes as the identity.
742 ///
743 /// If R:a:b is the same register as R:c, then composeSubRegIndices(a, b)
744 /// returns c. Note that composeSubRegIndices does not tell you about illegal
745 /// compositions. If R does not have a subreg a, or R:a does not have a subreg
746 /// b, composeSubRegIndices doesn't tell you.
747 ///
748 /// The ARM register Q0 has two D subregs dsub_0:D0 and dsub_1:D1. It also has
749 /// ssub_0:S0 - ssub_3:S3 subregs.
750 /// If you compose subreg indices dsub_1, ssub_0 you get ssub_2.
751 unsigned composeSubRegIndices(unsigned a, unsigned b) const {
752 if (!a) return b;
753 if (!b) return a;
754 return composeSubRegIndicesImpl(a, b);
755 }
756
757 /// Return a subregister index that will compose to give you the subregister
758 /// index.
759 ///
760 /// Finds a subregister index x such that composeSubRegIndices(a, x) ==
761 /// b. Note that this relationship does not hold if
762 /// reverseComposeSubRegIndices returns the null subregister.
763 ///
764 /// The special null sub-register index composes as the identity.
765 unsigned reverseComposeSubRegIndices(unsigned a, unsigned b) const {
766 if (!a)
767 return b;
768 if (!b)
769 return a;
771 }
772
773 /// Transforms a LaneMask computed for one subregister to the lanemask that
774 /// would have been computed when composing the subsubregisters with IdxA
775 /// first. @sa composeSubRegIndices()
777 LaneBitmask Mask) const {
778 if (!IdxA)
779 return Mask;
780 return composeSubRegIndexLaneMaskImpl(IdxA, Mask);
781 }
782
783 /// Transform a lanemask given for a virtual register to the corresponding
784 /// lanemask before using subregister with index \p IdxA.
785 /// This is the reverse of composeSubRegIndexLaneMask(), assuming Mask is a
786 /// valie lane mask (no invalid bits set) the following holds:
787 /// X0 = composeSubRegIndexLaneMask(Idx, Mask)
788 /// X1 = reverseComposeSubRegIndexLaneMask(Idx, X0)
789 /// => X1 == Mask
791 LaneBitmask LaneMask) const {
792 if (!IdxA)
793 return LaneMask;
794 return reverseComposeSubRegIndexLaneMaskImpl(IdxA, LaneMask);
795 }
796
797 /// Debugging helper: dump register in human readable form to dbgs() stream.
798 static void dumpReg(Register Reg, unsigned SubRegIndex = 0,
799 const TargetRegisterInfo *TRI = nullptr);
800
801 /// Return target defined base register class for a physical register.
802 /// This is the register class with the lowest BaseClassOrder containing the
803 /// register.
804 /// Will be nullptr if the register is not in any base register class.
806 return nullptr;
807 }
808
809protected:
810 /// Overridden by TableGen in targets that have sub-registers.
811 virtual unsigned composeSubRegIndicesImpl(unsigned, unsigned) const {
812 llvm_unreachable("Target has no sub-registers");
813 }
814
815 /// Overridden by TableGen in targets that have sub-registers.
816 virtual unsigned reverseComposeSubRegIndicesImpl(unsigned, unsigned) const {
817 llvm_unreachable("Target has no sub-registers");
818 }
819
820 /// Overridden by TableGen in targets that have sub-registers.
821 virtual LaneBitmask
823 llvm_unreachable("Target has no sub-registers");
824 }
825
827 LaneBitmask) const {
828 llvm_unreachable("Target has no sub-registers");
829 }
830
831 /// Return the register cost table index. This implementation is sufficient
832 /// for most architectures and can be overriden by targets in case there are
833 /// multiple cost values associated with each register.
834 virtual unsigned getRegisterCostTableIndex(const MachineFunction &MF) const {
835 return 0;
836 }
837
838public:
839 /// Find a common super-register class if it exists.
840 ///
841 /// Find a register class, SuperRC and two sub-register indices, PreA and
842 /// PreB, such that:
843 ///
844 /// 1. PreA + SubA == PreB + SubB (using composeSubRegIndices()), and
845 ///
846 /// 2. For all Reg in SuperRC: Reg:PreA in RCA and Reg:PreB in RCB, and
847 ///
848 /// 3. SuperRC->getSize() >= max(RCA->getSize(), RCB->getSize()).
849 ///
850 /// SuperRC will be chosen such that no super-class of SuperRC satisfies the
851 /// requirements, and there is no register class with a smaller spill size
852 /// that satisfies the requirements.
853 ///
854 /// SubA and SubB must not be 0. Use getMatchingSuperRegClass() instead.
855 ///
856 /// Either of the PreA and PreB sub-register indices may be returned as 0. In
857 /// that case, the returned register class will be a sub-class of the
858 /// corresponding argument register class.
859 ///
860 /// The function returns NULL if no register class can be found.
862 getCommonSuperRegClass(const TargetRegisterClass *RCA, unsigned SubA,
863 const TargetRegisterClass *RCB, unsigned SubB,
864 unsigned &PreA, unsigned &PreB) const;
865
866 //===--------------------------------------------------------------------===//
867 // Register Class Information
868 //
869protected:
871 return RCInfos[getNumRegClasses() * HwMode + RC.getID()];
872 }
873
874public:
875 /// Register class iterators
876 regclass_iterator regclass_begin() const { return RegClassBegin; }
877 regclass_iterator regclass_end() const { return RegClassEnd; }
881
882 unsigned getNumRegClasses() const {
883 return (unsigned)(regclass_end()-regclass_begin());
884 }
885
886 /// Returns the register class associated with the enumeration value.
887 /// See class MCOperandInfo.
888 const TargetRegisterClass *getRegClass(unsigned i) const {
889 assert(i < getNumRegClasses() && "Register Class ID out of range");
890 return RegClassBegin[i];
891 }
892
893 /// Returns the name of the register class.
894 const char *getRegClassName(const TargetRegisterClass *Class) const {
895 return MCRegisterInfo::getRegClassName(Class->MC);
896 }
897
898 /// Find the largest common subclass of A and B.
899 /// Return NULL if there is no common subclass.
900 const TargetRegisterClass *
901 getCommonSubClass(const TargetRegisterClass *A,
902 const TargetRegisterClass *B) const;
903
904 /// Returns a TargetRegisterClass used for pointer values.
905 /// If a target supports multiple different pointer register classes,
906 /// kind specifies which one is indicated.
907 virtual const TargetRegisterClass *
908 getPointerRegClass(unsigned Kind = 0) const {
909 llvm_unreachable("Target didn't implement getPointerRegClass!");
910 }
911
912 /// Returns a legal register class to copy a register in the specified class
913 /// to or from. If it is possible to copy the register directly without using
914 /// a cross register class copy, return the specified RC. Returns NULL if it
915 /// is not possible to copy between two registers of the specified class.
916 virtual const TargetRegisterClass *
918 return RC;
919 }
920
921 /// Returns the largest super class of RC that is legal to use in the current
922 /// sub-target and has the same spill size.
923 /// The returned register class can be used to create virtual registers which
924 /// means that all its registers can be copied and spilled.
925 virtual const TargetRegisterClass *
927 const MachineFunction &) const {
928 /// The default implementation is very conservative and doesn't allow the
929 /// register allocator to inflate register classes.
930 return RC;
931 }
932
933 /// Return the register pressure "high water mark" for the specific register
934 /// class. The scheduler is in high register pressure mode (for the specific
935 /// register class) if it goes over the limit.
936 ///
937 /// Note: this is the old register pressure model that relies on a manually
938 /// specified representative register class per value type.
939 virtual unsigned getRegPressureLimit(const TargetRegisterClass *RC,
940 MachineFunction &MF) const {
941 return 0;
942 }
943
944 /// Return a heuristic for the machine scheduler to compare the profitability
945 /// of increasing one register pressure set versus another. The scheduler
946 /// will prefer increasing the register pressure of the set which returns
947 /// the largest value for this function.
948 virtual unsigned getRegPressureSetScore(const MachineFunction &MF,
949 unsigned PSetID) const {
950 return PSetID;
951 }
952
953 /// Get the weight in units of pressure for this register class.
955 const TargetRegisterClass *RC) const = 0;
956
957 /// Returns size in bits of a phys/virtual/generic register.
959
960 /// Get the weight in units of pressure for this register unit.
961 virtual unsigned getRegUnitWeight(unsigned RegUnit) const = 0;
962
963 /// Get the number of dimensions of register pressure.
964 virtual unsigned getNumRegPressureSets() const = 0;
965
966 /// Get the name of this register unit pressure set.
967 virtual const char *getRegPressureSetName(unsigned Idx) const = 0;
968
969 /// Get the register unit pressure limit for this dimension.
970 /// This limit must be adjusted dynamically for reserved registers.
971 virtual unsigned getRegPressureSetLimit(const MachineFunction &MF,
972 unsigned Idx) const = 0;
973
974 /// Get the dimensions of register pressure impacted by this register class.
975 /// Returns a -1 terminated array of pressure set IDs.
976 virtual const int *getRegClassPressureSets(
977 const TargetRegisterClass *RC) const = 0;
978
979 /// Get the dimensions of register pressure impacted by this register unit.
980 /// Returns a -1 terminated array of pressure set IDs.
981 virtual const int *getRegUnitPressureSets(unsigned RegUnit) const = 0;
982
983 /// Get the scale factor of spill weight for this register class.
984 virtual float getSpillWeightScaleFactor(const TargetRegisterClass *RC) const;
985
986 /// Get a list of 'hint' registers that the register allocator should try
987 /// first when allocating a physical register for the virtual register
988 /// VirtReg. These registers are effectively moved to the front of the
989 /// allocation order. If true is returned, regalloc will try to only use
990 /// hints to the greatest extent possible even if it means spilling.
991 ///
992 /// The Order argument is the allocation order for VirtReg's register class
993 /// as returned from RegisterClassInfo::getOrder(). The hint registers must
994 /// come from Order, and they must not be reserved.
995 ///
996 /// The default implementation of this function will only add target
997 /// independent register allocation hints. Targets that override this
998 /// function should typically call this default implementation as well and
999 /// expect to see generic copy hints added.
1000 virtual bool
1003 const MachineFunction &MF,
1004 const VirtRegMap *VRM = nullptr,
1005 const LiveRegMatrix *Matrix = nullptr) const;
1006
1007 /// A callback to allow target a chance to update register allocation hints
1008 /// when a register is "changed" (e.g. coalesced) to another register.
1009 /// e.g. On ARM, some virtual registers should target register pairs,
1010 /// if one of pair is coalesced to another register, the allocation hint of
1011 /// the other half of the pair should be changed to point to the new register.
1013 MachineFunction &MF) const {
1014 // Do nothing.
1015 }
1016
1017 /// Allow the target to reverse allocation order of local live ranges. This
1018 /// will generally allocate shorter local live ranges first. For targets with
1019 /// many registers, this could reduce regalloc compile time by a large
1020 /// factor. It is disabled by default for three reasons:
1021 /// (1) Top-down allocation is simpler and easier to debug for targets that
1022 /// don't benefit from reversing the order.
1023 /// (2) Bottom-up allocation could result in poor evicition decisions on some
1024 /// targets affecting the performance of compiled code.
1025 /// (3) Bottom-up allocation is no longer guaranteed to optimally color.
1026 virtual bool reverseLocalAssignment() const { return false; }
1027
1028 /// Allow the target to override the cost of using a callee-saved register for
1029 /// the first time. Default value of 0 means we will use a callee-saved
1030 /// register if it is available.
1031 virtual unsigned getCSRFirstUseCost() const { return 0; }
1032
1033 /// Returns true if the target requires (and can make use of) the register
1034 /// scavenger.
1035 virtual bool requiresRegisterScavenging(const MachineFunction &MF) const {
1036 return false;
1037 }
1038
1039 /// Returns true if the target wants to use frame pointer based accesses to
1040 /// spill to the scavenger emergency spill slot.
1041 virtual bool useFPForScavengingIndex(const MachineFunction &MF) const {
1042 return true;
1043 }
1044
1045 /// Returns true if the target requires post PEI scavenging of registers for
1046 /// materializing frame index constants.
1047 virtual bool requiresFrameIndexScavenging(const MachineFunction &MF) const {
1048 return false;
1049 }
1050
1051 /// Returns true if the target requires using the RegScavenger directly for
1052 /// frame elimination despite using requiresFrameIndexScavenging.
1054 const MachineFunction &MF) const {
1055 return false;
1056 }
1057
1058 /// Returns true if the target wants the LocalStackAllocation pass to be run
1059 /// and virtual base registers used for more efficient stack access.
1060 virtual bool requiresVirtualBaseRegisters(const MachineFunction &MF) const {
1061 return false;
1062 }
1063
1064 /// Return true if target has reserved a spill slot in the stack frame of
1065 /// the given function for the specified register. e.g. On x86, if the frame
1066 /// register is required, the first fixed stack object is reserved as its
1067 /// spill slot. This tells PEI not to create a new stack frame
1068 /// object for the given register. It should be called only after
1069 /// determineCalleeSaves().
1071 int &FrameIdx) const {
1072 return false;
1073 }
1074
1075 /// Returns true if the live-ins should be tracked after register allocation.
1076 virtual bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const {
1077 return true;
1078 }
1079
1080 /// True if the stack can be realigned for the target.
1081 virtual bool canRealignStack(const MachineFunction &MF) const;
1082
1083 /// True if storage within the function requires the stack pointer to be
1084 /// aligned more than the normal calling convention calls for.
1085 virtual bool shouldRealignStack(const MachineFunction &MF) const;
1086
1087 /// True if stack realignment is required and still possible.
1088 bool hasStackRealignment(const MachineFunction &MF) const {
1089 return shouldRealignStack(MF) && canRealignStack(MF);
1090 }
1091
1092 /// Get the offset from the referenced frame index in the instruction,
1093 /// if there is one.
1095 int Idx) const {
1096 return 0;
1097 }
1098
1099 /// Returns true if the instruction's frame index reference would be better
1100 /// served by a base register other than FP or SP.
1101 /// Used by LocalStackFrameAllocation to determine which frame index
1102 /// references it should create new base registers for.
1103 virtual bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const {
1104 return false;
1105 }
1106
1107 /// Insert defining instruction(s) for a pointer to FrameIdx before
1108 /// insertion point I. Return materialized frame pointer.
1110 int FrameIdx,
1111 int64_t Offset) const {
1112 llvm_unreachable("materializeFrameBaseRegister does not exist on this "
1113 "target");
1114 }
1115
1116 /// Resolve a frame index operand of an instruction
1117 /// to reference the indicated base register plus offset instead.
1119 int64_t Offset) const {
1120 llvm_unreachable("resolveFrameIndex does not exist on this target");
1121 }
1122
1123 /// Determine whether a given base register plus offset immediate is
1124 /// encodable to resolve a frame index.
1125 virtual bool isFrameOffsetLegal(const MachineInstr *MI, Register BaseReg,
1126 int64_t Offset) const {
1127 llvm_unreachable("isFrameOffsetLegal does not exist on this target");
1128 }
1129
1130 /// Gets the DWARF expression opcodes for \p Offset.
1131 virtual void getOffsetOpcodes(const StackOffset &Offset,
1133
1134 /// Prepends a DWARF expression for \p Offset to DIExpression \p Expr.
1135 DIExpression *
1136 prependOffsetExpression(const DIExpression *Expr, unsigned PrependFlags,
1137 const StackOffset &Offset) const;
1138
1139 virtual int64_t getDwarfRegNumForVirtReg(Register RegNum, bool isEH) const {
1140 llvm_unreachable("getDwarfRegNumForVirtReg does not exist on this target");
1141 }
1142
1143 /// Spill the register so it can be used by the register scavenger.
1144 /// Return true if the register was spilled, false otherwise.
1145 /// If this function does not spill the register, the scavenger
1146 /// will instead spill it to the emergency spill slot.
1150 const TargetRegisterClass *RC,
1151 Register Reg) const {
1152 return false;
1153 }
1154
1155 /// Process frame indices in reverse block order. This changes the behavior of
1156 /// the RegScavenger passed to eliminateFrameIndex. If this is true targets
1157 /// should scavengeRegisterBackwards in eliminateFrameIndex. New targets
1158 /// should prefer reverse scavenging behavior.
1159 /// TODO: Remove this when all targets return true.
1160 virtual bool eliminateFrameIndicesBackwards() const { return true; }
1161
1162 /// This method must be overriden to eliminate abstract frame indices from
1163 /// instructions which may use them. The instruction referenced by the
1164 /// iterator contains an MO_FrameIndex operand which must be eliminated by
1165 /// this method. This method may modify or replace the specified instruction,
1166 /// as long as it keeps the iterator pointing at the finished product.
1167 /// SPAdj is the SP adjustment due to call frame setup instruction.
1168 /// FIOperandNum is the FI operand number.
1169 /// Returns true if the current instruction was removed and the iterator
1170 /// is not longer valid
1172 int SPAdj, unsigned FIOperandNum,
1173 RegScavenger *RS = nullptr) const = 0;
1174
1175 /// Return the assembly name for \p Reg.
1177 // FIXME: We are assuming that the assembly name is equal to the TableGen
1178 // name converted to lower case
1179 //
1180 // The TableGen name is the name of the definition for this register in the
1181 // target's tablegen files. For example, the TableGen name of
1182 // def EAX : Register <...>; is "EAX"
1183 return StringRef(getName(Reg));
1184 }
1185
1186 //===--------------------------------------------------------------------===//
1187 /// Subtarget Hooks
1188
1189 /// SrcRC and DstRC will be morphed into NewRC if this returns true.
1191 const TargetRegisterClass *SrcRC,
1192 unsigned SubReg,
1193 const TargetRegisterClass *DstRC,
1194 unsigned DstSubReg,
1195 const TargetRegisterClass *NewRC,
1196 LiveIntervals &LIS) const
1197 { return true; }
1198
1199 /// Region split has a high compile time cost especially for large live range.
1200 /// This method is used to decide whether or not \p VirtReg should
1201 /// go through this expensive splitting heuristic.
1202 virtual bool shouldRegionSplitForVirtReg(const MachineFunction &MF,
1203 const LiveInterval &VirtReg) const;
1204
1205 /// Last chance recoloring has a high compile time cost especially for
1206 /// targets with a lot of registers.
1207 /// This method is used to decide whether or not \p VirtReg should
1208 /// go through this expensive heuristic.
1209 /// When this target hook is hit, by returning false, there is a high
1210 /// chance that the register allocation will fail altogether (usually with
1211 /// "ran out of registers").
1212 /// That said, this error usually points to another problem in the
1213 /// optimization pipeline.
1214 virtual bool
1216 const LiveInterval &VirtReg) const {
1217 return true;
1218 }
1219
1220 /// When prioritizing live ranges in register allocation, if this hook returns
1221 /// true then the AllocationPriority of the register class will be treated as
1222 /// more important than whether the range is local to a basic block or global.
1223 virtual bool
1225 return false;
1226 }
1227
1228 //===--------------------------------------------------------------------===//
1229 /// Debug information queries.
1230
1231 /// getFrameRegister - This method should return the register used as a base
1232 /// for values allocated in the current stack frame.
1233 virtual Register getFrameRegister(const MachineFunction &MF) const = 0;
1234
1235 /// Mark a register and all its aliases as reserved in the given set.
1236 void markSuperRegs(BitVector &RegisterSet, MCRegister Reg) const;
1237
1238 /// Returns true if for every register in the set all super registers are part
1239 /// of the set as well.
1240 bool checkAllSuperRegsMarked(const BitVector &RegisterSet,
1241 ArrayRef<MCPhysReg> Exceptions = ArrayRef<MCPhysReg>()) const;
1242
1243 virtual const TargetRegisterClass *
1245 const MachineRegisterInfo &MRI) const {
1246 return nullptr;
1247 }
1248
1249 /// Some targets have non-allocatable registers that aren't technically part
1250 /// of the explicit callee saved register list, but should be handled as such
1251 /// in certain cases.
1253 return false;
1254 }
1255
1256 /// Some targets delay assigning the frame until late and use a placeholder
1257 /// to represent it earlier. This method can be used to identify the frame
1258 /// register placeholder.
1259 virtual bool isVirtualFrameRegister(MCRegister Reg) const { return false; }
1260
1261 virtual std::optional<uint8_t> getVRegFlagValue(StringRef Name) const {
1262 return {};
1263 }
1264
1267 return {};
1268 }
1269
1270 // Whether this register should be ignored when generating CodeView debug
1271 // info, because it's a known there is no mapping available.
1272 virtual bool isIgnoredCVReg(MCRegister LLVMReg) const { return false; }
1273};
1274
1275//===----------------------------------------------------------------------===//
1276// SuperRegClassIterator
1277//===----------------------------------------------------------------------===//
1278//
1279// Iterate over the possible super-registers for a given register class. The
1280// iterator will visit a list of pairs (Idx, Mask) corresponding to the
1281// possible classes of super-registers.
1282//
1283// Each bit mask will have at least one set bit, and each set bit in Mask
1284// corresponds to a SuperRC such that:
1285//
1286// For all Reg in SuperRC: Reg:Idx is in RC.
1287//
1288// The iterator can include (O, RC->getSubClassMask()) as the first entry which
1289// also satisfies the above requirement, assuming Reg:0 == Reg.
1290//
1292 const unsigned RCMaskWords;
1293 unsigned SubReg = 0;
1294 const uint16_t *Idx;
1295 const uint32_t *Mask;
1296
1297public:
1298 /// Create a SuperRegClassIterator that visits all the super-register classes
1299 /// of RC. When IncludeSelf is set, also include the (0, sub-classes) entry.
1301 const TargetRegisterInfo *TRI,
1302 bool IncludeSelf = false)
1303 : RCMaskWords((TRI->getNumRegClasses() + 31) / 32),
1304 Idx(RC->getSuperRegIndices()), Mask(RC->getSubClassMask()) {
1305 if (!IncludeSelf)
1306 ++*this;
1307 }
1308
1309 /// Returns true if this iterator is still pointing at a valid entry.
1310 bool isValid() const { return Idx; }
1311
1312 /// Returns the current sub-register index.
1313 unsigned getSubReg() const { return SubReg; }
1314
1315 /// Returns the bit mask of register classes that getSubReg() projects into
1316 /// RC.
1317 /// See TargetRegisterClass::getSubClassMask() for how to use it.
1318 const uint32_t *getMask() const { return Mask; }
1319
1320 /// Advance iterator to the next entry.
1321 void operator++() {
1322 assert(isValid() && "Cannot move iterator past end.");
1323 Mask += RCMaskWords;
1324 SubReg = *Idx++;
1325 if (!SubReg)
1326 Idx = nullptr;
1327 }
1328};
1329
1330//===----------------------------------------------------------------------===//
1331// BitMaskClassIterator
1332//===----------------------------------------------------------------------===//
1333/// This class encapuslates the logic to iterate over bitmask returned by
1334/// the various RegClass related APIs.
1335/// E.g., this class can be used to iterate over the subclasses provided by
1336/// TargetRegisterClass::getSubClassMask or SuperRegClassIterator::getMask.
1338 /// Total number of register classes.
1339 const unsigned NumRegClasses;
1340 /// Base index of CurrentChunk.
1341 /// In other words, the number of bit we read to get at the
1342 /// beginning of that chunck.
1343 unsigned Base = 0;
1344 /// Adjust base index of CurrentChunk.
1345 /// Base index + how many bit we read within CurrentChunk.
1346 unsigned Idx = 0;
1347 /// Current register class ID.
1348 unsigned ID = 0;
1349 /// Mask we are iterating over.
1350 const uint32_t *Mask;
1351 /// Current chunk of the Mask we are traversing.
1352 uint32_t CurrentChunk;
1353
1354 /// Move ID to the next set bit.
1355 void moveToNextID() {
1356 // If the current chunk of memory is empty, move to the next one,
1357 // while making sure we do not go pass the number of register
1358 // classes.
1359 while (!CurrentChunk) {
1360 // Move to the next chunk.
1361 Base += 32;
1362 if (Base >= NumRegClasses) {
1363 ID = NumRegClasses;
1364 return;
1365 }
1366 CurrentChunk = *++Mask;
1367 Idx = Base;
1368 }
1369 // Otherwise look for the first bit set from the right
1370 // (representation of the class ID is big endian).
1371 // See getSubClassMask for more details on the representation.
1372 unsigned Offset = llvm::countr_zero(CurrentChunk);
1373 // Add the Offset to the adjusted base number of this chunk: Idx.
1374 // This is the ID of the register class.
1375 ID = Idx + Offset;
1376
1377 // Consume the zeros, if any, and the bit we just read
1378 // so that we are at the right spot for the next call.
1379 // Do not do Offset + 1 because Offset may be 31 and 32
1380 // will be UB for the shift, though in that case we could
1381 // have make the chunk being equal to 0, but that would
1382 // have introduced a if statement.
1383 moveNBits(Offset);
1384 moveNBits(1);
1385 }
1386
1387 /// Move \p NumBits Bits forward in CurrentChunk.
1388 void moveNBits(unsigned NumBits) {
1389 assert(NumBits < 32 && "Undefined behavior spotted!");
1390 // Consume the bit we read for the next call.
1391 CurrentChunk >>= NumBits;
1392 // Adjust the base for the chunk.
1393 Idx += NumBits;
1394 }
1395
1396public:
1397 /// Create a BitMaskClassIterator that visits all the register classes
1398 /// represented by \p Mask.
1399 ///
1400 /// \pre \p Mask != nullptr
1402 : NumRegClasses(TRI.getNumRegClasses()), Mask(Mask), CurrentChunk(*Mask) {
1403 // Move to the first ID.
1404 moveToNextID();
1405 }
1406
1407 /// Returns true if this iterator is still pointing at a valid entry.
1408 bool isValid() const { return getID() != NumRegClasses; }
1409
1410 /// Returns the current register class ID.
1411 unsigned getID() const { return ID; }
1412
1413 /// Advance iterator to the next entry.
1414 void operator++() {
1415 assert(isValid() && "Cannot move iterator past end.");
1416 moveToNextID();
1417 }
1418};
1419
1420// This is useful when building IndexedMaps keyed on virtual registers
1423 unsigned operator()(Register Reg) const { return Reg.virtRegIndex(); }
1424};
1425
1426/// Prints virtual and physical registers with or without a TRI instance.
1427///
1428/// The format is:
1429/// %noreg - NoRegister
1430/// %5 - a virtual register.
1431/// %5:sub_8bit - a virtual register with sub-register index (with TRI).
1432/// %eax - a physical register
1433/// %physreg17 - a physical register when no TRI instance given.
1434///
1435/// Usage: OS << printReg(Reg, TRI, SubRegIdx) << '\n';
1436LLVM_ABI Printable printReg(Register Reg,
1437 const TargetRegisterInfo *TRI = nullptr,
1438 unsigned SubIdx = 0,
1439 const MachineRegisterInfo *MRI = nullptr);
1440
1441/// Create Printable object to print register units on a \ref raw_ostream.
1442///
1443/// Register units are named after their root registers:
1444///
1445/// al - Single root.
1446/// fp0~st7 - Dual roots.
1447///
1448/// Usage: OS << printRegUnit(Unit, TRI) << '\n';
1449LLVM_ABI Printable printRegUnit(unsigned Unit, const TargetRegisterInfo *TRI);
1450
1451/// Create Printable object to print virtual registers and physical
1452/// registers on a \ref raw_ostream.
1453LLVM_ABI Printable printVRegOrUnit(unsigned VRegOrUnit,
1454 const TargetRegisterInfo *TRI);
1455
1456/// Create Printable object to print register classes or register banks
1457/// on a \ref raw_ostream.
1459 const MachineRegisterInfo &RegInfo,
1460 const TargetRegisterInfo *TRI);
1461
1462} // end namespace llvm
1463
1464#endif // LLVM_CODEGEN_TARGETREGISTERINFO_H
unsigned SubReg
unsigned const MachineRegisterInfo * MRI
MachineInstrBuilder & UseMI
unsigned RegSize
assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")
MachineBasicBlock & MBB
static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
#define LLVM_ABI
Definition Compiler.h:213
IRTranslator LLVM IR MI
const AbstractManglingParser< Derived, Alloc >::OperatorInfo AbstractManglingParser< Derived, Alloc >::Ops[]
A common definition of LaneBitmask for use in TableGen and CodeGen.
Live Register Matrix
#define I(x, y, z)
Definition MD5.cpp:58
Register Reg
Register const TargetRegisterInfo * TRI
Promote Memory to Register
Definition Mem2Reg.cpp:110
#define T
static StringRef getName(Value *V)
static cl::opt< RegAllocEvictionAdvisorAnalysisLegacy::AdvisorMode > Mode("regalloc-enable-advisor", cl::Hidden, cl::init(RegAllocEvictionAdvisorAnalysisLegacy::AdvisorMode::Default), cl::desc("Enable regalloc advisor mode"), cl::values(clEnumValN(RegAllocEvictionAdvisorAnalysisLegacy::AdvisorMode::Default, "default", "Default"), clEnumValN(RegAllocEvictionAdvisorAnalysisLegacy::AdvisorMode::Release, "release", "precompiled"), clEnumValN(RegAllocEvictionAdvisorAnalysisLegacy::AdvisorMode::Development, "development", "for training")))
This file defines the SmallVector class.
static const TargetRegisterClass * getMinimalPhysRegClass(const TargetRegisterInfo *TRI, MCRegister Reg, TypeT Ty)
static const TargetRegisterClass * getCommonMinimalPhysRegClass(const TargetRegisterInfo *TRI, MCRegister Reg1, MCRegister Reg2, TypeT Ty)
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition ArrayRef.h:41
void operator++()
Advance iterator to the next entry.
unsigned getID() const
Returns the current register class ID.
BitMaskClassIterator(const uint32_t *Mask, const TargetRegisterInfo &TRI)
Create a BitMaskClassIterator that visits all the register classes represented by Mask.
bool isValid() const
Returns true if this iterator is still pointing at a valid entry.
DWARF expression.
LiveInterval - This class represents the liveness of a register, or stack slot.
MCRegisterClass - Base class of TargetRegisterClass.
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
unsigned getNumSubRegIndices() const
Return the number of sub-register indices understood by the target.
bool regsOverlap(MCRegister RegA, MCRegister RegB) const
Returns true if the two registers are equal or alias each other.
MCRegister getMatchingSuperReg(MCRegister Reg, unsigned SubIdx, const MCRegisterClass *RC) const
Return a super-register of the specified register Reg so its sub-register of index SubIdx is Reg.
const char * getRegClassName(const MCRegisterClass *Class) const
iterator_range< MCRegUnitIterator > regunits(MCRegister Reg) const
Returns an iterator range over all regunits for Reg.
unsigned getNumRegs() const
Return the number of registers this target has (useful for sizing arrays holding per register informa...
Wrapper class representing physical registers. Should be passed by value.
Definition MCRegister.h:33
Machine Value Type.
MachineInstrBundleIterator< MachineInstr > iterator
Representation of each machine instruction.
MachineOperand class - Representation of each machine instruction operand.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Holds all the information related to register banks.
Wrapper class representing virtual and physical registers.
Definition Register.h:19
MCRegister asMCReg() const
Utility to check-convert this value to a MCRegister.
Definition Register.h:102
constexpr bool isPhysical() const
Return true if the specified register number is in the physical register namespace.
Definition Register.h:78
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
StackOffset holds a fixed and a scalable offset in bytes.
Definition TypeSize.h:31
StringRef - Represent a constant reference to a string, i.e.
Definition StringRef.h:55
void operator++()
Advance iterator to the next entry.
unsigned getSubReg() const
Returns the current sub-register index.
const uint32_t * getMask() const
Returns the bit mask of register classes that getSubReg() projects into RC.
SuperRegClassIterator(const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, bool IncludeSelf=false)
Create a SuperRegClassIterator that visits all the super-register classes of RC.
bool isValid() const
Returns true if this iterator is still pointing at a valid entry.
unsigned getNumRegs() const
Return the number of registers in this class.
const uint8_t TSFlags
Configurable target specific flags.
ArrayRef< MCPhysReg > getRegisters() const
bool isBaseClass() const
Return true if this register class has a defined BaseClassOrder.
const uint16_t * getSuperRegIndices() const
Returns a 0-terminated list of sub-register indices that project some super-register class into this ...
unsigned getID() const
Return the register class ID number.
ArrayRef< MCPhysReg > getRawAllocationOrder(const MachineFunction &MF, bool Rev=false) const
Returns the preferred order for allocating registers from this register class in MF.
const bool HasDisjunctSubRegs
Whether the class supports two (or more) disjunct subregister indices.
bool contains(Register Reg) const
Return true if the specified register is included in this register class.
bool isAllocatable() const
Return true if this register class may be used to create virtual registers.
ArrayRef< MCPhysReg >(* OrderFunc)(const MachineFunction &, bool Rev)
uint8_t getCopyCost() const
Return the cost of copying a value between two registers in this class.
bool hasSubClassEq(const TargetRegisterClass *RC) const
Returns true if RC is a sub-class of or equal to this class.
bool hasSubClass(const TargetRegisterClass *RC) const
Return true if the specified TargetRegisterClass is a proper sub-class of this TargetRegisterClass.
ArrayRef< unsigned > superclasses() const
Returns a list of super-classes.
const MCRegisterClass * MC
const MCPhysReg * const_iterator
bool hasSuperClassEq(const TargetRegisterClass *RC) const
Returns true if RC is a super-class of or equal to this class.
const bool CoveredBySubRegs
Whether a combination of subregisters can cover every register in the class.
LaneBitmask getLaneMask() const
Returns the combination of all lane masks of register in this class.
bool hasSuperClass(const TargetRegisterClass *RC) const
Return true if the specified TargetRegisterClass is a proper super-class of this TargetRegisterClass.
bool contains(Register Reg1, Register Reg2) const
Return true if both registers are in this class.
bool isASubClass() const
Return true if this TargetRegisterClass is a subset class of at least one other TargetRegisterClass.
const uint32_t * getSubClassMask() const
Returns a bit vector of subclasses, including this one.
const uint8_t AllocationPriority
Classes with a higher priority value are assigned first by register allocators using a greedy heurist...
MCRegister getRegister(unsigned i) const
Return the specified register in the class.
iterator begin() const
begin/end - Return all of the registers in this class.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
virtual bool isConstantPhysReg(MCRegister PhysReg) const
Returns true if PhysReg is unallocatable and constant throughout the function.
virtual SmallVector< StringLiteral > getVRegFlagsOfReg(Register Reg, const MachineFunction &MF) const
const TargetRegisterClass *const * regclass_iterator
virtual bool isFrameOffsetLegal(const MachineInstr *MI, Register BaseReg, int64_t Offset) const
Determine whether a given base register plus offset immediate is encodable to resolve a frame index.
vt_iterator legalclasstypes_end(const TargetRegisterClass &RC) const
bool isTypeLegalForClass(const TargetRegisterClass &RC, LLT T) const
Return true if the given TargetRegisterClass is compatible with LLT T.
bool hasRegUnit(MCRegister Reg, MCRegUnit RegUnit) const
Returns true if Reg contains RegUnit.
virtual unsigned getNumRegPressureSets() const =0
Get the number of dimensions of register pressure.
unsigned reverseComposeSubRegIndices(unsigned a, unsigned b) const
Return a subregister index that will compose to give you the subregister index.
iterator_range< regclass_iterator > regclasses() const
virtual const TargetRegisterClass * getPhysRegBaseClass(MCRegister Reg) const
Return target defined base register class for a physical register.
virtual bool canRealignStack(const MachineFunction &MF) const
True if the stack can be realigned for the target.
virtual bool isAsmClobberable(const MachineFunction &MF, MCRegister PhysReg) const
Returns false if we can't guarantee that Physreg, specified as an IR asm clobber constraint,...
virtual const TargetRegisterClass * getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const
Returns the largest legal sub-class of RC that supports the sub-register index Idx.
const TargetRegisterClass * getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
virtual bool useFPForScavengingIndex(const MachineFunction &MF) const
Returns true if the target wants to use frame pointer based accesses to spill to the scavenger emerge...
virtual const TargetRegisterClass * getCrossCopyRegClass(const TargetRegisterClass *RC) const
Returns a legal register class to copy a register in the specified class to or from.
virtual bool isVirtualFrameRegister(MCRegister Reg) const
Some targets delay assigning the frame until late and use a placeholder to represent it earlier.
virtual bool shouldUseLastChanceRecoloringForVirtReg(const MachineFunction &MF, const LiveInterval &VirtReg) const
Last chance recoloring has a high compile time cost especially for targets with a lot of registers.
virtual bool eliminateFrameIndicesBackwards() const
Process frame indices in reverse block order.
unsigned composeSubRegIndices(unsigned a, unsigned b) const
Return the subregister index you get from composing two subregister indices.
virtual LaneBitmask composeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const
Overridden by TableGen in targets that have sub-registers.
virtual bool isIgnoredCVReg(MCRegister LLVMReg) const
virtual bool isGeneralPurposeRegisterClass(const TargetRegisterClass *RC) const
Returns true if RC is a class/subclass of general purpose register.
virtual const int * getRegUnitPressureSets(unsigned RegUnit) const =0
Get the dimensions of register pressure impacted by this register unit.
virtual unsigned getCSRFirstUseCost() const
Allow the target to override the cost of using a callee-saved register for the first time.
void markSuperRegs(BitVector &RegisterSet, MCRegister Reg) const
Mark a register and all its aliases as reserved in the given set.
virtual const MCPhysReg * getIPRACSRegs(const MachineFunction *MF) const
Return a null-terminated list of all of the callee-saved registers on this target when IPRA is on.
virtual const uint32_t * getCustomEHPadPreservedMask(const MachineFunction &MF) const
Return a register mask for the registers preserved by the unwinder, or nullptr if no custom mask is n...
virtual float getSpillWeightScaleFactor(const TargetRegisterClass *RC) const
Get the scale factor of spill weight for this register class.
const MVT::SimpleValueType * vt_iterator
virtual bool isUniformReg(const MachineRegisterInfo &MRI, const RegisterBankInfo &RBI, Register Reg) const
Returns true if the register is considered uniform.
TypeSize getRegSizeInBits(const TargetRegisterClass &RC) const
Return the size in bits of a register from class RC.
virtual std::optional< std::string > explainReservedReg(const MachineFunction &MF, MCRegister PhysReg) const
Returns either a string explaining why the given register is reserved for this function,...
virtual bool requiresFrameIndexScavenging(const MachineFunction &MF) const
Returns true if the target requires post PEI scavenging of registers for materializing frame index co...
const char * getSubRegIndexName(unsigned SubIdx) const
Return the human-readable symbolic target-specific name for the specified SubRegIndex.
virtual const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const
Return a mask of call-preserved registers for the given calling convention on the current function.
virtual const char * getRegPressureSetName(unsigned Idx) const =0
Get the name of this register unit pressure set.
virtual LaneBitmask reverseComposeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const
LaneBitmask getCoveringLanes() const
The lane masks returned by getSubRegIndexLaneMask() above can only be used to determine if sub-regist...
virtual int64_t getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const
Get the offset from the referenced frame index in the instruction, if there is one.
ArrayRef< uint8_t > getRegisterCosts(const MachineFunction &MF) const
Get a list of cost values for all registers that correspond to the index returned by RegisterCostTabl...
virtual bool isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const
Returns true if PhysReg is a general purpose register.
virtual ArrayRef< const uint32_t * > getRegMasks() const =0
Return all the call-preserved register masks defined for this target.
LaneBitmask reverseComposeSubRegIndexLaneMask(unsigned IdxA, LaneBitmask LaneMask) const
Transform a lanemask given for a virtual register to the corresponding lanemask before using subregis...
regclass_iterator regclass_begin() const
Register class iterators.
virtual unsigned getRegPressureSetScore(const MachineFunction &MF, unsigned PSetID) const
Return a heuristic for the machine scheduler to compare the profitability of increasing one register ...
unsigned getNumRegClasses() const
virtual const int * getRegClassPressureSets(const TargetRegisterClass *RC) const =0
Get the dimensions of register pressure impacted by this register class.
virtual const RegClassWeight & getRegClassWeight(const TargetRegisterClass *RC) const =0
Get the weight in units of pressure for this register class.
virtual ArrayRef< MCPhysReg > getIntraCallClobberedRegs(const MachineFunction *MF) const
Return a list of all of the registers which are clobbered "inside" a call to the given function.
virtual bool reverseLocalAssignment() const
Allow the target to reverse allocation order of local live ranges.
virtual bool isNonallocatableRegisterCalleeSave(MCRegister Reg) const
Some targets have non-allocatable registers that aren't technically part of the explicit callee saved...
vt_iterator legalclasstypes_begin(const TargetRegisterClass &RC) const
Loop over all of the value types that can be represented by values in the given register class.
virtual unsigned getRegPressureLimit(const TargetRegisterClass *RC, MachineFunction &MF) const
Return the register pressure "high water mark" for the specific register class.
LaneBitmask getSubRegIndexLaneMask(unsigned SubIdx) const
Return a bitmask representing the parts of a register that are covered by SubIdx.
bool checkAllSuperRegsMarked(const BitVector &RegisterSet, ArrayRef< MCPhysReg > Exceptions=ArrayRef< MCPhysReg >()) const
Returns true if for every register in the set all super registers are part of the set as well.
virtual int64_t getDwarfRegNumForVirtReg(Register RegNum, bool isEH) const
virtual const TargetRegisterClass * getLargestLegalSuperClass(const TargetRegisterClass *RC, const MachineFunction &) const
Returns the largest super class of RC that is legal to use in the current sub-target and has the same...
virtual BitVector getReservedRegs(const MachineFunction &MF) const =0
Returns a bitset indexed by physical register number indicating if a register is a special register t...
const RegClassInfo & getRegClassInfo(const TargetRegisterClass &RC) const
virtual const uint32_t * getNoPreservedMask() const
Return a register mask that clobbers everything.
virtual bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const
Returns true if the live-ins should be tracked after register allocation.
virtual bool isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const
Returns true if PhysReg can be used as an argument to a function.
Align getSpillAlign(const TargetRegisterClass &RC) const
Return the minimum required alignment in bytes for a spill slot for a register of this class.
virtual std::optional< uint8_t > getVRegFlagValue(StringRef Name) const
virtual const TargetRegisterClass * getSubRegisterClass(const TargetRegisterClass *SuperRC, unsigned SubRegIdx) const
Return a register class that can be used for a subregister copy from/into SuperRC at SubRegIdx.
virtual unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const =0
Get the register unit pressure limit for this dimension.
virtual bool requiresFrameIndexReplacementScavenging(const MachineFunction &MF) const
Returns true if the target requires using the RegScavenger directly for frame elimination despite usi...
virtual bool eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const =0
This method must be overriden to eliminate abstract frame indices from instructions which may use the...
virtual bool requiresRegisterScavenging(const MachineFunction &MF) const
Returns true if the target requires (and can make use of) the register scavenger.
regclass_iterator regclass_end() const
LaneBitmask composeSubRegIndexLaneMask(unsigned IdxA, LaneBitmask Mask) const
Transforms a LaneMask computed for one subregister to the lanemask that would have been computed when...
bool hasStackRealignment(const MachineFunction &MF) const
True if stack realignment is required and still possible.
virtual bool shouldAnalyzePhysregInMachineLoopInfo(MCRegister R) const
Returns true if MachineLoopInfo should analyze the given physreg for loop invariance.
virtual bool saveScavengerRegister(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, MachineBasicBlock::iterator &UseMI, const TargetRegisterClass *RC, Register Reg) const
Spill the register so it can be used by the register scavenger.
virtual bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC, unsigned DefSubReg, const TargetRegisterClass *SrcRC, unsigned SrcSubReg) const
MCRegister getMatchingSuperReg(MCRegister Reg, unsigned SubIdx, const TargetRegisterClass *RC) const
Return a super-register of the specified register Reg so its sub-register of index SubIdx is Reg.
virtual bool isCallerPreservedPhysReg(MCRegister PhysReg, const MachineFunction &MF) const
Physical registers that may be modified within a function but are guaranteed to be restored before an...
virtual bool hasReservedSpillSlot(const MachineFunction &MF, Register Reg, int &FrameIdx) const
Return true if target has reserved a spill slot in the stack frame of the given function for the spec...
virtual void resolveFrameIndex(MachineInstr &MI, Register BaseReg, int64_t Offset) const
Resolve a frame index operand of an instruction to reference the indicated base register plus offset ...
virtual unsigned getRegUnitWeight(unsigned RegUnit) const =0
Get the weight in units of pressure for this register unit.
virtual bool isDivergentRegClass(const TargetRegisterClass *RC) const
Returns true if the register class is considered divergent.
virtual Register materializeFrameBaseRegister(MachineBasicBlock *MBB, int FrameIdx, int64_t Offset) const
Insert defining instruction(s) for a pointer to FrameIdx before insertion point I.
bool regsOverlap(Register RegA, Register RegB) const
Returns true if the two registers are equal or alias each other.
virtual bool shouldRealignStack(const MachineFunction &MF) const
True if storage within the function requires the stack pointer to be aligned more than the normal cal...
virtual unsigned getNumSupportedRegs(const MachineFunction &) const
Return the number of registers for the function. (may overestimate)
virtual ArrayRef< const char * > getRegMaskNames() const =0
TargetRegisterInfo(const TargetRegisterInfoDesc *ID, regclass_iterator RCB, regclass_iterator RCE, const char *const *SRINames, const SubRegCoveredBits *SubIdxRanges, const LaneBitmask *SRILaneMasks, LaneBitmask CoveringLanes, const RegClassInfo *const RCIs, const MVT::SimpleValueType *const RCVTLists, unsigned Mode=0)
virtual bool isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const
Returns true if PhysReg is a fixed register.
const TargetRegisterClass * findCommonRegClass(const TargetRegisterClass *DefRC, unsigned DefSubReg, const TargetRegisterClass *SrcRC, unsigned SrcSubReg) const
Find a common register class that can accomodate both the source and destination operands of a copy-l...
virtual const TargetRegisterClass * getConstrainedRegClassForOperand(const MachineOperand &MO, const MachineRegisterInfo &MRI) const
unsigned getSpillSize(const TargetRegisterClass &RC) const
Return the size in bytes of the stack slot allocated to hold a spilled copy of a register from class ...
virtual StringRef getRegAsmName(MCRegister Reg) const
Return the assembly name for Reg.
virtual const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const =0
Return a null-terminated list of all of the callee-saved registers on this target.
bool isTypeLegalForClass(const TargetRegisterClass &RC, MVT T) const
Return true if the given TargetRegisterClass has the ValueType T.
virtual unsigned getRegisterCostTableIndex(const MachineFunction &MF) const
Return the register cost table index.
virtual bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const
Returns true if the instruction's frame index reference would be better served by a base register oth...
virtual unsigned composeSubRegIndicesImpl(unsigned, unsigned) const
Overridden by TableGen in targets that have sub-registers.
virtual const TargetRegisterClass * getPointerRegClass(unsigned Kind=0) const
Returns a TargetRegisterClass used for pointer values.
virtual unsigned reverseComposeSubRegIndicesImpl(unsigned, unsigned) const
Overridden by TableGen in targets that have sub-registers.
virtual void adjustStackMapLiveOutMask(uint32_t *Mask) const
Prior to adding the live-out mask to a stackmap or patchpoint instruction, provide the target the opp...
virtual bool isInlineAsmReadOnlyReg(const MachineFunction &MF, MCRegister PhysReg) const
Returns true if PhysReg cannot be written to in inline asm statements.
virtual bool shouldCoalesce(MachineInstr *MI, const TargetRegisterClass *SrcRC, unsigned SubReg, const TargetRegisterClass *DstRC, unsigned DstSubReg, const TargetRegisterClass *NewRC, LiveIntervals &LIS) const
Subtarget Hooks.
virtual Register getFrameRegister(const MachineFunction &MF) const =0
Debug information queries.
const char * getRegClassName(const TargetRegisterClass *Class) const
Returns the name of the register class.
virtual bool regClassPriorityTrumpsGlobalness(const MachineFunction &MF) const
When prioritizing live ranges in register allocation, if this hook returns true then the AllocationPr...
bool isInAllocatableClass(MCRegister RegNo) const
Return true if the register is in the allocation of any register class.
virtual void updateRegAllocHint(Register Reg, Register NewReg, MachineFunction &MF) const
A callback to allow target a chance to update register allocation hints when a register is "changed" ...
virtual bool getRegAllocationHints(Register VirtReg, ArrayRef< MCPhysReg > Order, SmallVectorImpl< MCPhysReg > &Hints, const MachineFunction &MF, const VirtRegMap *VRM=nullptr, const LiveRegMatrix *Matrix=nullptr) const
Get a list of 'hint' registers that the register allocator should try first when allocating a physica...
virtual bool requiresVirtualBaseRegisters(const MachineFunction &MF) const
Returns true if the target wants the LocalStackAllocation pass to be run and virtual base registers u...
static constexpr TypeSize getFixed(ScalarTy ExactSize)
Definition TypeSize.h:344
A range adaptor for a pair of iterators.
This provides a very simple, boring adaptor for a begin and end iterator into a range type.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition CallingConv.h:24
This is an optimization pass for GlobalISel generic memory operations.
@ Offset
Definition DWP.cpp:477
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
LLVM_ABI Printable printRegUnit(unsigned Unit, const TargetRegisterInfo *TRI)
Create Printable object to print register units on a raw_ostream.
int countr_zero(T Val)
Count number of 0's from the least significant bit to the most stopping at the first 1.
Definition bit.h:186
LLVM_ABI Printable printVRegOrUnit(unsigned VRegOrUnit, const TargetRegisterInfo *TRI)
Create Printable object to print virtual registers and physical registers on a raw_ostream.
LLVM_ABI Printable printRegClassOrBank(Register Reg, const MachineRegisterInfo &RegInfo, const TargetRegisterInfo *TRI)
Create Printable object to print register classes or register banks on a raw_ostream.
unsigned MCRegUnit
Register units are used to compute register aliasing.
Definition MCRegister.h:30
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
Definition MCRegister.h:21
ArrayRef(const T &OneElt) -> ArrayRef< T >
bool is_contained(R &&Range, const E &Element)
Returns true if Element is found in Range.
Definition STLExtras.h:1877
LLVM_ABI Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition Alignment.h:39
Each TargetRegisterClass has a per register weight, and weight limit which must be less than the limi...
Extra information, not in MCRegisterDesc, about registers.
SubRegCoveredBits - Emitted by tablegen: bit range covered by a subreg index, -1 in any being invalid...
unsigned operator()(Register Reg) const