LLVM 23.0.0git
RegisterScavenging.h
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1//===- RegisterScavenging.h - Machine register scavenging -------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9/// \file
10/// This file declares the machine register scavenger class. It can provide
11/// information such as unused register at any point in a machine basic block.
12/// It also provides a mechanism to make registers available by evicting them
13/// to spill slots.
14//
15//===----------------------------------------------------------------------===//
16
17#ifndef LLVM_CODEGEN_REGISTERSCAVENGING_H
18#define LLVM_CODEGEN_REGISTERSCAVENGING_H
19
20#include "llvm/ADT/BitVector.h"
25#include "llvm/MC/LaneBitmask.h"
26
27namespace llvm {
28
29class MachineInstr;
30class TargetInstrInfo;
31class MCRegisterClass;
34
36 const TargetRegisterInfo *TRI = nullptr;
37 const TargetInstrInfo *TII = nullptr;
38 MachineRegisterInfo *MRI = nullptr;
39 MachineBasicBlock *MBB = nullptr;
41
42 /// Information on scavenged registers (held in a spill slot).
43 struct ScavengedInfo {
44 ScavengedInfo(int FI = -1) : FrameIndex(FI) {}
45
46 /// A spill slot used for scavenging a register post register allocation.
47 int FrameIndex;
48
49 /// If non-zero, the specific register is currently being
50 /// scavenged. That is, it is spilled to this scavenging stack slot.
52
53 /// The instruction that restores the scavenged register from stack.
54 const MachineInstr *Restore = nullptr;
55 };
56
57 /// A vector of information on scavenged registers.
59
60 LiveRegUnits LiveUnits;
61
62public:
63 RegScavenger() = default;
64
65 /// Record that \p Reg is in use at scavenging index \p FI. This is for
66 /// targets which need to directly manage the spilling process, and need to
67 /// update the scavenger's internal state. It's expected this be called a
68 /// second time with \p Restore set to a non-null value, so that the
69 /// externally inserted restore instruction resets the scavenged slot
70 /// liveness when encountered.
72 MachineInstr *Restore = nullptr) {
73 for (ScavengedInfo &Slot : Scavenged) {
74 if (Slot.FrameIndex == FI) {
75 assert(!Slot.Reg || Slot.Reg == Reg);
76 Slot.Reg = Reg;
77 Slot.Restore = Restore;
78 return;
79 }
80 }
81
82 llvm_unreachable("did not find scavenging index");
83 }
84
85 /// Start tracking liveness from the begin of basic block \p MBB.
87
88 /// Start tracking liveness from the end of basic block \p MBB.
89 /// Use backward() to move towards the beginning of the block.
91
92 /// Update internal register state and move MBB iterator backwards. This
93 /// method gives precise results even in the absence of kill flags.
94 LLVM_ABI void backward();
95
96 /// Call backward() to update internal register state to just before \p *I.
98 while (MBBI != I)
99 backward();
100 }
101
102 /// Return if a specific register is currently used.
103 LLVM_ABI bool isRegUsed(Register Reg, bool includeReserved = true) const;
104
105 /// Return all available registers in the register class in Mask.
107
108 /// Find an unused register of the specified register class.
109 /// Return 0 if none is found.
111
112 /// Add a scavenging frame index.
114 Scavenged.push_back(ScavengedInfo(FI));
115 }
116
117 /// Query whether a frame index is a scavenging frame index.
118 bool isScavengingFrameIndex(int FI) const {
119 for (const ScavengedInfo &SI : Scavenged)
120 if (SI.FrameIndex == FI)
121 return true;
122
123 return false;
124 }
125
126 /// Get an array of scavenging frame indices.
128 for (const ScavengedInfo &I : Scavenged)
129 if (I.FrameIndex >= 0)
130 A.push_back(I.FrameIndex);
131 }
132
133 size_t getNumScavengingFrameIndices() const { return Scavenged.size(); }
134
135 /// Make a register of the specific register class available from the current
136 /// position backwards to the place before \p To. If \p RestoreAfter is true
137 /// this includes the instruction following the current position.
138 /// SPAdj is the stack adjustment due to call frame, it's passed along to
139 /// eliminateFrameIndex().
140 /// Returns the scavenged register.
141 ///
142 /// If \p AllowSpill is false, fail if a spill is required to make the
143 /// register available, and return NoRegister.
146 bool RestoreAfter, int SPAdj,
147 bool AllowSpill = true);
148
149 /// Tell the scavenger a register is used.
151 LaneBitmask LaneMask = LaneBitmask::getAll());
152
153private:
154 /// Returns true if a register is reserved. It is never "unused".
155 bool isReserved(Register Reg) const { return MRI->isReserved(Reg); }
156
157 /// Initialize RegisterScavenger.
158 void init(MachineBasicBlock &MBB);
159
160 /// Spill a register after position \p After and reload it before position
161 /// \p UseMI.
162 ScavengedInfo &spill(Register Reg, const TargetRegisterClass &RC, int SPAdj,
165};
166
167/// Replaces all frame index virtual registers with physical registers. Uses the
168/// register scavenger to find an appropriate register to use.
170
171} // end namespace llvm
172
173#endif // LLVM_CODEGEN_REGISTERSCAVENGING_H
MachineInstrBuilder & UseMI
assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")
MachineBasicBlock & MBB
This file implements the BitVector class.
static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")
#define LLVM_ABI
Definition Compiler.h:215
A common definition of LaneBitmask for use in TableGen and CodeGen.
A set of register units.
#define I(x, y, z)
Definition MD5.cpp:57
Register Reg
Promote Memory to Register
Definition Mem2Reg.cpp:110
This file defines the SmallVector class.
A set of register units used to track register liveness.
MCRegisterClass - Base class of TargetRegisterClass.
MachineInstrBundleIterator< MachineInstr > iterator
Representation of each machine instruction.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
bool isReserved(MCRegister PhysReg) const
isReserved - Returns true when PhysReg is a reserved register.
void backward(MachineBasicBlock::iterator I)
Call backward() to update internal register state to just before *I.
LLVM_ABI void enterBasicBlockEnd(MachineBasicBlock &MBB)
Start tracking liveness from the end of basic block MBB.
LLVM_ABI bool isRegUsed(Register Reg, bool includeReserved=true) const
Return if a specific register is currently used.
LLVM_ABI Register FindUnusedReg(const TargetRegisterClass *RC) const
Find an unused register of the specified register class.
LLVM_ABI void setRegUsed(Register Reg, LaneBitmask LaneMask=LaneBitmask::getAll())
Tell the scavenger a register is used.
void assignRegToScavengingIndex(int FI, Register Reg, MachineInstr *Restore=nullptr)
Record that Reg is in use at scavenging index FI.
LLVM_ABI void backward()
Update internal register state and move MBB iterator backwards.
LLVM_ABI void enterBasicBlock(MachineBasicBlock &MBB)
Start tracking liveness from the begin of basic block MBB.
LLVM_ABI Register scavengeRegisterBackwards(const TargetRegisterClass &RC, MachineBasicBlock::iterator To, bool RestoreAfter, int SPAdj, bool AllowSpill=true)
Make a register of the specific register class available from the current position backwards to the p...
void getScavengingFrameIndices(SmallVectorImpl< int > &A) const
Get an array of scavenging frame indices.
bool isScavengingFrameIndex(int FI) const
Query whether a frame index is a scavenging frame index.
RegScavenger()=default
size_t getNumScavengingFrameIndices() const
void addScavengingFrameIndex(int FI)
Add a scavenging frame index.
LLVM_ABI BitVector getRegsAvailable(const TargetRegisterClass *RC)
Return all available registers in the register class in Mask.
Wrapper class representing virtual and physical registers.
Definition Register.h:20
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
TargetInstrInfo - Interface to description of machine instruction set.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
This is an optimization pass for GlobalISel generic memory operations.
LLVM_ABI void scavengeFrameVirtualRegs(MachineFunction &MF, RegScavenger &RS)
Replaces all frame index virtual registers with physical registers.
MCRegisterClass TargetRegisterClass
Definition FastISel.h:58
static constexpr LaneBitmask getAll()
Definition LaneBitmask.h:82