Representation of each machine instruction. More...
#include "llvm/CodeGen/MachineInstr.h"
Public Member Functions | |
| MachineInstr (const MachineInstr &)=delete | |
| MachineInstr & | operator= (const MachineInstr &)=delete |
| ~MachineInstr ()=delete | |
| const MachineBasicBlock * | getParent () const |
| MachineBasicBlock * | getParent () |
| LLVM_ABI void | moveBefore (MachineInstr *MovePos) |
Move the instruction before MovePos. | |
| LLVM_ABI const MachineFunction * | getMF () const |
| Return the function that contains the basic block that this instruction belongs to. | |
| MachineFunction * | getMF () |
| uint8_t | getAsmPrinterFlags () const |
| Return the asm printer flags bitvector. | |
| void | clearAsmPrinterFlags () |
| Clear the AsmPrinter bitvector. | |
| bool | getAsmPrinterFlag (CommentFlag Flag) const |
| Return whether an AsmPrinter flag is set. | |
| void | setAsmPrinterFlag (uint8_t Flag) |
| Set a flag for the AsmPrinter. | |
| void | clearAsmPrinterFlag (CommentFlag Flag) |
| Clear specific AsmPrinter flags. | |
| uint32_t | getFlags () const |
| Return the MI flags bitvector. | |
| bool | getFlag (MIFlag Flag) const |
| Return whether an MI flag is set. | |
| void | setFlag (MIFlag Flag) |
| Set a MI flag. | |
| void | setFlags (unsigned flags) |
| void | clearFlag (MIFlag Flag) |
| clearFlag - Clear a MI flag. | |
| void | clearFlags (unsigned flags) |
| bool | isInsideBundle () const |
| Return true if MI is in a bundle (but not the first MI in a bundle). | |
| bool | isBundled () const |
| Return true if this instruction part of a bundle. | |
| bool | isBundledWithPred () const |
| Return true if this instruction is part of a bundle, and it is not the first instruction in the bundle. | |
| bool | isBundledWithSucc () const |
| Return true if this instruction is part of a bundle, and it is not the last instruction in the bundle. | |
| LLVM_ABI void | bundleWithPred () |
| Bundle this instruction with its predecessor. | |
| LLVM_ABI void | bundleWithSucc () |
| Bundle this instruction with its successor. | |
| LLVM_ABI void | unbundleFromPred () |
| Break bundle above this instruction. | |
| LLVM_ABI void | unbundleFromSucc () |
| Break bundle below this instruction. | |
| const DebugLoc & | getDebugLoc () const |
| Returns the debug location id of this MachineInstr. | |
| const MachineOperand & | getDebugOffset () const |
| Return the operand containing the offset to be used if this DBG_VALUE instruction is indirect; will be an invalid register if this value is not indirect, and an immediate with value 0 otherwise. | |
| MachineOperand & | getDebugOffset () |
| LLVM_ABI const MachineOperand & | getDebugVariableOp () const |
| Return the operand for the debug variable referenced by this DBG_VALUE instruction. | |
| LLVM_ABI MachineOperand & | getDebugVariableOp () |
| LLVM_ABI const DILocalVariable * | getDebugVariable () const |
| Return the debug variable referenced by this DBG_VALUE instruction. | |
| LLVM_ABI const MachineOperand & | getDebugExpressionOp () const |
| Return the operand for the complex address expression referenced by this DBG_VALUE instruction. | |
| LLVM_ABI MachineOperand & | getDebugExpressionOp () |
| LLVM_ABI const DIExpression * | getDebugExpression () const |
| Return the complex address expression referenced by this DBG_VALUE instruction. | |
| LLVM_ABI const DILabel * | getDebugLabel () const |
| Return the debug label referenced by this DBG_LABEL instruction. | |
| LLVM_ABI unsigned | getDebugInstrNum () |
| Fetch the instruction number of this MachineInstr. | |
| LLVM_ABI unsigned | getDebugInstrNum (MachineFunction &MF) |
Fetch instruction number of this MachineInstr – but before it's inserted into MF. | |
| unsigned | peekDebugInstrNum () const |
| Examine the instruction number of this MachineInstr. | |
| void | setDebugInstrNum (unsigned Num) |
| Set instruction number of this MachineInstr. | |
| void | dropDebugNumber () |
| Drop any variable location debugging information associated with this instruction. | |
| LLVM_ABI const MDNode * | getLocCookieMD () const |
| For inline asm, get the !srcloc metadata node if we have it, and decode the loc cookie from it. | |
| LLVM_ABI void | emitInlineAsmError (const Twine &ErrMsg) const |
| Emit an error referring to the source location of this instruction. | |
| LLVM_ABI void | emitGenericError (const Twine &ErrMsg) const |
| const MCInstrDesc & | getDesc () const |
| Returns the target instruction descriptor of this MachineInstr. | |
| unsigned | getOpcode () const |
| Returns the opcode of this MachineInstr. | |
| unsigned | getNumOperands () const |
| Retuns the total number of operands. | |
| unsigned | getNumDebugOperands () const |
| Returns the total number of operands which are debug locations. | |
| const MachineOperand & | getOperand (unsigned i) const |
| MachineOperand & | getOperand (unsigned i) |
| MachineOperand & | getDebugOperand (unsigned Index) |
| const MachineOperand & | getDebugOperand (unsigned Index) const |
| bool | hasDebugOperandForReg (Register Reg) const |
Returns whether this debug value has at least one debug operand with the register Reg. | |
| LLVM_ABI iterator_range< filter_iterator< const MachineOperand *, std::function< bool(const MachineOperand &Op)> > > | getDebugOperandsForReg (Register Reg) const |
Returns a range of all of the operands that correspond to a debug use of Reg. | |
| LLVM_ABI iterator_range< filter_iterator< MachineOperand *, std::function< bool(MachineOperand &Op)> > > | getDebugOperandsForReg (Register Reg) |
| bool | isDebugOperand (const MachineOperand *Op) const |
| unsigned | getDebugOperandIndex (const MachineOperand *Op) const |
| unsigned | getNumDefs () const |
| Returns the total number of definitions. | |
| bool | hasImplicitDef () const |
| Returns true if the instruction has implicit definition. | |
| unsigned | getNumImplicitOperands () const |
| Returns the implicit operands number. | |
| bool | isOperandSubregIdx (unsigned OpIdx) const |
Return true if operand OpIdx is a subregister index. | |
| LLVM_ABI unsigned | getNumExplicitOperands () const |
| Returns the number of non-implicit operands. | |
| LLVM_ABI unsigned | getNumExplicitDefs () const |
| Returns the number of non-implicit definitions. | |
| mop_iterator | operands_begin () |
| mop_iterator | operands_end () |
| const_mop_iterator | operands_begin () const |
| const_mop_iterator | operands_end () const |
| mop_range | operands () |
| const_mop_range | operands () const |
| mop_range | explicit_operands () |
| const_mop_range | explicit_operands () const |
| mop_range | implicit_operands () |
| const_mop_range | implicit_operands () const |
| mop_range | debug_operands () |
| Returns all operands that are used to determine the variable location for this DBG_VALUE instruction. | |
| const_mop_range | debug_operands () const |
| Returns all operands that are used to determine the variable location for this DBG_VALUE instruction. | |
| mop_range | defs () |
| Returns all explicit operands that are register definitions. | |
| const_mop_range | defs () const |
| Returns all explicit operands that are register definitions. | |
| mop_range | uses () |
| Returns all operands which may be register uses. | |
| const_mop_range | uses () const |
| Returns all operands which may be register uses. | |
| mop_range | explicit_uses () |
| const_mop_range | explicit_uses () const |
| filtered_mop_range | all_defs () |
| Returns an iterator range over all operands that are (explicit or implicit) register defs. | |
| filtered_const_mop_range | all_defs () const |
| Returns an iterator range over all operands that are (explicit or implicit) register defs. | |
| filtered_mop_range | all_uses () |
| Returns an iterator range over all operands that are (explicit or implicit) register uses. | |
| filtered_const_mop_range | all_uses () const |
| Returns an iterator range over all operands that are (explicit or implicit) register uses. | |
| unsigned | getOperandNo (const_mop_iterator I) const |
Returns the number of the operand iterator I points to. | |
| ArrayRef< MachineMemOperand * > | memoperands () const |
| Access to memory operands of the instruction. | |
| mmo_iterator | memoperands_begin () const |
| Access to memory operands of the instruction. | |
| mmo_iterator | memoperands_end () const |
| Access to memory operands of the instruction. | |
| bool | memoperands_empty () const |
| Return true if we don't have any memory operands which described the memory access done by this instruction. | |
| bool | hasOneMemOperand () const |
| Return true if this instruction has exactly one MachineMemOperand. | |
| unsigned | getNumMemOperands () const |
| Return the number of memory operands. | |
| MCSymbol * | getPreInstrSymbol () const |
| Helper to extract a pre-instruction symbol if one has been added. | |
| MCSymbol * | getPostInstrSymbol () const |
| Helper to extract a post-instruction symbol if one has been added. | |
| MDNode * | getHeapAllocMarker () const |
| Helper to extract a heap alloc marker if one has been added. | |
| MDNode * | getPCSections () const |
| Helper to extract PCSections metadata target sections. | |
| MDNode * | getMMRAMetadata () const |
| Helper to extract mmra.op metadata. | |
| uint32_t | getCFIType () const |
| Helper to extract a CFI type hash if one has been added. | |
| bool | hasProperty (unsigned MCFlag, QueryType Type=AnyInBundle) const |
| Return true if the instruction (or in the case of a bundle, the instructions inside the bundle) has the specified property. | |
| bool | isPreISelOpcode (QueryType Type=IgnoreBundle) const |
| Return true if this is an instruction that should go through the usual legalization steps. | |
| bool | isVariadic (QueryType Type=IgnoreBundle) const |
| Return true if this instruction can have a variable number of operands. | |
| bool | hasOptionalDef (QueryType Type=IgnoreBundle) const |
| Set if this instruction has an optional definition, e.g. | |
| bool | isPseudo (QueryType Type=IgnoreBundle) const |
| Return true if this is a pseudo instruction that doesn't correspond to a real machine instruction. | |
| bool | isMetaInstruction (QueryType Type=IgnoreBundle) const |
| Return true if this instruction doesn't produce any output in the form of executable instructions. | |
| bool | isReturn (QueryType Type=AnyInBundle) const |
| bool | isEHScopeReturn (QueryType Type=AnyInBundle) const |
| Return true if this is an instruction that marks the end of an EH scope, i.e., a catchpad or a cleanuppad instruction. | |
| bool | isCall (QueryType Type=AnyInBundle) const |
| LLVM_ABI bool | isCandidateForAdditionalCallInfo (QueryType Type=IgnoreBundle) const |
| Return true if this is a call instruction that may have an additional information associated with it. | |
| LLVM_ABI bool | shouldUpdateAdditionalCallInfo () const |
| Return true if copying, moving, or erasing this instruction requires updating additional call info (see copyCallInfo, moveCallInfo, eraseCallInfo). | |
| bool | isBarrier (QueryType Type=AnyInBundle) const |
| Returns true if the specified instruction stops control flow from executing the instruction immediately following it. | |
| bool | isTerminator (QueryType Type=AnyInBundle) const |
| Returns true if this instruction part of the terminator for a basic block. | |
| bool | isBranch (QueryType Type=AnyInBundle) const |
| Returns true if this is a conditional, unconditional, or indirect branch. | |
| bool | isIndirectBranch (QueryType Type=AnyInBundle) const |
| Return true if this is an indirect branch, such as a branch through a register. | |
| bool | isConditionalBranch (QueryType Type=AnyInBundle) const |
| Return true if this is a branch which may fall through to the next instruction or may transfer control flow to some other block. | |
| bool | isUnconditionalBranch (QueryType Type=AnyInBundle) const |
| Return true if this is a branch which always transfers control flow to some other block. | |
| bool | isPredicable (QueryType Type=AllInBundle) const |
| Return true if this instruction has a predicate operand that controls execution. | |
| bool | isCompare (QueryType Type=IgnoreBundle) const |
| Return true if this instruction is a comparison. | |
| bool | isMoveImmediate (QueryType Type=IgnoreBundle) const |
| Return true if this instruction is a move immediate (including conditional moves) instruction. | |
| bool | isMoveReg (QueryType Type=IgnoreBundle) const |
| Return true if this instruction is a register move. | |
| bool | isBitcast (QueryType Type=IgnoreBundle) const |
| Return true if this instruction is a bitcast instruction. | |
| bool | isSelect (QueryType Type=IgnoreBundle) const |
| Return true if this instruction is a select instruction. | |
| bool | isNotDuplicable (QueryType Type=AnyInBundle) const |
| Return true if this instruction cannot be safely duplicated. | |
| bool | isConvergent (QueryType Type=AnyInBundle) const |
| Return true if this instruction is convergent. | |
| bool | hasDelaySlot (QueryType Type=AnyInBundle) const |
| Returns true if the specified instruction has a delay slot which must be filled by the code generator. | |
| bool | canFoldAsLoad (QueryType Type=IgnoreBundle) const |
| Return true for instructions that can be folded as memory operands in other instructions. | |
| bool | isRegSequenceLike (QueryType Type=IgnoreBundle) const |
| Return true if this instruction behaves the same way as the generic REG_SEQUENCE instructions. | |
| bool | isExtractSubregLike (QueryType Type=IgnoreBundle) const |
| Return true if this instruction behaves the same way as the generic EXTRACT_SUBREG instructions. | |
| bool | isInsertSubregLike (QueryType Type=IgnoreBundle) const |
| Return true if this instruction behaves the same way as the generic INSERT_SUBREG instructions. | |
| bool | mayLoad (QueryType Type=AnyInBundle) const |
| Return true if this instruction could possibly read memory. | |
| bool | mayStore (QueryType Type=AnyInBundle) const |
| Return true if this instruction could possibly modify memory. | |
| bool | mayLoadOrStore (QueryType Type=AnyInBundle) const |
| Return true if this instruction could possibly read or modify memory. | |
| bool | mayRaiseFPException () const |
| Return true if this instruction could possibly raise a floating-point exception. | |
| bool | isCommutable (QueryType Type=IgnoreBundle) const |
| Return true if this may be a 2- or 3-address instruction (of the form "X = op Y, Z, ..."), which produces the same result if Y and Z are exchanged. | |
| bool | isConvertibleTo3Addr (QueryType Type=IgnoreBundle) const |
| Return true if this is a 2-address instruction which can be changed into a 3-address instruction if needed. | |
| bool | usesCustomInsertionHook (QueryType Type=IgnoreBundle) const |
| Return true if this instruction requires custom insertion support when the DAG scheduler is inserting it into a machine basic block. | |
| bool | hasPostISelHook (QueryType Type=IgnoreBundle) const |
| Return true if this instruction requires adjustment after instruction selection by calling a target hook. | |
| bool | isRematerializable (QueryType Type=AllInBundle) const |
| Returns true if this instruction is a candidate for remat. | |
| bool | isAsCheapAsAMove (QueryType Type=AllInBundle) const |
| Returns true if this instruction has the same cost (or less) than a move instruction. | |
| bool | hasExtraSrcRegAllocReq (QueryType Type=AnyInBundle) const |
| Returns true if this instruction source operands have special register allocation requirements that are not captured by the operand register classes. | |
| bool | hasExtraDefRegAllocReq (QueryType Type=AnyInBundle) const |
| Returns true if this instruction def operands have special register allocation requirements that are not captured by the operand register classes. | |
| LLVM_ABI bool | isIdenticalTo (const MachineInstr &Other, MICheckType Check=CheckDefs) const |
Return true if this instruction is identical to Other. | |
| LLVM_ABI bool | isEquivalentDbgInstr (const MachineInstr &Other) const |
Returns true if this instruction is a debug instruction that represents an identical debug value to Other. | |
| LLVM_ABI MachineInstr * | removeFromParent () |
| Unlink 'this' from the containing basic block, and return it without deleting it. | |
| LLVM_ABI MachineInstr * | removeFromBundle () |
| Unlink this instruction from its basic block and return it without deleting it. | |
| LLVM_ABI void | eraseFromParent () |
| Unlink 'this' from the containing basic block and delete it. | |
| LLVM_ABI void | eraseFromBundle () |
| Unlink 'this' from its basic block and delete it. | |
| bool | isEHLabel () const |
| bool | isGCLabel () const |
| bool | isAnnotationLabel () const |
| bool | isLifetimeMarker () const |
| bool | isLabel () const |
| Returns true if the MachineInstr represents a label. | |
| bool | isCFIInstruction () const |
| bool | isPseudoProbe () const |
| bool | isPosition () const |
| bool | isNonListDebugValue () const |
| bool | isDebugValueList () const |
| bool | isDebugValue () const |
| bool | isDebugLabel () const |
| bool | isDebugRef () const |
| bool | isDebugValueLike () const |
| bool | isDebugPHI () const |
| bool | isDebugInstr () const |
| bool | isDebugOrPseudoInstr () const |
| bool | isDebugOffsetImm () const |
| bool | isIndirectDebugValue () const |
| A DBG_VALUE is indirect iff the location operand is a register and the offset operand is an immediate. | |
| LLVM_ABI bool | isDebugEntryValue () const |
| A DBG_VALUE is an entry value iff its debug expression contains the DW_OP_LLVM_entry_value operation. | |
| bool | isUndefDebugValue () const |
| Return true if the instruction is a debug value which describes a part of a variable as unavailable. | |
| bool | isJumpTableDebugInfo () const |
| bool | isPHI () const |
| bool | isKill () const |
| bool | isImplicitDef () const |
| bool | isInlineAsm () const |
| LLVM_ABI bool | mayFoldInlineAsmRegOp (unsigned OpId) const |
| Returns true if the register operand can be folded with a load or store into a frame index. | |
| LLVM_ABI bool | isStackAligningInlineAsm () const |
| LLVM_ABI InlineAsm::AsmDialect | getInlineAsmDialect () const |
| bool | isInsertSubreg () const |
| bool | isSubregToReg () const |
| bool | isRegSequence () const |
| bool | isBundle () const |
| bool | isCopy () const |
| bool | isFullCopy () const |
| bool | isExtractSubreg () const |
| bool | isFakeUse () const |
| bool | isCopyLike () const |
| Return true if the instruction behaves like a copy. | |
| bool | isIdentityCopy () const |
| Return true is the instruction is an identity copy. | |
| bool | isTransient () const |
| Return true if this is a transient instruction that is either very likely to be eliminated during register allocation (such as copy-like instructions), or if this instruction doesn't have an execution-time cost. | |
| LLVM_ABI unsigned | getBundleSize () const |
| Return the number of instructions inside the MI bundle, excluding the bundle header. | |
| bool | readsRegister (Register Reg, const TargetRegisterInfo *TRI) const |
| Return true if the MachineInstr reads the specified register. | |
| bool | readsVirtualRegister (Register Reg) const |
| Return true if the MachineInstr reads the specified virtual register. | |
| LLVM_ABI std::pair< bool, bool > | readsWritesVirtualRegister (Register Reg, SmallVectorImpl< unsigned > *Ops=nullptr) const |
| Return a pair of bools (reads, writes) indicating if this instruction reads or writes Reg. | |
| bool | killsRegister (Register Reg, const TargetRegisterInfo *TRI) const |
| Return true if the MachineInstr kills the specified register. | |
| bool | definesRegister (Register Reg, const TargetRegisterInfo *TRI) const |
| Return true if the MachineInstr fully defines the specified register. | |
| bool | modifiesRegister (Register Reg, const TargetRegisterInfo *TRI) const |
| Return true if the MachineInstr modifies (fully define or partially define) the specified register. | |
| bool | registerDefIsDead (Register Reg, const TargetRegisterInfo *TRI) const |
| Returns true if the register is dead in this machine instruction. | |
| LLVM_ABI bool | hasRegisterImplicitUseOperand (Register Reg) const |
| Returns true if the MachineInstr has an implicit-use operand of exactly the given register (not considering sub/super-registers). | |
| LLVM_ABI int | findRegisterUseOperandIdx (Register Reg, const TargetRegisterInfo *TRI, bool isKill=false) const |
| Returns the operand index that is a use of the specific register or -1 if it is not found. | |
| MachineOperand * | findRegisterUseOperand (Register Reg, const TargetRegisterInfo *TRI, bool isKill=false) |
| Wrapper for findRegisterUseOperandIdx, it returns a pointer to the MachineOperand rather than an index. | |
| const MachineOperand * | findRegisterUseOperand (Register Reg, const TargetRegisterInfo *TRI, bool isKill=false) const |
| LLVM_ABI int | findRegisterDefOperandIdx (Register Reg, const TargetRegisterInfo *TRI, bool isDead=false, bool Overlap=false) const |
| Returns the operand index that is a def of the specified register or -1 if it is not found. | |
| MachineOperand * | findRegisterDefOperand (Register Reg, const TargetRegisterInfo *TRI, bool isDead=false, bool Overlap=false) |
| Wrapper for findRegisterDefOperandIdx, it returns a pointer to the MachineOperand rather than an index. | |
| const MachineOperand * | findRegisterDefOperand (Register Reg, const TargetRegisterInfo *TRI, bool isDead=false, bool Overlap=false) const |
| LLVM_ABI int | findFirstPredOperandIdx () const |
| Find the index of the first operand in the operand list that is used to represent the predicate. | |
| LLVM_ABI int | findInlineAsmFlagIdx (unsigned OpIdx, unsigned *GroupNo=nullptr) const |
| Find the index of the flag word operand that corresponds to operand OpIdx on an inline asm instruction. | |
| LLVM_ABI const TargetRegisterClass * | getRegClassConstraint (unsigned OpIdx, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const |
| Compute the static register class constraint for operand OpIdx. | |
| LLVM_ABI const TargetRegisterClass * | getRegClassConstraintEffectForVReg (Register Reg, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI, bool ExploreBundle=false) const |
Applies the constraints (def/use) implied by this MI on Reg to the given CurRC. | |
| LLVM_ABI const TargetRegisterClass * | getRegClassConstraintEffect (unsigned OpIdx, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const |
Applies the constraints (def/use) implied by the OpIdx operand to the given CurRC. | |
| LLVM_ABI void | tieOperands (unsigned DefIdx, unsigned UseIdx) |
| Add a tie between the register operands at DefIdx and UseIdx. | |
| LLVM_ABI unsigned | findTiedOperandIdx (unsigned OpIdx) const |
| Given the index of a tied register operand, find the operand it is tied to. | |
| bool | isRegTiedToUseOperand (unsigned DefOpIdx, unsigned *UseOpIdx=nullptr) const |
| Given the index of a register def operand, check if the register def is tied to a source operand, due to either two-address elimination or inline assembly constraints. | |
| bool | isRegTiedToDefOperand (unsigned UseOpIdx, unsigned *DefOpIdx=nullptr) const |
| Return true if the use operand of the specified index is tied to a def operand. | |
| LLVM_ABI void | clearKillInfo () |
| Clears kill flags on all operands. | |
| LLVM_ABI void | substituteRegister (Register FromReg, Register ToReg, unsigned SubIdx, const TargetRegisterInfo &RegInfo) |
| Replace all occurrences of FromReg with ToReg:SubIdx, properly composing subreg indices where necessary. | |
| LLVM_ABI bool | addRegisterKilled (Register IncomingReg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false) |
| We have determined MI kills a register. | |
| LLVM_ABI void | clearRegisterKills (Register Reg, const TargetRegisterInfo *RegInfo) |
| Clear all kill flags affecting Reg. | |
| LLVM_ABI bool | addRegisterDead (Register Reg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false) |
| We have determined MI defined a register without a use. | |
| LLVM_ABI void | clearRegisterDeads (Register Reg) |
Clear all dead flags on operands defining register Reg. | |
| LLVM_ABI void | setRegisterDefReadUndef (Register Reg, bool IsUndef=true) |
Mark all subregister defs of register Reg with the undef flag. | |
| LLVM_ABI void | addRegisterDefined (Register Reg, const TargetRegisterInfo *RegInfo=nullptr) |
| We have determined MI defines a register. | |
| LLVM_ABI void | setPhysRegsDeadExcept (ArrayRef< Register > UsedRegs, const TargetRegisterInfo &TRI) |
| Mark every physreg used by this instruction as dead except those in the UsedRegs list. | |
| LLVM_ABI bool | isSafeToMove (bool &SawStore) const |
| Return true if it is safe to move this instruction. | |
| LLVM_ABI bool | wouldBeTriviallyDead () const |
| Return true if this instruction would be trivially dead if all of its defined registers were dead. | |
| LLVM_ABI bool | isDead (const MachineRegisterInfo &MRI, LiveRegUnits *LivePhysRegs=nullptr) const |
| Check whether an MI is dead. | |
| LLVM_ABI bool | mayAlias (BatchAAResults *AA, const MachineInstr &Other, bool UseTBAA) const |
| Returns true if this instruction's memory access aliases the memory access of Other. | |
| LLVM_ABI bool | mayAlias (AAResults *AA, const MachineInstr &Other, bool UseTBAA) const |
| LLVM_ABI bool | hasOrderedMemoryRef () const |
| Return true if this instruction may have an ordered or volatile memory reference, or if the information describing the memory reference is not available. | |
| LLVM_ABI bool | isDereferenceableInvariantLoad () const |
| Return true if this load instruction never traps and points to a memory location whose value doesn't change during the execution of this function. | |
| LLVM_ABI Register | isConstantValuePHI () const |
| If the specified instruction is a PHI that always merges together the same virtual register, return the register, otherwise return Register(). | |
| LLVM_ABI bool | hasUnmodeledSideEffects () const |
| Return true if this instruction has side effects that are not modeled by mayLoad / mayStore, etc. | |
| LLVM_ABI bool | isLoadFoldBarrier () const |
| Returns true if it is illegal to fold a load across this instruction. | |
| LLVM_ABI bool | allDefsAreDead () const |
| Return true if all the defs of this instruction are dead. | |
| LLVM_ABI bool | allImplicitDefsAreDead () const |
| Return true if all the implicit defs of this instruction are dead. | |
| LLVM_ABI std::optional< LocationSize > | getSpillSize (const TargetInstrInfo *TII) const |
| Return a valid size if the instruction is a spill instruction. | |
| LLVM_ABI std::optional< LocationSize > | getFoldedSpillSize (const TargetInstrInfo *TII) const |
| Return a valid size if the instruction is a folded spill instruction. | |
| LLVM_ABI std::optional< LocationSize > | getRestoreSize (const TargetInstrInfo *TII) const |
| Return a valid size if the instruction is a restore instruction. | |
| LLVM_ABI std::optional< LocationSize > | getFoldedRestoreSize (const TargetInstrInfo *TII) const |
| Return a valid size if the instruction is a folded restore instruction. | |
| LLVM_ABI void | copyImplicitOps (MachineFunction &MF, const MachineInstr &MI) |
| Copy implicit register operands from specified instruction to this instruction. | |
| LLVM_ABI void | addOperand (MachineFunction &MF, const MachineOperand &Op) |
| Add the specified operand to the instruction. | |
| LLVM_ABI void | addOperand (const MachineOperand &Op) |
| Add an operand without providing an MF reference. | |
| LLVM_ABI void | insert (mop_iterator InsertBefore, ArrayRef< MachineOperand > Ops) |
| Inserts Ops BEFORE It. Can untie/retie tied operands. | |
| LLVM_ABI void | setDesc (const MCInstrDesc &TID) |
| Replace the instruction descriptor (thus opcode) of the current instruction with a new one. | |
| void | setDebugLoc (DebugLoc DL) |
| Replace current source information with new such. | |
| LLVM_ABI void | removeOperand (unsigned OpNo) |
| Erase an operand from an instruction, leaving it with one fewer operand than it started with. | |
| LLVM_ABI void | dropMemRefs (MachineFunction &MF) |
| Clear this MachineInstr's memory reference descriptor list. | |
| LLVM_ABI void | setMemRefs (MachineFunction &MF, ArrayRef< MachineMemOperand * > MemRefs) |
| Assign this MachineInstr's memory reference descriptor list. | |
| LLVM_ABI void | addMemOperand (MachineFunction &MF, MachineMemOperand *MO) |
| Add a MachineMemOperand to the machine instruction. | |
| LLVM_ABI void | cloneMemRefs (MachineFunction &MF, const MachineInstr &MI) |
| Clone another MachineInstr's memory reference descriptor list and replace ours with it. | |
| LLVM_ABI void | cloneMergedMemRefs (MachineFunction &MF, ArrayRef< const MachineInstr * > MIs) |
| Clone the merge of multiple MachineInstrs' memory reference descriptors list and replace ours with it. | |
| LLVM_ABI void | setPreInstrSymbol (MachineFunction &MF, MCSymbol *Symbol) |
| Set a symbol that will be emitted just prior to the instruction itself. | |
| LLVM_ABI void | setPostInstrSymbol (MachineFunction &MF, MCSymbol *Symbol) |
| Set a symbol that will be emitted just after the instruction itself. | |
| LLVM_ABI void | cloneInstrSymbols (MachineFunction &MF, const MachineInstr &MI) |
| Clone another MachineInstr's pre- and post- instruction symbols and replace ours with it. | |
| LLVM_ABI void | setHeapAllocMarker (MachineFunction &MF, MDNode *MD) |
| Set a marker on instructions that denotes where we should create and emit heap alloc site labels. | |
| LLVM_ABI void | setPCSections (MachineFunction &MF, MDNode *MD) |
| LLVM_ABI void | setMMRAMetadata (MachineFunction &MF, MDNode *MMRAs) |
| LLVM_ABI void | setCFIType (MachineFunction &MF, uint32_t Type) |
| Set the CFI type for the instruction. | |
| LLVM_ABI uint32_t | mergeFlagsWith (const MachineInstr &Other) const |
| Return the MIFlags which represent both MachineInstrs. | |
| LLVM_ABI void | copyIRFlags (const Instruction &I) |
| Copy all flags to MachineInst MIFlags. | |
| void | untieRegOperand (unsigned OpIdx) |
| Break any tie involving OpIdx. | |
| LLVM_ABI void | addImplicitDefUseOperands (MachineFunction &MF) |
| Add all implicit def and use operands to this instruction. | |
| LLVM_ABI void | collectDebugValues (SmallVectorImpl< MachineInstr * > &DbgValues) |
| Scan instructions immediately following MI and collect any matching DBG_VALUEs. | |
| LLVM_ABI void | changeDebugValuesDefReg (Register Reg) |
Find all DBG_VALUEs that point to the register def in this instruction and point them to Reg instead. | |
| void | setDebugValueUndef () |
| Sets all register debug operands in this debug value instruction to be undef. | |
| std::tuple< Register, Register > | getFirst2Regs () const |
| std::tuple< Register, Register, Register > | getFirst3Regs () const |
| std::tuple< Register, Register, Register, Register > | getFirst4Regs () const |
| std::tuple< Register, Register, Register, Register, Register > | getFirst5Regs () const |
| LLVM_ABI std::tuple< LLT, LLT > | getFirst2LLTs () const |
| LLVM_ABI std::tuple< LLT, LLT, LLT > | getFirst3LLTs () const |
| LLVM_ABI std::tuple< LLT, LLT, LLT, LLT > | getFirst4LLTs () const |
| LLVM_ABI std::tuple< LLT, LLT, LLT, LLT, LLT > | getFirst5LLTs () const |
| LLVM_ABI std::tuple< Register, LLT, Register, LLT > | getFirst2RegLLTs () const |
| LLVM_ABI std::tuple< Register, LLT, Register, LLT, Register, LLT > | getFirst3RegLLTs () const |
| LLVM_ABI std::tuple< Register, LLT, Register, LLT, Register, LLT, Register, LLT > | getFirst4RegLLTs () const |
| LLVM_ABI std::tuple< Register, LLT, Register, LLT, Register, LLT, Register, LLT, Register, LLT > | getFirst5RegLLTs () const |
| LLVM_ABI LLT | getTypeToPrint (unsigned OpIdx, SmallBitVector &PrintedTypes, const MachineRegisterInfo &MRI) const |
| Debugging supportDetermine the generic type to be printed (if needed) on uses and defs. | |
| LLVM_ABI bool | hasComplexRegisterTies () const |
| Return true when an instruction has tied register that can't be determined by the instruction's descriptor. | |
| LLVM_ABI void | print (raw_ostream &OS, bool IsStandalone=true, bool SkipOpers=false, bool SkipDebugLoc=false, bool AddNewLine=true, const TargetInstrInfo *TII=nullptr) const |
Print this MI to OS. | |
| LLVM_ABI void | print (raw_ostream &OS, ModuleSlotTracker &MST, bool IsStandalone=true, bool SkipOpers=false, bool SkipDebugLoc=false, bool AddNewLine=true, const TargetInstrInfo *TII=nullptr) const |
| LLVM_ABI void | dump () const |
| LLVM_ABI void | dumpr (const MachineRegisterInfo &MRI, unsigned MaxDepth=UINT_MAX) const |
Print on dbgs() the current instruction and the instructions defining its operands and so on until we reach MaxDepth. | |
 Public Member Functions inherited from llvm::ilist_node_with_parent< MachineInstr, MachineBasicBlock, ilist_sentinel_tracking< true > > | |
| MachineInstr * | getPrevNode () |
| const MachineInstr * | getPrevNode () const |
Get the previous node, or nullptr for the list head. | |
| MachineInstr * | getNextNode () |
Get the next node, or nullptr for the list tail. | |
| const MachineInstr * | getNextNode () const |
Get the next node, or nullptr for the list tail. | |
| Public Member Functions inherited from llvm::ilist_node_impl< ilist_detail::compute_node_options< T, Options... >::type > | |
| self_iterator | getIterator () |
| const_self_iterator | getIterator () const |
| reverse_self_iterator | getReverseIterator () |
| const_reverse_self_iterator | getReverseIterator () const |
| std::enable_if_t< T::is_sentinel_tracking_explicit, bool > | isSentinel () const |
| Check whether this is the sentinel node. | |
| Public Member Functions inherited from llvm::ilist_detail::node_parent_access< NodeTy, ParentTy > | |
| const ParentTy * | getParent () const |
| ParentTy * | getParent () |
| void | setParent (ParentTy *Parent) |
Static Public Member Functions | |
| static LLVM_ABI uint32_t | copyFlagsFromInstruction (const Instruction &I) |
Friends | |
| struct | ilist_traits< MachineInstr > |
| struct | ilist_callback_traits< MachineBasicBlock > |
| class | MachineFunction |
Detailed Description
Representation of each machine instruction.
This class isn't a POD type, but it must have a trivial destructor. When a MachineFunction is deleted, all the contained MachineInstrs are deallocated without having their destructor called.
Definition at line 70 of file MachineInstr.h.
Member Typedef Documentation
◆ const_mop_iterator
Definition at line 682 of file MachineInstr.h.
◆ const_mop_range
Definition at line 685 of file MachineInstr.h.
◆ filtered_const_mop_range
| using llvm::MachineInstr::filtered_const_mop_range = iterator_range< filter_iterator<const_mop_iterator, bool (*)(const MachineOperand &)> > |
Definition at line 749 of file MachineInstr.h.
◆ filtered_mop_range
| using llvm::MachineInstr::filtered_mop_range = iterator_range< filter_iterator<mop_iterator, bool (*)(const MachineOperand &)> > |
Definition at line 747 of file MachineInstr.h.
◆ mmo_iterator
| using llvm::MachineInstr::mmo_iterator = ArrayRef<MachineMemOperand *>::iterator |
Definition at line 74 of file MachineInstr.h.
◆ mop_iterator
iterator/begin/end - Iterate over all operands of a machine instruction.
Definition at line 681 of file MachineInstr.h.
◆ mop_range
Definition at line 684 of file MachineInstr.h.
Member Enumeration Documentation
◆ CommentFlag
Flags to specify different kinds of comments to output in assembly code.
These flags carry semantic information not otherwise easily derivable from the IR text.
| Enumerator | |
|---|---|
| ReloadReuse | |
| NoSchedComment | |
| TAsmComments | |
Definition at line 80 of file MachineInstr.h.
◆ MICheckType
| Enumerator | |
|---|---|
| CheckDefs | |
| CheckKillDead | |
| IgnoreDefs | |
| IgnoreVRegDefs | |
Definition at line 1271 of file MachineInstr.h.
◆ MIFlag
Definition at line 86 of file MachineInstr.h.
◆ QueryType
API for querying MachineInstr properties.
They are the same as MCInstrDesc queries but they are bundle aware.
| Enumerator | |
|---|---|
| IgnoreBundle | |
| AnyInBundle | |
| AllInBundle | |
Definition at line 884 of file MachineInstr.h.
Constructor & Destructor Documentation
◆ MachineInstr()
|
delete |
◆ ~MachineInstr()
|
delete |
Member Function Documentation
◆ addImplicitDefUseOperands()
| void MachineInstr::addImplicitDefUseOperands | ( | MachineFunction & | MF | ) |
Add all implicit def and use operands to this instruction.
Definition at line 90 of file MachineInstr.cpp.
References addOperand(), llvm::MachineOperand::CreateReg(), llvm::MCInstrDesc::implicit_defs(), and llvm::MCInstrDesc::implicit_uses().
Referenced by ExpandMOVImmSExti8().
◆ addMemOperand()
| void MachineInstr::addMemOperand | ( | MachineFunction & | MF, |
| MachineMemOperand * | MO | ||
| ) |
Add a MachineMemOperand to the machine instruction.
This function should be used only occasionally. The setMemRefs function is the primary method for setting up a MachineInstr's MemRefs list.
Definition at line 383 of file MachineInstr.cpp.
References llvm::SmallVectorImpl< T >::append(), memoperands_begin(), memoperands_end(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), and setMemRefs().
Referenced by llvm::TargetLoweringBase::emitPatchPoint(), foldInlineAsmMemOperand(), and llvm::TargetInstrInfo::foldMemoryOperand().
◆ addOperand() [1/2]
| void MachineInstr::addOperand | ( | const MachineOperand & | Op | ) |
Add an operand without providing an MF reference.
This only works for instructions that are inserted in a basic block.
MachineInstrBuilder and the two-argument addOperand(MF, MO) should be preferred.
Definition at line 183 of file MachineInstr.cpp.
References addOperand(), assert(), llvm::MachineBasicBlock::getParent(), getParent(), and MBB.
◆ addOperand() [2/2]
| void MachineInstr::addOperand | ( | MachineFunction & | MF, |
| const MachineOperand & | Op | ||
| ) |
Add the specified operand to the instruction.
addOperand - Add the specified operand to the instruction.
If it is an implicit operand, it is added to the end of the operand list. If it is an explicit operand it is added at the end of the explicit operand list (before the first implicit operand).
MF must be the machine function that was used to allocate this instruction.
MachineInstrBuilder provides a more convenient interface for creating instructions and adding operands.
If it is an implicit operand, it is added to the end of the operand list. If it is an explicit operand it is added at the end of the explicit operand list (before the first implicit operand).
Definition at line 206 of file MachineInstr.cpp.
References addOperand(), llvm::MachineFunction::allocateOperandArray(), assert(), llvm::MachineFunction::deallocateOperandArray(), llvm::MCOI::EARLY_CLOBBER, getNumOperands(), llvm::MCInstrDesc::getOperandConstraint(), isDebugInstr(), isInlineAsm(), llvm::MachineOperand::isReg(), isReg(), llvm::MachineOperand::isUse(), moveOperands(), MRI, llvm::MachineOperand::setIsDebug(), llvm::MachineOperand::setIsEarlyClobber(), llvm::MCOI::TIED_TO, and tieOperands().
Referenced by addConstantsToTrack(), addImplicitDefUseOperands(), addOperand(), addRegisterDead(), addRegisterDefined(), addRegisterKilled(), llvm::X86InstrInfo::commuteInstructionImpl(), llvm::SIInstrInfo::convertToThreeAddress(), copyImplicitOps(), llvm::XCoreFrameLowering::emitEpilogue(), llvm::HexagonFrameLowering::emitPrologue(), expandSGPRCopy(), insert(), llvm::XtensaInstrInfo::insertIndirectBranch(), LowerCallResults(), llvm::SIInstrInfo::moveToVALUImpl(), llvm::PPCInstrInfo::promoteInstr32To64ForElimEXTSW(), and llvm::X86InstrInfo::replaceBranchWithTailCall().
◆ addRegisterDead()
| bool MachineInstr::addRegisterDead | ( | Register | Reg, |
| const TargetRegisterInfo * | RegInfo, | ||
| bool | AddIfNotFound = false |
||
| ) |
We have determined MI defined a register without a use.
Look for the operand that defines it and mark it as IsDead. If AddIfNotFound is true, add a implicit operand if it's not found. Returns true if the operand exists / is added.
Definition at line 2195 of file MachineInstr.cpp.
References addOperand(), llvm::SmallVectorTemplateCommon< T, typename >::back(), llvm::MachineOperand::CreateReg(), llvm::SmallVectorBase< Size_T >::empty(), findInlineAsmFlagIdx(), getNumOperands(), getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::isDead(), llvm::MachineOperand::isDef(), isInlineAsm(), llvm::Register::isPhysical(), llvm::MachineOperand::isReg(), llvm::MCRegisterInfo::isSubRegister(), llvm::MCRegisterInfo::isSuperRegister(), llvm::MCRegAliasIterator::isValid(), OpIdx, llvm::SmallVectorTemplateBase< T, bool >::pop_back(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), removeOperand(), and llvm::MachineOperand::setIsDead().
Referenced by llvm::Thumb1InstrInfo::copyPhysReg(), and llvm::SystemZInstrInfo::foldMemoryOperandImpl().
◆ addRegisterDefined()
| void MachineInstr::addRegisterDefined | ( | Register | Reg, |
| const TargetRegisterInfo * | RegInfo = nullptr |
||
| ) |
We have determined MI defines a register.
Make sure there is an operand defining Reg.
Definition at line 2259 of file MachineInstr.cpp.
References addOperand(), all_defs(), llvm::MachineOperand::CreateReg(), findRegisterDefOperand(), llvm::MachineOperand::getReg(), and llvm::MachineOperand::getSubReg().
Referenced by llvm::ARMBaseInstrInfo::copyPhysReg(), llvm::SparcInstrInfo::copyPhysReg(), copyPhysSubRegs(), and setPhysRegsDeadExcept().
◆ addRegisterKilled()
| bool MachineInstr::addRegisterKilled | ( | Register | IncomingReg, |
| const TargetRegisterInfo * | RegInfo, | ||
| bool | AddIfNotFound = false |
||
| ) |
We have determined MI kills a register.
Look for the operand that uses it and mark it as IsKill. If AddIfNotFound is true, add a implicit operand if it's not found. Returns true if the operand exists / is added.
Definition at line 2116 of file MachineInstr.cpp.
References addOperand(), llvm::SmallVectorTemplateCommon< T, typename >::back(), llvm::MachineOperand::CreateReg(), llvm::SmallVectorBase< Size_T >::empty(), findInlineAsmFlagIdx(), getNumOperands(), getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::isDebug(), isInlineAsm(), llvm::MachineOperand::isKill(), llvm::Register::isPhysical(), llvm::MachineOperand::isReg(), isRegTiedToDefOperand(), llvm::MCRegisterInfo::isSubRegister(), llvm::MCRegisterInfo::isSuperRegister(), llvm::MachineOperand::isUndef(), llvm::MachineOperand::isUse(), llvm::MCRegAliasIterator::isValid(), OpIdx, llvm::SmallVectorTemplateBase< T, bool >::pop_back(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), removeOperand(), and llvm::MachineOperand::setIsKill().
Referenced by llvm::ARMBaseInstrInfo::copyPhysReg(), llvm::SparcInstrInfo::copyPhysReg(), llvm::VEInstrInfo::copyPhysReg(), copyPhysSubRegs(), emitAlignedDPRCS2Restores(), emitAlignedDPRCS2Spills(), llvm::XCoreFrameLowering::emitPrologue(), and llvm::VEInstrInfo::expandPostRAPseudo().
◆ all_defs() [1/2]
|
inline |
Returns an iterator range over all operands that are (explicit or implicit) register defs.
Definition at line 754 of file MachineInstr.h.
References llvm::make_filter_range(), and operands().
Referenced by addRegisterDefined(), llvm::GCNDownwardRPTracker::advanceToNext(), clearRegisterDeads(), computeLiveOuts(), isDead(), llvm::MachineFunction::salvageCopySSAImpl(), and setRegisterDefReadUndef().
◆ all_defs() [2/2]
|
inline |
Returns an iterator range over all operands that are (explicit or implicit) register defs.
Definition at line 758 of file MachineInstr.h.
References llvm::make_filter_range(), and operands().
◆ all_uses() [1/2]
|
inline |
Returns an iterator range over all operands that are (explicit or implicit) register uses.
Definition at line 764 of file MachineInstr.h.
References llvm::make_filter_range(), and uses().
Referenced by llvm::ScheduleDAGInstrs::addSchedBarrierDeps().
◆ all_uses() [2/2]
|
inline |
Returns an iterator range over all operands that are (explicit or implicit) register uses.
Definition at line 768 of file MachineInstr.h.
References llvm::make_filter_range(), and uses().
◆ allDefsAreDead()
| bool MachineInstr::allDefsAreDead | ( | ) | const |
Return true if all the defs of this instruction are dead.
allDefsAreDead - Return true if all the defs of this instruction are dead.
Definition at line 1663 of file MachineInstr.cpp.
References llvm::MachineOperand::isDead(), llvm::MachineOperand::isReg(), llvm::MachineOperand::isUse(), and operands().
◆ allImplicitDefsAreDead()
| bool MachineInstr::allImplicitDefsAreDead | ( | ) | const |
Return true if all the implicit defs of this instruction are dead.
Definition at line 1673 of file MachineInstr.cpp.
References implicit_operands(), llvm::MachineOperand::isDead(), llvm::MachineOperand::isReg(), and llvm::MachineOperand::isUse().
◆ bundleWithPred()
| void MachineInstr::bundleWithPred | ( | ) |
Bundle this instruction with its predecessor.
This can be an unbundled instruction, or it can be the first instruction in a bundle.
Definition at line 852 of file MachineInstr.cpp.
References assert(), BundledPred, BundledSucc, llvm::ilist_node_impl< ilist_detail::compute_node_options< T, Options... >::type >::getIterator(), isBundledWithPred(), and setFlag().
Referenced by llvm::MachineFunction::cloneMachineInstrBundle().
◆ bundleWithSucc()
| void MachineInstr::bundleWithSucc | ( | ) |
Bundle this instruction with its successor.
This can be an unbundled instruction, or it can be the last instruction in a bundle.
Definition at line 861 of file MachineInstr.cpp.
References assert(), BundledPred, BundledSucc, llvm::ilist_node_impl< ilist_detail::compute_node_options< T, Options... >::type >::getIterator(), isBundledWithSucc(), and setFlag().
◆ canFoldAsLoad()
|
inline |
Return true for instructions that can be folded as memory operands in other instructions.
The most common use for this is instructions that are simple loads from memory that don't modify the loaded value in any way, but it can also be used for instructions that can be expressed as constant-pool loads, such as V_SETALLONES on x86, to allow them to be folded when it is beneficial. This should only be set on instructions that return a value in their only virtual register definition.
Definition at line 1082 of file MachineInstr.h.
References llvm::MCID::FoldableAsLoad, and hasProperty().
Referenced by llvm::TargetInstrInfo::foldMemoryOperand().
◆ changeDebugValuesDefReg()
| void MachineInstr::changeDebugValuesDefReg | ( | Register | Reg | ) |
Find all DBG_VALUEs that point to the register def in this instruction and point them to Reg instead.
Definition at line 2525 of file MachineInstr.cpp.
References getOperand(), llvm::MachineOperand::getParent(), llvm::MachineOperand::getReg(), isReg(), MRI, and llvm::SmallVectorTemplateBase< T, bool >::push_back().
◆ clearAsmPrinterFlag()
|
inline |
Clear specific AsmPrinter flags.
Definition at line 397 of file MachineInstr.h.
References assert().
◆ clearAsmPrinterFlags()
|
inline |
Clear the AsmPrinter bitvector.
Definition at line 380 of file MachineInstr.h.
◆ clearFlag()
|
inline |
clearFlag - Clear a MI flag.
Definition at line 431 of file MachineInstr.h.
References assert().
Referenced by llvm::TargetInstrInfo::reassociateOps(), unbundleFromPred(), and unbundleFromSucc().
◆ clearFlags()
|
inline |
Definition at line 437 of file MachineInstr.h.
References assert().
Referenced by llvm::GenericMachineInstr::dropPoisonGeneratingFlags().
◆ clearKillInfo()
| void MachineInstr::clearKillInfo | ( | ) |
Clears kill flags on all operands.
clearKillInfo - Clears kill flags on all operands.
Definition at line 1295 of file MachineInstr.cpp.
References llvm::MachineOperand::isReg(), llvm::MachineOperand::isUse(), operands(), and llvm::MachineOperand::setIsKill().
Referenced by llvm::LanaiInstrInfo::optimizeSelect(), llvm::ARMBaseInstrInfo::optimizeSelect(), and llvm::RISCVInstrInfo::optimizeSelect().
◆ clearRegisterDeads()
| void MachineInstr::clearRegisterDeads | ( | Register | Reg | ) |
Clear all dead flags on operands defining register Reg.
Definition at line 2247 of file MachineInstr.cpp.
References all_defs(), llvm::MachineOperand::getReg(), and llvm::MachineOperand::setIsDead().
Referenced by llvm::PPCInstrInfo::optimizeCmpPostRA().
◆ clearRegisterKills()
| void MachineInstr::clearRegisterKills | ( | Register | Reg, |
| const TargetRegisterInfo * | RegInfo | ||
| ) |
Clear all kill flags affecting Reg.
If RegInfo is provided, this includes all aliasing registers.
Definition at line 2182 of file MachineInstr.cpp.
References llvm::MachineOperand::getReg(), llvm::MachineOperand::isKill(), llvm::MachineOperand::isReg(), llvm::MachineOperand::isUse(), operands(), llvm::TargetRegisterInfo::regsOverlap(), and llvm::MachineOperand::setIsKill().
◆ cloneInstrSymbols()
| void MachineInstr::cloneInstrSymbols | ( | MachineFunction & | MF, |
| const MachineInstr & | MI | ||
| ) |
Clone another MachineInstr's pre- and post- instruction symbols and replace ours with it.
Definition at line 547 of file MachineInstr.cpp.
References assert(), MI, setHeapAllocMarker(), setMMRAMetadata(), setPCSections(), setPostInstrSymbol(), and setPreInstrSymbol().
Referenced by llvm::TargetInstrInfo::foldMemoryOperand().
◆ cloneMemRefs()
| void MachineInstr::cloneMemRefs | ( | MachineFunction & | MF, |
| const MachineInstr & | MI | ||
| ) |
Clone another MachineInstr's memory reference descriptor list and replace ours with it.
Note that *this may be the incoming MI!
Prefer this API whenever possible as it can avoid allocations in common cases.
Definition at line 391 of file MachineInstr.cpp.
References assert(), getHeapAllocMarker(), getMMRAMetadata(), getPCSections(), getPostInstrSymbol(), getPreInstrSymbol(), MI, and setMemRefs().
Referenced by llvm::CombinerHelper::applyCombineIndexedLoadStore(), and cloneMergedMemRefs().
◆ cloneMergedMemRefs()
| void MachineInstr::cloneMergedMemRefs | ( | MachineFunction & | MF, |
| ArrayRef< const MachineInstr * > | MIs | ||
| ) |
Clone the merge of multiple MachineInstrs' memory reference descriptors list and replace ours with it.
Note that *this may be one of the incoming MIs!
Prefer this API whenever possible as it can avoid allocations in common cases.
Definition at line 427 of file MachineInstr.cpp.
References llvm::SmallVectorImpl< T >::append(), assert(), cloneMemRefs(), dropMemRefs(), llvm::ArrayRef< T >::empty(), getMF(), hasIdenticalMMOs(), llvm::make_pointee_range(), memoperands(), memoperands_begin(), memoperands_empty(), memoperands_end(), MI, setMemRefs(), llvm::ArrayRef< T >::size(), and llvm::ArrayRef< T >::slice().
◆ collectDebugValues()
| void MachineInstr::collectDebugValues | ( | SmallVectorImpl< MachineInstr * > & | DbgValues | ) |
Scan instructions immediately following MI and collect any matching DBG_VALUEs.
Definition at line 2509 of file MachineInstr.cpp.
References MI, and llvm::SmallVectorTemplateBase< T, bool >::push_back().
Referenced by emitSelectPseudo().
◆ copyFlagsFromInstruction()
|
static |
◆ copyImplicitOps()
| void MachineInstr::copyImplicitOps | ( | MachineFunction & | MF, |
| const MachineInstr & | MI | ||
| ) |
Copy implicit register operands from specified instruction to this instruction.
copyImplicitOps - Copy implicit register operands from specified instruction to this instruction.
Definition at line 1685 of file MachineInstr.cpp.
References addOperand(), llvm::drop_begin(), llvm::MachineOperand::isImplicit(), llvm::MachineOperand::isReg(), llvm::MachineOperand::isRegMask(), and MI.
◆ copyIRFlags()
| void MachineInstr::copyIRFlags | ( | const Instruction & | I | ) |
Copy all flags to MachineInst MIFlags.
Definition at line 638 of file MachineInstr.cpp.
References copyFlagsFromInstruction(), and I.
◆ debug_operands() [1/2]
|
inline |
Returns all operands that are used to determine the variable location for this DBG_VALUE instruction.
Definition at line 711 of file MachineInstr.h.
References assert(), isDebugValueLike(), and isNonListDebugValue().
Referenced by llvm::buildDbgValueForSpill(), getDebugOperand(), getDebugOperandIndex(), getNumDebugOperands(), handleNewDebugValue(), hasDebugOperandForReg(), isDebugOperand(), isUndefDebugValue(), and setDebugValueUndef().
◆ debug_operands() [2/2]
|
inline |
Returns all operands that are used to determine the variable location for this DBG_VALUE instruction.
Definition at line 717 of file MachineInstr.h.
References assert(), isDebugValueLike(), and isNonListDebugValue().
◆ definesRegister()
|
inline |
Return true if the MachineInstr fully defines the specified register.
If TargetRegisterInfo is non-null, then it also checks if there is a def of a super-register. NOTE: It's ignoring subreg indices on virtual registers.
Definition at line 1516 of file MachineInstr.h.
References findRegisterDefOperandIdx(), Reg, and TRI.
Referenced by checkAndUpdateCCRKill(), checkAndUpdateCPSRKill(), llvm::SystemZInstrInfo::foldMemoryOperandImpl(), isCmpCSelPair(), isCmpCSetPair(), llvm::PPCInstrInfo::optimizeCmpPostRA(), and llvm::AArch64InstrInfo::optimizeCompareInstr().
◆ defs() [1/2]
|
inline |
Returns all explicit operands that are register definitions.
Implicit definition are not included!
Definition at line 724 of file MachineInstr.h.
References getNumExplicitDefs().
Referenced by findSingleRegDef(), getSalvageOpsForTrunc(), llvm::SPIRVGlobalRegistry::getSPIRVTypeID(), isSafeToMove(), LowerCallResults(), llvm::PeelSingleBlockLoop(), llvm::MipsInstrInfo::SafeInFPUDelaySlot(), and llvm::MipsInstrInfo::SafeInLoadDelaySlot().
◆ defs() [2/2]
|
inline |
Returns all explicit operands that are register definitions.
Implicit definition are not included!
Definition at line 726 of file MachineInstr.h.
References getNumExplicitDefs().
◆ dropDebugNumber()
|
inline |
Drop any variable location debugging information associated with this instruction.
Use when an instruction is modified in such a way that it no longer defines the value it used to. Variable locations using that value will be dropped.
Definition at line 568 of file MachineInstr.h.
Referenced by llvm::X86InstrInfo::optimizeCompareInstr().
◆ dropMemRefs()
| void MachineInstr::dropMemRefs | ( | MachineFunction & | MF | ) |
Clear this MachineInstr's memory reference descriptor list.
This resets the memrefs to their most conservative state. This should be used only as a last resort since it greatly pessimizes our knowledge of the memory access performed by the instruction.
Definition at line 362 of file MachineInstr.cpp.
References getCFIType(), getHeapAllocMarker(), getMMRAMetadata(), getPCSections(), getPostInstrSymbol(), getPreInstrSymbol(), and memoperands_empty().
Referenced by cloneMergedMemRefs(), and setMemRefs().
◆ dump()
| LLVM_DUMP_METHOD void MachineInstr::dump | ( | ) | const |
Definition at line 1735 of file MachineInstr.cpp.
References llvm::dbgs(), and print().
Referenced by llvm::PPCInstrInfo::combineRLWINM(), llvm::ScheduleDAGInstrs::dumpNode(), llvm::PPCInstrInfo::foldFrameOffset(), llvm::SMSchedule::insert(), llvm::SwingSchedulerDAG::mayOverlapInLaterIter(), moveAndTeeForMultiUse(), MoveVPNOTBeforeFirstUser(), llvm::PPCInstrInfo::optimizeCmpPostRA(), rematerializeCheapDef(), and updateOperandRegConstraints().
◆ dumpr()
| LLVM_DUMP_METHOD void MachineInstr::dumpr | ( | const MachineRegisterInfo & | MRI, |
| unsigned | MaxDepth = UINT_MAX |
||
| ) | const |
Print on dbgs() the current instruction and the instructions defining its operands and so on until we reach MaxDepth.
Definition at line 1765 of file MachineInstr.cpp.
References MRI.
◆ emitGenericError()
Definition at line 2342 of file MachineInstr.cpp.
References llvm::LLVMContext::diagnose(), llvm::Function::getContext(), getDebugLoc(), llvm::MachineFunction::getFunction(), and getMF().
◆ emitInlineAsmError()
Emit an error referring to the source location of this instruction.
This should only be used for inline assembly that is somehow impossible to compile. Other errors should have been handled much earlier.
Definition at line 2331 of file MachineInstr.cpp.
References assert(), llvm::LLVMContext::diagnose(), llvm::Function::getContext(), llvm::MachineFunction::getFunction(), getLocCookieMD(), getMF(), llvm::MDNode::getOperand(), and isInlineAsm().
Referenced by llvm::RegAllocBase::getErrorAssignment().
◆ eraseFromBundle()
| void MachineInstr::eraseFromBundle | ( | ) |
Unlink 'this' from its basic block and delete it.
If the instruction is part of a bundle, the other instructions in the bundle remain bundled.
Definition at line 775 of file MachineInstr.cpp.
References assert(), llvm::MachineBasicBlock::erase_instr(), and getParent().
◆ eraseFromParent()
| void MachineInstr::eraseFromParent | ( | ) |
Unlink 'this' from the containing basic block and delete it.
If this instruction is the header of a bundle, the whole bundle is erased. This function can not be used for instructions inside a bundle, use eraseFromBundle() to erase individual bundled instructions.
Definition at line 770 of file MachineInstr.cpp.
References assert(), llvm::MachineBasicBlock::erase(), and getParent().
Referenced by llvm::ARCInstrInfo::analyzeBranch(), llvm::MipsInstrInfo::analyzeBranch(), llvm::AArch64InstrInfo::analyzeBranch(), llvm::ARMBaseInstrInfo::analyzeBranch(), llvm::SparcInstrInfo::analyzeBranch(), llvm::VEInstrInfo::analyzeBranch(), llvm::CombinerHelper::applyBuildFnMO(), llvm::CombinerHelper::applyCombineDivRem(), llvm::CombinerHelper::applyCombineExtendingLoads(), llvm::CombinerHelper::applyCombineIndexedLoadStore(), llvm::CombinerHelper::applyExtendThroughPhis(), llvm::CombinerHelper::applySextInRegOfLoad(), llvm::CombinerHelper::applyShiftOfShiftedLogic(), llvm::LegalizerHelper::bitcastExtractSubvector(), llvm::LegalizerHelper::bitcastInsertSubvector(), CombineCVTAToLocal(), llvm::createLibcall(), llvm::createMemLibcall(), EmitLoweredCascadedSelect(), emitSelectPseudo(), llvm::M68kInstrInfo::ExpandMOVEM(), llvm::M68kInstrInfo::ExpandMOVSZX_RR(), llvm::M68kInstrInfo::ExpandMOVX_RR(), llvm::M68kInstrInfo::ExpandPUSH_POP(), llvm::PPCInstrInfo::foldFrameOffset(), foldVGPRCopyIntoRegSequence(), llvm::HexagonInstrInfo::genAllInsnTimingClasses(), llvm::MachineSSAUpdater::GetValueInMiddleOfBlock(), llvm::SystemZELFFrameLowering::inlineStackProbe(), llvm::SystemZXPLINKFrameLowering::inlineStackProbe(), LowerCallResults(), llvm::LegalizerHelper::lowerLoad(), llvm::LegalizerHelper::lowerStore(), llvm::CombinerHelper::matchCombineExtractedVectorLoad(), llvm::CombinerHelper::matchCombineLoadWithAndMask(), llvm::SIInstrInfo::moveFlatAddrToVGPR(), llvm::SIInstrInfo::moveToVALUImpl(), llvm::AArch64InstrInfo::optimizeCompareInstr(), llvm::SIInstrInfo::optimizeCompareInstr(), llvm::ARMBaseInstrInfo::optimizeCompareInstr(), llvm::LanaiInstrInfo::optimizeCompareInstr(), llvm::X86InstrInfo::optimizeCompareInstr(), llvm::PPCInstrInfo::optimizeCompareInstr(), llvm::LanaiInstrInfo::optimizeSelect(), llvm::ARMBaseInstrInfo::optimizeSelect(), llvm::RISCVInstrInfo::optimizeSelect(), llvm::LegalizerHelper::reduceLoadStoreWidth(), RemoveDeadAddBetweenLEAAndJT(), llvm::LegalizerHelper::scalarizeVectorBooleanStore(), and llvm::FastISel::selectPatchpoint().
◆ explicit_operands() [1/2]
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inline |
Definition at line 696 of file MachineInstr.h.
References getNumExplicitOperands().
Referenced by llvm::SIInstrInfo::moveToVALUImpl(), and llvm::TargetInstrInfo::reassociateOps().
◆ explicit_operands() [2/2]
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inline |
Definition at line 699 of file MachineInstr.h.
References getNumExplicitOperands().
◆ explicit_uses() [1/2]
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inline |
Definition at line 736 of file MachineInstr.h.
References getNumExplicitDefs(), and getNumExplicitOperands().
◆ explicit_uses() [2/2]
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inline |
Definition at line 741 of file MachineInstr.h.
References getNumExplicitDefs(), and getNumExplicitOperands().
◆ findFirstPredOperandIdx()
| int MachineInstr::findFirstPredOperandIdx | ( | ) | const |
Find the index of the first operand in the operand list that is used to represent the predicate.
findFirstPredOperandIdx() - Find the index of the first operand in the operand list that is used to represent the predicate.
It returns -1 if none is found.
Definition at line 1161 of file MachineInstr.cpp.
References getDesc(), getNumOperands(), llvm::MCInstrDesc::isPredicable(), and llvm::MCInstrDesc::operands().
Referenced by llvm::ARMBaseInstrInfo::commuteInstructionImpl().
◆ findInlineAsmFlagIdx()
Find the index of the flag word operand that corresponds to operand OpIdx on an inline asm instruction.
Returns -1 if getOperand(OpIdx) does not belong to an inline asm operand group.
If GroupNo is not NULL, it will receive the number of the operand group containing OpIdx.
Definition at line 903 of file MachineInstr.cpp.
References assert(), F, llvm::MachineOperand::getImm(), getNumOperands(), getOperand(), llvm::MachineOperand::isImm(), isInlineAsm(), llvm::InlineAsm::MIOp_FirstOperand, and OpIdx.
Referenced by addRegisterDead(), addRegisterKilled(), and getRegClassConstraint().
◆ findRegisterDefOperand() [1/2]
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inline |
Wrapper for findRegisterDefOperandIdx, it returns a pointer to the MachineOperand rather than an index.
Definition at line 1574 of file MachineInstr.h.
References findRegisterDefOperandIdx(), getOperand(), Idx, isDead(), Reg, and TRI.
Referenced by addRegisterDefined(), findRegisterDefOperand(), llvm::SystemZInstrInfo::foldMemoryOperandImpl(), handleNDDOrNFInstructions(), llvm::X86InstrInfo::hasReassociableOperands(), llvm::X86InstrInfo::setSpecialOperandAttr(), and transferDeadCC().
◆ findRegisterDefOperand() [2/2]
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inline |
Definition at line 1582 of file MachineInstr.h.
References findRegisterDefOperand(), isDead(), Reg, and TRI.
◆ findRegisterDefOperandIdx()
| int MachineInstr::findRegisterDefOperandIdx | ( | Register | Reg, |
| const TargetRegisterInfo * | TRI, | ||
| bool | isDead = false, |
||
| bool | Overlap = false |
||
| ) | const |
Returns the operand index that is a def of the specified register or -1 if it is not found.
findRegisterDefOperandIdx() - Returns the operand index that is a def of the specified register or -1 if it is not found.
If isDead is true, defs that are not dead are skipped. If Overlap is true, then it also looks for defs that merely overlap the specified register. If TargetRegisterInfo is non-null, then it also checks if there is a def of a super-register. This may also return a register mask operand when Overlap is true.
If isDead is true, defs that are not dead are skipped. If TargetRegisterInfo is non-null, then it also checks if there is a def of a super-register.
Definition at line 1132 of file MachineInstr.cpp.
References llvm::MachineOperand::clobbersPhysReg(), getNumOperands(), getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::isDead(), isDead(), llvm::MachineOperand::isDef(), llvm::Register::isPhysical(), llvm::MachineOperand::isReg(), llvm::MachineOperand::isRegMask(), and TRI.
Referenced by canFoldIntoCSel(), definesRegister(), findRegisterDefOperand(), getMaddPatterns(), getMiscPatterns(), hasSameValue(), llvm::CombinerHelper::matchEqualDefs(), modifiesRegister(), llvm::SIInstrInfo::moveToVALUImpl(), llvm::AArch64InstrInfo::optimizeCompareInstr(), llvm::AArch64InstrInfo::optimizeCondBranch(), and registerDefIsDead().
◆ findRegisterUseOperand() [1/2]
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inline |
Wrapper for findRegisterUseOperandIdx, it returns a pointer to the MachineOperand rather than an index.
Definition at line 1547 of file MachineInstr.h.
References findRegisterUseOperandIdx(), getOperand(), Idx, isKill(), Reg, and TRI.
Referenced by findRegisterUseOperand(), and llvm::CombinerHelper::matchFreezeOfSingleMaybePoisonOperand().
◆ findRegisterUseOperand() [2/2]
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inline |
Definition at line 1554 of file MachineInstr.h.
References findRegisterUseOperand(), isKill(), Reg, and TRI.
◆ findRegisterUseOperandIdx()
| int MachineInstr::findRegisterUseOperandIdx | ( | Register | Reg, |
| const TargetRegisterInfo * | TRI, | ||
| bool | isKill = false |
||
| ) | const |
Returns the operand index that is a use of the specific register or -1 if it is not found.
findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of the specific register or -1 if it is not found.
It further tightens the search criteria to a use that kills the register if isKill is true.
Definition at line 1083 of file MachineInstr.cpp.
References getNumOperands(), getOperand(), llvm::MachineOperand::getReg(), isKill(), llvm::MachineOperand::isKill(), llvm::MachineOperand::isReg(), llvm::MachineOperand::isUse(), and TRI.
Referenced by findRegisterUseOperand(), killsRegister(), readsRegister(), and llvm::salvageDebugInfoForDbgValue().
◆ findTiedOperandIdx()
Given the index of a tied register operand, find the operand it is tied to.
Defs are tied to uses and vice versa. Returns the index of the tied operand which must exist.
Definition at line 1218 of file MachineInstr.cpp.
References assert(), F, llvm::StatepointOpers::getFirstGCPtrIdx(), llvm::MachineOperand::getImm(), llvm::StackMaps::getNextMetaArgIdx(), getNumDefs(), getNumOperands(), getOpcode(), getOperand(), llvm::MachineOperand::isImm(), isInlineAsm(), llvm::MachineOperand::isReg(), isReg(), llvm::MachineOperand::isTied(), llvm::MachineOperand::isUse(), llvm_unreachable, llvm::InlineAsm::MIOp_FirstOperand, OpIdx, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::SmallVectorBase< Size_T >::size(), and TiedMax.
Referenced by hasComplexRegisterTies(), insert(), isRegTiedToDefOperand(), isRegTiedToUseOperand(), print(), and untieRegOperand().
◆ getAsmPrinterFlag()
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inline |
Return whether an AsmPrinter flag is set.
Definition at line 383 of file MachineInstr.h.
References assert().
◆ getAsmPrinterFlags()
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inline |
Return the asm printer flags bitvector.
Definition at line 377 of file MachineInstr.h.
◆ getBundleSize()
| unsigned MachineInstr::getBundleSize | ( | ) | const |
Return the number of instructions inside the MI bundle, excluding the bundle header.
Return the number of instructions inside the MI bundle, not counting the header instruction.
This is the number of instructions that MachineBasicBlock::iterator skips, 0 for unbundled instructions.
Definition at line 1060 of file MachineInstr.cpp.
References llvm::ilist_node_impl< ilist_detail::compute_node_options< T, Options... >::type >::getIterator(), I, and Size.
◆ getCFIType()
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inline |
Helper to extract a CFI type hash if one has been added.
Definition at line 872 of file MachineInstr.h.
References Info.
Referenced by dropMemRefs(), isIdenticalTo(), print(), setCFIType(), setHeapAllocMarker(), setMemRefs(), setMMRAMetadata(), setPCSections(), setPostInstrSymbol(), and setPreInstrSymbol().
◆ getDebugExpression()
| const DIExpression * MachineInstr::getDebugExpression | ( | ) | const |
Return the complex address expression referenced by this DBG_VALUE instruction.
Definition at line 965 of file MachineInstr.cpp.
References getDebugExpressionOp().
Referenced by handleNewDebugValue(), if(), isDebugEntryValue(), isEquivalentDbgInstr(), and llvm::salvageDebugInfoForDbgValue().
◆ getDebugExpressionOp() [1/2]
| MachineOperand & MachineInstr::getDebugExpressionOp | ( | ) |
Definition at line 959 of file MachineInstr.cpp.
References assert(), getOperand(), isDebugValueLike(), and isNonListDebugValue().
◆ getDebugExpressionOp() [2/2]
| const MachineOperand & MachineInstr::getDebugExpressionOp | ( | ) | const |
Return the operand for the complex address expression referenced by this DBG_VALUE instruction.
Definition at line 953 of file MachineInstr.cpp.
References assert(), getOperand(), isDebugValueLike(), and isNonListDebugValue().
Referenced by getDebugExpression(), if(), llvm::salvageDebugInfoForDbgValue(), and llvm::updateDbgValueForSpill().
◆ getDebugInstrNum() [1/2]
| unsigned MachineInstr::getDebugInstrNum | ( | ) |
Fetch the instruction number of this MachineInstr.
If it does not have one already, a new and unique number will be assigned.
Definition at line 2610 of file MachineInstr.cpp.
References llvm::MachineFunction::getNewDebugInstrNum(), llvm::MachineBasicBlock::getParent(), and getParent().
Referenced by llvm::InstrEmitter::EmitDbgInstrRef(), and llvm::MachineFunction::salvageCopySSAImpl().
◆ getDebugInstrNum() [2/2]
| unsigned MachineInstr::getDebugInstrNum | ( | MachineFunction & | MF | ) |
Fetch instruction number of this MachineInstr – but before it's inserted into MF.
Needed for transformations that create an instruction but don't immediately insert them.
Definition at line 2616 of file MachineInstr.cpp.
References llvm::MachineFunction::getNewDebugInstrNum().
◆ getDebugLabel()
Return the debug label referenced by this DBG_LABEL instruction.
Definition at line 932 of file MachineInstr.cpp.
References assert(), getOperand(), and isDebugLabel().
◆ getDebugLoc()
Returns the debug location id of this MachineInstr.
Definition at line 511 of file MachineInstr.h.
Referenced by addUnreachableAfterTryTables(), llvm::buildDbgValueForSpill(), llvm::WebAssemblyDebugValueManager::cloneSink(), CombineCVTAToLocal(), combineFPFusedMultiply(), llvm::constrainOperandRegClass(), llvm::ARCFrameLowering::eliminateCallFramePseudoInstr(), llvm::MSP430FrameLowering::eliminateCallFramePseudoInstr(), llvm::XCoreFrameLowering::eliminateCallFramePseudoInstr(), llvm::Thumb1FrameLowering::eliminateCallFramePseudoInstr(), emitGenericError(), llvm::DwarfDebug::emitInitialLocDirective(), llvm::AArch64InstrInfo::emitLdStWithAddr(), llvm::RISCVInstrInfo::emitLdStWithAddr(), expandLoadStackGuard(), expandMOV32r1(), llvm::M68kInstrInfo::ExpandMOVEM(), llvm::M68kInstrInfo::ExpandMOVI(), ExpandMOVImmSExti8(), llvm::M68kInstrInfo::ExpandMOVSZX_RM(), llvm::M68kInstrInfo::ExpandMOVSZX_RR(), llvm::M68kInstrInfo::ExpandMOVX_RR(), llvm::X86InstrInfo::expandPostRAPseudo(), llvm::M68kInstrInfo::ExpandPUSH_POP(), llvm::RegAllocBase::getErrorAssignment(), INITIALIZE_PASS(), llvm::SystemZELFFrameLowering::inlineStackProbe(), llvm::SystemZXPLINKFrameLowering::inlineStackProbe(), insertPHI(), isEquivalentDbgInstr(), isIdenticalTo(), llvm::SIInstrInfo::legalizeOperands(), llvm::SIInstrInfo::moveToVALUImpl(), print(), llvm::ARMBaseInstrInfo::reMaterialize(), llvm::X86InstrInfo::reMaterialize(), llvm::WebAssemblyDebugValueManager::sink(), and splitEdge().
◆ getDebugOffset() [1/2]
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inline |
Definition at line 520 of file MachineInstr.h.
References assert(), getOperand(), and isNonListDebugValue().
◆ getDebugOffset() [2/2]
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inline |
Return the operand containing the offset to be used if this DBG_VALUE instruction is indirect; will be an invalid register if this value is not indirect, and an immediate with value 0 otherwise.
Definition at line 516 of file MachineInstr.h.
References assert(), getOperand(), and isNonListDebugValue().
Referenced by isDebugOffsetImm(), and llvm::updateDbgValueForSpill().
◆ getDebugOperand() [1/2]
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inline |
Definition at line 600 of file MachineInstr.h.
References assert(), llvm::iterator_range< IteratorT >::begin(), debug_operands(), getNumDebugOperands(), and Index.
Referenced by isEquivalentDbgInstr(), and isIndirectDebugValue().
◆ getDebugOperand() [2/2]
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inline |
Definition at line 604 of file MachineInstr.h.
References assert(), llvm::iterator_range< IteratorT >::begin(), debug_operands(), getNumDebugOperands(), and Index.
◆ getDebugOperandIndex()
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inline |
Definition at line 631 of file MachineInstr.h.
References llvm::adl_begin(), assert(), debug_operands(), and isDebugOperand().
Referenced by if().
◆ getDebugOperandsForReg() [1/2]
| iterator_range< filter_iterator< MachineOperand *, std::function< bool(MachineOperand &Op)> > > MachineInstr::getDebugOperandsForReg | ( | Register | Reg | ) |
Definition at line 817 of file MachineInstr.cpp.
◆ getDebugOperandsForReg() [2/2]
| iterator_range< filter_iterator< const MachineOperand *, std::function< bool(const MachineOperand &Op)> > > MachineInstr::getDebugOperandsForReg | ( | Register | Reg | ) | const |
Returns a range of all of the operands that correspond to a debug use of Reg.
Definition at line 810 of file MachineInstr.cpp.
Referenced by attemptDebugCopyProp(), and llvm::updateDbgValueForSpill().
◆ getDebugVariable()
| const DILocalVariable * MachineInstr::getDebugVariable | ( | ) | const |
Return the debug variable referenced by this DBG_VALUE instruction.
Definition at line 949 of file MachineInstr.cpp.
References getDebugVariableOp().
Referenced by llvm::buildDbgValueForSpill(), isEquivalentDbgInstr(), and print().
◆ getDebugVariableOp() [1/2]
| MachineOperand & MachineInstr::getDebugVariableOp | ( | ) |
Definition at line 943 of file MachineInstr.cpp.
References assert(), getOperand(), isDebugValueLike(), and isNonListDebugValue().
◆ getDebugVariableOp() [2/2]
| const MachineOperand & MachineInstr::getDebugVariableOp | ( | ) | const |
Return the operand for the debug variable referenced by this DBG_VALUE instruction.
Definition at line 937 of file MachineInstr.cpp.
References assert(), getOperand(), isDebugValueLike(), and isNonListDebugValue().
Referenced by getDebugVariable(), and print().
◆ getDesc()
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inline |
Returns the target instruction descriptor of this MachineInstr.
Definition at line 584 of file MachineInstr.h.
Referenced by llvm::ScheduleDAGInstrs::addPhysRegDataDeps(), llvm::ScheduleDAGInstrs::addSchedBarrierDeps(), llvm::buildDbgValueForSpill(), llvm::HexagonPacketizerList::canPromoteToDotNew(), llvm::HexagonPacketizerList::canPromoteToNewValueStore(), llvm::ResourceManager::canReserveResources(), llvm::checkVOPDRegConstraints(), cloneInstr(), llvm::TargetSchedModel::computeOperandLatency(), findFirstPredOperandIdx(), llvm::X86InstrInfo::foldMemoryOperandImpl(), llvm::HexagonInstrInfo::genAllInsnTimingClasses(), llvm::X86InstrInfo::getAddrModeFromMemoryOp(), llvm::ARMHazardRecognizerFPMLx::getHazardType(), llvm::ScheduleDAG::getInstrDesc(), llvm::ARMBaseInstrInfo::getOperandLatency(), getRegClassConstraint(), getTargetMBB(), getTypeToPrint(), hasComplexRegisterTies(), hasProperty(), llvm::HexagonInstrInfo::isDependent(), oneUseDominatesOtherUses(), llvm::LanaiInstrInfo::optimizeSelect(), llvm::ARMBaseInstrInfo::optimizeSelect(), llvm::RISCVInstrInfo::optimizeSelect(), parseCondBranch(), llvm::ResourceManager::reserveResources(), tryChangeVGPRtoSGPRinCopy(), and updateOperandRegConstraints().
◆ getFirst2LLTs()
Definition at line 2622 of file MachineInstr.cpp.
References getOperand(), getReg(), and getType().
◆ getFirst2RegLLTs()
Definition at line 2649 of file MachineInstr.cpp.
References getOperand(), llvm::MachineOperand::getReg(), and getType().
◆ getFirst2Regs()
Definition at line 2015 of file MachineInstr.h.
References getOperand(), and getReg().
◆ getFirst3LLTs()
Definition at line 2627 of file MachineInstr.cpp.
References getOperand(), getReg(), and getType().
◆ getFirst3RegLLTs()
Definition at line 2657 of file MachineInstr.cpp.
References getOperand(), llvm::MachineOperand::getReg(), and getType().
◆ getFirst3Regs()
Definition at line 2019 of file MachineInstr.h.
References getOperand(), and getReg().
◆ getFirst4LLTs()
Definition at line 2633 of file MachineInstr.cpp.
References getOperand(), getReg(), and getType().
◆ getFirst4RegLLTs()
| std::tuple< Register, LLT, Register, LLT, Register, LLT, Register, LLT > MachineInstr::getFirst4RegLLTs | ( | ) | const |
Definition at line 2667 of file MachineInstr.cpp.
References getOperand(), llvm::MachineOperand::getReg(), and getType().
◆ getFirst4Regs()
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inline |
Definition at line 2024 of file MachineInstr.h.
References getOperand(), and getReg().
◆ getFirst5LLTs()
Definition at line 2640 of file MachineInstr.cpp.
References getOperand(), getReg(), and getType().
◆ getFirst5RegLLTs()
| std::tuple< Register, LLT, Register, LLT, Register, LLT, Register, LLT, Register, LLT > MachineInstr::getFirst5RegLLTs | ( | ) | const |
Definition at line 2679 of file MachineInstr.cpp.
References getOperand(), llvm::MachineOperand::getReg(), and getType().
◆ getFirst5Regs()
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inline |
Definition at line 2030 of file MachineInstr.h.
References getOperand(), and getReg().
◆ getFlag()
Return whether an MI flag is set.
Definition at line 409 of file MachineInstr.h.
References assert().
Referenced by canCombineFPFusedMultiply(), getFNEGPatterns(), llvm::AArch64InstrInfo::isAssociativeAndCommutative(), llvm::PPCInstrInfo::isAssociativeAndCommutative(), llvm::RISCVInstrInfo::isAssociativeAndCommutative(), llvm::SystemZInstrInfo::isAssociativeAndCommutative(), llvm::X86InstrInfo::isAssociativeAndCommutative(), isBundledWithPred(), isBundledWithSucc(), llvm::AArch64GISelUtils::isCMN(), isCombineInstrCandidateFP(), isConvergent(), isInsideBundle(), llvm::isKnownNeverNaN(), llvm::CombinerHelper::matchAddOverflow(), llvm::CombinerHelper::matchExtOfExt(), llvm::CombinerHelper::matchSextOfTrunc(), mayRaiseFPException(), print(), propagateFrameFlags(), and transferMIFlag().
◆ getFlags()
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inline |
Return the MI flags bitvector.
Definition at line 404 of file MachineInstr.h.
Referenced by combineFPFusedMultiply(), llvm::AArch64InstrInfo::emitLdStWithAddr(), llvm::RISCVInstrInfo::emitLdStWithAddr(), llvm::AArch64InstrInfo::genAlternativeCodeSequence(), llvm::GenericMachineInstr::hasPoisonGeneratingFlags(), llvm::MIPatternMatch::BinaryOp_match< LHS_P, RHS_P, Opcode, Commutable, Flags >::match(), llvm::AMDGPUCombinerHelper::matchCombineFmulWithSelectToFldexp(), llvm::CombinerHelper::matchPtrAddImmedChain(), mergeFlagsWith(), llvm::SIInstrInfo::moveToVALUImpl(), llvm::TargetInstrInfo::reassociateOps(), and llvm::TargetInstrInfo::reduceAccumulatorTree().
◆ getFoldedRestoreSize()
| std::optional< LocationSize > MachineInstr::getFoldedRestoreSize | ( | const TargetInstrInfo * | TII | ) | const |
Return a valid size if the instruction is a folded restore instruction.
Definition at line 2603 of file MachineInstr.cpp.
References Accesses, getMF(), getSpillSlotSize(), llvm::HexagonInstrInfo::hasLoadFromStackSlot(), and TII.
◆ getFoldedSpillSize()
| std::optional< LocationSize > MachineInstr::getFoldedSpillSize | ( | const TargetInstrInfo * | TII | ) | const |
Return a valid size if the instruction is a folded spill instruction.
Definition at line 2584 of file MachineInstr.cpp.
References Accesses, getMF(), getSpillSlotSize(), llvm::HexagonInstrInfo::hasStoreToStackSlot(), and TII.
◆ getHeapAllocMarker()
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inline |
Helper to extract a heap alloc marker if one has been added.
Definition at line 843 of file MachineInstr.h.
References Info.
Referenced by cloneMemRefs(), dropMemRefs(), print(), setCFIType(), setHeapAllocMarker(), setMemRefs(), setMMRAMetadata(), setPCSections(), setPostInstrSymbol(), and setPreInstrSymbol().
◆ getInlineAsmDialect()
| InlineAsm::AsmDialect MachineInstr::getInlineAsmDialect | ( | ) | const |
Definition at line 897 of file MachineInstr.cpp.
References assert(), llvm::InlineAsm::Extra_AsmDialect, llvm::MachineOperand::getImm(), getOperand(), isInlineAsm(), and llvm::InlineAsm::MIOp_ExtraInfo.
Referenced by print(), printAsmMRegister(), and printAsmVRegister().
◆ getLocCookieMD()
For inline asm, get the !srcloc metadata node if we have it, and decode the loc cookie from it.
Definition at line 2316 of file MachineInstr.cpp.
References getNumOperands(), llvm::MDNode::getNumOperands(), getOperand(), and llvm::MDNode::getOperand().
Referenced by emitInlineAsmError().
◆ getMF() [1/2]
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inline |
Definition at line 371 of file MachineInstr.h.
References getMF().
◆ getMF() [2/2]
| const MachineFunction * MachineInstr::getMF | ( | ) | const |
Return the function that contains the basic block that this instruction belongs to.
Note: this is undefined behaviour if the instruction does not have a parent.
Definition at line 756 of file MachineInstr.cpp.
References llvm::MachineBasicBlock::getParent(), and getParent().
Referenced by attemptDebugCopyProp(), canCombineFPFusedMultiply(), llvm::AArch64InstrInfo::canFoldIntoAddrMode(), llvm::checkVOPDRegConstraints(), cloneMergedMemRefs(), collectCallSiteParameters(), combineFPFusedMultiply(), llvm::TargetSchedModel::computeOutputLatency(), emitGenericError(), emitInlineAsmError(), llvm::AArch64InstrInfo::emitLdStWithAddr(), llvm::GIMatchTableExecutor::executeMatchTable(), llvm::PPCInstrInfo::finalizeInsInstrs(), llvm::RISCVInstrInfo::finalizeInsInstrs(), foldInlineAsmMemOperand(), llvm::TargetInstrInfo::genAlternativeCodeSequence(), llvm::RISCVInstrInfo::genAlternativeCodeSequence(), genAlternativeDpCodeSequence(), genIndexedMultiply(), genShXAddAddShift(), getFoldedRestoreSize(), getFoldedSpillSize(), getGatherLanePattern(), getMF(), getRegClassConstraint(), getRestoreSize(), getSpillSize(), llvm::RISCVInstrInfo::hasReassociableSibling(), interpretValues(), llvm::isKnownNeverNaN(), mayAlias(), llvm::SIInstrInfo::moveFlatAddrToVGPR(), performSink(), llvm::TargetInstrInfo::reassociateOps(), setDesc(), llvm::SIInstrInfo::shouldClusterMemOps(), llvm::stableHashValue(), and UpdatePredRedefs().
◆ getMMRAMetadata()
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inline |
Helper to extract mmra.op metadata.
Definition at line 863 of file MachineInstr.h.
References Info.
Referenced by cloneMemRefs(), dropMemRefs(), print(), setCFIType(), setHeapAllocMarker(), setMemRefs(), setMMRAMetadata(), setPCSections(), setPostInstrSymbol(), and setPreInstrSymbol().
◆ getNumDebugOperands()
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inline |
Returns the total number of operands which are debug locations.
Definition at line 593 of file MachineInstr.h.
References debug_operands(), and llvm::size().
Referenced by getDebugOperand(), and isEquivalentDbgInstr().
◆ getNumDefs()
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inline |
Returns the total number of definitions.
Definition at line 637 of file MachineInstr.h.
References getNumExplicitDefs(), and llvm::MCInstrDesc::implicit_defs().
Referenced by findTiedOperandIdx(), llvm::X86InstrInfo::hasReassociableOperands(), and llvm::MIPatternMatch::BinaryOpc_match< LHS_P, RHS_P, Commutable >::match().
◆ getNumExplicitDefs()
| unsigned MachineInstr::getNumExplicitDefs | ( | ) | const |
Returns the number of non-implicit definitions.
Definition at line 839 of file MachineInstr.cpp.
References llvm::MCInstrDesc::getNumDefs(), and llvm::MCInstrDesc::isVariadic().
Referenced by defs(), explicit_uses(), llvm::GIntrinsic::getIntrinsicID(), getNumDefs(), llvm::X86InstrInfo::hasReassociableOperands(), isConstReg(), and uses().
◆ getNumExplicitOperands()
| unsigned MachineInstr::getNumExplicitOperands | ( | ) | const |
Returns the number of non-implicit operands.
Definition at line 821 of file MachineInstr.cpp.
References llvm::MCInstrDesc::getNumOperands(), and llvm::MCInstrDesc::isVariadic().
Referenced by llvm::HexagonInstrInfo::analyzeBranch(), explicit_operands(), explicit_uses(), llvm::AArch64InstrInfo::getMemOpBaseRegImmOfsOffsetOperand(), llvm::PPCInstrInfo::getMemOperandWithOffsetWidth(), llvm::RISCVInstrInfo::getMemOperandWithOffsetWidth(), llvm::AArch64InstrInfo::getMemOperandWithOffsetWidth(), getNumImplicitOperands(), getTypeToPrint(), llvm::X86InstrInfo::hasReassociableOperands(), implicit_operands(), isLdStSafeToCluster(), llvm::RISCVInstrInfo::isLdStSafeToPair(), and parseCondBranch().
◆ getNumImplicitOperands()
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Returns the implicit operands number.
Definition at line 650 of file MachineInstr.h.
References getNumExplicitOperands(), and getNumOperands().
◆ getNumMemOperands()
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Return the number of memory operands.
Definition at line 816 of file MachineInstr.h.
References memoperands().
Referenced by llvm::ARMBankConflictHazardRecognizer::getHazardType(), and mayAlias().
◆ getNumOperands()
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Retuns the total number of operands.
Definition at line 590 of file MachineInstr.h.
Referenced by addOperand(), addRegisterDead(), addRegisterKilled(), llvm::HexagonSubtarget::adjustSchedDependency(), allPhiOperandsUndefined(), llvm::X86InstrInfo::analyzeBranchPredicate(), llvm::HexagonInstrInfo::canExecuteInBundle(), cloneInstr(), llvm::SIInstrInfo::convertToThreeAddress(), llvm::TargetLoweringBase::emitPatchPoint(), llvm::LegalizerHelper::fewerElementsVectorUnmergeValues(), findFirstPredOperandIdx(), findInlineAsmFlagIdx(), findLoopComponents(), findRegisterDefOperandIdx(), findRegisterUseOperandIdx(), findTiedOperandIdx(), foldPatchpoint(), getLocCookieMD(), llvm::LanaiInstrInfo::getMemOperandWithOffsetWidth(), llvm::PatchPointOpers::getNextScratchIdx(), llvm::GUnmerge::getNumDefs(), getNumImplicitOperands(), llvm::GPhi::getNumIncomingValues(), llvm::GMergeLikeInstr::getNumSources(), llvm::PeelingModuloScheduleExpander::getPhiCanonicalReg(), hasComplexRegisterTies(), INITIALIZE_PASS(), insert(), interpretNextInstr(), llvm::SPIRV::irhandle_sampled_image(), isConstantValuePHI(), isIdenticalTo(), llvm::HexagonInstrInfo::isToBeScheduledASAP(), llvm::InlineAsmLowering::lowerInlineAsm(), llvm::MIPatternMatch::BinaryOp_match< LHS_P, RHS_P, Opcode, Commutable, Flags >::match(), llvm::MIPatternMatch::BinaryOpc_match< LHS_P, RHS_P, Commutable >::match(), llvm::MIPatternMatch::UnaryOp_match< SrcTy, Opcode >::match(), llvm::MIPatternMatch::TernaryOp_match< Src0Ty, Src1Ty, Src2Ty, Opcode >::match(), llvm::CombinerHelper::matchCombineInsertVecElts(), llvm::CombinerHelper::matchHoistLogicOpWithSameOpcodeHands(), llvm::LanaiInstrInfo::optimizeSelect(), llvm::ARMBaseInstrInfo::optimizeSelect(), print(), llvm::ARMBaseInstrInfo::produceSameValue(), readsWritesVirtualRegister(), removeOperand(), llvm::MachineFunction::substituteDebugValuesForInst(), llvm::LegalizationArtifactCombiner::tryCombineExtract(), typesLogicallyMatch(), updateOperandRegConstraints(), validateFunCallMachineDef(), and validatePtrUnwrapStructField().
◆ getOpcode()
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Returns the opcode of this MachineInstr.
Definition at line 587 of file MachineInstr.h.
Referenced by addConstantsToTrack(), llvm::AArch64Subtarget::adjustSchedDependency(), llvm::R600InstrInfo::analyzeBranch(), llvm::HexagonInstrInfo::analyzeBranch(), llvm::NVPTXInstrInfo::analyzeBranch(), llvm::PPCInstrInfo::analyzeBranch(), llvm::XCoreInstrInfo::analyzeBranch(), llvm::MipsInstrInfo::analyzeBranch(), llvm::AArch64InstrInfo::analyzeBranch(), llvm::ARMBaseInstrInfo::analyzeBranch(), llvm::SparcInstrInfo::analyzeBranch(), llvm::VEInstrInfo::analyzeBranch(), llvm::AArch64InstrInfo::analyzeBranchPredicate(), llvm::X86InstrInfo::analyzeBranchPredicate(), llvm::AArch64InstrInfo::analyzeLoopForPipelining(), llvm::ARMBaseInstrInfo::analyzeLoopForPipelining(), llvm::CombinerHelper::applyCombineExtendingLoads(), llvm::CombinerHelper::applyCombineTruncOfShift(), llvm::CombinerHelper::applyCombineUnmergeZExtToZExt(), llvm::CombinerHelper::applyExtendThroughPhis(), llvm::AMDGPUCombinerHelper::applyFoldableFneg(), llvm::MipsRegisterBankInfo::applyMappingImpl(), llvm::CombinerHelper::applyShiftOfShiftedLogic(), areCandidatesToMergeOrPair(), areCombinableOperations(), BBIsJumpedOver(), bbIsJumpedOver(), llvm::buildAtomicCompareExchangeInst(), llvm::buildBoolRegister(), llvm::buildEnqueueKernel(), llvm::buildNDRange(), llvm::ResourceManager::calculateResMII(), canCmpInstrBeRemoved(), canCompareBeNewValueJump(), canCreateUndefOrPoison(), canEmitConjunction(), llvm::AArch64InstrInfo::canFoldIntoAddrMode(), llvm::RISCVInstrInfo::canFoldIntoAddrMode(), canFoldIntoCSel(), canInstrSubstituteCmpInstr(), canRenameMOP(), llvm::checkVOPDRegConstraints(), combineFPFusedMultiply(), llvm::PPCInstrInfo::combineRLWINM(), llvm::ARMBasicBlockUtils::computeBlockSize(), computeNumSignBitsFromRangeMetadata(), llvm::HexagonInstrInfo::doesNotReturn(), llvm::SystemZHazardRecognizer::dumpSU(), llvm::ARCFrameLowering::eliminateCallFramePseudoInstr(), llvm::MSP430FrameLowering::eliminateCallFramePseudoInstr(), llvm::XCoreFrameLowering::eliminateCallFramePseudoInstr(), llvm::Thumb1FrameLowering::eliminateCallFramePseudoInstr(), llvm::HexagonRegisterInfo::eliminateFrameIndex(), llvm::SIRegisterInfo::eliminateFrameIndex(), llvm::AArch64InstrInfo::emitLdStWithAddr(), llvm::RISCVInstrInfo::emitLdStWithAddr(), EmitLoweredCascadedSelect(), llvm::HexagonFrameLowering::emitPrologue(), llvm::HexagonEvaluator::evaluate(), llvm::M68kInstrInfo::ExpandCCR(), ExpandMOVImmSExti8(), expandXorFP(), llvm::AArch64GISelUtils::extractPtrauthBlendDiscriminators(), llvm::PPCInstrInfo::finalizeInsInstrs(), llvm::RISCVInstrInfo::finalizeInsInstrs(), llvm::SPIRVTargetLowering::finalizeLowering(), findLoopComponents(), findRedundantFlagInstr(), findTiedOperandIdx(), llvm::AArch64TargetLowering::fixupPtrauthDiscriminator(), llvm::SystemZInstrInfo::foldMemoryOperandImpl(), llvm::X86InstrInfo::foldMemoryOperandImpl(), llvm::fuseInstructionPair(), llvm::HexagonInstrInfo::genAllInsnTimingClasses(), llvm::TargetInstrInfo::genAlternativeCodeSequence(), genAlternativeDpCodeSequence(), generateAssignInstrs(), llvm::generateDotOrFMulInst(), generateGatherLanePattern(), llvm::generateGroupInst(), llvm::generateICarryBorrowInst(), llvm::generateImageSizeQueryInst(), genIndexedMultiply(), genShXAddAddShift(), genSubAdd2SubSub(), llvm::TargetInstrInfo::getAccumulatorChain(), llvm::TargetInstrInfo::getAccumulatorReassociationPatterns(), llvm::ARMAsmPrinter::getCodeViewJumpTableInfo(), llvm::HexagonInstrInfo::getCompoundOpcode(), llvm::getConstFromIntrinsic(), llvm::X86InstrInfo::getConstValDefinedInReg(), llvm::getDefInstrMaybeConstant(), llvm::getDefSrcRegIgnoringCopies(), getFMAPatterns(), llvm::PPCInstrInfo::getFMAPatterns(), getFMULPatterns(), getFNEGPatterns(), getFPFusedMultiplyPatterns(), llvm::ARMHazardRecognizerFPMLx::getHazardType(), llvm::AArch64RegisterBankInfo::getInstrMapping(), getLoadPatterns(), llvm::X86InstrInfo::getMachineCombinerPatterns(), getMaddPatterns(), llvm::SIInstrInfo::getMemOperandsWithOffsetWidth(), llvm::LanaiInstrInfo::getMemOperandsWithOffsetWidth(), llvm::RISCVInstrInfo::getMemOperandsWithOffsetWidth(), llvm::LanaiInstrInfo::getMemOperandWithOffsetWidth(), llvm::AArch64InstrInfo::getMemOperandWithOffsetWidth(), getMiscPatterns(), llvm::getNumSizeComponents(), llvm::getOpcodeDef(), llvm::SPIRVGlobalRegistry::getPointeeType(), llvm::SPIRVGlobalRegistry::getPointeeTypeOp(), llvm::RISCVInstrInfo::getReassociateOperandIndices(), llvm::TargetInstrInfo::getReassociationOpcodes(), llvm::SPIRVGlobalRegistry::getRegClass(), llvm::SPIRVGlobalRegistry::getRegType(), getSalvageOpsForTrunc(), llvm::GVecReduce::getScalarOpcForReduction(), llvm::SPIRVGlobalRegistry::getScalarOrVectorComponentType(), getSHXADDPatterns(), llvm::SPIRVGlobalRegistry::getSPIRVTypeID(), getTypeReg(), llvm::getVRegDef(), llvm::LiveIntervals::handleMoveIntoNewBundle(), hasAllNBitUsers(), llvm::RISCV::hasEqualFRM(), llvm::TargetInstrInfo::hasReassociableSibling(), llvm::RISCVInstrInfo::hasReassociableSibling(), llvm::GIntrinsic::hasSideEffects(), INITIALIZE_PASS(), llvm::SMSchedule::insert(), llvm::SPIRV::irhandle_sampled_image(), llvm::GAddSubCarryOut::isAdd(), isADDIInstr(), llvm::PPCInstrInfo::isADDIInstrEligibleForFolding(), llvm::PPCInstrInfo::isADDInstrEligibleForFolding(), isAddressLdStPair(), isAddSub2RegAndConstOnePair(), isAdrpAddPair(), isAESPair(), llvm::isAESPair(), isAnnotationLabel(), isArithmeticBccPair(), isArithmeticCbzPair(), isArithmeticLogicPair(), llvm::AArch64InstrInfo::isAssociativeAndCommutative(), llvm::PPCInstrInfo::isAssociativeAndCommutative(), llvm::RISCVInstrInfo::isAssociativeAndCommutative(), llvm::SystemZInstrInfo::isAssociativeAndCommutative(), llvm::X86InstrInfo::isAssociativeAndCommutative(), llvm::GIMatchTableExecutor::isBaseWithConstantOffset(), llvm::SPIRVGlobalRegistry::isBitcastCompatible(), isBundle(), isCandidateForAdditionalCallInfo(), isCFIInstruction(), llvm::AArch64GISelUtils::isCMN(), isCmpCSelPair(), isCmpCSetPair(), isCombineInstrCandidateFP(), isConstReg(), llvm::GIntrinsic::isConvergent(), isCopy(), isCryptoEORPair(), isCVTAToLocalCombinationCandidate(), isDebugLabel(), isDebugPHI(), isDebugRef(), isDebugValueList(), isEHLabel(), llvm::AArch64InstrInfo::isExtendLikelyToBeFolded(), isExtractHiElt(), isExtractSubreg(), isFakeUse(), isGCLabel(), isGFX12CacheInvOrWBInst(), isGuaranteedNotToBeUndefOrPoison(), isIdenticalTo(), isImplicitDef(), isInlineAsm(), isInsertSubreg(), isJumpTableDebugInfo(), isKill(), llvm::isKnownNeverNaN(), llvm::HexagonPacketizerList::isLegalToPacketizeTogether(), isLifetimeMarker(), isLiteralsPair(), llvm::isLiteralsPair(), isNonFoldablePartialRegisterLoad(), isNonListDebugValue(), isPHI(), isPreLdStPairCandidate(), llvm::ARMBaseInstrInfo::isProfitableToIfCvt(), isPseudoProbe(), isRedundantFlagInstr(), isRegSequence(), llvm::VLIWResourceModel::isResourceAvailable(), isSafeToMove(), llvm::SPIRVGlobalRegistry::isScalarOrVectorOfType(), isSExtLoad(), llvm::GAddSubCarryOut::isSigned(), llvm::GAddCarryOut::isSigned(), llvm::GSubCarryOut::isSigned(), llvm::GSUCmp::isSigned(), isSubregToReg(), llvm::HexagonInstrInfo::isToBeScheduledASAP(), isTransient(), IsVPNOTEquivalent(), isWaitInstr(), isZExtLoad(), llvm::MipsCallLowering::lowerCall(), LowerCallResults(), llvm::LegalizerHelper::lowerLoad(), llvm::ARMOverrideBypasses::makeBundleAssumptions(), llvm::MIPatternMatch::BinaryOp_match< LHS_P, RHS_P, Opcode, Commutable, Flags >::match(), llvm::MIPatternMatch::BinaryOpc_match< LHS_P, RHS_P, Commutable >::match(), llvm::MIPatternMatch::UnaryOp_match< SrcTy, Opcode >::match(), llvm::MIPatternMatch::CompareOp_match< Pred_P, LHS_P, RHS_P, Opcode, Commutable >::match(), llvm::MIPatternMatch::ClassifyOp_match< LHS_P, Test_P, Opcode >::match(), llvm::MIPatternMatch::TernaryOp_match< Src0Ty, Src1Ty, Src2Ty, Opcode >::match(), llvm::MIPatternMatch::ImplicitDefMatch::match(), llvm::CombinerHelper::matchCastOfBuildVector(), llvm::CombinerHelper::matchCastOfInteger(), llvm::CombinerHelper::matchCastOfSelect(), llvm::CombinerHelper::matchCombineFAddFMAFMulToFMadOrFMA(), llvm::CombinerHelper::matchCombineFAddFpExtFMulToFMadOrFMAAggressive(), llvm::AMDGPUCombinerHelper::matchCombineFmulWithSelectToFldexp(), llvm::CombinerHelper::matchCombineInsertVecElts(), llvm::CombinerHelper::matchCombineTruncOfShift(), llvm::CombinerHelper::matchCombineUnmergeConstant(), llvm::CombinerHelper::matchCommuteConstantToRHS(), llvm::CombinerHelper::matchExtendThroughPhis(), llvm::CombinerHelper::matchExtOfExt(), llvm::CombinerHelper::matchExtractVecEltBuildVec(), llvm::AMDGPUCombinerHelper::matchFoldableFneg(), llvm::CombinerHelper::matchHoistLogicOpWithSameOpcodeHands(), llvm::CombinerHelper::matchNarrowBinop(), llvm::CombinerHelper::matchNarrowBinopFeedingAnd(), llvm::CombinerHelper::matchOptBrCondByInvertingCond(), llvm::CombinerHelper::matchPtrAddImmedChain(), llvm::CombinerHelper::matchRedundantSextInReg(), llvm::CombinerHelper::matchShiftImmedChain(), llvm::CombinerHelper::matchShiftOfShiftedLogic(), llvm::CombinerHelper::matchSimplifyNegMinMax(), llvm::matchUnaryPredicate(), llvm::CombinerHelper::matchUseVectorTruncate(), mayOverlapWrite(), llvm::SIInstrInfo::moveFlatAddrToVGPR(), llvm::SIInstrInfo::moveToVALUImpl(), llvm::PPCInstrInfo::optimizeCmpPostRA(), llvm::AArch64InstrInfo::optimizeCompareInstr(), llvm::SIInstrInfo::optimizeCompareInstr(), llvm::ARMBaseInstrInfo::optimizeCompareInstr(), llvm::LanaiInstrInfo::optimizeCompareInstr(), llvm::X86InstrInfo::optimizeCompareInstr(), llvm::PPCInstrInfo::optimizeCompareInstr(), llvm::AArch64InstrInfo::optimizeCondBranch(), llvm::RISCVInstrInfo::optimizeSelect(), llvm::CallLowering::parametersInCSRMatch(), parseCondBranch(), print(), processBlockAddr(), processNewInstrs(), llvm::ARMBaseInstrInfo::produceSameValue(), propagateSPIRVType(), llvm::TargetInstrInfo::reduceAccumulatorTree(), llvm::SIInstrInfo::reMaterialize(), llvm::ARMBaseInstrInfo::reMaterialize(), llvm::X86InstrInfo::reMaterialize(), llvm::VLIWResourceModel::reserveResources(), llvm::ARMBlockPlacement::revertWhileToDoLoop(), llvm::MipsInstrInfo::SafeInFPUDelaySlot(), llvm::salvageDebugInfoForDbgValue(), llvm::SIScheduleDAGMI::schedule(), llvm::AArch64InstrInfo::shouldClusterMemOps(), llvm::PPCInstrInfo::shouldClusterMemOps(), shouldScheduleVOPDAdjacent(), stripVRegCopies(), tieOperands(), tryChangeVGPRtoSGPRinCopy(), llvm::LegalizationArtifactCombiner::tryCombineAnyExt(), llvm::LegalizationArtifactCombiner::tryCombineSExt(), AMDGPURegBankLegalizeCombiner::tryEliminateReadAnyLane(), llvm::LegalizationArtifactCombiner::tryFoldUnmergeCast(), AMDGPURegBankLegalizeCombiner::tryMatch(), AMDGPURegBankLegalizeCombiner::tryMatchRALFromUnmerge(), llvm::CombinerHelper::tryReassocBinOp(), typesLogicallyMatch(), llvm::X86InstrInfo::unfoldMemoryOperand(), updateGetPCBundle(), validateAccessChain(), validateFunCallMachineDef(), validateGroupWaitEventsPtr(), validateLifetimeStart(), validatePtrTypes(), validatePtrUnwrapStructField(), valueIsKnownNeverF32Denorm(), verifyCFIntrinsic(), and wouldBeTriviallyDead().
◆ getOperand() [1/2]
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Definition at line 598 of file MachineInstr.h.
◆ getOperand() [2/2]
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Definition at line 595 of file MachineInstr.h.
Referenced by addDebugSubstitutionsToTable(), addMemoryOperands(), llvm::ScheduleDAGInstrs::addPhysRegDataDeps(), llvm::ScheduleDAGInstrs::addPhysRegDeps(), addRegisterDead(), addRegisterKilled(), llvm::SrcOp::addSrcToMIB(), llvm::AArch64Subtarget::adjustSchedDependency(), llvm::HexagonSubtarget::adjustSchedDependency(), allPhiOperandsUndefined(), llvm::R600InstrInfo::analyzeBranch(), llvm::HexagonInstrInfo::analyzeBranch(), llvm::NVPTXInstrInfo::analyzeBranch(), llvm::PPCInstrInfo::analyzeBranch(), llvm::XCoreInstrInfo::analyzeBranch(), llvm::MipsInstrInfo::analyzeBranch(), llvm::AArch64InstrInfo::analyzeBranch(), llvm::SparcInstrInfo::analyzeBranch(), llvm::VEInstrInfo::analyzeBranch(), llvm::AArch64InstrInfo::analyzeBranchPredicate(), llvm::X86InstrInfo::analyzeBranchPredicate(), llvm::AArch64InstrInfo::analyzeLoopForPipelining(), llvm::CombinerHelper::applyCombineDivRem(), llvm::CombinerHelper::applyCombineExtendingLoads(), llvm::CombinerHelper::applyCombineTruncOfShift(), llvm::CombinerHelper::applyCombineUnmergeZExtToZExt(), llvm::CombinerHelper::applyExtendThroughPhis(), llvm::AMDGPUCombinerHelper::applyFoldableFneg(), llvm::SwingSchedulerDAG::applyInstrChange(), llvm::CombinerHelper::applyOptBrCondByInvertingCond(), llvm::CombinerHelper::applyShiftOfShiftedLogic(), areCombinableOperations(), llvm::HexagonInstrInfo::areMemAccessesTriviallyDisjoint(), BBIsJumpedOver(), bbIsJumpedOver(), llvm::buildAtomicCompareExchangeInst(), llvm::buildBoolRegister(), llvm::buildEnqueueKernel(), llvm::SPIRVGlobalRegistry::buildGlobalVariable(), llvm::SPIRVGlobalRegistry::buildMemAliasingOpDecorate(), llvm::buildNDRange(), buildRegSequence(), buildScratchExecCopy(), llvm::R600InstrInfo::buildSlotOfVectorInstruction(), canCombineShiftIntoShXAdd(), canCreateUndefOrPoison(), canEmitConjunction(), llvm::HexagonInstrInfo::canExecuteInBundle(), llvm::AArch64InstrInfo::canFoldIntoAddrMode(), llvm::RISCVInstrInfo::canFoldIntoAddrMode(), canFoldIntoCSel(), canInstrSubstituteCmpInstr(), canRenameMOP(), changeDebugValuesDefReg(), cloneInstr(), llvm::WebAssemblyDebugValueManager::cloneSink(), CombineCVTAToLocal(), combineFPFusedMultiply(), llvm::PPCInstrInfo::combineRLWINM(), llvm::X86InstrInfo::commuteInstructionImpl(), llvm::TargetInstrInfo::commuteInstructionImpl(), llvm::ARMBaseInstrInfo::commuteInstructionImpl(), llvm::TargetSchedModel::computeOperandLatency(), llvm::TargetSchedModel::computeOutputLatency(), ConsecutiveInstr(), llvm::SIInstrInfo::convertToThreeAddress(), llvm::R600InstrInfo::copyPhysReg(), createNewPtrType(), createPHIsForSelects(), llvm::ARCFrameLowering::eliminateCallFramePseudoInstr(), llvm::XCoreFrameLowering::eliminateCallFramePseudoInstr(), llvm::HexagonRegisterInfo::eliminateFrameIndex(), llvm::X86AsmPrinter::emitInstruction(), llvm::SITargetLowering::EmitInstrWithCustomInserter(), llvm::AArch64InstrInfo::emitLdStWithAddr(), llvm::RISCVInstrInfo::emitLdStWithAddr(), EmitLoweredCascadedSelect(), llvm::HexagonEvaluator::evaluate(), Expand2AddrUndef(), llvm::M68kInstrInfo::ExpandCCR(), expandFillPPRFromZPRSlotPseudo(), llvm::M68kInstrInfo::ExpandMOVEM(), llvm::M68kInstrInfo::ExpandMOVI(), ExpandMOVImmSExti8(), llvm::M68kInstrInfo::ExpandMOVSZX_RM(), llvm::M68kInstrInfo::ExpandMOVSZX_RR(), llvm::M68kInstrInfo::ExpandMOVX_RR(), expandNOVLXLoad(), expandNOVLXStore(), llvm::SIInstrInfo::expandPostRAPseudo(), llvm::X86InstrInfo::expandPostRAPseudo(), llvm::M68kInstrInfo::ExpandPUSH_POP(), expandSHXDROT(), expandSMEPPRToZPRSpillPseudos(), llvm::AArch64GISelUtils::extractPtrauthBlendDiscriminators(), llvm::PPCInstrInfo::finalizeInsInstrs(), llvm::RISCVInstrInfo::finalizeInsInstrs(), llvm::SPIRVTargetLowering::finalizeLowering(), findAssignTypeInstr(), findInlineAsmFlagIdx(), findLoopComponents(), findRedundantFlagInstr(), findRegisterDefOperand(), findRegisterDefOperandIdx(), findRegisterUseOperand(), findRegisterUseOperandIdx(), findTiedOperandIdx(), llvm::AArch64TargetLowering::fixupPtrauthDiscriminator(), llvm::SwingSchedulerDAG::fixupRegisterOverlaps(), llvm::PPCInstrInfo::foldFrameOffset(), foldInlineAsmMemOperand(), llvm::AArch64InstrInfo::foldMemoryOperandImpl(), llvm::SystemZInstrInfo::foldMemoryOperandImpl(), llvm::X86InstrInfo::foldMemoryOperandImpl(), foldVGPRCopyIntoRegSequence(), llvm::TargetInstrInfo::genAlternativeCodeSequence(), llvm::AArch64InstrInfo::genAlternativeCodeSequence(), llvm::RISCVInstrInfo::genAlternativeCodeSequence(), genAlternativeDpCodeSequence(), generateAssignInstrs(), llvm::generateCoopMatrInst(), generateGatherLanePattern(), llvm::generateImageMiscQueryInst(), llvm::generateImageSizeQueryInst(), genFNegatedMAD(), genFusedMultiply(), genIndexedMultiply(), genMaddR(), genNeg(), genShXAddAddShift(), genSubAdd2SubSub(), llvm::TargetInstrInfo::getAccumulatorChain(), llvm::TargetInstrInfo::getAccumulatorReassociationPatterns(), llvm::X86InstrInfo::getAddrModeFromMemoryOp(), llvm::getArrayComponentCount(), getAS(), llvm::GIndexedLoad::getBaseReg(), llvm::GIndexedStore::getBaseReg(), llvm::GInsertSubvector::getBigVec(), llvm::getBlockStructInstr(), llvm::HexagonInstrInfo::getBundleNoShuf(), llvm::ARMAsmPrinter::getCodeViewJumpTableInfo(), llvm::HexagonInstrInfo::getCompoundOpcode(), llvm::GAnyCmp::getCond(), llvm::getConstFromIntrinsic(), llvm::X86InstrInfo::getConstValDefinedInReg(), getDebugExpressionOp(), getDebugLabel(), getDebugOffset(), getDebugVariableOp(), llvm::getDefInstrMaybeConstant(), llvm::getDefSrcRegIgnoringCopies(), llvm::GIndexedLoad::getDstReg(), llvm::GAnyLoad::getDstReg(), llvm::GInsertVectorElement::getElementReg(), getFirst2LLTs(), getFirst2RegLLTs(), getFirst2Regs(), getFirst3LLTs(), getFirst3RegLLTs(), getFirst3Regs(), getFirst4LLTs(), getFirst4RegLLTs(), getFirst4Regs(), getFirst5LLTs(), getFirst5RegLLTs(), getFirst5Regs(), getFMAPatterns(), llvm::PPCInstrInfo::getFMAPatterns(), getFMULPatterns(), getFNEGPatterns(), getFPFusedMultiplyPatterns(), getGatherLanePattern(), llvm::StatepointOpers::getGCPointerMap(), llvm::GPhi::getIncomingBlock(), llvm::GPhi::getIncomingValue(), llvm::GExtractSubvector::getIndexImm(), llvm::GInsertSubvector::getIndexImm(), llvm::GExtractVectorElement::getIndexReg(), llvm::GInsertVectorElement::getIndexReg(), getInlineAsmDialect(), llvm::GIntrinsic::getIntrinsicID(), getLegalRegBank(), llvm::GBinOpCarryOut::getLHS(), llvm::GBinOpCarryOut::getLHSReg(), llvm::GSUCmp::getLHSReg(), llvm::SrcOp::getLLTTy(), getLocCookieMD(), llvm::getMachineInstrType(), getMaddPatterns(), llvm::GShuffleVector::getMask(), llvm::AArch64InstrInfo::getMemOpBaseRegImmOfsOffsetOperand(), llvm::SIInstrInfo::getMemOperandsWithOffsetWidth(), llvm::LanaiInstrInfo::getMemOperandWithOffsetWidth(), llvm::PPCInstrInfo::getMemOperandWithOffsetWidth(), llvm::RISCVInstrInfo::getMemOperandWithOffsetWidth(), llvm::AArch64InstrInfo::getMemOperandWithOffsetWidth(), getMiscPatterns(), getNewSource(), llvm::PatchPointOpers::getNextScratchIdx(), llvm::getNumSizeComponents(), llvm::GIndexedLoad::getOffsetReg(), llvm::GIndexedStore::getOffsetReg(), llvm::SPIRVGlobalRegistry::getOrCreateConsIntVector(), llvm::SPIRVGlobalRegistry::getOrCreateConstIntArray(), llvm::SPIRVGlobalRegistry::getOrCreateConstVector(), llvm::SPIRVGlobalRegistry::getOrCreateOpTypeSampledImage(), llvm::PeelingModuloScheduleExpander::getPhiCanonicalReg(), llvm::SPIRVGlobalRegistry::getPointeeType(), llvm::GLoadStore::getPointerReg(), llvm::SSAUpdaterTraits< MachineSSAUpdater >::GetPoisonVal(), llvm::SrcOp::getReg(), llvm::GenericMachineInstr::getReg(), llvm::SPIRVGlobalRegistry::getRegClass(), getRegClassConstraint(), getRegClassConstraintEffect(), llvm::SPIRVGlobalRegistry::getRegType(), llvm::GBinOpCarryOut::getRHS(), llvm::GBinOpCarryOut::getRHSReg(), llvm::GSUCmp::getRHSReg(), getSalvageOpsForTrunc(), llvm::GSplatVector::getScalarReg(), llvm::GShl::getShiftReg(), getSHXADDPatterns(), getSingleUnwindDest(), llvm::GUnmerge::getSourceReg(), llvm::GFreeze::getSourceReg(), llvm::GVScale::getSrc(), llvm::GShuffleVector::getSrc1Reg(), llvm::GShuffleVector::getSrc2Reg(), llvm::GCastOp::getSrcReg(), llvm::GShl::getSrcReg(), llvm::GExtractSubvector::getSrcVec(), llvm::GStepVector::getStep(), llvm::GInsertSubvector::getSubVec(), getTargetMBB(), getTypeReg(), getTypeToPrint(), llvm::MachineSSAUpdater::GetValueInMiddleOfBlock(), llvm::GIndexedStore::getValueReg(), llvm::GStore::getValueReg(), llvm::GExtractVectorElement::getVectorReg(), llvm::GInsertVectorElement::getVectorReg(), llvm::getVRegDef(), llvm::GIndexedLoad::getWritebackReg(), llvm::GIndexedStore::getWritebackReg(), handleADRP(), hasAllNBitUsers(), hasComplexRegisterTies(), llvm::RISCV::hasEqualFRM(), hasMoreUses(), hasRAWHazard(), llvm::TargetInstrInfo::hasReassociableOperands(), llvm::RISCVInstrInfo::hasReassociableOperands(), llvm::TargetInstrInfo::hasReassociableSibling(), llvm::RISCVInstrInfo::hasReassociableSibling(), hasUnmodeledSideEffects(), if(), INITIALIZE_PASS(), llvm::SystemZELFFrameLowering::inlineStackProbe(), insert(), llvm::R600InstrInfo::insertBranch(), llvm::SIInstrInfo::insertBranch(), insertDivByZeroTrap(), llvm::LoongArchInstrInfo::insertIndirectBranch(), insertPHI(), llvm::SIInstrInfo::insertScratchExecCopy(), llvm::SPIRV::irhandle_sampled_image(), llvm::PPCInstrInfo::isADDIInstrEligibleForFolding(), isAddressLdStPair(), isAddSub2RegAndConstOnePair(), isAGPRCopy(), isArithmeticBccPair(), llvm::GIMatchTableExecutor::isBaseWithConstantOffset(), llvm::AArch64GISelUtils::isCMN(), isCmpCSetPair(), isConstantValuePHI(), isConstReg(), isConvergent(), isCVTAToLocalCombinationCandidate(), llvm::AArch64InstrInfo::isExtendLikelyToBeFolded(), isExtractHiElt(), isFullCopy(), isIdenticalTo(), isIdentityCopy(), llvm::isKnownNeverNaN(), isLdStSafeToCluster(), llvm::RISCVInstrInfo::isLdStSafeToPair(), llvm::HexagonPacketizerList::isLegalToPacketizeTogether(), isLiteralsPair(), isMatchingStartStopPair(), isNonFoldablePartialRegisterLoad(), isOperandSubregIdx(), llvm::GIndexedLoad::isPre(), llvm::GIndexedStore::isPre(), isRedundantFlagInstr(), isRegTiedToDefOperand(), isRegTiedToUseOperand(), llvm::SPIRVGlobalRegistry::isScalarOrVectorSigned(), isSignExtendedW(), llvm::PPCInstrInfo::isSignOrZeroExtended(), isStackAligningInlineAsm(), llvm::HexagonInstrInfo::isToBeScheduledASAP(), llvm::PPCInstrInfo::isValidToBeChangedReg(), IsVPNOTEquivalent(), isWaitInstr(), llvm::AArch64LegalizerInfo::legalizeIntrinsic(), llvm::AMDGPULegalizerInfo::legalizeIntrinsic(), llvm::X86InstrInfo::loadStoreTileReg(), llvm::MipsCallLowering::lowerCall(), llvm::X86CallLowering::lowerCall(), LowerCallResults(), llvm::SPIRVCallLowering::lowerFormalArguments(), llvm::AMDGPUCallLowering::lowerTailCall(), llvm::MIPatternMatch::BinaryOp_match< LHS_P, RHS_P, Opcode, Commutable, Flags >::match(), llvm::MIPatternMatch::BinaryOpc_match< LHS_P, RHS_P, Commutable >::match(), llvm::MIPatternMatch::UnaryOp_match< SrcTy, Opcode >::match(), llvm::MIPatternMatch::CompareOp_match< Pred_P, LHS_P, RHS_P, Opcode, Commutable >::match(), llvm::MIPatternMatch::ClassifyOp_match< LHS_P, Test_P, Opcode >::match(), llvm::MIPatternMatch::TernaryOp_match< Src0Ty, Src1Ty, Src2Ty, Opcode >::match(), llvm::CombinerHelper::matchCombineExtractedVectorLoad(), llvm::CombinerHelper::matchCombineFAddFMAFMulToFMadOrFMA(), llvm::CombinerHelper::matchCombineFAddFpExtFMulToFMadOrFMA(), llvm::CombinerHelper::matchCombineFAddFpExtFMulToFMadOrFMAAggressive(), llvm::AMDGPUCombinerHelper::matchCombineFmulWithSelectToFldexp(), llvm::CombinerHelper::matchCombineFSubFNegFMulToFMadOrFMA(), llvm::CombinerHelper::matchCombineFSubFpExtFMulToFMadOrFMA(), llvm::CombinerHelper::matchCombineFSubFpExtFNegFMulToFMadOrFMA(), llvm::CombinerHelper::matchCombineInsertVecElts(), llvm::CombinerHelper::matchCombineTruncOfShift(), llvm::CombinerHelper::matchCombineUnmergeConstant(), llvm::CombinerHelper::matchExtractVecEltBuildVec(), llvm::AMDGPUCombinerHelper::matchFoldableFneg(), llvm::CombinerHelper::matchHoistLogicOpWithSameOpcodeHands(), llvm::CombinerHelper::matchNarrowBinopFeedingAnd(), llvm::CombinerHelper::matchOptBrCondByInvertingCond(), llvm::CombinerHelper::matchPtrAddImmedChain(), llvm::CombinerHelper::matchRedundantSextInReg(), llvm::CombinerHelper::matchShiftImmedChain(), llvm::CombinerHelper::matchShiftOfShiftedLogic(), llvm::CombinerHelper::matchTruncUSatU(), llvm::CombinerHelper::matchTruncUSatUToFPTOUISat(), llvm::matchUnaryPredicate(), llvm::CombinerHelper::matchUnmergeValuesAnyExtBuildVector(), llvm::CombinerHelper::matchUseVectorTruncate(), mayFoldInlineAsmRegOp(), mayLoad(), mayStore(), llvm::SIInstrInfo::moveFlatAddrToVGPR(), llvm::PeelingModuloScheduleExpander::moveStageBetweenBlocks(), llvm::SIInstrInfo::moveToVALUImpl(), MoveVPNOTBeforeFirstUser(), oneUseDominatesOtherUses(), llvm::PPCInstrInfo::optimizeCmpPostRA(), llvm::AArch64InstrInfo::optimizeCompareInstr(), llvm::ARMBaseInstrInfo::optimizeCompareInstr(), llvm::X86InstrInfo::optimizeCompareInstr(), llvm::PPCInstrInfo::optimizeCompareInstr(), llvm::AArch64InstrInfo::optimizeCondBranch(), llvm::LanaiInstrInfo::optimizeSelect(), llvm::ARMBaseInstrInfo::optimizeSelect(), llvm::RISCVInstrInfo::optimizeSelect(), llvm::CallLowering::parametersInCSRMatch(), parseCondBranch(), llvm::PeelSingleBlockLoop(), print(), processBlockAddr(), processNewInstrs(), processSwitchesConstants(), llvm::ARMBaseInstrInfo::produceSameValue(), readsWritesVirtualRegister(), llvm::SGPRSpillBuilder::readWriteTmpVGPR(), llvm::TargetInstrInfo::reassociateOps(), llvm::TargetInstrInfo::reduceAccumulatorTree(), reinsertVectorIndexAdd(), llvm::SIInstrInfo::reMaterialize(), llvm::ARMBaseInstrInfo::reMaterialize(), llvm::X86InstrInfo::reMaterialize(), removeCopies(), RemoveDeadAddBetweenLEAAndJT(), llvm::X86FrameLowering::restoreWin32EHStackPointers(), llvm::RevertLoopDec(), llvm::ARMBlockPlacement::revertWhileToDoLoop(), llvm::MachineSSAUpdater::RewriteUse(), llvm::SelectionDAGISel::runOnMachineFunction(), llvm::salvageDebugInfoForDbgValue(), llvm::AArch64InstrInfo::shouldClusterMemOps(), splitBlock(), splitEdge(), stripVRegCopies(), llvm::MachineFunction::substituteDebugValuesForInst(), substituteSimpleCopyRegs(), tieOperands(), llvm::LegalizationArtifactCombiner::tryCombineExtract(), AMDGPURegBankLegalizeCombiner::tryEliminateReadAnyLane(), llvm::LegalizationArtifactCombiner::tryFoldUnmergeCast(), AMDGPURegBankLegalizeCombiner::tryMatch(), AMDGPURegBankLegalizeCombiner::tryMatchRALFromUnmerge(), llvm::CombinerHelper::tryReassocBinOp(), typesLogicallyMatch(), llvm::X86InstrInfo::unfoldMemoryOperand(), untieRegOperand(), llvm::HexagonPacketizerList::updateOffset(), updateOperandRegConstraints(), updatePhysDepsDownwards(), llvm::WebAssemblyDebugValueManager::updateReg(), validateAccessChain(), validateFunCall(), validateFunCallMachineDef(), validateGroupWaitEventsPtr(), validateLifetimeStart(), validatePtrTypes(), validatePtrUnwrapStructField(), valueIsKnownNeverF32Denorm(), and verifyCFIntrinsic().
◆ getOperandNo()
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inline |
Returns the number of the operand iterator I points to.
Definition at line 773 of file MachineInstr.h.
References I, and operands_begin().
Referenced by llvm::ScheduleDAGInstrs::addSchedBarrierDeps(), llvm::MachineOperand::getOperandNo(), llvm::RISCVRegisterInfo::getRegAllocationHints(), hasAllNBitUsers(), insert(), and tryChangeVGPRtoSGPRinCopy().
◆ getParent() [1/2]
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inline |
Definition at line 360 of file MachineInstr.h.
◆ getParent() [2/2]
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inline |
Definition at line 359 of file MachineInstr.h.
Referenced by llvm::SIRegisterInfo::addImplicitUsesForBlockCSRLoad(), addOperand(), llvm::LiveIntervals::addSegmentToEndOfBlock(), addUnreachableAfterTryTables(), llvm::GCNSubtarget::adjustSchedDependency(), analyzeCompressibleUses(), llvm::AMDGPU::RegBankLegalizeHelper::applyMappingPHI(), canCombineFPFusedMultiply(), llvm::checkVOPDRegConstraints(), llvm::WebAssemblyDebugValueManager::cloneSink(), collectCallSiteParameters(), CombineCVTAToLocal(), llvm::constrainOperandRegClass(), RegBankSelectHelper::constrainRegBankUse(), llvm::SPIRVGlobalRegistry::createConstFP(), llvm::SPIRVGlobalRegistry::createConstInt(), llvm::AArch64InstrInfo::emitLdStWithAddr(), llvm::RISCVInstrInfo::emitLdStWithAddr(), llvm::DebugHandlerBase::endInstruction(), eraseFromBundle(), eraseFromParent(), llvm::examineCFlagsUse(), expandLoadStackGuard(), expandMOV32r1(), llvm::M68kInstrInfo::ExpandMOVEM(), llvm::M68kInstrInfo::ExpandMOVI(), ExpandMOVImmSExti8(), llvm::M68kInstrInfo::ExpandMOVSZX_RM(), llvm::M68kInstrInfo::ExpandMOVSZX_RR(), llvm::X86InstrInfo::expandPostRAPseudo(), llvm::M68kInstrInfo::ExpandPUSH_POP(), expandXorFP(), llvm::findCMPToFoldIntoCBZ(), findPrologueEndLoc(), findRedundantFlagInstr(), findRenameRegForSameLdStRegPair(), findSingleRegUse(), llvm::ARMBlockPlacement::fixBackwardsWLS(), llvm::SystemZInstrInfo::foldMemoryOperandImpl(), llvm::TargetInstrInfo::genAlternativeCodeSequence(), llvm::AArch64InstrInfo::genAlternativeCodeSequence(), generateGatherLanePattern(), llvm::TargetInstrInfo::getAccumulatorChain(), llvm::TargetInstrInfo::getAccumulatorReassociationPatterns(), llvm::rdf::Liveness::getAllReachingDefs(), getDebugInstrNum(), getFMAPatterns(), llvm::PPCInstrInfo::getFMAPatterns(), getFMULPatterns(), getFNEGPatterns(), getFoldableImm(), getGatherLanePattern(), llvm::ARMHazardRecognizerFPMLx::getHazardType(), getLoadStoreOffsetSizeInBits(), getMaddPatterns(), getMF(), getMiscPatterns(), llvm::PPCInstrInfo::getOperandLatency(), llvm::SPIRVGlobalRegistry::getOrCreateSPIRVVectorType(), llvm::SPIRVGlobalRegistry::getOrCreateUndef(), llvm::PeelingModuloScheduleExpander::getPhiCanonicalReg(), getRegClassConstraint(), getSHXADDPatterns(), GetSymbolRef(), llvm::LiveVariables::HandleVirtRegUse(), hasAllNBitUsers(), llvm::TargetInstrInfo::hasReassociableOperands(), llvm::RISCVInstrInfo::hasReassociableOperands(), llvm::TargetInstrInfo::hasReassociableSibling(), hoistAndMergeSGPRInits(), INITIALIZE_PASS(), insertPHI(), isCombineInstrCandidateFP(), isCVTAToLocalCombinationCandidate(), isDereferenceableInvariantLoad(), llvm::SIInstrInfo::isLegalRegOperand(), llvm::GIMatchTableExecutor::isObviouslySafeToFold(), isReachable(), llvm::TargetInstrInfo::isReassociationCandidate(), isSafeToMove(), llvm::SIInstrInfo::isSafeToSink(), jumpTableFollowsTB(), llvm::AArch64MCInstLower::lowerSymbolOperandELF(), llvm::CombinerHelper::matchCombineExtractedVectorLoad(), llvm::CombinerHelper::matchFreezeOfSingleMaybePoisonOperand(), moveBefore(), llvm::SIInstrInfo::moveToVALUImpl(), llvm::PPCInstrInfo::optimizeCmpPostRA(), llvm::AArch64InstrInfo::optimizeCompareInstr(), llvm::SIInstrInfo::optimizeCompareInstr(), llvm::ARMBaseInstrInfo::optimizeCompareInstr(), llvm::LanaiInstrInfo::optimizeCompareInstr(), llvm::X86InstrInfo::optimizeCompareInstr(), llvm::PPCInstrInfo::optimizeCompareInstr(), llvm::AArch64InstrInfo::optimizeCondBranch(), llvm::LanaiInstrInfo::optimizeSelect(), llvm::ARMBaseInstrInfo::optimizeSelect(), llvm::RISCVInstrInfo::optimizeSelect(), llvm::ARMBaseInstrInfo::produceSameValue(), reinsertVectorIndexAdd(), removeFromBundle(), removeFromParent(), llvm::SlotIndexes::repairIndexesInRange(), rescheduleCanonically(), llvm::MachineSSAUpdater::RewriteUse(), llvm::salvageDebugInfoForDbgValue(), setDesc(), llvm::AArch64InstrInfo::shouldClusterMemOps(), llvm::SystemZRegisterInfo::shouldCoalesce(), llvm::WebAssemblyDebugValueManager::sink(), splitBlock(), llvm::TailDuplicator::tailDuplicateAndUpdate(), tryChangeVGPRtoSGPRinCopy(), updateGetPCBundle(), updatePHIs(), validateFunCall(), validateFunCallMachineDef(), validatePtrTypes(), validThroughout(), and verifyCFIntrinsic().
◆ getPCSections()
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inline |
Helper to extract PCSections metadata target sections.
Definition at line 853 of file MachineInstr.h.
References Info.
Referenced by cloneMemRefs(), dropMemRefs(), print(), setCFIType(), setHeapAllocMarker(), setMemRefs(), setMMRAMetadata(), setPCSections(), setPostInstrSymbol(), and setPreInstrSymbol().
◆ getPostInstrSymbol()
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inline |
Helper to extract a post-instruction symbol if one has been added.
Definition at line 831 of file MachineInstr.h.
References Info.
Referenced by cloneMemRefs(), dropMemRefs(), isIdenticalTo(), isNotDuplicable(), print(), setCFIType(), setHeapAllocMarker(), setMemRefs(), setMMRAMetadata(), setPCSections(), setPostInstrSymbol(), and setPreInstrSymbol().
◆ getPreInstrSymbol()
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inline |
Helper to extract a pre-instruction symbol if one has been added.
Definition at line 819 of file MachineInstr.h.
References Info.
Referenced by cloneMemRefs(), dropMemRefs(), isIdenticalTo(), isNotDuplicable(), print(), setCFIType(), setHeapAllocMarker(), setMemRefs(), setMMRAMetadata(), setPCSections(), setPostInstrSymbol(), and setPreInstrSymbol().
◆ getRegClassConstraint()
| const TargetRegisterClass * MachineInstr::getRegClassConstraint | ( | unsigned | OpIdx, |
| const TargetInstrInfo * | TII, | ||
| const TargetRegisterInfo * | TRI | ||
| ) | const |
Compute the static register class constraint for operand OpIdx.
For normal instructions, this is derived from the MCInstrDesc. For inline assembly it is derived from the flag words.
Returns NULL if the static register class constraint cannot be determined.
Definition at line 974 of file MachineInstr.cpp.
References assert(), F, findInlineAsmFlagIdx(), getDesc(), llvm::getImm(), getMF(), getOperand(), getParent(), isInlineAsm(), isReg(), isRegTiedToDefOperand(), OpIdx, TII, and TRI.
Referenced by getRegClassConstraintEffect(), and llvm::TargetInstrInfo::reassociateOps().
◆ getRegClassConstraintEffect()
| const TargetRegisterClass * MachineInstr::getRegClassConstraintEffect | ( | unsigned | OpIdx, |
| const TargetRegisterClass * | CurRC, | ||
| const TargetInstrInfo * | TII, | ||
| const TargetRegisterInfo * | TRI | ||
| ) | const |
Applies the constraints (def/use) implied by the OpIdx operand to the given CurRC.
Returns the register class that satisfies both CurRC and the constraints set by OpIdx MI. Returns NULL if such a register class does not exist.
- Precondition
- CurRC must not be NULL.
-
The operand at
OpIdxmust be a register.
Definition at line 1040 of file MachineInstr.cpp.
References assert(), getOperand(), getRegClassConstraint(), llvm::MachineOperand::getSubReg(), llvm::MachineOperand::isReg(), OpIdx, TII, and TRI.
◆ getRegClassConstraintEffectForVReg()
| const TargetRegisterClass * MachineInstr::getRegClassConstraintEffectForVReg | ( | Register | Reg, |
| const TargetRegisterClass * | CurRC, | ||
| const TargetInstrInfo * | TII, | ||
| const TargetRegisterInfo * | TRI, | ||
| bool | ExploreBundle = false |
||
| ) | const |
Applies the constraints (def/use) implied by this MI on Reg to the given CurRC.
If ExploreBundle is set and MI is part of a bundle, all the instructions inside the bundle will be taken into account. In other words, this method accumulates all the constraints of the operand of this MI and the related bundle if MI is a bundle or inside a bundle.
Returns the register class that satisfies both CurRC and the constraints set by MI. Returns NULL if such a register class does not exist.
- Precondition
- CurRC must not be NULL.
Definition at line 1011 of file MachineInstr.cpp.
References llvm::MIBundleOperandIteratorBase< ValueT >::isValid(), TII, and TRI.
◆ getRestoreSize()
| std::optional< LocationSize > MachineInstr::getRestoreSize | ( | const TargetInstrInfo * | TII | ) | const |
Return a valid size if the instruction is a restore instruction.
Definition at line 2592 of file MachineInstr.cpp.
References llvm::MachineFunction::getFrameInfo(), getMF(), llvm::MachineFrameInfo::isSpillSlotObjectIndex(), memoperands_begin(), and TII.
◆ getSpillSize()
| std::optional< LocationSize > MachineInstr::getSpillSize | ( | const TargetInstrInfo * | TII | ) | const |
Return a valid size if the instruction is a spill instruction.
Definition at line 2573 of file MachineInstr.cpp.
References llvm::MachineFunction::getFrameInfo(), getMF(), llvm::MachineFrameInfo::isSpillSlotObjectIndex(), memoperands_begin(), and TII.
◆ getTypeToPrint()
| LLT MachineInstr::getTypeToPrint | ( | unsigned | OpIdx, |
| SmallBitVector & | PrintedTypes, | ||
| const MachineRegisterInfo & | MRI | ||
| ) | const |
Debugging supportDetermine the generic type to be printed (if needed) on uses and defs.
Definition at line 1710 of file MachineInstr.cpp.
References getDesc(), getNumExplicitOperands(), getOperand(), llvm::LLT::isValid(), isVariadic(), MRI, llvm::MCInstrDesc::operands(), OpIdx, and llvm::SmallBitVector::set().
Referenced by print().
◆ hasComplexRegisterTies()
| bool MachineInstr::hasComplexRegisterTies | ( | ) | const |
Return true when an instruction has tied register that can't be determined by the instruction's descriptor.
This is useful for MIR printing, to determine whether we need to print the ties or not.
Definition at line 1693 of file MachineInstr.cpp.
References findTiedOperandIdx(), getDesc(), getNumOperands(), getOperand(), llvm::MCInstrDesc::getOperandConstraint(), I, llvm::MCInstrDesc::Opcode, and llvm::MCOI::TIED_TO.
Referenced by print().
◆ hasDebugOperandForReg()
Returns whether this debug value has at least one debug operand with the register Reg.
Definition at line 611 of file MachineInstr.h.
References llvm::any_of(), debug_operands(), and Reg.
Referenced by performSink(), and llvm::salvageDebugInfoForDbgValue().
◆ hasDelaySlot()
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inline |
Returns true if the specified instruction has a delay slot which must be filled by the code generator.
Definition at line 1070 of file MachineInstr.h.
References llvm::MCID::DelaySlot, and hasProperty().
Referenced by collectCallSiteParameters().
◆ hasExtraDefRegAllocReq()
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inline |
Returns true if this instruction def operands have special register allocation requirements that are not captured by the operand register classes.
e.g. ARM::LDRD's two def registers must be an even / odd pair, ARM::LDM registers have to be in ascending order. Post-register allocation passes should not attempt to change allocations for definitions of instructions with this flag.
Definition at line 1267 of file MachineInstr.h.
References llvm::MCID::ExtraDefRegAllocReq, and hasProperty().
◆ hasExtraSrcRegAllocReq()
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inline |
Returns true if this instruction source operands have special register allocation requirements that are not captured by the operand register classes.
e.g. ARM::STRD's two source registers must be an even / odd pair, ARM::STM registers have to be in ascending order. Post-register allocation passes should not attempt to change allocations for sources of instructions with this flag.
Definition at line 1257 of file MachineInstr.h.
References llvm::MCID::ExtraSrcRegAllocReq, and hasProperty().
◆ hasImplicitDef()
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inline |
Returns true if the instruction has implicit definition.
Definition at line 642 of file MachineInstr.h.
References implicit_operands().
Referenced by llvm::PPCInstrInfo::combineRLWINM(), and llvm::PPCInstrInfo::optimizeCmpPostRA().
◆ hasOneMemOperand()
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inline |
Return true if this instruction has exactly one MachineMemOperand.
Definition at line 813 of file MachineInstr.h.
References memoperands().
Referenced by llvm::SystemZInstrInfo::areMemAccessesTriviallyDisjoint(), llvm::X86InstrInfo::foldMemoryOperandImpl(), llvm::PPCInstrInfo::getMemOperandWithOffsetWidth(), llvm::RISCVInstrInfo::getMemOperandWithOffsetWidth(), and memOpsHaveSameBasePtr().
◆ hasOptionalDef()
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inline |
Set if this instruction has an optional definition, e.g.
ARM instructions which can set condition code if 's' bit is set.
Definition at line 922 of file MachineInstr.h.
References llvm::MCID::HasOptionalDef, and hasProperty().
Referenced by llvm::ARMBaseInstrInfo::optimizeSelect().
◆ hasOrderedMemoryRef()
| bool MachineInstr::hasOrderedMemoryRef | ( | ) | const |
Return true if this instruction may have an ordered or volatile memory reference, or if the information describing the memory reference is not available.
hasOrderedMemoryRef - Return true if this instruction may have an ordered or volatile memory reference, or if the information describing the memory reference is not available.
Return false if it is known to have no ordered or volatile memory references.
Return false if it is known to have no ordered memory references.
Definition at line 1573 of file MachineInstr.cpp.
References llvm::any_of(), hasUnmodeledSideEffects(), isCall(), llvm::MachineMemOperand::isUnordered(), mayLoad(), mayStore(), memoperands(), and memoperands_empty().
Referenced by areCandidatesToMergeOrPair(), llvm::AArch64InstrInfo::areMemAccessesTriviallyDisjoint(), llvm::SIInstrInfo::areMemAccessesTriviallyDisjoint(), llvm::HexagonInstrInfo::areMemAccessesTriviallyDisjoint(), llvm::LanaiInstrInfo::areMemAccessesTriviallyDisjoint(), llvm::PPCInstrInfo::areMemAccessesTriviallyDisjoint(), llvm::RISCVInstrInfo::areMemAccessesTriviallyDisjoint(), isLdStSafeToCluster(), llvm::RISCVInstrInfo::isLdStSafeToPair(), llvm::HexagonPacketizerList::isLegalToPacketizeTogether(), llvm::SwingSchedulerDAG::isLoopCarriedDep(), and isSafeToMove().
◆ hasPostISelHook()
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inline |
Return true if this instruction requires adjustment after instruction selection by calling a target hook.
For example, this can be used to fill in ARM 's' optional operand depending on whether the conditional flag register is used.
Definition at line 1226 of file MachineInstr.h.
References llvm::MCID::HasPostISelHook, and hasProperty().
◆ hasProperty()
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inline |
Return true if the instruction (or in the case of a bundle, the instructions inside the bundle) has the specified property.
The first argument is the property being queried. The second argument indicates whether the query should look inside instruction bundles.
Definition at line 895 of file MachineInstr.h.
References assert(), getDesc(), llvm::MCInstrDesc::getFlags(), IgnoreBundle, isBundled(), and isBundledWithPred().
Referenced by canFoldAsLoad(), hasDelaySlot(), hasExtraDefRegAllocReq(), hasExtraSrcRegAllocReq(), hasOptionalDef(), hasPostISelHook(), hasUnmodeledSideEffects(), isAsCheapAsAMove(), isBarrier(), isBitcast(), isBranch(), isCall(), isCommutable(), isCompare(), isConvergent(), isConvertibleTo3Addr(), isEHScopeReturn(), isExtractSubregLike(), isIndirectBranch(), isInsertSubregLike(), isMetaInstruction(), isMoveImmediate(), isMoveReg(), isNotDuplicable(), isPredicable(), isPreISelOpcode(), isPseudo(), isRegSequenceLike(), isRematerializable(), isReturn(), isSafeToMove(), isSelect(), isTerminator(), isVariadic(), mayLoad(), mayRaiseFPException(), mayStore(), and usesCustomInsertionHook().
◆ hasRegisterImplicitUseOperand()
Returns true if the MachineInstr has an implicit-use operand of exactly the given register (not considering sub/super-registers).
Definition at line 1072 of file MachineInstr.cpp.
References llvm::MachineOperand::getReg(), implicit_operands(), llvm::MachineOperand::isReg(), and llvm::MachineOperand::isUse().
◆ hasUnmodeledSideEffects()
| bool MachineInstr::hasUnmodeledSideEffects | ( | ) | const |
Return true if this instruction has side effects that are not modeled by mayLoad / mayStore, etc.
For all instructions, the property is encoded in MCInstrDesc::Flags (see MCInstrDesc::hasUnmodeledSideEffects(). The only exception is INLINEASM instruction, in which case the side effect property is encoded in one of its operands (see InlineAsm::Extra_HasSideEffect).
Definition at line 1644 of file MachineInstr.cpp.
References llvm::InlineAsm::Extra_HasSideEffects, llvm::MachineOperand::getImm(), getOperand(), hasProperty(), isInlineAsm(), llvm::InlineAsm::MIOp_ExtraInfo, and llvm::MCID::UnmodeledSideEffects.
Referenced by llvm::AArch64InstrInfo::areMemAccessesTriviallyDisjoint(), llvm::SIInstrInfo::areMemAccessesTriviallyDisjoint(), llvm::HexagonInstrInfo::areMemAccessesTriviallyDisjoint(), llvm::LanaiInstrInfo::areMemAccessesTriviallyDisjoint(), llvm::PPCInstrInfo::areMemAccessesTriviallyDisjoint(), llvm::RISCVInstrInfo::areMemAccessesTriviallyDisjoint(), hasOrderedMemoryRef(), hasSameValue(), isLoadFoldBarrier(), and llvm::SwingSchedulerDAG::isLoopCarriedDep().
◆ implicit_operands() [1/2]
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inline |
Definition at line 702 of file MachineInstr.h.
References getNumExplicitOperands().
Referenced by allImplicitDefsAreDead(), hasImplicitDef(), hasRegisterImplicitUseOperand(), and llvm::SIInstrInfo::moveToVALUImpl().
◆ implicit_operands() [2/2]
|
inline |
Definition at line 705 of file MachineInstr.h.
References getNumExplicitOperands().
◆ insert()
| void MachineInstr::insert | ( | mop_iterator | InsertBefore, |
| ArrayRef< MachineOperand > | Ops | ||
| ) |
Inserts Ops BEFORE It. Can untie/retie tied operands.
Definition at line 2691 of file MachineInstr.cpp.
References addOperand(), assert(), llvm::SmallVectorImpl< T >::emplace_back(), llvm::ArrayRef< T >::empty(), findTiedOperandIdx(), getNumOperands(), getOperand(), getOperandNo(), llvm::MachineOperand::getParent(), I, llvm::MachineOperand::isReg(), llvm::MachineOperand::isTied(), operands(), OpIdx, removeOperand(), llvm::SmallVectorImpl< T >::reserve(), llvm::ArrayRef< T >::size(), tieOperands(), and untieRegOperand().
Referenced by llvm::RegBankSelect::repairReg().
◆ isAnnotationLabel()
|
inline |
◆ isAsCheapAsAMove()
|
inline |
Returns true if this instruction has the same cost (or less) than a move instruction.
This is useful during certain types of optimizations (e.g., remat during two-address conversion or machine licm) where we would like to remat or hoist the instruction, but not if it costs more than moving the instruction into the appropriate register. Note, we are not marking copies from and to the same register class with this flag.
Definition at line 1246 of file MachineInstr.h.
References llvm::MCID::CheapAsAMove, and hasProperty().
◆ isBarrier()
|
inline |
Returns true if the specified instruction stops control flow from executing the instruction immediately following it.
Examples include unconditional branches and return instructions.
Definition at line 965 of file MachineInstr.h.
References llvm::MCID::Barrier, and hasProperty().
Referenced by llvm::ScheduleDAGInstrs::addSchedBarrierDeps(), cannotCoexistAsymm(), llvm::ARMHazardRecognizerFPMLx::getHazardType(), llvm::HexagonPacketizerList::hasControlDependence(), isConditionalBranch(), isUnconditionalBranch(), and ProfitableToMerge().
◆ isBitcast()
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inline |
Return true if this instruction is a bitcast instruction.
Definition at line 1036 of file MachineInstr.h.
References llvm::MCID::Bitcast, and hasProperty().
◆ isBranch()
|
inline |
Returns true if this is a conditional, unconditional, or indirect branch.
Predicates below can be used to discriminate between these cases, and the TargetInstrInfo::analyzeBranch method can be used to get more information.
Definition at line 982 of file MachineInstr.h.
References llvm::MCID::Branch, and hasProperty().
Referenced by cannotCoexistAsymm(), llvm::HexagonPacketizerList::hasControlDependence(), isConditionalBranch(), llvm::HexagonPacketizerList::isLegalToPacketizeTogether(), isUnconditionalBranch(), and splitBlock().
◆ isBundle()
|
inline |
Definition at line 1427 of file MachineInstr.h.
References getOpcode().
Referenced by llvm::GCNSubtarget::adjustSchedDependency(), llvm::GCNHazardRecognizer::AdvanceCycle(), llvm::HexagonInstrInfo::getBundleNoShuf(), interpretNextInstr(), isIdenticalTo(), and shouldUpdateAdditionalCallInfo().
◆ isBundled()
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inline |
Return true if this instruction part of a bundle.
This is true if either itself or its following instruction is marked "InsideBundle".
Definition at line 484 of file MachineInstr.h.
References isBundledWithPred(), and isBundledWithSucc().
Referenced by hasProperty(), isCopyOfBundle(), and updateGetPCBundle().
◆ isBundledWithPred()
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inline |
Return true if this instruction is part of a bundle, and it is not the first instruction in the bundle.
Definition at line 490 of file MachineInstr.h.
References BundledPred, and getFlag().
Referenced by bundleWithPred(), hasProperty(), isBundled(), isCopyOfBundle(), and unbundleFromPred().
◆ isBundledWithSucc()
|
inline |
Return true if this instruction is part of a bundle, and it is not the last instruction in the bundle.
Definition at line 494 of file MachineInstr.h.
References BundledSucc, and getFlag().
Referenced by bundleWithSucc(), isBundled(), isCopyOfBundle(), moveInstrOut(), and unbundleFromSucc().
◆ isCall()
|
inline |
Definition at line 948 of file MachineInstr.h.
References llvm::MCID::Call, and hasProperty().
Referenced by llvm::ScheduleDAGInstrs::addSchedBarrierDeps(), cannotCoexistAsymm(), llvm::HexagonRegisterInfo::eliminateFrameIndex(), llvm::ARMBaseInstrInfo::getOutliningCandidateInfo(), llvm::HexagonPacketizerList::hasControlDependence(), llvm::HexagonPacketizerList::hasDeadDependence(), hasOrderedMemoryRef(), llvm::HexagonPacketizerList::hasRegMaskDependence(), llvm::MIRParserImpl::initializeCallSiteInfo(), interpretNextInstr(), isCandidateForAdditionalCallInfo(), isIdenticalTo(), llvm::HexagonPacketizerList::isLegalToPacketizeTogether(), isLoadFoldBarrier(), llvm::ARMBaseInstrInfo::isMBBSafeToOutlineFrom(), isSafeToMove(), isSignExtendedW(), llvm::PPCInstrInfo::isSignOrZeroExtended(), llvm::TargetInstrInfo::isTailCall(), mayAlias(), and llvm::MIRParserImpl::parseCalledGlobals().
◆ isCandidateForAdditionalCallInfo()
| bool MachineInstr::isCandidateForAdditionalCallInfo | ( | QueryType | Type = IgnoreBundle | ) | const |
Return true if this is a call instruction that may have an additional information associated with it.
Definition at line 780 of file MachineInstr.cpp.
References getOpcode(), and isCall().
Referenced by llvm::MachineFunction::addCallSiteInfo(), and shouldUpdateAdditionalCallInfo().
◆ isCFIInstruction()
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inline |
Definition at line 1336 of file MachineInstr.h.
References getOpcode().
Referenced by llvm::TargetInstrInfo::duplicate(), isPosition(), and print().
◆ isCommutable()
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inline |
Return true if this may be a 2- or 3-address instruction (of the form "X = op Y, Z, ..."), which produces the same result if Y and Z are exchanged.
If this flag is set, then the TargetInstrInfo::commuteInstruction method may be used to hack on the instruction.
Note that this flag may be set on instructions that are only commutable sometimes. In these cases, the call to commuteInstruction will fail. Also note that some instructions require non-trivial modification to commute them.
Definition at line 1188 of file MachineInstr.h.
References llvm::MCID::Commutable, and hasProperty().
◆ isCompare()
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inline |
Return true if this instruction is a comparison.
Definition at line 1019 of file MachineInstr.h.
References llvm::MCID::Compare, and hasProperty().
◆ isConditionalBranch()
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inline |
Return true if this is a branch which may fall through to the next instruction or may transfer control flow to some other block.
The TargetInstrInfo::analyzeBranch method can be used to get more information about this branch.
Definition at line 996 of file MachineInstr.h.
References isBarrier(), isBranch(), and isIndirectBranch().
◆ isConstantValuePHI()
| Register MachineInstr::isConstantValuePHI | ( | ) | const |
If the specified instruction is a PHI that always merges together the same virtual register, return the register, otherwise return Register().
Definition at line 1631 of file MachineInstr.cpp.
References assert(), getNumOperands(), getOperand(), llvm::MachineOperand::getReg(), getReg(), and isPHI().
Referenced by llvm::MachineSSAUpdater::GetValueInMiddleOfBlock().
◆ isConvergent()
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inline |
Return true if this instruction is convergent.
Convergent instructions can not be made control-dependent on any additional values.
Definition at line 1057 of file MachineInstr.h.
References llvm::MCID::Convergent, llvm::InlineAsm::Extra_IsConvergent, getFlag(), llvm::MachineOperand::getImm(), getOperand(), hasProperty(), isInlineAsm(), llvm::InlineAsm::MIOp_ExtraInfo, and NoConvergent.
◆ isConvertibleTo3Addr()
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inline |
Return true if this is a 2-address instruction which can be changed into a 3-address instruction if needed.
Doing this transformation can be profitable in the register allocator, because it means that the instruction can use a 2-address form if possible, but degrade into a less efficient form if the source and dest register cannot be assigned to the same register. For example, this allows the x86 backend to turn a "shl reg, 3" instruction into an LEA instruction, which is the same speed as the shift but has bigger code size.
If this returns true, then the target must implement the TargetInstrInfo::convertToThreeAddress method for this instruction, which is allowed to fail if the transformation isn't valid for this specific instruction (e.g. shl reg, 4 on x86).
Definition at line 1206 of file MachineInstr.h.
References llvm::MCID::ConvertibleTo3Addr, and hasProperty().
◆ isCopy()
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inline |
Definition at line 1431 of file MachineInstr.h.
References getOpcode().
Referenced by llvm::HexagonSubtarget::adjustSchedDependency(), llvm::createLibcall(), llvm::createMemLibcall(), foldVGPRCopyIntoRegSequence(), isAGPRCopy(), isCopyLike(), isFullCopy(), isIdentityCopy(), llvm::SIInstrInfo::moveToVALUImpl(), and llvm::AArch64InstrInfo::optimizeCondBranch().
◆ isCopyLike()
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inline |
Return true if the instruction behaves like a copy.
This does not include native copy instructions.
Definition at line 1447 of file MachineInstr.h.
References isCopy(), and isSubregToReg().
Referenced by llvm::InstrEmitter::EmitDbgInstrRef(), llvm::ARMBaseInstrInfo::getOperandLatency(), and llvm::MachineFunction::salvageCopySSAImpl().
◆ isDead()
| bool MachineInstr::isDead | ( | const MachineRegisterInfo & | MRI, |
| LiveRegUnits * | LivePhysRegs = nullptr |
||
| ) | const |
Check whether an MI is dead.
If LivePhysRegs is provided, it is assumed to be at the position of MI and will be used to check the Liveness of physical register defs. If LivePhysRegs is not provided, this will pessimistically assume any PhysReg def is live. For trivially dead instructions (i.e. those without hard to model effects / wouldBeTriviallyDead), this checks deadness by analyzing defs of the MachineInstr. If the instruction wouldBeTriviallyDead, and all the defs either have dead flags or have no uses, then the instruction is said to be dead.
Definition at line 1394 of file MachineInstr.cpp.
References all_defs(), llvm::LivePhysRegs::available(), llvm::MachineOperand::getReg(), llvm::MachineOperand::isDead(), isInlineAsm(), isLifetimeMarker(), MRI, and wouldBeTriviallyDead().
Referenced by findRegisterDefOperand(), and findRegisterDefOperandIdx().
◆ isDebugEntryValue()
| bool MachineInstr::isDebugEntryValue | ( | ) | const |
A DBG_VALUE is an entry value iff its debug expression contains the DW_OP_LLVM_entry_value operation.
Definition at line 969 of file MachineInstr.cpp.
References getDebugExpression(), isDebugValue(), and llvm::DIExpression::isEntryValue().
Referenced by handleNewDebugValue().
◆ isDebugInstr()
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inline |
Definition at line 1360 of file MachineInstr.h.
References isDebugLabel(), isDebugPHI(), isDebugRef(), and isDebugValue().
Referenced by addOperand(), llvm::createLibcall(), llvm::createMemLibcall(), llvm::SlotIndexes::getInstructionIndex(), getMatchedEntries(), isDebugOrPseudoInstr(), isIdenticalTo(), and isSafeToMove().
◆ isDebugLabel()
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inline |
Definition at line 1356 of file MachineInstr.h.
References getOpcode().
Referenced by getDebugLabel(), isDebugInstr(), and print().
◆ isDebugOffsetImm()
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inline |
Definition at line 1367 of file MachineInstr.h.
References getDebugOffset(), llvm::MachineOperand::isImm(), and isNonListDebugValue().
Referenced by isIndirectDebugValue().
◆ isDebugOperand()
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inline |
Definition at line 627 of file MachineInstr.h.
References llvm::adl_begin(), llvm::adl_end(), and debug_operands().
Referenced by getDebugOperandIndex(), and if().
◆ isDebugOrPseudoInstr()
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inline |
Definition at line 1363 of file MachineInstr.h.
References isDebugInstr(), and isPseudoProbe().
Referenced by llvm::SlotIndexes::repairIndexesInRange().
◆ isDebugPHI()
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inline |
Definition at line 1359 of file MachineInstr.h.
References getOpcode().
Referenced by isDebugInstr().
◆ isDebugRef()
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inline |
Definition at line 1357 of file MachineInstr.h.
References getOpcode().
Referenced by llvm::buildDbgValueForSpill(), isDebugInstr(), isDebugValueLike(), and print().
◆ isDebugValue()
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inline |
Definition at line 1353 of file MachineInstr.h.
References isDebugValueList(), and isNonListDebugValue().
Referenced by isDebugEntryValue(), isDebugInstr(), isDebugValueLike(), isUndefDebugValue(), setDebugValueUndef(), and llvm::TailDuplicator::tailDuplicateAndUpdate().
◆ isDebugValueLike()
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inline |
Definition at line 1358 of file MachineInstr.h.
References isDebugRef(), and isDebugValue().
Referenced by debug_operands(), getDebugExpressionOp(), getDebugVariableOp(), isEquivalentDbgInstr(), and print().
◆ isDebugValueList()
|
inline |
Definition at line 1350 of file MachineInstr.h.
References getOpcode().
Referenced by llvm::buildDbgValueForSpill(), isDebugValue(), and print().
◆ isDereferenceableInvariantLoad()
| bool MachineInstr::isDereferenceableInvariantLoad | ( | ) | const |
Return true if this load instruction never traps and points to a memory location whose value doesn't change during the execution of this function.
isDereferenceableInvariantLoad - Return true if this instruction will never trap and is loading from a location whose value is invariant across a run of this function.
Examples include loading a value from the constant pool or from the argument area of a function (if it does not change). If the instruction does multiple loads, this returns true only if all of the loads are dereferenceable and invariant.
Definition at line 1595 of file MachineInstr.cpp.
References llvm::MachineFunction::getFrameInfo(), llvm::MachineBasicBlock::getParent(), getParent(), mayLoad(), memoperands(), and memoperands_empty().
Referenced by hasSameValue(), isSafeToMove(), and llvm::CombinerHelper::matchEqualDefs().
◆ isEHLabel()
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inline |
◆ isEHScopeReturn()
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inline |
Return true if this is an instruction that marks the end of an EH scope, i.e., a catchpad or a cleanuppad instruction.
Definition at line 944 of file MachineInstr.h.
References llvm::MCID::EHScopeReturn, and hasProperty().
Referenced by llvm::MachineBasicBlock::isEHScopeReturnBlock().
◆ isEquivalentDbgInstr()
| bool MachineInstr::isEquivalentDbgInstr | ( | const MachineInstr & | Other | ) | const |
Returns true if this instruction is a debug instruction that represents an identical debug value to Other.
This function considers these debug instructions equivalent if they have identical variables, debug locations, and debug operands, and if the DIExpressions combined with the directness flags are equivalent.
Definition at line 737 of file MachineInstr.cpp.
References getDebugExpression(), getDebugLoc(), getDebugOperand(), getDebugVariable(), getNumDebugOperands(), isDebugValueLike(), llvm::DIExpression::isEqualExpression(), llvm::MachineOperand::isIdenticalTo(), isIndirectDebugValue(), OpIdx, and llvm::Other.
◆ isExtractSubreg()
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inline |
Definition at line 1439 of file MachineInstr.h.
References getOpcode().
Referenced by isOperandSubregIdx().
◆ isExtractSubregLike()
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inline |
Return true if this instruction behaves the same way as the generic EXTRACT_SUBREG instructions.
E.g., on ARM, rX, rY VMOVRRD dZ is equivalent to two EXTRACT_SUBREG: rX = EXTRACT_SUBREG dZ, ssub_0 rY = EXTRACT_SUBREG dZ, ssub_1
Note that for the optimizers to be able to take advantage of this property, TargetInstrInfo::getExtractSubregLikeInputs has to be override accordingly.
Definition at line 1111 of file MachineInstr.h.
References llvm::MCID::ExtractSubreg, and hasProperty().
◆ isFakeUse()
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inline |
Definition at line 1443 of file MachineInstr.h.
References getOpcode().
Referenced by wouldBeTriviallyDead().
◆ isFullCopy()
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inline |
Definition at line 1435 of file MachineInstr.h.
References getOperand(), llvm::MachineOperand::getSubReg(), and isCopy().
Referenced by removeCopies().
◆ isGCLabel()
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inline |
◆ isIdenticalTo()
| bool MachineInstr::isIdenticalTo | ( | const MachineInstr & | Other, |
| MICheckType | Check = CheckDefs |
||
| ) | const |
Return true if this instruction is identical to Other.
Two instructions are identical if they have the same opcode and all their operands are identical (with respect to MachineOperand::isIdenticalTo()). Note that this means liveness related flags (dead, undef, kill) do not affect the notion of identical.
Definition at line 658 of file MachineInstr.cpp.
References assert(), Check, CheckKillDead, getCFIType(), getDebugLoc(), llvm::ilist_node_impl< ilist_detail::compute_node_options< T, Options... >::type >::getIterator(), getNumOperands(), getOpcode(), getOperand(), getPostInstrSymbol(), getPreInstrSymbol(), llvm::MachineOperand::getReg(), IgnoreDefs, IgnoreVRegDefs, isBundle(), isCall(), llvm::MachineOperand::isDead(), isDebugInstr(), llvm::MachineOperand::isDef(), llvm::MachineOperand::isIdenticalTo(), llvm::MachineOperand::isKill(), llvm::MachineOperand::isReg(), llvm::Register::isVirtual(), and llvm::Other.
Referenced by llvm::SwingSchedulerDAG::mayOverlapInLaterIter(), llvm::ARMBaseInstrInfo::produceSameValue(), and llvm::TargetInstrInfo::produceSameValue().
◆ isIdentityCopy()
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inline |
Return true is the instruction is an identity copy.
Definition at line 1452 of file MachineInstr.h.
References getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::getSubReg(), and isCopy().
◆ isImplicitDef()
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inline |
Definition at line 1402 of file MachineInstr.h.
References getOpcode().
Referenced by llvm::HexagonPacketizerList::canPromoteToDotNew(), llvm::ARMBaseInstrInfo::getOperandLatency(), and shouldPreventUndefRegUpdateMemFold().
◆ isIndirectBranch()
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inline |
Return true if this is an indirect branch, such as a branch through a register.
Definition at line 988 of file MachineInstr.h.
References hasProperty(), and llvm::MCID::IndirectBranch.
Referenced by llvm::MipsInstrInfo::analyzeBranch(), blockEndsInUnreachable(), isConditionalBranch(), llvm::HexagonInstrInfo::isHVXMemWithAIndirect(), isUnconditionalBranch(), llvm::TailDuplicator::shouldTailDuplicate(), and llvm::MachineBasicBlock::terminatorIsComputedGotoWithSuccessors().
◆ isIndirectDebugValue()
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inline |
A DBG_VALUE is indirect iff the location operand is a register and the offset operand is an immediate.
Definition at line 1373 of file MachineInstr.h.
References getDebugOperand(), isDebugOffsetImm(), and llvm::MachineOperand::isReg().
Referenced by isEquivalentDbgInstr(), print(), and llvm::salvageDebugInfoForDbgValue().
◆ isInlineAsm()
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inline |
Definition at line 1403 of file MachineInstr.h.
References getOpcode().
Referenced by addOperand(), addRegisterDead(), addRegisterKilled(), cannotCoexistAsymm(), llvm::HexagonPacketizerList::canPromoteToDotCur(), llvm::HexagonPacketizerList::canPromoteToDotNew(), emitInlineAsmError(), findInlineAsmFlagIdx(), findTiedOperandIdx(), llvm::RegAllocBase::getErrorAssignment(), getInlineAsmDialect(), getRegClassConstraint(), hasUnmodeledSideEffects(), isConvergent(), isDead(), isSafeToMove(), isStackAligningInlineAsm(), mayFoldInlineAsmRegOp(), mayLoad(), mayStore(), print(), llvm::MipsInstrInfo::SafeInFPUDelaySlot(), llvm::MipsInstrInfo::SafeInLoadDelaySlot(), and tieOperands().
◆ isInsertSubreg()
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inline |
Definition at line 1415 of file MachineInstr.h.
References getOpcode().
Referenced by llvm::ARMBaseInstrInfo::getOperandLatency(), and isOperandSubregIdx().
◆ isInsertSubregLike()
|
inline |
Return true if this instruction behaves the same way as the generic INSERT_SUBREG instructions.
E.g., on ARM, dX = VSETLNi32 dY, rZ, Imm is equivalent to a INSERT_SUBREG: dX = INSERT_SUBREG dY, rZ, translateImmToSubIdx(Imm)
Note that for the optimizers to be able to take advantage of this property, TargetInstrInfo::getInsertSubregLikeInputs has to be override accordingly.
Definition at line 1125 of file MachineInstr.h.
References hasProperty(), and llvm::MCID::InsertSubreg.
◆ isInsideBundle()
|
inline |
Return true if MI is in a bundle (but not the first MI in a bundle).
A bundle looks like this before it's finalized:
| MI |
|
| MI * |
|
| MI * |
In this case, the first MI starts a bundle but is not inside a bundle, the next 2 MIs are considered "inside" the bundle.
After a bundle is finalized, it looks like this:
| Bundle |
|
| MI * |
|
| MI * |
|
| MI * |
The first instruction has the special opcode "BUNDLE". It's not "inside" a bundle, but the next three MIs are.
Definition at line 478 of file MachineInstr.h.
References BundledPred, and getFlag().
◆ isJumpTableDebugInfo()
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inline |
Definition at line 1393 of file MachineInstr.h.
References getOpcode().
Referenced by isSafeToMove().
◆ isKill()
|
inline |
Definition at line 1401 of file MachineInstr.h.
References getOpcode().
Referenced by findRegisterUseOperand(), and findRegisterUseOperandIdx().
◆ isLabel()
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inline |
Returns true if the MachineInstr represents a label.
Definition at line 1332 of file MachineInstr.h.
References isAnnotationLabel(), isEHLabel(), and isGCLabel().
Referenced by isPosition().
◆ isLifetimeMarker()
|
inline |
Definition at line 1326 of file MachineInstr.h.
References getOpcode().
Referenced by isDead(), and wouldBeTriviallyDead().
◆ isLoadFoldBarrier()
| bool MachineInstr::isLoadFoldBarrier | ( | ) | const |
Returns true if it is illegal to fold a load across this instruction.
Definition at line 1656 of file MachineInstr.cpp.
References hasUnmodeledSideEffects(), isCall(), isPseudoProbe(), and mayStore().
Referenced by getGatherLanePattern().
◆ isMetaInstruction()
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inline |
Return true if this instruction doesn't produce any output in the form of executable instructions.
Definition at line 934 of file MachineInstr.h.
References hasProperty(), and llvm::MCID::Meta.
Referenced by llvm::DebugHandlerBase::endInstruction(), and isTransient().
◆ isMoveImmediate()
|
inline |
Return true if this instruction is a move immediate (including conditional moves) instruction.
Definition at line 1025 of file MachineInstr.h.
References hasProperty(), and llvm::MCID::MoveImm.
Referenced by llvm::SIInstrInfo::moveFlatAddrToVGPR().
◆ isMoveReg()
|
inline |
Return true if this instruction is a register move.
(including moving values from subreg to reg)
Definition at line 1031 of file MachineInstr.h.
References hasProperty(), and llvm::MCID::MoveReg.
◆ isNonListDebugValue()
|
inline |
Definition at line 1347 of file MachineInstr.h.
References getOpcode().
Referenced by llvm::buildDbgValueForSpill(), debug_operands(), getDebugExpressionOp(), getDebugOffset(), getDebugVariableOp(), if(), isDebugOffsetImm(), isDebugValue(), print(), and llvm::updateDbgValueForSpill().
◆ isNotDuplicable()
|
inline |
Return true if this instruction cannot be safely duplicated.
For example, if the instruction has a unique labels attached to it, duplicating it would cause multiple definition errors.
Definition at line 1048 of file MachineInstr.h.
References getPostInstrSymbol(), getPreInstrSymbol(), hasProperty(), and llvm::MCID::NotDuplicable.
Referenced by llvm::TargetInstrInfo::duplicate().
◆ isOperandSubregIdx()
Return true if operand OpIdx is a subregister index.
Definition at line 655 of file MachineInstr.h.
References assert(), getOperand(), isExtractSubreg(), isInsertSubreg(), isRegSequence(), isSubregToReg(), and OpIdx.
Referenced by print().
◆ isPHI()
|
inline |
Definition at line 1397 of file MachineInstr.h.
References getOpcode().
Referenced by llvm::SMSchedule::computeStart(), llvm::PeelingModuloScheduleExpander::getPhiCanonicalReg(), isConstantValuePHI(), llvm::SMSchedule::isLoopCarried(), isSafeToMove(), llvm::CombinerHelper::matchFreezeOfSingleMaybePoisonOperand(), llvm::SwingSchedulerDAG::mayOverlapInLaterIter(), llvm::PeelingModuloScheduleExpander::peelPrologAndEpilogs(), llvm::PeelSingleBlockLoop(), llvm::SMSchedule::reorderInstructions(), llvm::MachineSSAUpdater::RewriteUse(), llvm::TailDuplicator::tailDuplicateAndUpdate(), and wouldBeTriviallyDead().
◆ isPosition()
|
inline |
Definition at line 1345 of file MachineInstr.h.
References isCFIInstruction(), and isLabel().
Referenced by isSafeToMove().
◆ isPredicable()
|
inline |
Return true if this instruction has a predicate operand that controls execution.
It may be set to 'always', or may be set to other values. There are various methods in TargetInstrInfo that can be used to control and modify the predicate in this instruction.
Definition at line 1012 of file MachineInstr.h.
References hasProperty(), and llvm::MCID::Predicable.
◆ isPreISelOpcode()
|
inline |
Return true if this is an instruction that should go through the usual legalization steps.
Definition at line 908 of file MachineInstr.h.
References hasProperty(), and llvm::MCID::PreISelOpcode.
◆ isPseudo()
|
inline |
Return true if this is a pseudo instruction that doesn't correspond to a real machine instruction.
Definition at line 928 of file MachineInstr.h.
References hasProperty(), and llvm::MCID::Pseudo.
Referenced by canRenameUntilSecondLoad(), llvm::ResourceManager::canReserveResources(), llvm::ResourceManager::reserveResources(), and llvm::ConvergingVLIWScheduler::SchedulingCost().
◆ isPseudoProbe()
|
inline |
Definition at line 1340 of file MachineInstr.h.
References getOpcode().
Referenced by isDebugOrPseudoInstr(), and isLoadFoldBarrier().
◆ isRegSequence()
|
inline |
Definition at line 1423 of file MachineInstr.h.
References getOpcode().
Referenced by llvm::HexagonSubtarget::adjustSchedDependency(), llvm::ARMBaseInstrInfo::getOperandLatency(), and isOperandSubregIdx().
◆ isRegSequenceLike()
|
inline |
Return true if this instruction behaves the same way as the generic REG_SEQUENCE instructions.
E.g., on ARM, dX VMOVDRR rY, rZ is equivalent to dX = REG_SEQUENCE rY, ssub_0, rZ, ssub_1.
Note that for the optimizers to be able to take advantage of this property, TargetInstrInfo::getRegSequenceLikeInputs has to be override accordingly.
Definition at line 1096 of file MachineInstr.h.
References hasProperty(), and llvm::MCID::RegSequence.
◆ isRegTiedToDefOperand()
|
inline |
Return true if the use operand of the specified index is tied to a def operand.
It also returns the def operand index by reference if DefOpIdx is not null.
Definition at line 1675 of file MachineInstr.h.
References findTiedOperandIdx(), getOperand(), llvm::MachineOperand::isReg(), llvm::MachineOperand::isTied(), and llvm::MachineOperand::isUse().
Referenced by addRegisterKilled(), llvm::AnalyzeVirtRegInBundle(), and getRegClassConstraint().
◆ isRegTiedToUseOperand()
|
inline |
Given the index of a register def operand, check if the register def is tied to a source operand, due to either two-address elimination or inline assembly constraints.
Returns the first tied use operand index by reference if UseOpIdx is not null.
Definition at line 1662 of file MachineInstr.h.
References findTiedOperandIdx(), getOperand(), llvm::MachineOperand::isDef(), llvm::MachineOperand::isReg(), and llvm::MachineOperand::isTied().
◆ isRematerializable()
|
inline |
Returns true if this instruction is a candidate for remat.
This flag is deprecated, please don't use it anymore. If this flag is set, the isReallyTriviallyReMaterializable() method is called to verify the instruction is really rematerializable.
Definition at line 1234 of file MachineInstr.h.
References hasProperty(), and llvm::MCID::Rematerializable.
◆ isReturn()
|
inline |
Definition at line 938 of file MachineInstr.h.
References hasProperty(), and llvm::MCID::Return.
Referenced by blockEndsInUnreachable(), cannotInsertTailCall(), llvm::createLibcall(), llvm::createMemLibcall(), llvm::RISCVInstrInfo::getOutliningCandidateInfo(), llvm::MachineBasicBlock::isReturnBlock(), and llvm::TargetInstrInfo::isTailCall().
◆ isSafeToMove()
Return true if it is safe to move this instruction.
isSafeToMove - Return true if it is safe to move this instruction.
If SawStore is set to true, it means that there is a store (or call) between the instruction's location and its intended destination.
Definition at line 1325 of file MachineInstr.cpp.
References hasOrderedMemoryRef(), hasProperty(), isCall(), isDebugInstr(), isDereferenceableInvariantLoad(), isInlineAsm(), isJumpTableDebugInfo(), isPHI(), isPosition(), isTerminator(), mayLoad(), mayRaiseFPException(), mayStore(), and llvm::MCID::UnmodeledSideEffects.
Referenced by llvm::TargetInstrInfo::optimizeLoadInstr(), and wouldBeTriviallyDead().
◆ isSelect()
|
inline |
Return true if this instruction is a select instruction.
Definition at line 1041 of file MachineInstr.h.
References hasProperty(), and llvm::MCID::Select.
◆ isStackAligningInlineAsm()
| bool MachineInstr::isStackAligningInlineAsm | ( | ) | const |
Definition at line 888 of file MachineInstr.cpp.
References llvm::InlineAsm::Extra_IsAlignStack, llvm::MachineOperand::getImm(), getOperand(), isInlineAsm(), and llvm::InlineAsm::MIOp_ExtraInfo.
◆ isSubregToReg()
|
inline |
Definition at line 1419 of file MachineInstr.h.
References getOpcode().
Referenced by isCopyLike(), and isOperandSubregIdx().
◆ isTerminator()
|
inline |
Returns true if this instruction part of the terminator for a basic block.
Typically this is things like return and branch instructions.
Various passes use this to insert code into the bottom of a basic block, but before control flow occurs.
Definition at line 974 of file MachineInstr.h.
References hasProperty(), and llvm::MCID::Terminator.
Referenced by cannotCoexistAsymm(), and isSafeToMove().
◆ isTransient()
|
inline |
Return true if this is a transient instruction that is either very likely to be eliminated during register allocation (such as copy-like instructions), or if this instruction doesn't have an execution-time cost.
Definition at line 1460 of file MachineInstr.h.
References getOpcode(), and isMetaInstruction().
Referenced by llvm::TargetSchedModel::computeOperandLatency(), llvm::SchedDFSImpl::visitPostorderNode(), and llvm::SchedDFSImpl::visitPreorder().
◆ isUnconditionalBranch()
|
inline |
Return true if this is a branch which always transfers control flow to some other block.
The TargetInstrInfo::analyzeBranch method can be used to get more information about this branch.
Definition at line 1004 of file MachineInstr.h.
References isBarrier(), isBranch(), and isIndirectBranch().
Referenced by llvm::MipsInstrInfo::analyzeBranch(), and llvm::RegBankSelect::tryAvoidingSplit().
◆ isUndefDebugValue()
|
inline |
Return true if the instruction is a debug value which describes a part of a variable as unavailable.
Definition at line 1383 of file MachineInstr.h.
References debug_operands(), and isDebugValue().
◆ isVariadic()
|
inline |
Return true if this instruction can have a variable number of operands.
In this case, the variable operands will be after the normal operands but before the implicit definitions and uses (if any are present).
Definition at line 916 of file MachineInstr.h.
References hasProperty(), and llvm::MCID::Variadic.
Referenced by getTypeToPrint().
◆ killsRegister()
|
inline |
Return true if the MachineInstr kills the specified register.
If TargetRegisterInfo is non-null, then it also checks if there is a kill of a super-register.
Definition at line 1508 of file MachineInstr.h.
References findRegisterUseOperandIdx(), Reg, and TRI.
◆ mayAlias() [1/2]
| bool MachineInstr::mayAlias | ( | AAResults * | AA, |
| const MachineInstr & | Other, | ||
| bool | UseTBAA | ||
| ) | const |
Definition at line 1560 of file MachineInstr.cpp.
References mayAlias(), llvm::Other, and UseTBAA.
◆ mayAlias() [2/2]
| bool MachineInstr::mayAlias | ( | BatchAAResults * | AA, |
| const MachineInstr & | Other, | ||
| bool | UseTBAA | ||
| ) | const |
Returns true if this instruction's memory access aliases the memory access of Other.
Assumes any physical registers used to compute addresses have the same value for both instructions. Returns false if neither instruction writes to memory.
- Parameters
-
AA Optional alias analysis, used to compare memory operands. Other MachineInstr to check aliasing against. UseTBAA Whether to pass TBAA information to alias analysis.
Definition at line 1516 of file MachineInstr.cpp.
References llvm::HexagonInstrInfo::areMemAccessesTriviallyDisjoint(), llvm::MachineFunction::getFrameInfo(), llvm::TargetSubtargetInfo::getInstrInfo(), getMF(), getNumMemOperands(), llvm::MachineFunction::getSubtarget(), isCall(), mayLoadOrStore(), mayStore(), memoperands(), memoperands_empty(), MemOperandsHaveAlias(), llvm::Other, TII, and UseTBAA.
Referenced by llvm::ScheduleDAGInstrs::addChainDependency(), mayAlias(), and mayAlias().
◆ mayFoldInlineAsmRegOp()
Returns true if the register operand can be folded with a load or store into a frame index.
Does so by checking the InlineAsm::Flag immediate operand at OpId - 1.
Definition at line 2736 of file MachineInstr.cpp.
References assert(), F, llvm::MachineOperand::getImm(), getOperand(), llvm::MachineOperand::isImm(), isInlineAsm(), and isReg().
◆ mayLoad()
|
inline |
Return true if this instruction could possibly read memory.
Instructions with this flag set are not necessarily simple load instructions, they may load a value and modify it, for example.
Definition at line 1136 of file MachineInstr.h.
References llvm::InlineAsm::Extra_MayLoad, llvm::MachineOperand::getImm(), getOperand(), hasProperty(), isInlineAsm(), llvm::MCID::MayLoad, and llvm::InlineAsm::MIOp_ExtraInfo.
Referenced by llvm::SUnit::addPredBarrier(), llvm::HexagonSubtarget::HVXMemLatencyMutation::apply(), llvm::HexagonSubtarget::BankConflictMutation::apply(), llvm::HexagonInstrInfo::areMemAccessesTriviallyDisjoint(), llvm::HexagonPacketizerList::canPromoteToNewValueStore(), llvm::AArch64InstrInfo::emitLdStWithAddr(), llvm::RISCVInstrInfo::emitLdStWithAddr(), llvm::TargetLoweringBase::emitPatchPoint(), findRenameRegForSameLdStRegPair(), llvm::TargetInstrInfo::foldMemoryOperand(), llvm::ARMBankConflictHazardRecognizer::getHazardType(), llvm::SIInstrInfo::getMemOperandsWithOffsetWidth(), hasOrderedMemoryRef(), isDereferenceableInvariantLoad(), llvm::HexagonPacketizerList::isLegalToPacketizeTogether(), isSafeToMove(), mayLoadOrStore(), llvm::LoopCarriedEdges::modifySUnits(), llvm::HexagonHazardRecognizer::ShouldPreferAnother(), and llvm::GCNMaxMemoryClauseSchedStrategy::tryCandidate().
◆ mayLoadOrStore()
|
inline |
Return true if this instruction could possibly read or modify memory.
Definition at line 1159 of file MachineInstr.h.
References mayLoad(), and mayStore().
Referenced by llvm::TargetInstrInfo::areMemAccessesTriviallyDisjoint(), llvm::AArch64InstrInfo::areMemAccessesTriviallyDisjoint(), llvm::SIInstrInfo::areMemAccessesTriviallyDisjoint(), llvm::LanaiInstrInfo::areMemAccessesTriviallyDisjoint(), llvm::PPCInstrInfo::areMemAccessesTriviallyDisjoint(), llvm::RISCVInstrInfo::areMemAccessesTriviallyDisjoint(), llvm::ARMHazardRecognizerFPMLx::getHazardType(), llvm::AArch64InstrInfo::getMemOpBaseRegImmOfsOffsetOperand(), llvm::SIInstrInfo::getMemOperandsWithOffsetWidth(), llvm::AArch64InstrInfo::getMemOperandsWithOffsetWidth(), llvm::RISCVInstrInfo::getMemOperandsWithOffsetWidth(), llvm::PPCInstrInfo::getMemOperandWithOffsetWidth(), llvm::RISCVInstrInfo::getMemOperandWithOffsetWidth(), llvm::AArch64InstrInfo::getMemOperandWithOffsetWidth(), hasSameValue(), llvm::SwingSchedulerDAG::isLoopCarriedDep(), llvm::CombinerHelper::matchEqualDefs(), and mayAlias().
◆ mayRaiseFPException()
|
inline |
Return true if this instruction could possibly raise a floating-point exception.
This is the case if the instruction is a floating-point instruction that can in principle raise an exception, as indicated by the MCID::MayRaiseFPException property, and at the same time, the instruction is used in a context where we expect floating-point exceptions are not disabled, as indicated by the NoFPExcept MI flag.
Definition at line 1169 of file MachineInstr.h.
References getFlag(), hasProperty(), llvm::MCID::MayRaiseFPException, and NoFPExcept.
Referenced by llvm::SwingSchedulerDAG::isLoopCarriedDep(), and isSafeToMove().
◆ mayStore()
|
inline |
Return true if this instruction could possibly modify memory.
Instructions with this flag set are not necessarily simple store instructions, they may store a modified value based on their operands, or may not actually modify anything, for example.
Definition at line 1149 of file MachineInstr.h.
References llvm::InlineAsm::Extra_MayStore, llvm::MachineOperand::getImm(), getOperand(), hasProperty(), isInlineAsm(), llvm::MCID::MayStore, and llvm::InlineAsm::MIOp_ExtraInfo.
Referenced by llvm::SUnit::addPredBarrier(), llvm::HexagonSubtarget::HVXMemLatencyMutation::apply(), llvm::HexagonSubtarget::BankConflictMutation::apply(), llvm::HexagonInstrInfo::canExecuteInBundle(), cannotCoexistAsymm(), llvm::HexagonPacketizerList::canPromoteToNewValueStore(), canRenameUpToDef(), llvm::TargetInstrInfo::foldMemoryOperand(), llvm::ARMBankConflictHazardRecognizer::getHazardType(), llvm::SIInstrInfo::getMemOperandsWithOffsetWidth(), llvm::HexagonPacketizerList::hasDualStoreDependence(), hasOrderedMemoryRef(), llvm::HexagonPacketizerList::isLegalToPacketizeTogether(), isLoadFoldBarrier(), isSafeToMove(), mayAlias(), mayLoadOrStore(), and llvm::LoopCarriedEdges::modifySUnits().
◆ memoperands()
|
inline |
Access to memory operands of the instruction.
If there are none, that does not imply anything about whether the function accesses memory. Instead, the caller must behave conservatively.
Definition at line 780 of file MachineInstr.h.
References Info.
Referenced by llvm::VLIWPacketizerList::alias(), cloneMergedMemRefs(), llvm::AArch64InstrInfo::emitLdStWithAddr(), llvm::RISCVInstrInfo::emitLdStWithAddr(), llvm::TargetInstrInfo::foldMemoryOperand(), llvm::ARMBankConflictHazardRecognizer::getHazardType(), getNumMemOperands(), hasOneMemOperand(), hasOrderedMemoryRef(), isDereferenceableInvariantLoad(), mayAlias(), memoperands_begin(), memoperands_empty(), memoperands_end(), llvm::ARMOverrideBypasses::memoryRAWHazard(), print(), llvm::SIInstrInfo::reMaterialize(), setCFIType(), setHeapAllocMarker(), setMMRAMetadata(), setPCSections(), setPostInstrSymbol(), and setPreInstrSymbol().
◆ memoperands_begin()
|
inline |
Access to memory operands of the instruction.
If memoperands_begin() == memoperands_end(), that does not imply anything about whether the function accesses memory. Instead, the caller must behave conservatively.
Definition at line 798 of file MachineInstr.h.
References memoperands().
Referenced by addMemOperand(), llvm::SystemZInstrInfo::areMemAccessesTriviallyDisjoint(), cloneMergedMemRefs(), expandLoadStackGuard(), llvm::TargetInstrInfo::foldMemoryOperand(), llvm::X86InstrInfo::foldMemoryOperandImpl(), llvm::PPCInstrInfo::getMemOperandWithOffsetWidth(), llvm::RISCVInstrInfo::getMemOperandWithOffsetWidth(), llvm::GMemOperation::getMMO(), getRestoreSize(), getSpillSize(), llvm::LegalizerHelper::lowerStore(), llvm::SwingSchedulerDAG::mayOverlapInLaterIter(), memOpsHaveSameBasePtr(), and llvm::LegalizerHelper::scalarizeVectorBooleanStore().
◆ memoperands_empty()
|
inline |
Return true if we don't have any memory operands which described the memory access done by this instruction.
If this is true, calling code must be conservative.
Definition at line 810 of file MachineInstr.h.
References memoperands().
Referenced by llvm::VLIWPacketizerList::alias(), cloneMergedMemRefs(), dropMemRefs(), hasOrderedMemoryRef(), isDereferenceableInvariantLoad(), mayAlias(), and print().
◆ memoperands_end()
|
inline |
Access to memory operands of the instruction.
If memoperands_begin() == memoperands_end(), that does not imply anything about whether the function accesses memory. Instead, the caller must behave conservatively.
Definition at line 805 of file MachineInstr.h.
References memoperands().
Referenced by addMemOperand(), cloneMergedMemRefs(), and llvm::TargetInstrInfo::foldMemoryOperand().
◆ mergeFlagsWith()
| uint32_t MachineInstr::mergeFlagsWith | ( | const MachineInstr & | Other | ) | const |
Return the MIFlags which represent both MachineInstrs.
This should be used when merging two MachineInstrs into one. This routine does not modify the MIFlags of this MachineInstr.
Definition at line 563 of file MachineInstr.cpp.
References getFlags(), and llvm::Other.
Referenced by llvm::AArch64InstrInfo::genAlternativeCodeSequence(), and genSubAdd2SubSub().
◆ modifiesRegister()
|
inline |
Return true if the MachineInstr modifies (fully define or partially define) the specified register.
NOTE: It's ignoring subreg indices on virtual registers.
Definition at line 1523 of file MachineInstr.h.
References findRegisterDefOperandIdx(), Reg, and TRI.
Referenced by llvm::HexagonPacketizerList::canPromoteToNewValueStore(), llvm::checkVOPDRegConstraints(), findRedundantFlagInstr(), isLdStSafeToCluster(), llvm::RISCVInstrInfo::isLdStSafeToPair(), llvm::HexagonPacketizerList::isLegalToPacketizeTogether(), and llvm::X86InstrInfo::reMaterialize().
◆ moveBefore()
| void MachineInstr::moveBefore | ( | MachineInstr * | MovePos | ) |
Move the instruction before MovePos.
Definition at line 152 of file MachineInstr.cpp.
References llvm::ilist_node_impl< ilist_detail::compute_node_options< T, Options... >::type >::getIterator(), getParent(), and llvm::MachineBasicBlock::splice().
Referenced by expandFillPPRFromZPRSlotPseudo().
◆ operands() [1/2]
|
inline |
Definition at line 693 of file MachineInstr.h.
Referenced by addDebugSubstitutionsToTable(), llvm::GCNDownwardRPTracker::advanceBeforeNext(), all_defs(), allDefsAreDead(), llvm::LiveRangeEdit::allUsesAvailableAt(), llvm::HexagonPacketizerList::canPromoteToNewValueStore(), canRenameUpToDef(), canUsePressureDiffs(), clearKillInfo(), clearRegisterKills(), llvm::PPCInstrInfo::convertToImmediateForm(), llvm::SIFrameLowering::determineCalleeSaves(), llvm::HexagonRegisterInfo::eliminateFrameIndex(), llvm::InstrEmitter::EmitDbgInstrRef(), llvm::GIMatchTableExecutor::executeMatchTable(), llvm::SystemZInstrInfo::foldMemoryOperandImpl(), llvm::LiveIntervals::handleMoveIntoNewBundle(), llvm::HexagonPacketizerList::hasDeadDependence(), llvm::HexagonPacketizerList::hasRegMaskDependence(), hasWriteToReadDep(), insert(), isSafeToMove(), scavengeFrameVirtualRegsInBlock(), setPhysRegsDeadExcept(), substituteRegister(), and updatePhysDepsDownwards().
◆ operands() [2/2]
|
inline |
Definition at line 694 of file MachineInstr.h.
◆ operands_begin() [1/2]
|
inline |
Definition at line 687 of file MachineInstr.h.
References Operands.
Referenced by eliminateMove(), llvm::X86InstrInfo::foldMemoryOperandImpl(), getOperandNo(), and llvm::R600SchedStrategy::schedNode().
◆ operands_begin() [2/2]
|
inline |
Definition at line 690 of file MachineInstr.h.
References Operands.
◆ operands_end() [1/2]
|
inline |
Definition at line 688 of file MachineInstr.h.
References Operands.
Referenced by llvm::R600SchedStrategy::schedNode().
◆ operands_end() [2/2]
|
inline |
Definition at line 691 of file MachineInstr.h.
References Operands.
◆ operator=()
|
delete |
◆ peekDebugInstrNum()
|
inline |
Examine the instruction number of this MachineInstr.
May be zero if it hasn't been assigned a number yet.
Definition at line 558 of file MachineInstr.h.
Referenced by addDebugSubstitutionsToTable(), llvm::TargetInstrInfo::reassociateOps(), and llvm::MachineFunction::substituteDebugValuesForInst().
◆ print() [1/2]
| void MachineInstr::print | ( | raw_ostream & | OS, |
| bool | IsStandalone = true, |
||
| bool | SkipOpers = false, |
||
| bool | SkipDebugLoc = false, |
||
| bool | AddNewLine = true, |
||
| const TargetInstrInfo * | TII = nullptr |
||
| ) | const |
Print this MI to OS.
Don't print information that can be inferred from other instructions if IsStandalone is false. It is usually true when only a fragment of the function is printed. Only print the defs and the opcode if SkipOpers is true. Otherwise, also print operands if SkipDebugLoc is true. Otherwise, also print the debug loc, with a terminating newline. TII is used to print the opcode name. If it's not present, but the MI is in a function, the opcode will be printed using the function's TII.
Definition at line 1772 of file MachineInstr.cpp.
References F, llvm::MachineFunction::getFunction(), llvm::TargetSubtargetInfo::getInstrInfo(), getMFIfAvailable(), llvm::MachineFunction::getSubtarget(), llvm::ModuleSlotTracker::incorporateFunction(), OS, print(), and TII.
Referenced by dump(), llvm::ScheduleDAGInstrs::getGraphNodeLabel(), llvm::SMSchedule::print(), print(), false::Chain::str(), and llvm::DbgValueHistoryMap::trimLocationRanges().
◆ print() [2/2]
| void MachineInstr::print | ( | raw_ostream & | OS, |
| ModuleSlotTracker & | MST, | ||
| bool | IsStandalone = true, |
||
| bool | SkipOpers = false, |
||
| bool | SkipDebugLoc = false, |
||
| bool | AddNewLine = true, |
||
| const TargetInstrInfo * | TII = nullptr |
||
| ) | const |
Definition at line 1790 of file MachineInstr.cpp.
References llvm::InlineAsm::AD_ATT, llvm::InlineAsm::AD_Intel, assert(), Context, Disjoint, DL, llvm::InlineAsm::Extra_HasSideEffects, llvm::InlineAsm::Extra_IsAlignStack, llvm::InlineAsm::Extra_IsConvergent, llvm::InlineAsm::Extra_MayLoad, llvm::InlineAsm::Extra_MayStore, F, findTiedOperandIdx(), FmAfn, FmArcp, FmContract, FmNoInfs, FmNoNans, FmNsz, FmReassoc, FrameDestroy, FrameSetup, getCFIType(), llvm::Function::getContext(), getDebugLoc(), getDebugVariable(), getDebugVariableOp(), getFlag(), llvm::MachineFunction::getFrameInfo(), llvm::MachineFunction::getFunction(), getHeapAllocMarker(), llvm::MachineOperand::getImm(), getInlineAsmDialect(), llvm::InlineAsm::getMemConstraintName(), llvm::MachineOperand::getMetadata(), getMFIfAvailable(), getMMRAMetadata(), getNumOperands(), getOpcode(), getOperand(), getPCSections(), getPostInstrSymbol(), getPreInstrSymbol(), getTypeToPrint(), hasComplexRegisterTies(), InBounds, isCFIInstruction(), isDebugLabel(), isDebugRef(), isDebugValueLike(), isDebugValueList(), llvm::MachineOperand::isDef(), IsExact, llvm::MachineOperand::isImm(), llvm::MachineOperand::isImplicit(), isIndirectDebugValue(), isInlineAsm(), llvm::MachineOperand::isMetadata(), isNonListDebugValue(), isOperandSubregIdx(), llvm::MachineOperand::isReg(), llvm::MachineOperand::isTied(), memoperands(), memoperands_empty(), llvm::InlineAsm::MIOp_AsmString, llvm::InlineAsm::MIOp_ExtraInfo, llvm::InlineAsm::MIOp_FirstOperand, MRI, NoFPExcept, NoMerge, NonNeg, NoSWrap, NoUSWrap, NoUWrap, OpIdx, OS, llvm::MachineBasicBlock::print(), llvm::MachineOperand::print(), llvm::MachineBasicBlock::printAsOperand(), llvm::Metadata::printAsOperand(), PrintMIAddrs, llvm::MachineOperand::printSubRegIdx(), llvm::MachineOperand::printSymbol(), SameSign, TII, TRI, and tryToGetTargetInfo().
◆ readsRegister()
|
inline |
Return true if the MachineInstr reads the specified register.
If TargetRegisterInfo is non-null, then it also checks if there is a read of a super-register. This does not count partial redefines of virtual registers as reads: reg1024:6 = OP.
Definition at line 1487 of file MachineInstr.h.
References findRegisterUseOperandIdx(), Reg, and TRI.
Referenced by checkAndUpdateCCRKill(), checkAndUpdateCPSRKill(), llvm::TargetSchedModel::computeOutputLatency(), llvm::HexagonInstrInfo::getCompoundOpcode(), hasWriteToReadDep(), llvm::HexagonPacketizerList::isLegalToPacketizeTogether(), and llvm::RegBankSelect::tryAvoidingSplit().
◆ readsVirtualRegister()
Return true if the MachineInstr reads the specified virtual register.
Take into account that a partial define is a read-modify-write operation.
Definition at line 1494 of file MachineInstr.h.
References readsWritesVirtualRegister(), and Reg.
◆ readsWritesVirtualRegister()
| std::pair< bool, bool > MachineInstr::readsWritesVirtualRegister | ( | Register | Reg, |
| SmallVectorImpl< unsigned > * | Ops = nullptr |
||
| ) | const |
Return a pair of bools (reads, writes) indicating if this instruction reads or writes Reg.
readsWritesVirtualRegister - Return a pair of bools (reads, writes) indicating if this instruction reads or writes Reg.
This also considers partial defines. If Ops is not null, all operand indices for Reg are added.
This also considers partial defines.
Definition at line 1104 of file MachineInstr.cpp.
References getNumOperands(), getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::getSubReg(), llvm::MachineOperand::isReg(), llvm::MachineOperand::isUndef(), llvm::MachineOperand::isUse(), and llvm::SmallVectorTemplateBase< T, bool >::push_back().
Referenced by readsVirtualRegister(), and llvm::MipsInstrInfo::SafeInFPUDelaySlot().
◆ registerDefIsDead()
|
inline |
Returns true if the register is dead in this machine instruction.
If TargetRegisterInfo is non-null, then it also checks if there is a dead def of a super-register.
Definition at line 1530 of file MachineInstr.h.
References findRegisterDefOperandIdx(), Reg, and TRI.
Referenced by transferDeadCC().
◆ removeFromBundle()
| MachineInstr * MachineInstr::removeFromBundle | ( | ) |
Unlink this instruction from its basic block and return it without deleting it.
If the instruction is part of a bundle, the other instructions in the bundle remain bundled.
Definition at line 765 of file MachineInstr.cpp.
References assert(), getParent(), and llvm::MachineBasicBlock::remove_instr().
◆ removeFromParent()
| MachineInstr * MachineInstr::removeFromParent | ( | ) |
Unlink 'this' from the containing basic block, and return it without deleting it.
This function can not be used on bundled instructions, use removeFromBundle() to remove individual instructions from a bundle.
Definition at line 760 of file MachineInstr.cpp.
References assert(), getParent(), and llvm::MachineBasicBlock::remove().
Referenced by llvm::M68kInstrInfo::ExpandMOVI(), llvm::WebAssemblyDebugValueManager::removeDef(), and llvm::ARMBlockPlacement::revertWhileToDoLoop().
◆ removeOperand()
| void MachineInstr::removeOperand | ( | unsigned | OpNo | ) |
Erase an operand from an instruction, leaving it with one fewer operand than it started with.
Definition at line 296 of file MachineInstr.cpp.
References assert(), getNumOperands(), isReg(), moveOperands(), MRI, N, and untieRegOperand().
Referenced by addRegisterDead(), addRegisterKilled(), llvm::X86InstrInfo::commuteInstructionImpl(), llvm::SIInstrInfo::convertToThreeAddress(), ExpandMOVImmSExti8(), expandSHXDROT(), genAlternativeDpCodeSequence(), llvm::MipsInstrInfo::genInstrWithNewOpc(), insert(), LowerCallResults(), llvm::SIInstrInfo::moveFlatAddrToVGPR(), llvm::SIInstrInfo::moveToVALUImpl(), llvm::AArch64InstrInfo::optimizeCompareInstr(), and llvm::X86InstrInfo::optimizeCompareInstr().
◆ setAsmPrinterFlag()
|
inline |
Set a flag for the AsmPrinter.
Definition at line 390 of file MachineInstr.h.
References assert().
Referenced by llvm::addNumImm(), llvm::SIRegisterInfo::buildSpillLoadStore(), and spillVGPRtoAGPR().
◆ setCFIType()
| void MachineInstr::setCFIType | ( | MachineFunction & | MF, |
| uint32_t | Type | ||
| ) |
Set the CFI type for the instruction.
Definition at line 529 of file MachineInstr.cpp.
References getCFIType(), getHeapAllocMarker(), getMMRAMetadata(), getPCSections(), getPostInstrSymbol(), getPreInstrSymbol(), and memoperands().
◆ setDebugInstrNum()
|
inline |
Set instruction number of this MachineInstr.
Avoid using unless you're deserializing this information.
Definition at line 562 of file MachineInstr.h.
Referenced by llvm::TargetInstrInfo::reassociateOps().
◆ setDebugLoc()
|
inline |
Replace current source information with new such.
Avoid using this, the constructor argument is preferable.
Definition at line 1894 of file MachineInstr.h.
Referenced by llvm::WebAssemblyDebugValueManager::cloneSink(), expandLoadStackGuard(), and llvm::WebAssemblyDebugValueManager::sink().
◆ setDebugValueUndef()
|
inline |
Sets all register debug operands in this debug value instruction to be undef.
Definition at line 2005 of file MachineInstr.h.
References assert(), debug_operands(), and isDebugValue().
Referenced by performSink(), and llvm::WebAssemblyDebugValueManager::removeDef().
◆ setDesc()
| void MachineInstr::setDesc | ( | const MCInstrDesc & | TID | ) |
Replace the instruction descriptor (thus opcode) of the current instruction with a new one.
Definition at line 145 of file MachineInstr.cpp.
References getMF(), getParent(), llvm::MachineFunction::handleChangeDesc(), and llvm::MCInstrDesc::Opcode.
Referenced by addConstantsToTrack(), llvm::X86InstrInfo::commuteInstructionImpl(), llvm::SIInstrInfo::commuteInstructionImpl(), llvm::SIInstrInfo::convertToThreeAddress(), Expand2AddrKreg(), Expand2AddrUndef(), llvm::M68kInstrInfo::ExpandCCR(), expandLoadStackGuard(), expandMOV32r1(), llvm::M68kInstrInfo::ExpandMOVI(), ExpandMOVImmSExti8(), expandMOVSHP(), llvm::M68kInstrInfo::ExpandMOVSZX_RM(), llvm::M68kInstrInfo::ExpandMOVX_RR(), expandNOVLXLoad(), expandNOVLXStore(), llvm::X86InstrInfo::expandPostRAPseudo(), expandSHXDROT(), expandXorFP(), genAlternativeDpCodeSequence(), llvm::SIInstrInfo::moveFlatAddrToVGPR(), llvm::PPCInstrInfo::optimizeCmpPostRA(), llvm::AArch64InstrInfo::optimizeCompareInstr(), llvm::X86InstrInfo::optimizeCompareInstr(), llvm::CombinerHelper::replaceOpcodeWith(), selectMergeValues(), selectUnmergeValues(), llvm::HexagonPacketizerList::shouldAddToPacket(), and llvm::X86InstrInfo::unfoldMemoryOperand().
◆ setFlag()
|
inline |
Set a MI flag.
Definition at line 416 of file MachineInstr.h.
References assert().
Referenced by bundleWithPred(), bundleWithSucc(), emitFROUND(), emitQuietFCMP(), fuseInst(), and transferMIFlag().
◆ setFlags()
|
inline |
Definition at line 422 of file MachineInstr.h.
References assert(), BundledPred, and BundledSucc.
Referenced by llvm::TargetInstrInfo::genAlternativeCodeSequence(), llvm::TargetInstrInfo::reassociateOps(), and llvm::TargetInstrInfo::reduceAccumulatorTree().
◆ setHeapAllocMarker()
| void MachineInstr::setHeapAllocMarker | ( | MachineFunction & | MF, |
| MDNode * | MD | ||
| ) |
Set a marker on instructions that denotes where we should create and emit heap alloc site labels.
This waits until after instruction selection and optimizations to create the label, so it should still work if the instruction is removed or duplicated.
Definition at line 510 of file MachineInstr.cpp.
References getCFIType(), getHeapAllocMarker(), getMMRAMetadata(), getPCSections(), getPostInstrSymbol(), getPreInstrSymbol(), and memoperands().
Referenced by cloneInstrSymbols(), and llvm::FastISel::lowerCallTo().
◆ setMemRefs()
| void MachineInstr::setMemRefs | ( | MachineFunction & | MF, |
| ArrayRef< MachineMemOperand * > | MemRefs | ||
| ) |
Assign this MachineInstr's memory reference descriptor list.
Unlike other methods, this will allocate them into a new array associated with the provided MachineFunction.
Definition at line 371 of file MachineInstr.cpp.
References dropMemRefs(), llvm::ArrayRef< T >::empty(), getCFIType(), getHeapAllocMarker(), getMMRAMetadata(), getPCSections(), getPostInstrSymbol(), and getPreInstrSymbol().
Referenced by addMemOperand(), cloneMemRefs(), cloneMergedMemRefs(), and llvm::TargetInstrInfo::foldMemoryOperand().
◆ setMMRAMetadata()
| void MachineInstr::setMMRAMetadata | ( | MachineFunction & | MF, |
| MDNode * | MMRAs | ||
| ) |
Definition at line 538 of file MachineInstr.cpp.
References getCFIType(), getHeapAllocMarker(), getMMRAMetadata(), getPCSections(), getPostInstrSymbol(), getPreInstrSymbol(), and memoperands().
Referenced by cloneInstrSymbols().
◆ setPCSections()
| void MachineInstr::setPCSections | ( | MachineFunction & | MF, |
| MDNode * | MD | ||
| ) |
Definition at line 519 of file MachineInstr.cpp.
References getCFIType(), getHeapAllocMarker(), getMMRAMetadata(), getPCSections(), getPostInstrSymbol(), getPreInstrSymbol(), and memoperands().
Referenced by cloneInstrSymbols().
◆ setPhysRegsDeadExcept()
| void MachineInstr::setPhysRegsDeadExcept | ( | ArrayRef< Register > | UsedRegs, |
| const TargetRegisterInfo & | TRI | ||
| ) |
Mark every physreg used by this instruction as dead except those in the UsedRegs list.
On instructions with register mask operands, also add implicit-def operands for all registers in UsedRegs.
Definition at line 2276 of file MachineInstr.cpp.
References addRegisterDefined(), llvm::MachineOperand::getReg(), llvm::MachineOperand::isDef(), llvm::MachineOperand::isReg(), llvm::MachineOperand::isRegMask(), llvm::none_of(), operands(), llvm::MachineOperand::setIsDead(), and TRI.
Referenced by llvm::FastISel::lowerCallTo(), and llvm::FastISel::selectPatchpoint().
◆ setPostInstrSymbol()
| void MachineInstr::setPostInstrSymbol | ( | MachineFunction & | MF, |
| MCSymbol * | Symbol | ||
| ) |
Set a symbol that will be emitted just after the instruction itself.
Setting this to a null pointer will remove any such symbol.
FIXME: This is not fully implemented yet.
Definition at line 494 of file MachineInstr.cpp.
References getCFIType(), getHeapAllocMarker(), getMMRAMetadata(), getPCSections(), getPostInstrSymbol(), getPreInstrSymbol(), and memoperands().
Referenced by cloneInstrSymbols(), and llvm::SIInstrInfo::insertIndirectBranch().
◆ setPreInstrSymbol()
| void MachineInstr::setPreInstrSymbol | ( | MachineFunction & | MF, |
| MCSymbol * | Symbol | ||
| ) |
Set a symbol that will be emitted just prior to the instruction itself.
Setting this to a null pointer will remove any such symbol.
FIXME: This is not fully implemented yet.
Definition at line 478 of file MachineInstr.cpp.
References getCFIType(), getHeapAllocMarker(), getMMRAMetadata(), getPCSections(), getPostInstrSymbol(), getPreInstrSymbol(), and memoperands().
Referenced by cloneInstrSymbols().
◆ setRegisterDefReadUndef()
Mark all subregister defs of register Reg with the undef flag.
This function is used when we determined to have a subregister def in an otherwise undefined super register.
Definition at line 2253 of file MachineInstr.cpp.
References all_defs(), llvm::MachineOperand::getReg(), llvm::MachineOperand::getSubReg(), and llvm::MachineOperand::setIsUndef().
Referenced by llvm::RegisterOperands::adjustLaneLiveness().
◆ shouldUpdateAdditionalCallInfo()
| bool MachineInstr::shouldUpdateAdditionalCallInfo | ( | ) | const |
Return true if copying, moving, or erasing this instruction requires updating additional call info (see copyCallInfo, moveCallInfo, eraseCallInfo).
Definition at line 793 of file MachineInstr.cpp.
References AnyInBundle, isBundle(), and isCandidateForAdditionalCallInfo().
Referenced by llvm::MachineFunction::cloneMachineInstrBundle(), llvm::MachineFunction::copyAdditionalCallInfo(), and llvm::MachineFunction::moveAdditionalCallInfo().
◆ substituteRegister()
| void MachineInstr::substituteRegister | ( | Register | FromReg, |
| Register | ToReg, | ||
| unsigned | SubIdx, | ||
| const TargetRegisterInfo & | RegInfo | ||
| ) |
Replace all occurrences of FromReg with ToReg:SubIdx, properly composing subreg indices where necessary.
Definition at line 1302 of file MachineInstr.cpp.
References llvm::MachineOperand::getReg(), llvm::MCRegisterInfo::getSubReg(), llvm::Register::isPhysical(), llvm::MachineOperand::isReg(), operands(), llvm::MachineOperand::substPhysReg(), and llvm::MachineOperand::substVirtReg().
Referenced by llvm::X86InstrInfo::reMaterialize().
◆ tieOperands()
Add a tie between the register operands at DefIdx and UseIdx.
tieOperands - Mark operands at DefIdx and UseIdx as tied to each other.
The tie will cause the register allocator to ensure that the two operands are assigned the same physical register.
Tied operands are managed automatically for explicit operands in the MCInstrDesc. This method is for exceptional cases like inline asm.
Use and def operands can be tied together, indicated by a non-zero TiedTo field. TiedTo can have these values:
0: Operand is not tied to anything. 1 to TiedMax-1: Tied to getOperand(TiedTo-1). TiedMax: Tied to an operand >= TiedMax-1.
The tied def must be one of the first TiedMax operands on a normal instruction. INLINEASM instructions allow more tied defs.
Definition at line 1191 of file MachineInstr.cpp.
References assert(), getOpcode(), getOperand(), llvm::MachineOperand::isDef(), isInlineAsm(), llvm::MachineOperand::isTied(), llvm::MachineOperand::isUse(), and TiedMax.
Referenced by addOperand(), llvm::SIInstrInfo::copyPhysReg(), llvm::TargetLoweringBase::emitPatchPoint(), llvm::SIInstrInfo::expandPostRAPseudo(), foldPatchpoint(), insert(), llvm::SIInstrInfo::moveFlatAddrToVGPR(), llvm::LanaiInstrInfo::optimizeSelect(), and llvm::ARMBaseInstrInfo::optimizeSelect().
◆ unbundleFromPred()
| void MachineInstr::unbundleFromPred | ( | ) |
Break bundle above this instruction.
Definition at line 870 of file MachineInstr.cpp.
References assert(), BundledPred, BundledSucc, clearFlag(), llvm::ilist_node_impl< ilist_detail::compute_node_options< T, Options... >::type >::getIterator(), and isBundledWithPred().
Referenced by moveInstrOut().
◆ unbundleFromSucc()
| void MachineInstr::unbundleFromSucc | ( | ) |
Break bundle below this instruction.
Definition at line 879 of file MachineInstr.cpp.
References assert(), BundledPred, BundledSucc, clearFlag(), llvm::ilist_node_impl< ilist_detail::compute_node_options< T, Options... >::type >::getIterator(), and isBundledWithSucc().
◆ untieRegOperand()
|
inline |
Break any tie involving OpIdx.
Definition at line 1984 of file MachineInstr.h.
References findTiedOperandIdx(), getOperand(), llvm::MachineOperand::isReg(), llvm::MachineOperand::isTied(), and OpIdx.
Referenced by genAlternativeDpCodeSequence(), insert(), llvm::SIInstrInfo::moveFlatAddrToVGPR(), and removeOperand().
◆ uses() [1/2]
|
inline |
Returns all operands which may be register uses.
This may include unrelated operands which are not register uses.
Definition at line 731 of file MachineInstr.h.
References getNumExplicitDefs().
Referenced by all_uses(), llvm::checkVOPDRegConstraints(), collectCallSiteParameters(), eliminateMove(), llvm::PPCInstrInfo::getConstantFromConstantPool(), llvm::SPIRVGlobalRegistry::getSPIRVTypeID(), hasSameValue(), llvm::StatepointOpers::isFoldableReg(), isGuaranteedNotToBeUndefOrPoison(), llvm::isKnownNeverNaN(), LowerCallResults(), and llvm::CombinerHelper::matchFreezeOfSingleMaybePoisonOperand().
◆ uses() [2/2]
|
inline |
Returns all operands which may be register uses.
This may include unrelated operands which are not register uses.
Definition at line 733 of file MachineInstr.h.
References getNumExplicitDefs().
◆ usesCustomInsertionHook()
|
inline |
Return true if this instruction requires custom insertion support when the DAG scheduler is inserting it into a machine basic block.
If this is true for the instruction, it basically means that it is a pseudo instruction used at SelectionDAG time that is expanded out into magic code by the target when MachineInstrs are formed.
If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method is used to insert this into the MachineBasicBlock.
Definition at line 1218 of file MachineInstr.h.
References hasProperty(), and llvm::MCID::UsesCustomInserter.
◆ wouldBeTriviallyDead()
| bool MachineInstr::wouldBeTriviallyDead | ( | ) | const |
Return true if this instruction would be trivially dead if all of its defined registers were dead.
Definition at line 1372 of file MachineInstr.cpp.
References getOpcode(), isFakeUse(), isLifetimeMarker(), isPHI(), and isSafeToMove().
Referenced by isDead().
Friends And Related Function Documentation
◆ ilist_callback_traits< MachineBasicBlock >
|
friend |
Definition at line 314 of file MachineInstr.h.
◆ ilist_traits< MachineInstr >
|
friend |
Definition at line 314 of file MachineInstr.h.
◆ MachineFunction
|
friend |
Definition at line 332 of file MachineInstr.h.
The documentation for this class was generated from the following files:
- include/llvm/CodeGen/MachineInstr.h
- lib/CodeGen/MachineInstr.cpp
