LLVM 23.0.0git
SPIRVInstructionSelector.cpp
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1//===- SPIRVInstructionSelector.cpp ------------------------------*- C++ -*-==//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements the targeting of the InstructionSelector class for
10// SPIRV.
11// TODO: This should be generated by TableGen.
12//
13//===----------------------------------------------------------------------===//
14
15#include "MCTargetDesc/SPIRVBaseInfo.h"
16#include "MCTargetDesc/SPIRVMCTargetDesc.h"
17#include "SPIRV.h"
18#include "SPIRVGlobalRegistry.h"
19#include "SPIRVInstrInfo.h"
20#include "SPIRVRegisterInfo.h"
21#include "SPIRVTargetMachine.h"
22#include "SPIRVUtils.h"
23#include "llvm/ADT/APFloat.h"
24#include "llvm/ADT/StringExtras.h"
25#include "llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h"
26#include "llvm/CodeGen/GlobalISel/GenericMachineInstrs.h"
27#include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
28#include "llvm/CodeGen/MachineInstrBuilder.h"
29#include "llvm/CodeGen/MachineRegisterInfo.h"
30#include "llvm/CodeGen/Register.h"
31#include "llvm/CodeGen/TargetOpcodes.h"
32#include "llvm/IR/IntrinsicsSPIRV.h"
33#include "llvm/Support/Debug.h"
34#include "llvm/Support/ErrorHandling.h"
35
36#define DEBUG_TYPE "spirv-isel"
37
38using namespace llvm;
39namespace CL = SPIRV::OpenCLExtInst;
40namespace GL = SPIRV::GLSLExtInst;
41
42using ExtInstList =
43 std::vector<std::pair<SPIRV::InstructionSet::InstructionSet, uint32_t>>;
44
45namespace {
46
47struct ImageOperands {
48 std::optional<Register> Bias;
49 std::optional<Register> Offset;
50 std::optional<Register> MinLod;
51 std::optional<Register> GradX;
52 std::optional<Register> GradY;
53 std::optional<Register> Lod;
54 std::optional<Register> Compare;
55};
56
57llvm::SPIRV::SelectionControl::SelectionControl
58getSelectionOperandForImm(int Imm) {
59 if (Imm == 2)
60 return SPIRV::SelectionControl::Flatten;
61 if (Imm == 1)
62 return SPIRV::SelectionControl::DontFlatten;
63 if (Imm == 0)
64 return SPIRV::SelectionControl::None;
65 llvm_unreachable("Invalid immediate");
66}
67
68#define GET_GLOBALISEL_PREDICATE_BITSET
69#include "SPIRVGenGlobalISel.inc"
70#undef GET_GLOBALISEL_PREDICATE_BITSET
71
72class SPIRVInstructionSelector : public InstructionSelector {
73 const SPIRVSubtarget &STI;
74 const SPIRVInstrInfo &TII;
75 const SPIRVRegisterInfo &TRI;
76 const RegisterBankInfo &RBI;
77 SPIRVGlobalRegistry &GR;
78 MachineRegisterInfo *MRI;
79 MachineFunction *HasVRegsReset = nullptr;
80
81 /// We need to keep track of the number we give to anonymous global values to
82 /// generate the same name every time when this is needed.
83 mutable DenseMap<const GlobalValue *, unsigned> UnnamedGlobalIDs;
84 SmallPtrSet<MachineInstr *, 8> DeadMIs;
85
86public:
87 SPIRVInstructionSelector(const SPIRVTargetMachine &TM,
88 const SPIRVSubtarget &ST,
89 const RegisterBankInfo &RBI);
90 void setupMF(MachineFunction &MF, GISelValueTracking *VT,
91 CodeGenCoverage *CoverageInfo, ProfileSummaryInfo *PSI,
92 BlockFrequencyInfo *BFI) override;
93 // Common selection code. Instruction-specific selection occurs in spvSelect.
94 bool select(MachineInstr &I) override;
95 static const char *getName() { return DEBUG_TYPE; }
96
97#define GET_GLOBALISEL_PREDICATES_DECL
98#include "SPIRVGenGlobalISel.inc"
99#undef GET_GLOBALISEL_PREDICATES_DECL
100
101#define GET_GLOBALISEL_TEMPORARIES_DECL
102#include "SPIRVGenGlobalISel.inc"
103#undef GET_GLOBALISEL_TEMPORARIES_DECL
104
105private:
106 void resetVRegsType(MachineFunction &MF);
107 void removeDeadInstruction(MachineInstr &MI) const;
108 void removeOpNamesForDeadMI(MachineInstr &MI) const;
109
110 // tblgen-erated 'select' implementation, used as the initial selector for
111 // the patterns that don't require complex C++.
112 bool selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const;
113
114 // All instruction-specific selection that didn't happen in "select()".
115 // Is basically a large Switch/Case delegating to all other select method.
116 bool spvSelect(Register ResVReg, SPIRVTypeInst ResType,
117 MachineInstr &I) const;
118
119 bool selectFirstBitHigh(Register ResVReg, SPIRVTypeInst ResType,
120 MachineInstr &I, bool IsSigned) const;
121
122 bool selectFirstBitLow(Register ResVReg, SPIRVTypeInst ResType,
123 MachineInstr &I) const;
124
125 bool selectFirstBitSet16(Register ResVReg, SPIRVTypeInst ResType,
126 MachineInstr &I, unsigned ExtendOpcode,
127 unsigned BitSetOpcode) const;
128
129 bool selectFirstBitSet32(Register ResVReg, SPIRVTypeInst ResType,
130 MachineInstr &I, Register SrcReg,
131 unsigned BitSetOpcode) const;
132
133 bool selectFirstBitSet64(Register ResVReg, SPIRVTypeInst ResType,
134 MachineInstr &I, Register SrcReg,
135 unsigned BitSetOpcode, bool SwapPrimarySide) const;
136
137 bool selectFirstBitSet64Overflow(Register ResVReg, SPIRVTypeInst ResType,
138 MachineInstr &I, Register SrcReg,
139 unsigned BitSetOpcode,
140 bool SwapPrimarySide) const;
141
142 bool selectGlobalValue(Register ResVReg, MachineInstr &I,
143 const MachineInstr *Init = nullptr) const;
144
145 bool selectOpWithSrcs(Register ResVReg, SPIRVTypeInst ResType,
146 MachineInstr &I, std::vector<Register> SrcRegs,
147 unsigned Opcode) const;
148
149 bool selectUnOp(Register ResVReg, SPIRVTypeInst ResType, MachineInstr &I,
150 unsigned Opcode) const;
151
152 bool selectBitcast(Register ResVReg, SPIRVTypeInst ResType,
153 MachineInstr &I) const;
154
155 bool selectLoad(Register ResVReg, SPIRVTypeInst ResType,
156 MachineInstr &I) const;
157 bool selectStore(MachineInstr &I) const;
158
159 bool selectStackSave(Register ResVReg, SPIRVTypeInst ResType,
160 MachineInstr &I) const;
161 bool selectStackRestore(MachineInstr &I) const;
162
163 bool selectMemOperation(Register ResVReg, MachineInstr &I) const;
164 Register getOrCreateMemSetGlobal(MachineInstr &I) const;
165 bool selectCopyMemory(MachineInstr &I, Register SrcReg) const;
166 bool selectCopyMemorySized(MachineInstr &I, Register SrcReg) const;
167
168 bool selectAtomicRMW(Register ResVReg, SPIRVTypeInst ResType, MachineInstr &I,
169 unsigned NewOpcode, unsigned NegateOpcode = 0) const;
170
171 bool selectAtomicCmpXchg(Register ResVReg, SPIRVTypeInst ResType,
172 MachineInstr &I) const;
173
174 bool selectFence(MachineInstr &I) const;
175
176 bool selectAddrSpaceCast(Register ResVReg, SPIRVTypeInst ResType,
177 MachineInstr &I) const;
178
179 bool selectAnyOrAll(Register ResVReg, SPIRVTypeInst ResType, MachineInstr &I,
180 unsigned OpType) const;
181
182 bool selectAll(Register ResVReg, SPIRVTypeInst ResType,
183 MachineInstr &I) const;
184
185 bool selectAny(Register ResVReg, SPIRVTypeInst ResType,
186 MachineInstr &I) const;
187
188 bool selectBitreverse(Register ResVReg, SPIRVTypeInst ResType,
189 MachineInstr &I) const;
190
191 bool selectBuildVector(Register ResVReg, SPIRVTypeInst ResType,
192 MachineInstr &I) const;
193 bool selectSplatVector(Register ResVReg, SPIRVTypeInst ResType,
194 MachineInstr &I) const;
195
196 bool selectCmp(Register ResVReg, SPIRVTypeInst ResType,
197 unsigned comparisonOpcode, MachineInstr &I) const;
198 bool selectDiscard(Register ResVReg, SPIRVTypeInst ResType,
199 MachineInstr &I) const;
200
201 bool selectICmp(Register ResVReg, SPIRVTypeInst ResType,
202 MachineInstr &I) const;
203 bool selectFCmp(Register ResVReg, SPIRVTypeInst ResType,
204 MachineInstr &I) const;
205
206 bool selectSign(Register ResVReg, SPIRVTypeInst ResType,
207 MachineInstr &I) const;
208
209 bool selectFloatDot(Register ResVReg, SPIRVTypeInst ResType,
210 MachineInstr &I) const;
211
212 bool selectOverflowArith(Register ResVReg, SPIRVTypeInst ResType,
213 MachineInstr &I, unsigned Opcode) const;
214 bool selectDebugTrap(Register ResVReg, SPIRVTypeInst ResType,
215 MachineInstr &I) const;
216
217 bool selectIntegerDot(Register ResVReg, SPIRVTypeInst ResType,
218 MachineInstr &I, bool Signed) const;
219
220 bool selectIntegerDotExpansion(Register ResVReg, SPIRVTypeInst ResType,
221 MachineInstr &I) const;
222
223 bool selectOpIsInf(Register ResVReg, SPIRVTypeInst ResType,
224 MachineInstr &I) const;
225
226 bool selectOpIsNan(Register ResVReg, SPIRVTypeInst ResType,
227 MachineInstr &I) const;
228
229 template <bool Signed>
230 bool selectDot4AddPacked(Register ResVReg, SPIRVTypeInst ResType,
231 MachineInstr &I) const;
232 template <bool Signed>
233 bool selectDot4AddPackedExpansion(Register ResVReg, SPIRVTypeInst ResType,
234 MachineInstr &I) const;
235
236 bool selectWavePrefixBitCount(Register ResVReg, SPIRVTypeInst ResType,
237 MachineInstr &I) const;
238
239 template <typename PickOpcodeFn>
240 bool selectWaveReduce(Register ResVReg, SPIRVTypeInst ResType,
241 MachineInstr &I, bool IsUnsigned,
242 PickOpcodeFn &&PickOpcode) const;
243
244 bool selectWaveReduceMax(Register ResVReg, SPIRVTypeInst ResType,
245 MachineInstr &I, bool IsUnsigned) const;
246
247 bool selectWaveReduceMin(Register ResVReg, SPIRVTypeInst ResType,
248 MachineInstr &I, bool IsUnsigned) const;
249
250 bool selectWaveReduceSum(Register ResVReg, SPIRVTypeInst ResType,
251 MachineInstr &I) const;
252
253 template <typename PickOpcodeFn>
254 bool selectWaveExclusiveScan(Register ResVReg, SPIRVTypeInst ResType,
255 MachineInstr &I, bool IsUnsigned,
256 PickOpcodeFn &&PickOpcode) const;
257
258 bool selectWaveExclusiveScanSum(Register ResVReg, SPIRVTypeInst ResType,
259 MachineInstr &I) const;
260
261 bool selectWaveExclusiveScanProduct(Register ResVReg, SPIRVTypeInst ResType,
262 MachineInstr &I) const;
263
264 bool selectConst(Register ResVReg, SPIRVTypeInst ResType,
265 MachineInstr &I) const;
266
267 bool selectSelect(Register ResVReg, SPIRVTypeInst ResType,
268 MachineInstr &I) const;
269 bool selectSelectDefaultArgs(Register ResVReg, SPIRVTypeInst ResType,
270 MachineInstr &I, bool IsSigned) const;
271 bool selectIToF(Register ResVReg, SPIRVTypeInst ResType, MachineInstr &I,
272 bool IsSigned, unsigned Opcode) const;
273 bool selectExt(Register ResVReg, SPIRVTypeInst ResType, MachineInstr &I,
274 bool IsSigned) const;
275
276 bool selectTrunc(Register ResVReg, SPIRVTypeInst ResType,
277 MachineInstr &I) const;
278
279 bool selectSUCmp(Register ResVReg, SPIRVTypeInst ResType, MachineInstr &I,
280 bool IsSigned) const;
281
282 bool selectIntToBool(Register IntReg, Register ResVReg, MachineInstr &I,
283 SPIRVTypeInst intTy, SPIRVTypeInst boolTy) const;
284
285 bool selectOpUndef(Register ResVReg, SPIRVTypeInst ResType,
286 MachineInstr &I) const;
287 bool selectFreeze(Register ResVReg, SPIRVTypeInst ResType,
288 MachineInstr &I) const;
289 bool selectIntrinsic(Register ResVReg, SPIRVTypeInst ResType,
290 MachineInstr &I) const;
291 bool selectExtractVal(Register ResVReg, SPIRVTypeInst ResType,
292 MachineInstr &I) const;
293 bool selectInsertVal(Register ResVReg, SPIRVTypeInst ResType,
294 MachineInstr &I) const;
295 bool selectExtractElt(Register ResVReg, SPIRVTypeInst ResType,
296 MachineInstr &I) const;
297 bool selectInsertElt(Register ResVReg, SPIRVTypeInst ResType,
298 MachineInstr &I) const;
299 bool selectGEP(Register ResVReg, SPIRVTypeInst ResType,
300 MachineInstr &I) const;
301
302 bool selectFrameIndex(Register ResVReg, SPIRVTypeInst ResType,
303 MachineInstr &I) const;
304 bool selectAllocaArray(Register ResVReg, SPIRVTypeInst ResType,
305 MachineInstr &I) const;
306
307 bool selectBranch(MachineInstr &I) const;
308 bool selectBranchCond(MachineInstr &I) const;
309
310 bool selectPhi(Register ResVReg, MachineInstr &I) const;
311
312 bool selectExtInst(Register ResVReg, SPIRVTypeInst RestType, MachineInstr &I,
313 GL::GLSLExtInst GLInst, bool setMIFlags = true,
314 bool useMISrc = true,
315 ArrayRef<Register> SrcRegs = {}) const;
316 bool selectExtInst(Register ResVReg, SPIRVTypeInst ResType, MachineInstr &I,
317 CL::OpenCLExtInst CLInst, bool setMIFlags = true,
318 bool useMISrc = true,
319 ArrayRef<Register> SrcRegs = {}) const;
320 bool selectExtInst(Register ResVReg, SPIRVTypeInst ResType, MachineInstr &I,
321 CL::OpenCLExtInst CLInst, GL::GLSLExtInst GLInst,
322 bool setMIFlags = true, bool useMISrc = true,
323 ArrayRef<Register> SrcRegs = {}) const;
324 bool selectExtInst(Register ResVReg, SPIRVTypeInst ResType, MachineInstr &I,
325 const ExtInstList &ExtInsts, bool setMIFlags = true,
326 bool useMISrc = true,
327 ArrayRef<Register> SrcRegs = {}) const;
328
329 bool selectLog10(Register ResVReg, SPIRVTypeInst ResType,
330 MachineInstr &I) const;
331
332 bool selectSaturate(Register ResVReg, SPIRVTypeInst ResType,
333 MachineInstr &I) const;
334
335 bool selectWaveOpInst(Register ResVReg, SPIRVTypeInst ResType,
336 MachineInstr &I, unsigned Opcode) const;
337
338 bool selectWaveActiveCountBits(Register ResVReg, SPIRVTypeInst ResType,
339 MachineInstr &I) const;
340
341 bool selectUnmergeValues(MachineInstr &I) const;
342
343 bool selectHandleFromBinding(Register &ResVReg, SPIRVTypeInst ResType,
344 MachineInstr &I) const;
345
346 bool selectCounterHandleFromBinding(Register &ResVReg, SPIRVTypeInst ResType,
347 MachineInstr &I) const;
348
349 bool selectReadImageIntrinsic(Register &ResVReg, SPIRVTypeInst ResType,
350 MachineInstr &I) const;
351 bool selectSampleBasicIntrinsic(Register &ResVReg, SPIRVTypeInst ResType,
352 MachineInstr &I) const;
353 bool selectSampleBiasIntrinsic(Register &ResVReg, SPIRVTypeInst ResType,
354 MachineInstr &I) const;
355 bool selectSampleGradIntrinsic(Register &ResVReg, SPIRVTypeInst ResType,
356 MachineInstr &I) const;
357 bool selectSampleLevelIntrinsic(Register &ResVReg, SPIRVTypeInst ResType,
358 MachineInstr &I) const;
359 bool selectSampleCmpIntrinsic(Register &ResVReg, SPIRVTypeInst ResType,
360 MachineInstr &I) const;
361 bool selectSampleCmpLevelZeroIntrinsic(Register &ResVReg,
362 SPIRVTypeInst ResType,
363 MachineInstr &I) const;
364 bool selectGatherIntrinsic(Register &ResVReg, SPIRVTypeInst ResType,
365 MachineInstr &I) const;
366 bool selectImageWriteIntrinsic(MachineInstr &I) const;
367 bool selectResourceGetPointer(Register &ResVReg, SPIRVTypeInst ResType,
368 MachineInstr &I) const;
369 bool selectPushConstantGetPointer(Register &ResVReg, SPIRVTypeInst ResType,
370 MachineInstr &I) const;
371 bool selectResourceNonUniformIndex(Register &ResVReg, SPIRVTypeInst ResType,
372 MachineInstr &I) const;
373 bool selectModf(Register ResVReg, SPIRVTypeInst ResType,
374 MachineInstr &I) const;
375 bool selectUpdateCounter(Register &ResVReg, SPIRVTypeInst ResType,
376 MachineInstr &I) const;
377 bool selectFrexp(Register ResVReg, SPIRVTypeInst ResType,
378 MachineInstr &I) const;
379 bool selectSincos(Register ResVReg, SPIRVTypeInst ResType,
380 MachineInstr &I) const;
381 bool selectExp10(Register ResVReg, SPIRVTypeInst ResType,
382 MachineInstr &I) const;
383 bool selectDerivativeInst(Register ResVReg, SPIRVTypeInst ResType,
384 MachineInstr &I, const unsigned DPdOpCode) const;
385 // Utilities
386 Register buildI32Constant(uint32_t Val, MachineInstr &I,
387 SPIRVTypeInst ResType = nullptr) const;
388
389 Register buildZerosVal(SPIRVTypeInst ResType, MachineInstr &I) const;
390 bool isScalarOrVectorIntConstantZero(Register Reg) const;
391 Register buildZerosValF(SPIRVTypeInst ResType, MachineInstr &I) const;
392 Register buildOnesVal(bool AllOnes, SPIRVTypeInst ResType,
393 MachineInstr &I) const;
394 Register buildOnesValF(SPIRVTypeInst ResType, MachineInstr &I) const;
395
396 bool wrapIntoSpecConstantOp(MachineInstr &I,
397 SmallVector<Register> &CompositeArgs) const;
398
399 Register getUcharPtrTypeReg(MachineInstr &I,
400 SPIRV::StorageClass::StorageClass SC) const;
401 MachineInstrBuilder buildSpecConstantOp(MachineInstr &I, Register Dest,
402 Register Src, Register DestType,
403 uint32_t Opcode) const;
404 MachineInstrBuilder buildConstGenericPtr(MachineInstr &I, Register SrcPtr,
405 SPIRVTypeInst SrcPtrTy) const;
406 Register buildPointerToResource(SPIRVTypeInst ResType,
407 SPIRV::StorageClass::StorageClass SC,
408 uint32_t Set, uint32_t Binding,
409 uint32_t ArraySize, Register IndexReg,
410 StringRef Name,
411 MachineIRBuilder MIRBuilder) const;
412 SPIRVTypeInst widenTypeToVec4(SPIRVTypeInst Type, MachineInstr &I) const;
413 bool extractSubvector(Register &ResVReg, SPIRVTypeInst ResType,
414 Register &ReadReg, MachineInstr &InsertionPoint) const;
415 bool generateImageReadOrFetch(Register &ResVReg, SPIRVTypeInst ResType,
416 Register ImageReg, Register IdxReg,
417 DebugLoc Loc, MachineInstr &Pos) const;
418 bool generateSampleImage(Register ResVReg, SPIRVTypeInst ResType,
419 Register ImageReg, Register SamplerReg,
420 Register CoordinateReg, const ImageOperands &ImOps,
421 DebugLoc Loc, MachineInstr &I) const;
422 bool BuildCOPY(Register DestReg, Register SrcReg, MachineInstr &I) const;
423 bool loadVec3BuiltinInputID(SPIRV::BuiltIn::BuiltIn BuiltInValue,
424 Register ResVReg, SPIRVTypeInst ResType,
425 MachineInstr &I) const;
426 bool loadBuiltinInputID(SPIRV::BuiltIn::BuiltIn BuiltInValue,
427 Register ResVReg, SPIRVTypeInst ResType,
428 MachineInstr &I) const;
429 bool loadHandleBeforePosition(Register &HandleReg, SPIRVTypeInst ResType,
430 GIntrinsic &HandleDef, MachineInstr &Pos) const;
431 void decorateUsesAsNonUniform(Register &NonUniformReg) const;
432 void errorIfInstrOutsideShader(MachineInstr &I) const;
433};
434
435bool sampledTypeIsSignedInteger(const llvm::Type *HandleType) {
436 const TargetExtType *TET = cast<TargetExtType>(HandleType);
437 if (TET->getTargetExtName() == "spirv.Image") {
438 return false;
439 }
440 assert(TET->getTargetExtName() == "spirv.SignedImage");
441 return TET->getTypeParameter(0)->isIntegerTy();
442}
443} // end anonymous namespace
444
445#define GET_GLOBALISEL_IMPL
446#include "SPIRVGenGlobalISel.inc"
447#undef GET_GLOBALISEL_IMPL
448
449SPIRVInstructionSelector::SPIRVInstructionSelector(const SPIRVTargetMachine &TM,
450 const SPIRVSubtarget &ST,
451 const RegisterBankInfo &RBI)
452 : InstructionSelector(), STI(ST), TII(*ST.getInstrInfo()),
453 TRI(*ST.getRegisterInfo()), RBI(RBI), GR(*ST.getSPIRVGlobalRegistry()),
454 MRI(nullptr),
455#define GET_GLOBALISEL_PREDICATES_INIT
456#include "SPIRVGenGlobalISel.inc"
457#undef GET_GLOBALISEL_PREDICATES_INIT
458#define GET_GLOBALISEL_TEMPORARIES_INIT
459#include "SPIRVGenGlobalISel.inc"
460#undef GET_GLOBALISEL_TEMPORARIES_INIT
461{
462}
463
464void SPIRVInstructionSelector::setupMF(MachineFunction &MF,
465 GISelValueTracking *VT,
466 CodeGenCoverage *CoverageInfo,
467 ProfileSummaryInfo *PSI,
468 BlockFrequencyInfo *BFI) {
469 MRI = &MF.getRegInfo();
470 GR.setCurrentFunc(MF);
471 InstructionSelector::setupMF(MF, VT, CoverageInfo, PSI, BFI);
472}
473
474// Ensure that register classes correspond to pattern matching rules.
475void SPIRVInstructionSelector::resetVRegsType(MachineFunction &MF) {
476 if (HasVRegsReset == &MF)
477 return;
478 HasVRegsReset = &MF;
479
480 MachineRegisterInfo &MRI = MF.getRegInfo();
481 for (unsigned I = 0, E = MRI.getNumVirtRegs(); I != E; ++I) {
482 Register Reg = Register::index2VirtReg(I);
483 LLT RegType = MRI.getType(Reg);
484 if (RegType.isScalar())
485 MRI.setType(Reg, LLT::scalar(64));
486 else if (RegType.isPointer())
487 MRI.setType(Reg, LLT::pointer(0, 64));
488 else if (RegType.isVector())
489 MRI.setType(Reg, LLT::fixed_vector(2, LLT::scalar(64)));
490 }
491 for (const auto &MBB : MF) {
492 for (const auto &MI : MBB) {
493 if (isPreISelGenericOpcode(MI.getOpcode()))
494 GR.erase(&MI);
495 if (MI.getOpcode() != SPIRV::ASSIGN_TYPE)
496 continue;
497
498 Register DstReg = MI.getOperand(0).getReg();
499 LLT DstType = MRI.getType(DstReg);
500 Register SrcReg = MI.getOperand(1).getReg();
501 LLT SrcType = MRI.getType(SrcReg);
502 if (DstType != SrcType)
503 MRI.setType(DstReg, MRI.getType(SrcReg));
504
505 const TargetRegisterClass *DstRC = MRI.getRegClassOrNull(DstReg);
506 const TargetRegisterClass *SrcRC = MRI.getRegClassOrNull(SrcReg);
507 if (DstRC != SrcRC && SrcRC)
508 MRI.setRegClass(DstReg, SrcRC);
509 }
510 }
511}
512
513// Return true if the MachineInstr represents a constant register
514static bool isConstReg(MachineRegisterInfo *MRI, MachineInstr *OpDef) {
515
516 SmallVector<MachineInstr *> Stack = {OpDef};
517 SmallPtrSet<MachineInstr *, 4> Visited;
518
519 while (!Stack.empty()) {
520 MachineInstr *MI = Stack.pop_back_val();
521 MI = passCopy(MI, MRI);
522 if (!Visited.insert(MI).second)
523 continue;
524 switch (MI->getOpcode()) {
525 case TargetOpcode::G_INTRINSIC:
526 case TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS:
527 case TargetOpcode::G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS:
528 if (cast<GIntrinsic>(*OpDef).getIntrinsicID() !=
529 Intrinsic::spv_const_composite)
530 return false;
531 continue;
532 case TargetOpcode::G_BUILD_VECTOR:
533 case TargetOpcode::G_SPLAT_VECTOR:
534 for (unsigned i = OpDef->getNumExplicitDefs();
535 i < OpDef->getNumOperands(); i++) {
536 if (!OpDef->getOperand(i).isReg())
537 continue;
538 MachineInstr *OpNestedDef =
539 MRI->getVRegDef(OpDef->getOperand(i).getReg());
540 Stack.push_back(OpNestedDef);
541 }
542 continue;
543 case TargetOpcode::G_CONSTANT:
544 case TargetOpcode::G_FCONSTANT:
545 case TargetOpcode::G_IMPLICIT_DEF:
546 case SPIRV::OpConstantTrue:
547 case SPIRV::OpConstantFalse:
548 case SPIRV::OpConstantI:
549 case SPIRV::OpConstantF:
550 case SPIRV::OpConstantComposite:
551 case SPIRV::OpConstantCompositeContinuedINTEL:
552 case SPIRV::OpConstantSampler:
553 case SPIRV::OpConstantNull:
554 case SPIRV::OpUndef:
555 case SPIRV::OpConstantFunctionPointerINTEL:
556 continue;
557 default:
558 return false;
559 }
560 }
561 return true;
562}
563
564// Return true if the virtual register represents a constant
565static bool isConstReg(MachineRegisterInfo *MRI, Register OpReg) {
566 if (MachineInstr *OpDef = MRI->getVRegDef(OpReg))
567 return isConstReg(MRI, OpDef);
568 return false;
569}
570
571// TODO(168736): We should make this either a flag in tabelgen
572// or reduce our dependence on the global registry, so we can remove this
573// function. It can easily be missed when new intrinsics are added.
574
575// Most SPIR-V intrinsics are considered to have side-effects in their tablegen
576// definition because they are referenced in the global registry. This is a list
577// of intrinsics that have no side effects other than their references in the
578// global registry.
579static bool intrinsicHasSideEffects(Intrinsic::ID ID) {
580 switch (ID) {
581 // This is not an exhaustive list and may need to be updated.
582 case Intrinsic::spv_all:
583 case Intrinsic::spv_alloca:
584 case Intrinsic::spv_any:
585 case Intrinsic::spv_bitcast:
586 case Intrinsic::spv_const_composite:
587 case Intrinsic::spv_cross:
588 case Intrinsic::spv_degrees:
589 case Intrinsic::spv_distance:
590 case Intrinsic::spv_extractelt:
591 case Intrinsic::spv_extractv:
592 case Intrinsic::spv_faceforward:
593 case Intrinsic::spv_fdot:
594 case Intrinsic::spv_firstbitlow:
595 case Intrinsic::spv_firstbitshigh:
596 case Intrinsic::spv_firstbituhigh:
597 case Intrinsic::spv_frac:
598 case Intrinsic::spv_gep:
599 case Intrinsic::spv_global_offset:
600 case Intrinsic::spv_global_size:
601 case Intrinsic::spv_group_id:
602 case Intrinsic::spv_insertelt:
603 case Intrinsic::spv_insertv:
604 case Intrinsic::spv_isinf:
605 case Intrinsic::spv_isnan:
606 case Intrinsic::spv_lerp:
607 case Intrinsic::spv_length:
608 case Intrinsic::spv_normalize:
609 case Intrinsic::spv_num_subgroups:
610 case Intrinsic::spv_num_workgroups:
611 case Intrinsic::spv_ptrcast:
612 case Intrinsic::spv_radians:
613 case Intrinsic::spv_reflect:
614 case Intrinsic::spv_refract:
615 case Intrinsic::spv_resource_getpointer:
616 case Intrinsic::spv_resource_handlefrombinding:
617 case Intrinsic::spv_resource_handlefromimplicitbinding:
618 case Intrinsic::spv_resource_nonuniformindex:
619 case Intrinsic::spv_resource_sample:
620 case Intrinsic::spv_rsqrt:
621 case Intrinsic::spv_saturate:
622 case Intrinsic::spv_sdot:
623 case Intrinsic::spv_sign:
624 case Intrinsic::spv_smoothstep:
625 case Intrinsic::spv_step:
626 case Intrinsic::spv_subgroup_id:
627 case Intrinsic::spv_subgroup_local_invocation_id:
628 case Intrinsic::spv_subgroup_max_size:
629 case Intrinsic::spv_subgroup_size:
630 case Intrinsic::spv_thread_id:
631 case Intrinsic::spv_thread_id_in_group:
632 case Intrinsic::spv_udot:
633 case Intrinsic::spv_undef:
634 case Intrinsic::spv_value_md:
635 case Intrinsic::spv_workgroup_size:
636 return false;
637 default:
638 return true;
639 }
640}
641
642// TODO(168736): We should make this either a flag in tabelgen
643// or reduce our dependence on the global registry, so we can remove this
644// function. It can easily be missed when new intrinsics are added.
645static bool isOpcodeWithNoSideEffects(unsigned Opcode) {
646 switch (Opcode) {
647 case SPIRV::OpTypeVoid:
648 case SPIRV::OpTypeBool:
649 case SPIRV::OpTypeInt:
650 case SPIRV::OpTypeFloat:
651 case SPIRV::OpTypeVector:
652 case SPIRV::OpTypeMatrix:
653 case SPIRV::OpTypeImage:
654 case SPIRV::OpTypeSampler:
655 case SPIRV::OpTypeSampledImage:
656 case SPIRV::OpTypeArray:
657 case SPIRV::OpTypeRuntimeArray:
658 case SPIRV::OpTypeStruct:
659 case SPIRV::OpTypeOpaque:
660 case SPIRV::OpTypePointer:
661 case SPIRV::OpTypeFunction:
662 case SPIRV::OpTypeEvent:
663 case SPIRV::OpTypeDeviceEvent:
664 case SPIRV::OpTypeReserveId:
665 case SPIRV::OpTypeQueue:
666 case SPIRV::OpTypePipe:
667 case SPIRV::OpTypeForwardPointer:
668 case SPIRV::OpTypePipeStorage:
669 case SPIRV::OpTypeNamedBarrier:
670 case SPIRV::OpTypeAccelerationStructureNV:
671 case SPIRV::OpTypeCooperativeMatrixNV:
672 case SPIRV::OpTypeCooperativeMatrixKHR:
673 return true;
674 default:
675 return false;
676 }
677}
678
679bool isDead(const MachineInstr &MI, const MachineRegisterInfo &MRI) {
680 // If there are no definitions, then assume there is some other
681 // side-effect that makes this instruction live.
682 if (MI.getNumDefs() == 0)
683 return false;
684
685 for (const auto &MO : MI.all_defs()) {
686 Register Reg = MO.getReg();
687 if (Reg.isPhysical()) {
688 LLVM_DEBUG(dbgs() << "Not dead: def of physical register " << Reg);
689 return false;
690 }
691 for (const auto &UseMI : MRI.use_nodbg_instructions(Reg)) {
692 if (UseMI.getOpcode() != SPIRV::OpName) {
693 LLVM_DEBUG(dbgs() << "Not dead: def " << MO << " has use in " << UseMI);
694 return false;
695 }
696 }
697 }
698
699 if (MI.getOpcode() == TargetOpcode::LOCAL_ESCAPE || MI.isFakeUse() ||
700 MI.isLifetimeMarker()) {
701 LLVM_DEBUG(
702 dbgs()
703 << "Not dead: Opcode is LOCAL_ESCAPE, fake use, or lifetime marker.\n");
704 return false;
705 }
706 if (MI.isPHI()) {
707 LLVM_DEBUG(dbgs() << "Dead: Phi instruction with no uses.\n");
708 return true;
709 }
710
711 // It is possible that the only side effect is that the instruction is
712 // referenced in the global registry. If that is the only side effect, the
713 // intrinsic is dead.
714 if (MI.getOpcode() == TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS ||
715 MI.getOpcode() == TargetOpcode::G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS) {
716 const auto &Intr = cast<GIntrinsic>(MI);
717 if (!intrinsicHasSideEffects(Intr.getIntrinsicID())) {
718 LLVM_DEBUG(dbgs() << "Dead: Intrinsic with no real side effects.\n");
719 return true;
720 }
721 }
722
723 if (MI.mayStore() || MI.isCall() ||
724 (MI.mayLoad() && MI.hasOrderedMemoryRef()) || MI.isPosition() ||
725 MI.isDebugInstr() || MI.isTerminator() || MI.isJumpTableDebugInfo()) {
726 LLVM_DEBUG(dbgs() << "Not dead: instruction has side effects.\n");
727 return false;
728 }
729
730 if (isPreISelGenericOpcode(MI.getOpcode())) {
731 // TODO: Is there a generic way to check if the opcode has side effects?
732 LLVM_DEBUG(dbgs() << "Dead: Generic opcode with no uses.\n");
733 return true;
734 }
735
736 if (isOpcodeWithNoSideEffects(MI.getOpcode())) {
737 LLVM_DEBUG(dbgs() << "Dead: known opcode with no side effects\n");
738 return true;
739 }
740
741 return false;
742}
743
744void SPIRVInstructionSelector::removeOpNamesForDeadMI(MachineInstr &MI) const {
745 // Delete the OpName that uses the result if there is one.
746 for (const auto &MO : MI.all_defs()) {
747 Register Reg = MO.getReg();
748 if (Reg.isPhysical())
749 continue;
750 SmallVector<MachineInstr *, 4> UselessOpNames;
751 for (MachineInstr &UseMI : MRI->use_nodbg_instructions(Reg)) {
752 assert(UseMI.getOpcode() == SPIRV::OpName &&
753 "There is still a use of the dead function.");
754 UselessOpNames.push_back(&UseMI);
755 }
756 for (MachineInstr *OpNameMI : UselessOpNames) {
757 GR.invalidateMachineInstr(OpNameMI);
758 OpNameMI->eraseFromParent();
759 }
760 }
761}
762
763void SPIRVInstructionSelector::removeDeadInstruction(MachineInstr &MI) const {
764 salvageDebugInfo(*MRI, MI);
765 GR.invalidateMachineInstr(&MI);
766 removeOpNamesForDeadMI(MI);
767 MI.eraseFromParent();
768}
769
770bool SPIRVInstructionSelector::select(MachineInstr &I) {
771 resetVRegsType(*I.getParent()->getParent());
772
773 assert(I.getParent() && "Instruction should be in a basic block!");
774 assert(I.getParent()->getParent() && "Instruction should be in a function!");
775
776 LLVM_DEBUG(dbgs() << "Checking if instruction is dead: " << I;);
777 if (isDead(I, *MRI)) {
778 LLVM_DEBUG(dbgs() << "Instruction is dead.\n");
779 removeDeadInstruction(I);
780 return true;
781 }
782
783 Register Opcode = I.getOpcode();
784 // If it's not a GMIR instruction, we've selected it already.
785 if (!isPreISelGenericOpcode(Opcode)) {
786 if (Opcode == SPIRV::ASSIGN_TYPE) { // These pseudos aren't needed any more.
787 Register DstReg = I.getOperand(0).getReg();
788 Register SrcReg = I.getOperand(1).getReg();
789 auto *Def = MRI->getVRegDef(SrcReg);
790 if (isTypeFoldingSupported(Def->getOpcode()) &&
791 Def->getOpcode() != TargetOpcode::G_CONSTANT &&
792 Def->getOpcode() != TargetOpcode::G_FCONSTANT) {
793 bool Res = false;
794 if (Def->getOpcode() == TargetOpcode::G_SELECT) {
795 Register SelectDstReg = Def->getOperand(0).getReg();
796 Res = selectSelect(SelectDstReg, GR.getSPIRVTypeForVReg(SelectDstReg),
797 *Def);
798 GR.invalidateMachineInstr(Def);
799 Def->removeFromParent();
800 MRI->replaceRegWith(DstReg, SelectDstReg);
801 GR.invalidateMachineInstr(&I);
802 I.removeFromParent();
803 } else
804 Res = selectImpl(I, *CoverageInfo);
805 LLVM_DEBUG({
806 if (!Res && Def->getOpcode() != TargetOpcode::G_CONSTANT) {
807 dbgs() << "Unexpected pattern in ASSIGN_TYPE.\nInstruction: ";
808 I.print(dbgs());
809 }
810 });
811 assert(Res || Def->getOpcode() == TargetOpcode::G_CONSTANT);
812 if (Res) {
813 if (!isTriviallyDead(*Def, *MRI) && isDead(*Def, *MRI))
814 DeadMIs.insert(Def);
815 return Res;
816 }
817 }
818 MRI->setRegClass(SrcReg, MRI->getRegClass(DstReg));
819 MRI->replaceRegWith(SrcReg, DstReg);
820 GR.invalidateMachineInstr(&I);
821 I.removeFromParent();
822 return true;
823 } else if (I.getNumDefs() == 1) {
824 // Make all vregs 64 bits (for SPIR-V IDs).
825 MRI->setType(I.getOperand(0).getReg(), LLT::scalar(64));
826 }
827 constrainSelectedInstRegOperands(I, TII, TRI, RBI);
828 return true;
829 }
830
831 if (DeadMIs.contains(&I)) {
832 // if the instruction has been already made dead by folding it away
833 // erase it
834 LLVM_DEBUG(dbgs() << "Instruction is folded and dead.\n");
835 removeDeadInstruction(I);
836 return true;
837 }
838
839 if (I.getNumOperands() != I.getNumExplicitOperands()) {
840 LLVM_DEBUG(errs() << "Generic instr has unexpected implicit operands\n");
841 return false;
842 }
843
844 // Common code for getting return reg+type, and removing selected instr
845 // from parent occurs here. Instr-specific selection happens in spvSelect().
846 bool HasDefs = I.getNumDefs() > 0;
847 Register ResVReg = HasDefs ? I.getOperand(0).getReg() : Register(0);
848 SPIRVTypeInst ResType = HasDefs ? GR.getSPIRVTypeForVReg(ResVReg) : nullptr;
849 assert(!HasDefs || ResType || I.getOpcode() == TargetOpcode::G_GLOBAL_VALUE ||
850 I.getOpcode() == TargetOpcode::G_IMPLICIT_DEF);
851 if (spvSelect(ResVReg, ResType, I)) {
852 if (HasDefs) // Make all vregs 64 bits (for SPIR-V IDs).
853 for (unsigned i = 0; i < I.getNumDefs(); ++i)
854 MRI->setType(I.getOperand(i).getReg(), LLT::scalar(64));
855 GR.invalidateMachineInstr(&I);
856 I.eraseFromParent();
857 return true;
858 }
859 return false;
860}
861
862static bool mayApplyGenericSelection(unsigned Opcode) {
863 switch (Opcode) {
864 case TargetOpcode::G_CONSTANT:
865 case TargetOpcode::G_FCONSTANT:
866 return false;
867 case TargetOpcode::G_SADDO:
868 case TargetOpcode::G_SSUBO:
869 return true;
870 }
871 return isTypeFoldingSupported(Opcode);
872}
873
874bool SPIRVInstructionSelector::BuildCOPY(Register DestReg, Register SrcReg,
875 MachineInstr &I) const {
876 const TargetRegisterClass *DstRC = MRI->getRegClassOrNull(DestReg);
877 const TargetRegisterClass *SrcRC = MRI->getRegClassOrNull(SrcReg);
878 if (DstRC != SrcRC && SrcRC)
879 MRI->setRegClass(DestReg, SrcRC);
880 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(TargetOpcode::COPY))
881 .addDef(DestReg)
882 .addUse(SrcReg)
883 .constrainAllUses(TII, TRI, RBI);
884 return true;
885}
886
887bool SPIRVInstructionSelector::spvSelect(Register ResVReg,
888 SPIRVTypeInst ResType,
889 MachineInstr &I) const {
890 const unsigned Opcode = I.getOpcode();
891 if (mayApplyGenericSelection(Opcode))
892 return selectImpl(I, *CoverageInfo);
893 switch (Opcode) {
894 case TargetOpcode::G_CONSTANT:
895 case TargetOpcode::G_FCONSTANT:
896 return selectConst(ResVReg, ResType, I);
897 case TargetOpcode::G_GLOBAL_VALUE:
898 return selectGlobalValue(ResVReg, I);
899 case TargetOpcode::G_IMPLICIT_DEF:
900 return selectOpUndef(ResVReg, ResType, I);
901 case TargetOpcode::G_FREEZE:
902 return selectFreeze(ResVReg, ResType, I);
903
904 case TargetOpcode::G_INTRINSIC:
905 case TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS:
906 case TargetOpcode::G_INTRINSIC_CONVERGENT:
907 case TargetOpcode::G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS:
908 return selectIntrinsic(ResVReg, ResType, I);
909 case TargetOpcode::G_BITREVERSE:
910 return selectBitreverse(ResVReg, ResType, I);
911
912 case TargetOpcode::G_BUILD_VECTOR:
913 return selectBuildVector(ResVReg, ResType, I);
914 case TargetOpcode::G_SPLAT_VECTOR:
915 return selectSplatVector(ResVReg, ResType, I);
916
917 case TargetOpcode::G_SHUFFLE_VECTOR: {
918 MachineBasicBlock &BB = *I.getParent();
919 auto MIB = BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpVectorShuffle))
920 .addDef(ResVReg)
921 .addUse(GR.getSPIRVTypeID(ResType))
922 .addUse(I.getOperand(1).getReg())
923 .addUse(I.getOperand(2).getReg());
924 for (auto V : I.getOperand(3).getShuffleMask())
925 MIB.addImm(V);
926 MIB.constrainAllUses(TII, TRI, RBI);
927 return true;
928 }
929 case TargetOpcode::G_MEMMOVE:
930 case TargetOpcode::G_MEMCPY:
931 case TargetOpcode::G_MEMSET:
932 return selectMemOperation(ResVReg, I);
933
934 case TargetOpcode::G_ICMP:
935 return selectICmp(ResVReg, ResType, I);
936 case TargetOpcode::G_FCMP:
937 return selectFCmp(ResVReg, ResType, I);
938
939 case TargetOpcode::G_FRAME_INDEX:
940 return selectFrameIndex(ResVReg, ResType, I);
941
942 case TargetOpcode::G_LOAD:
943 return selectLoad(ResVReg, ResType, I);
944 case TargetOpcode::G_STORE:
945 return selectStore(I);
946
947 case TargetOpcode::G_BR:
948 return selectBranch(I);
949 case TargetOpcode::G_BRCOND:
950 return selectBranchCond(I);
951
952 case TargetOpcode::G_PHI:
953 return selectPhi(ResVReg, I);
954
955 case TargetOpcode::G_FPTOSI:
956 return selectUnOp(ResVReg, ResType, I, SPIRV::OpConvertFToS);
957 case TargetOpcode::G_FPTOUI:
958 return selectUnOp(ResVReg, ResType, I, SPIRV::OpConvertFToU);
959
960 case TargetOpcode::G_FPTOSI_SAT:
961 return selectUnOp(ResVReg, ResType, I, SPIRV::OpConvertFToS);
962 case TargetOpcode::G_FPTOUI_SAT:
963 return selectUnOp(ResVReg, ResType, I, SPIRV::OpConvertFToU);
964
965 case TargetOpcode::G_SITOFP:
966 return selectIToF(ResVReg, ResType, I, true, SPIRV::OpConvertSToF);
967 case TargetOpcode::G_UITOFP:
968 return selectIToF(ResVReg, ResType, I, false, SPIRV::OpConvertUToF);
969
970 case TargetOpcode::G_CTPOP:
971 return selectUnOp(ResVReg, ResType, I, SPIRV::OpBitCount);
972 case TargetOpcode::G_SMIN:
973 return selectExtInst(ResVReg, ResType, I, CL::s_min, GL::SMin);
974 case TargetOpcode::G_UMIN:
975 return selectExtInst(ResVReg, ResType, I, CL::u_min, GL::UMin);
976
977 case TargetOpcode::G_SMAX:
978 return selectExtInst(ResVReg, ResType, I, CL::s_max, GL::SMax);
979 case TargetOpcode::G_UMAX:
980 return selectExtInst(ResVReg, ResType, I, CL::u_max, GL::UMax);
981
982 case TargetOpcode::G_SCMP:
983 return selectSUCmp(ResVReg, ResType, I, true);
984 case TargetOpcode::G_UCMP:
985 return selectSUCmp(ResVReg, ResType, I, false);
986 case TargetOpcode::G_LROUND:
987 case TargetOpcode::G_LLROUND: {
988 Register regForLround =
989 MRI->createVirtualRegister(MRI->getRegClass(ResVReg), "lround");
990 MRI->setRegClass(regForLround, &SPIRV::iIDRegClass);
991 GR.assignSPIRVTypeToVReg(GR.getSPIRVTypeForVReg(I.getOperand(1).getReg()),
992 regForLround, *(I.getParent()->getParent()));
993 selectExtInst(regForLround, GR.getSPIRVTypeForVReg(regForLround), I,
994 CL::round, GL::Round, /* setMIFlags */ false);
995 MachineBasicBlock &BB = *I.getParent();
996 auto MIB = BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpConvertFToS))
997 .addDef(ResVReg)
998 .addUse(GR.getSPIRVTypeID(ResType))
999 .addUse(regForLround);
1000 MIB.constrainAllUses(TII, TRI, RBI);
1001 return true;
1002 }
1003 case TargetOpcode::G_STRICT_FMA:
1004 case TargetOpcode::G_FMA: {
1005 if (STI.canUseExtension(SPIRV::Extension::SPV_KHR_fma)) {
1006 MachineBasicBlock &BB = *I.getParent();
1007 auto MIB = BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpFmaKHR))
1008 .addDef(ResVReg)
1009 .addUse(GR.getSPIRVTypeID(ResType))
1010 .addUse(I.getOperand(1).getReg())
1011 .addUse(I.getOperand(2).getReg())
1012 .addUse(I.getOperand(3).getReg())
1013 .setMIFlags(I.getFlags());
1014 MIB.constrainAllUses(TII, TRI, RBI);
1015 return true;
1016 }
1017 return selectExtInst(ResVReg, ResType, I, CL::fma, GL::Fma);
1018 }
1019
1020 case TargetOpcode::G_STRICT_FLDEXP:
1021 return selectExtInst(ResVReg, ResType, I, CL::ldexp);
1022
1023 case TargetOpcode::G_FPOW:
1024 return selectExtInst(ResVReg, ResType, I, CL::pow, GL::Pow);
1025 case TargetOpcode::G_FPOWI:
1026 return selectExtInst(ResVReg, ResType, I, CL::pown);
1027
1028 case TargetOpcode::G_FEXP:
1029 return selectExtInst(ResVReg, ResType, I, CL::exp, GL::Exp);
1030 case TargetOpcode::G_FEXP2:
1031 return selectExtInst(ResVReg, ResType, I, CL::exp2, GL::Exp2);
1032 case TargetOpcode::G_FEXP10:
1033 return selectExp10(ResVReg, ResType, I);
1034
1035 case TargetOpcode::G_FMODF:
1036 return selectModf(ResVReg, ResType, I);
1037 case TargetOpcode::G_FSINCOS:
1038 return selectSincos(ResVReg, ResType, I);
1039
1040 case TargetOpcode::G_FLOG:
1041 return selectExtInst(ResVReg, ResType, I, CL::log, GL::Log);
1042 case TargetOpcode::G_FLOG2:
1043 return selectExtInst(ResVReg, ResType, I, CL::log2, GL::Log2);
1044 case TargetOpcode::G_FLOG10:
1045 return selectLog10(ResVReg, ResType, I);
1046
1047 case TargetOpcode::G_FABS:
1048 return selectExtInst(ResVReg, ResType, I, CL::fabs, GL::FAbs);
1049 case TargetOpcode::G_ABS:
1050 return selectExtInst(ResVReg, ResType, I, CL::s_abs, GL::SAbs);
1051
1052 case TargetOpcode::G_FMINNUM:
1053 case TargetOpcode::G_FMINIMUM:
1054 return selectExtInst(ResVReg, ResType, I, CL::fmin, GL::NMin);
1055 case TargetOpcode::G_FMAXNUM:
1056 case TargetOpcode::G_FMAXIMUM:
1057 return selectExtInst(ResVReg, ResType, I, CL::fmax, GL::NMax);
1058
1059 case TargetOpcode::G_FCOPYSIGN:
1060 return selectExtInst(ResVReg, ResType, I, CL::copysign);
1061
1062 case TargetOpcode::G_FCEIL:
1063 return selectExtInst(ResVReg, ResType, I, CL::ceil, GL::Ceil);
1064 case TargetOpcode::G_FFLOOR:
1065 return selectExtInst(ResVReg, ResType, I, CL::floor, GL::Floor);
1066
1067 case TargetOpcode::G_FCOS:
1068 return selectExtInst(ResVReg, ResType, I, CL::cos, GL::Cos);
1069 case TargetOpcode::G_FSIN:
1070 return selectExtInst(ResVReg, ResType, I, CL::sin, GL::Sin);
1071 case TargetOpcode::G_FTAN:
1072 return selectExtInst(ResVReg, ResType, I, CL::tan, GL::Tan);
1073 case TargetOpcode::G_FACOS:
1074 return selectExtInst(ResVReg, ResType, I, CL::acos, GL::Acos);
1075 case TargetOpcode::G_FASIN:
1076 return selectExtInst(ResVReg, ResType, I, CL::asin, GL::Asin);
1077 case TargetOpcode::G_FATAN:
1078 return selectExtInst(ResVReg, ResType, I, CL::atan, GL::Atan);
1079 case TargetOpcode::G_FATAN2:
1080 return selectExtInst(ResVReg, ResType, I, CL::atan2, GL::Atan2);
1081 case TargetOpcode::G_FCOSH:
1082 return selectExtInst(ResVReg, ResType, I, CL::cosh, GL::Cosh);
1083 case TargetOpcode::G_FSINH:
1084 return selectExtInst(ResVReg, ResType, I, CL::sinh, GL::Sinh);
1085 case TargetOpcode::G_FTANH:
1086 return selectExtInst(ResVReg, ResType, I, CL::tanh, GL::Tanh);
1087
1088 case TargetOpcode::G_STRICT_FSQRT:
1089 case TargetOpcode::G_FSQRT:
1090 return selectExtInst(ResVReg, ResType, I, CL::sqrt, GL::Sqrt);
1091
1092 case TargetOpcode::G_CTTZ:
1093 case TargetOpcode::G_CTTZ_ZERO_UNDEF:
1094 return selectExtInst(ResVReg, ResType, I, CL::ctz);
1095 case TargetOpcode::G_CTLZ:
1096 case TargetOpcode::G_CTLZ_ZERO_UNDEF:
1097 return selectExtInst(ResVReg, ResType, I, CL::clz);
1098
1099 case TargetOpcode::G_INTRINSIC_ROUND:
1100 return selectExtInst(ResVReg, ResType, I, CL::round, GL::Round);
1101 case TargetOpcode::G_INTRINSIC_ROUNDEVEN:
1102 return selectExtInst(ResVReg, ResType, I, CL::rint, GL::RoundEven);
1103 case TargetOpcode::G_INTRINSIC_TRUNC:
1104 return selectExtInst(ResVReg, ResType, I, CL::trunc, GL::Trunc);
1105 case TargetOpcode::G_FRINT:
1106 case TargetOpcode::G_FNEARBYINT:
1107 return selectExtInst(ResVReg, ResType, I, CL::rint, GL::RoundEven);
1108
1109 case TargetOpcode::G_SMULH:
1110 return selectExtInst(ResVReg, ResType, I, CL::s_mul_hi);
1111 case TargetOpcode::G_UMULH:
1112 return selectExtInst(ResVReg, ResType, I, CL::u_mul_hi);
1113
1114 case TargetOpcode::G_SADDSAT:
1115 return selectExtInst(ResVReg, ResType, I, CL::s_add_sat);
1116 case TargetOpcode::G_UADDSAT:
1117 return selectExtInst(ResVReg, ResType, I, CL::u_add_sat);
1118 case TargetOpcode::G_SSUBSAT:
1119 return selectExtInst(ResVReg, ResType, I, CL::s_sub_sat);
1120 case TargetOpcode::G_USUBSAT:
1121 return selectExtInst(ResVReg, ResType, I, CL::u_sub_sat);
1122
1123 case TargetOpcode::G_FFREXP:
1124 return selectFrexp(ResVReg, ResType, I);
1125
1126 case TargetOpcode::G_UADDO:
1127 return selectOverflowArith(ResVReg, ResType, I,
1128 ResType->getOpcode() == SPIRV::OpTypeVector
1129 ? SPIRV::OpIAddCarryV
1130 : SPIRV::OpIAddCarryS);
1131 case TargetOpcode::G_USUBO:
1132 return selectOverflowArith(ResVReg, ResType, I,
1133 ResType->getOpcode() == SPIRV::OpTypeVector
1134 ? SPIRV::OpISubBorrowV
1135 : SPIRV::OpISubBorrowS);
1136 case TargetOpcode::G_UMULO:
1137 return selectOverflowArith(ResVReg, ResType, I, SPIRV::OpUMulExtended);
1138 case TargetOpcode::G_SMULO:
1139 return selectOverflowArith(ResVReg, ResType, I, SPIRV::OpSMulExtended);
1140
1141 case TargetOpcode::G_SEXT:
1142 return selectExt(ResVReg, ResType, I, true);
1143 case TargetOpcode::G_ANYEXT:
1144 case TargetOpcode::G_ZEXT:
1145 return selectExt(ResVReg, ResType, I, false);
1146 case TargetOpcode::G_TRUNC:
1147 return selectTrunc(ResVReg, ResType, I);
1148 case TargetOpcode::G_FPTRUNC:
1149 case TargetOpcode::G_FPEXT:
1150 return selectUnOp(ResVReg, ResType, I, SPIRV::OpFConvert);
1151
1152 case TargetOpcode::G_PTRTOINT:
1153 return selectUnOp(ResVReg, ResType, I, SPIRV::OpConvertPtrToU);
1154 case TargetOpcode::G_INTTOPTR:
1155 return selectUnOp(ResVReg, ResType, I, SPIRV::OpConvertUToPtr);
1156 case TargetOpcode::G_BITCAST:
1157 return selectBitcast(ResVReg, ResType, I);
1158 case TargetOpcode::G_ADDRSPACE_CAST:
1159 return selectAddrSpaceCast(ResVReg, ResType, I);
1160 case TargetOpcode::G_PTR_ADD: {
1161 // Currently, we get G_PTR_ADD only applied to global variables.
1162 assert(I.getOperand(1).isReg() && I.getOperand(2).isReg());
1163 Register GV = I.getOperand(1).getReg();
1164 MachineRegisterInfo::def_instr_iterator II = MRI->def_instr_begin(GV);
1165 (void)II;
1166 assert(((*II).getOpcode() == TargetOpcode::G_GLOBAL_VALUE ||
1167 (*II).getOpcode() == TargetOpcode::COPY ||
1168 (*II).getOpcode() == SPIRV::OpVariable) &&
1169 getImm(I.getOperand(2), MRI));
1170 // It may be the initialization of a global variable.
1171 bool IsGVInit = false;
1172 for (MachineRegisterInfo::use_instr_iterator
1173 UseIt = MRI->use_instr_begin(I.getOperand(0).getReg()),
1174 UseEnd = MRI->use_instr_end();
1175 UseIt != UseEnd; UseIt = std::next(UseIt)) {
1176 if ((*UseIt).getOpcode() == TargetOpcode::G_GLOBAL_VALUE ||
1177 (*UseIt).getOpcode() == SPIRV::OpSpecConstantOp ||
1178 (*UseIt).getOpcode() == SPIRV::OpVariable) {
1179 IsGVInit = true;
1180 break;
1181 }
1182 }
1183 MachineBasicBlock &BB = *I.getParent();
1184 if (!IsGVInit) {
1185 SPIRVTypeInst GVType = GR.getSPIRVTypeForVReg(GV);
1186 SPIRVTypeInst GVPointeeType = GR.getPointeeType(GVType);
1187 SPIRVTypeInst ResPointeeType = GR.getPointeeType(ResType);
1188 if (GVPointeeType && ResPointeeType && GVPointeeType != ResPointeeType) {
1189 // Build a new virtual register that is associated with the required
1190 // data type.
1191 Register NewVReg = MRI->createGenericVirtualRegister(MRI->getType(GV));
1192 MRI->setRegClass(NewVReg, MRI->getRegClass(GV));
1193 // Having a correctly typed base we are ready to build the actually
1194 // required GEP. It may not be a constant though, because all Operands
1195 // of OpSpecConstantOp is to originate from other const instructions,
1196 // and only the AccessChain named opcodes accept a global OpVariable
1197 // instruction. We can't use an AccessChain opcode because of the type
1198 // mismatch between result and base types.
1199 if (!GR.isBitcastCompatible(ResType, GVType))
1200 report_fatal_error(
1201 "incompatible result and operand types in a bitcast");
1202 Register ResTypeReg = GR.getSPIRVTypeID(ResType);
1203 MachineInstrBuilder MIB =
1204 BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpBitcast))
1205 .addDef(NewVReg)
1206 .addUse(ResTypeReg)
1207 .addUse(GV);
1208 MIB.constrainAllUses(TII, TRI, RBI);
1209 BuildMI(BB, I, I.getDebugLoc(),
1210 TII.get(STI.isLogicalSPIRV() ? SPIRV::OpInBoundsAccessChain
1211 : SPIRV::OpInBoundsPtrAccessChain))
1212 .addDef(ResVReg)
1213 .addUse(ResTypeReg)
1214 .addUse(NewVReg)
1215 .addUse(I.getOperand(2).getReg())
1216 .constrainAllUses(TII, TRI, RBI);
1217 } else {
1218 BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpSpecConstantOp))
1219 .addDef(ResVReg)
1220 .addUse(GR.getSPIRVTypeID(ResType))
1221 .addImm(
1222 static_cast<uint32_t>(SPIRV::Opcode::InBoundsPtrAccessChain))
1223 .addUse(GV)
1224 .addUse(I.getOperand(2).getReg())
1225 .constrainAllUses(TII, TRI, RBI);
1226 }
1227 return true;
1228 }
1229 // It's possible to translate G_PTR_ADD to OpSpecConstantOp: either to
1230 // initialize a global variable with a constant expression (e.g., the test
1231 // case opencl/basic/progvar_prog_scope_init.ll), or for another use case
1232 Register Idx = buildZerosVal(GR.getOrCreateSPIRVIntegerType(32, I, TII), I);
1233 auto MIB = BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpSpecConstantOp))
1234 .addDef(ResVReg)
1235 .addUse(GR.getSPIRVTypeID(ResType))
1236 .addImm(static_cast<uint32_t>(
1237 SPIRV::Opcode::InBoundsPtrAccessChain))
1238 .addUse(GV)
1239 .addUse(Idx)
1240 .addUse(I.getOperand(2).getReg());
1241 MIB.constrainAllUses(TII, TRI, RBI);
1242 return true;
1243 }
1244
1245 case TargetOpcode::G_ATOMICRMW_OR:
1246 return selectAtomicRMW(ResVReg, ResType, I, SPIRV::OpAtomicOr);
1247 case TargetOpcode::G_ATOMICRMW_ADD:
1248 return selectAtomicRMW(ResVReg, ResType, I, SPIRV::OpAtomicIAdd);
1249 case TargetOpcode::G_ATOMICRMW_AND:
1250 return selectAtomicRMW(ResVReg, ResType, I, SPIRV::OpAtomicAnd);
1251 case TargetOpcode::G_ATOMICRMW_MAX:
1252 return selectAtomicRMW(ResVReg, ResType, I, SPIRV::OpAtomicSMax);
1253 case TargetOpcode::G_ATOMICRMW_MIN:
1254 return selectAtomicRMW(ResVReg, ResType, I, SPIRV::OpAtomicSMin);
1255 case TargetOpcode::G_ATOMICRMW_SUB:
1256 return selectAtomicRMW(ResVReg, ResType, I, SPIRV::OpAtomicISub);
1257 case TargetOpcode::G_ATOMICRMW_XOR:
1258 return selectAtomicRMW(ResVReg, ResType, I, SPIRV::OpAtomicXor);
1259 case TargetOpcode::G_ATOMICRMW_UMAX:
1260 return selectAtomicRMW(ResVReg, ResType, I, SPIRV::OpAtomicUMax);
1261 case TargetOpcode::G_ATOMICRMW_UMIN:
1262 return selectAtomicRMW(ResVReg, ResType, I, SPIRV::OpAtomicUMin);
1263 case TargetOpcode::G_ATOMICRMW_XCHG:
1264 return selectAtomicRMW(ResVReg, ResType, I, SPIRV::OpAtomicExchange);
1265 case TargetOpcode::G_ATOMIC_CMPXCHG:
1266 return selectAtomicCmpXchg(ResVReg, ResType, I);
1267
1268 case TargetOpcode::G_ATOMICRMW_FADD:
1269 return selectAtomicRMW(ResVReg, ResType, I, SPIRV::OpAtomicFAddEXT);
1270 case TargetOpcode::G_ATOMICRMW_FSUB:
1271 // Translate G_ATOMICRMW_FSUB to OpAtomicFAddEXT with negative value operand
1272 return selectAtomicRMW(ResVReg, ResType, I, SPIRV::OpAtomicFAddEXT,
1273 ResType->getOpcode() == SPIRV::OpTypeVector
1274 ? SPIRV::OpFNegateV
1275 : SPIRV::OpFNegate);
1276 case TargetOpcode::G_ATOMICRMW_FMIN:
1277 return selectAtomicRMW(ResVReg, ResType, I, SPIRV::OpAtomicFMinEXT);
1278 case TargetOpcode::G_ATOMICRMW_FMAX:
1279 return selectAtomicRMW(ResVReg, ResType, I, SPIRV::OpAtomicFMaxEXT);
1280
1281 case TargetOpcode::G_FENCE:
1282 return selectFence(I);
1283
1284 case TargetOpcode::G_STACKSAVE:
1285 return selectStackSave(ResVReg, ResType, I);
1286 case TargetOpcode::G_STACKRESTORE:
1287 return selectStackRestore(I);
1288
1289 case TargetOpcode::G_UNMERGE_VALUES:
1290 return selectUnmergeValues(I);
1291
1292 // Discard gen opcodes for intrinsics which we do not expect to actually
1293 // represent code after lowering or intrinsics which are not implemented but
1294 // should not crash when found in a customer's LLVM IR input.
1295 case TargetOpcode::G_TRAP:
1296 case TargetOpcode::G_UBSANTRAP:
1297 case TargetOpcode::DBG_LABEL:
1298 return true;
1299 case TargetOpcode::G_DEBUGTRAP:
1300 return selectDebugTrap(ResVReg, ResType, I);
1301
1302 default:
1303 return false;
1304 }
1305}
1306
1307bool SPIRVInstructionSelector::selectDebugTrap(Register ResVReg,
1308 SPIRVTypeInst ResType,
1309 MachineInstr &I) const {
1310 unsigned Opcode = SPIRV::OpNop;
1311 MachineBasicBlock &BB = *I.getParent();
1312 BuildMI(BB, I, I.getDebugLoc(), TII.get(Opcode))
1313 .constrainAllUses(TII, TRI, RBI);
1314 return true;
1315}
1316
1317bool SPIRVInstructionSelector::selectExtInst(Register ResVReg,
1318 SPIRVTypeInst ResType,
1319 MachineInstr &I,
1320 GL::GLSLExtInst GLInst,
1321 bool setMIFlags, bool useMISrc,
1322 ArrayRef<Register> SrcRegs) const {
1323 if (!STI.canUseExtInstSet(
1324 SPIRV::InstructionSet::InstructionSet::GLSL_std_450)) {
1325 std::string DiagMsg;
1326 raw_string_ostream OS(DiagMsg);
1327 I.print(OS, true, false, false, false);
1328 DiagMsg += " is only supported with the GLSL extended instruction set.\n";
1329 report_fatal_error(DiagMsg.c_str(), false);
1330 }
1331 return selectExtInst(ResVReg, ResType, I,
1332 {{SPIRV::InstructionSet::GLSL_std_450, GLInst}},
1333 setMIFlags, useMISrc, SrcRegs);
1334}
1335
1336bool SPIRVInstructionSelector::selectExtInst(Register ResVReg,
1337 SPIRVTypeInst ResType,
1338 MachineInstr &I,
1339 CL::OpenCLExtInst CLInst,
1340 bool setMIFlags, bool useMISrc,
1341 ArrayRef<Register> SrcRegs) const {
1342 return selectExtInst(ResVReg, ResType, I,
1343 {{SPIRV::InstructionSet::OpenCL_std, CLInst}},
1344 setMIFlags, useMISrc, SrcRegs);
1345}
1346
1347bool SPIRVInstructionSelector::selectExtInst(
1348 Register ResVReg, SPIRVTypeInst ResType, MachineInstr &I,
1349 CL::OpenCLExtInst CLInst, GL::GLSLExtInst GLInst, bool setMIFlags,
1350 bool useMISrc, ArrayRef<Register> SrcRegs) const {
1351 ExtInstList ExtInsts = {{SPIRV::InstructionSet::OpenCL_std, CLInst},
1352 {SPIRV::InstructionSet::GLSL_std_450, GLInst}};
1353 return selectExtInst(ResVReg, ResType, I, ExtInsts, setMIFlags, useMISrc,
1354 SrcRegs);
1355}
1356
1357bool SPIRVInstructionSelector::selectExtInst(Register ResVReg,
1358 SPIRVTypeInst ResType,
1359 MachineInstr &I,
1360 const ExtInstList &Insts,
1361 bool setMIFlags, bool useMISrc,
1362 ArrayRef<Register> SrcRegs) const {
1363
1364 for (const auto &[InstructionSet, Opcode] : Insts) {
1365 if (!STI.canUseExtInstSet(InstructionSet))
1366 continue;
1367 MachineBasicBlock &BB = *I.getParent();
1368 auto MIB = BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpExtInst))
1369 .addDef(ResVReg)
1370 .addUse(GR.getSPIRVTypeID(ResType))
1371 .addImm(static_cast<uint32_t>(InstructionSet))
1372 .addImm(Opcode);
1373 if (setMIFlags)
1374 MIB.setMIFlags(I.getFlags());
1375 if (useMISrc) {
1376 const unsigned NumOps = I.getNumOperands();
1377 unsigned Index = 1;
1378 if (Index < NumOps &&
1379 I.getOperand(Index).getType() ==
1380 MachineOperand::MachineOperandType::MO_IntrinsicID)
1381 Index = 2;
1382 for (; Index < NumOps; ++Index)
1383 MIB.add(I.getOperand(Index));
1384 } else {
1385 for (Register SReg : SrcRegs) {
1386 MIB.addUse(SReg);
1387 }
1388 }
1389 MIB.constrainAllUses(TII, TRI, RBI);
1390 return true;
1391 }
1392 return false;
1393}
1394
1395bool SPIRVInstructionSelector::selectFrexp(Register ResVReg,
1396 SPIRVTypeInst ResType,
1397 MachineInstr &I) const {
1398 ExtInstList ExtInsts = {{SPIRV::InstructionSet::OpenCL_std, CL::frexp},
1399 {SPIRV::InstructionSet::GLSL_std_450, GL::Frexp}};
1400 for (const auto &Ex : ExtInsts) {
1401 SPIRV::InstructionSet::InstructionSet Set = Ex.first;
1402 uint32_t Opcode = Ex.second;
1403 if (!STI.canUseExtInstSet(Set))
1404 continue;
1405
1406 MachineIRBuilder MIRBuilder(I);
1407 SPIRVTypeInst PointeeTy = GR.getSPIRVTypeForVReg(I.getOperand(1).getReg());
1408 const SPIRVTypeInst PointerType = GR.getOrCreateSPIRVPointerType(
1409 PointeeTy, MIRBuilder, SPIRV::StorageClass::Function);
1410 Register PointerVReg =
1411 createVirtualRegister(PointerType, &GR, MRI, MRI->getMF());
1412
1413 auto It = getOpVariableMBBIt(I);
1414 BuildMI(*It->getParent(), It, It->getDebugLoc(), TII.get(SPIRV::OpVariable))
1415 .addDef(PointerVReg)
1416 .addUse(GR.getSPIRVTypeID(PointerType))
1417 .addImm(static_cast<uint32_t>(SPIRV::StorageClass::Function))
1418 .constrainAllUses(TII, TRI, RBI);
1419
1420 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(SPIRV::OpExtInst))
1421 .addDef(ResVReg)
1422 .addUse(GR.getSPIRVTypeID(ResType))
1423 .addImm(static_cast<uint32_t>(Ex.first))
1424 .addImm(Opcode)
1425 .add(I.getOperand(2))
1426 .addUse(PointerVReg)
1427 .constrainAllUses(TII, TRI, RBI);
1428
1429 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(SPIRV::OpLoad))
1430 .addDef(I.getOperand(1).getReg())
1431 .addUse(GR.getSPIRVTypeID(PointeeTy))
1432 .addUse(PointerVReg)
1433 .constrainAllUses(TII, TRI, RBI);
1434 return true;
1435 }
1436 return false;
1437}
1438
1439bool SPIRVInstructionSelector::selectSincos(Register ResVReg,
1440 SPIRVTypeInst ResType,
1441 MachineInstr &I) const {
1442 Register CosResVReg = I.getOperand(1).getReg();
1443 unsigned SrcIdx = I.getNumExplicitDefs();
1444 Register ResTypeReg = GR.getSPIRVTypeID(ResType);
1445
1446 if (STI.canUseExtInstSet(SPIRV::InstructionSet::OpenCL_std)) {
1447 // OpenCL.std sincos(x, cosval*) -> returns sin(x), writes cos(x) to ptr.
1448 MachineIRBuilder MIRBuilder(I);
1449 const SPIRVTypeInst PointerType = GR.getOrCreateSPIRVPointerType(
1450 ResType, MIRBuilder, SPIRV::StorageClass::Function);
1451 Register PointerVReg =
1452 createVirtualRegister(PointerType, &GR, MRI, MRI->getMF());
1453
1454 auto It = getOpVariableMBBIt(I);
1455 BuildMI(*It->getParent(), It, It->getDebugLoc(), TII.get(SPIRV::OpVariable))
1456 .addDef(PointerVReg)
1457 .addUse(GR.getSPIRVTypeID(PointerType))
1458 .addImm(static_cast<uint32_t>(SPIRV::StorageClass::Function))
1459 .constrainAllUses(TII, TRI, RBI);
1460 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(SPIRV::OpExtInst))
1461 .addDef(ResVReg)
1462 .addUse(ResTypeReg)
1463 .addImm(static_cast<uint32_t>(SPIRV::InstructionSet::OpenCL_std))
1464 .addImm(CL::sincos)
1465 .add(I.getOperand(SrcIdx))
1466 .addUse(PointerVReg)
1467 .constrainAllUses(TII, TRI, RBI);
1468 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(SPIRV::OpLoad))
1469 .addDef(CosResVReg)
1470 .addUse(ResTypeReg)
1471 .addUse(PointerVReg)
1472 .constrainAllUses(TII, TRI, RBI);
1473 return true;
1474 } else if (STI.canUseExtInstSet(SPIRV::InstructionSet::GLSL_std_450)) {
1475 // GLSL.std.450 has no combined sincos; emit separate Sin and Cos.
1476 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(SPIRV::OpExtInst))
1477 .addDef(ResVReg)
1478 .addUse(ResTypeReg)
1479 .addImm(static_cast<uint32_t>(SPIRV::InstructionSet::GLSL_std_450))
1480 .addImm(GL::Sin)
1481 .add(I.getOperand(SrcIdx))
1482 .constrainAllUses(TII, TRI, RBI);
1483 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(SPIRV::OpExtInst))
1484 .addDef(CosResVReg)
1485 .addUse(ResTypeReg)
1486 .addImm(static_cast<uint32_t>(SPIRV::InstructionSet::GLSL_std_450))
1487 .addImm(GL::Cos)
1488 .add(I.getOperand(SrcIdx))
1489 .constrainAllUses(TII, TRI, RBI);
1490 return true;
1491 }
1492 return false;
1493}
1494
1495bool SPIRVInstructionSelector::selectOpWithSrcs(Register ResVReg,
1496 SPIRVTypeInst ResType,
1497 MachineInstr &I,
1498 std::vector<Register> Srcs,
1499 unsigned Opcode) const {
1500 auto MIB = BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(Opcode))
1501 .addDef(ResVReg)
1502 .addUse(GR.getSPIRVTypeID(ResType));
1503 for (Register SReg : Srcs) {
1504 MIB.addUse(SReg);
1505 }
1506 MIB.constrainAllUses(TII, TRI, RBI);
1507 return true;
1508}
1509
1510bool SPIRVInstructionSelector::selectUnOp(Register ResVReg,
1511 SPIRVTypeInst ResType,
1512 MachineInstr &I,
1513 unsigned Opcode) const {
1514 if (STI.isPhysicalSPIRV() && I.getOperand(1).isReg()) {
1515 Register SrcReg = I.getOperand(1).getReg();
1516 bool IsGV = false;
1517 for (MachineRegisterInfo::def_instr_iterator DefIt =
1518 MRI->def_instr_begin(SrcReg);
1519 DefIt != MRI->def_instr_end(); DefIt = std::next(DefIt)) {
1520 unsigned DefOpCode = DefIt->getOpcode();
1521 if (DefOpCode == SPIRV::ASSIGN_TYPE || DefOpCode == TargetOpcode::COPY) {
1522 // We need special handling to look through the type assignment or the
1523 // COPY pseudo-op and see if this is a constant or a global.
1524 if (auto *VRD = getVRegDef(*MRI, DefIt->getOperand(1).getReg()))
1525 DefOpCode = VRD->getOpcode();
1526 }
1527 if (DefOpCode == TargetOpcode::G_GLOBAL_VALUE ||
1528 DefOpCode == TargetOpcode::G_CONSTANT ||
1529 DefOpCode == SPIRV::OpVariable || DefOpCode == SPIRV::OpConstantI) {
1530 IsGV = true;
1531 break;
1532 }
1533 }
1534 if (IsGV) {
1535 uint32_t SpecOpcode = 0;
1536 switch (Opcode) {
1537 case SPIRV::OpConvertPtrToU:
1538 SpecOpcode = static_cast<uint32_t>(SPIRV::Opcode::ConvertPtrToU);
1539 break;
1540 case SPIRV::OpConvertUToPtr:
1541 SpecOpcode = static_cast<uint32_t>(SPIRV::Opcode::ConvertUToPtr);
1542 break;
1543 }
1544 if (SpecOpcode) {
1545 BuildMI(*I.getParent(), I, I.getDebugLoc(),
1546 TII.get(SPIRV::OpSpecConstantOp))
1547 .addDef(ResVReg)
1548 .addUse(GR.getSPIRVTypeID(ResType))
1549 .addImm(SpecOpcode)
1550 .addUse(SrcReg)
1551 .constrainAllUses(TII, TRI, RBI);
1552 return true;
1553 }
1554 }
1555 }
1556 return selectOpWithSrcs(ResVReg, ResType, I, {I.getOperand(1).getReg()},
1557 Opcode);
1558}
1559
1560bool SPIRVInstructionSelector::selectBitcast(Register ResVReg,
1561 SPIRVTypeInst ResType,
1562 MachineInstr &I) const {
1563 Register OpReg = I.getOperand(1).getReg();
1564 SPIRVTypeInst OpType =
1565 OpReg.isValid() ? GR.getSPIRVTypeForVReg(OpReg) : nullptr;
1566 if (!GR.isBitcastCompatible(ResType, OpType))
1567 report_fatal_error("incompatible result and operand types in a bitcast");
1568 return selectUnOp(ResVReg, ResType, I, SPIRV::OpBitcast);
1569}
1570
1571static void addMemoryOperands(MachineMemOperand *MemOp,
1572 MachineInstrBuilder &MIB,
1573 MachineIRBuilder &MIRBuilder,
1574 SPIRVGlobalRegistry &GR) {
1575 const SPIRVSubtarget *ST =
1576 static_cast<const SPIRVSubtarget *>(&MIRBuilder.getMF().getSubtarget());
1577 uint32_t SpvMemOp = static_cast<uint32_t>(SPIRV::MemoryOperand::None);
1578 if (MemOp->isVolatile())
1579 SpvMemOp |= static_cast<uint32_t>(SPIRV::MemoryOperand::Volatile);
1580 if (MemOp->isNonTemporal())
1581 SpvMemOp |= static_cast<uint32_t>(SPIRV::MemoryOperand::Nontemporal);
1582 // Aligned memory operand requires the Kernel capability.
1583 if (!ST->isShader() && MemOp->getAlign().value())
1584 SpvMemOp |= static_cast<uint32_t>(SPIRV::MemoryOperand::Aligned);
1585
1586 [[maybe_unused]] MachineInstr *AliasList = nullptr;
1587 [[maybe_unused]] MachineInstr *NoAliasList = nullptr;
1588 if (ST->canUseExtension(SPIRV::Extension::SPV_INTEL_memory_access_aliasing)) {
1589 if (auto *MD = MemOp->getAAInfo().Scope) {
1590 AliasList = GR.getOrAddMemAliasingINTELInst(MIRBuilder, MD);
1591 if (AliasList)
1592 SpvMemOp |=
1593 static_cast<uint32_t>(SPIRV::MemoryOperand::AliasScopeINTELMask);
1594 }
1595 if (auto *MD = MemOp->getAAInfo().NoAlias) {
1596 NoAliasList = GR.getOrAddMemAliasingINTELInst(MIRBuilder, MD);
1597 if (NoAliasList)
1598 SpvMemOp |=
1599 static_cast<uint32_t>(SPIRV::MemoryOperand::NoAliasINTELMask);
1600 }
1601 }
1602
1603 if (SpvMemOp != static_cast<uint32_t>(SPIRV::MemoryOperand::None)) {
1604 MIB.addImm(SpvMemOp);
1605 if (SpvMemOp & static_cast<uint32_t>(SPIRV::MemoryOperand::Aligned))
1606 MIB.addImm(MemOp->getAlign().value());
1607 if (AliasList)
1608 MIB.addUse(AliasList->getOperand(0).getReg());
1609 if (NoAliasList)
1610 MIB.addUse(NoAliasList->getOperand(0).getReg());
1611 }
1612}
1613
1614static void addMemoryOperands(uint64_t Flags, MachineInstrBuilder &MIB) {
1615 uint32_t SpvMemOp = static_cast<uint32_t>(SPIRV::MemoryOperand::None);
1616 if (Flags & MachineMemOperand::Flags::MOVolatile)
1617 SpvMemOp |= static_cast<uint32_t>(SPIRV::MemoryOperand::Volatile);
1618 if (Flags & MachineMemOperand::Flags::MONonTemporal)
1619 SpvMemOp |= static_cast<uint32_t>(SPIRV::MemoryOperand::Nontemporal);
1620
1621 if (SpvMemOp != static_cast<uint32_t>(SPIRV::MemoryOperand::None))
1622 MIB.addImm(SpvMemOp);
1623}
1624
1625bool SPIRVInstructionSelector::selectLoad(Register ResVReg,
1626 SPIRVTypeInst ResType,
1627 MachineInstr &I) const {
1628 unsigned OpOffset = isa<GIntrinsic>(I) ? 1 : 0;
1629 Register Ptr = I.getOperand(1 + OpOffset).getReg();
1630
1631 auto *PtrDef = getVRegDef(*MRI, Ptr);
1632 auto *IntPtrDef = dyn_cast<GIntrinsic>(PtrDef);
1633 if (IntPtrDef &&
1634 IntPtrDef->getIntrinsicID() == Intrinsic::spv_resource_getpointer) {
1635 Register HandleReg = IntPtrDef->getOperand(2).getReg();
1636 SPIRVTypeInst HandleType = GR.getSPIRVTypeForVReg(HandleReg);
1637 if (HandleType->getOpcode() == SPIRV::OpTypeImage) {
1638 Register NewHandleReg =
1639 MRI->createVirtualRegister(MRI->getRegClass(HandleReg));
1640 auto *HandleDef = cast<GIntrinsic>(getVRegDef(*MRI, HandleReg));
1641 if (!loadHandleBeforePosition(NewHandleReg, HandleType, *HandleDef, I)) {
1642 return false;
1643 }
1644
1645 Register IdxReg = IntPtrDef->getOperand(3).getReg();
1646 return generateImageReadOrFetch(ResVReg, ResType, NewHandleReg, IdxReg,
1647 I.getDebugLoc(), I);
1648 }
1649 }
1650
1651 auto MIB = BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(SPIRV::OpLoad))
1652 .addDef(ResVReg)
1653 .addUse(GR.getSPIRVTypeID(ResType))
1654 .addUse(Ptr);
1655 if (!I.getNumMemOperands()) {
1656 assert(I.getOpcode() == TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS ||
1657 I.getOpcode() ==
1658 TargetOpcode::G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS);
1659 addMemoryOperands(I.getOperand(2 + OpOffset).getImm(), MIB);
1660 } else {
1661 MachineIRBuilder MIRBuilder(I);
1662 addMemoryOperands(*I.memoperands_begin(), MIB, MIRBuilder, GR);
1663 }
1664 MIB.constrainAllUses(TII, TRI, RBI);
1665 return true;
1666}
1667
1668bool SPIRVInstructionSelector::selectStore(MachineInstr &I) const {
1669 unsigned OpOffset = isa<GIntrinsic>(I) ? 1 : 0;
1670 Register StoreVal = I.getOperand(0 + OpOffset).getReg();
1671 Register Ptr = I.getOperand(1 + OpOffset).getReg();
1672
1673 auto *PtrDef = getVRegDef(*MRI, Ptr);
1674 auto *IntPtrDef = dyn_cast<GIntrinsic>(PtrDef);
1675 if (IntPtrDef &&
1676 IntPtrDef->getIntrinsicID() == Intrinsic::spv_resource_getpointer) {
1677 Register HandleReg = IntPtrDef->getOperand(2).getReg();
1678 Register NewHandleReg =
1679 MRI->createVirtualRegister(MRI->getRegClass(HandleReg));
1680 auto *HandleDef = cast<GIntrinsic>(getVRegDef(*MRI, HandleReg));
1681 SPIRVTypeInst HandleType = GR.getSPIRVTypeForVReg(HandleReg);
1682 if (!loadHandleBeforePosition(NewHandleReg, HandleType, *HandleDef, I)) {
1683 return false;
1684 }
1685
1686 Register IdxReg = IntPtrDef->getOperand(3).getReg();
1687 if (HandleType->getOpcode() == SPIRV::OpTypeImage) {
1688 auto BMI = BuildMI(*I.getParent(), I, I.getDebugLoc(),
1689 TII.get(SPIRV::OpImageWrite))
1690 .addUse(NewHandleReg)
1691 .addUse(IdxReg)
1692 .addUse(StoreVal);
1693
1694 const llvm::Type *LLVMHandleType = GR.getTypeForSPIRVType(HandleType);
1695 if (sampledTypeIsSignedInteger(LLVMHandleType))
1696 BMI.addImm(0x1000); // SignExtend
1697
1698 BMI.constrainAllUses(TII, TRI, RBI);
1699 return true;
1700 }
1701 }
1702
1703 MachineBasicBlock &BB = *I.getParent();
1704 auto MIB = BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpStore))
1705 .addUse(Ptr)
1706 .addUse(StoreVal);
1707 if (!I.getNumMemOperands()) {
1708 assert(I.getOpcode() == TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS ||
1709 I.getOpcode() ==
1710 TargetOpcode::G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS);
1711 addMemoryOperands(I.getOperand(2 + OpOffset).getImm(), MIB);
1712 } else {
1713 MachineIRBuilder MIRBuilder(I);
1714 addMemoryOperands(*I.memoperands_begin(), MIB, MIRBuilder, GR);
1715 }
1716 MIB.constrainAllUses(TII, TRI, RBI);
1717 return true;
1718}
1719
1720bool SPIRVInstructionSelector::selectStackSave(Register ResVReg,
1721 SPIRVTypeInst ResType,
1722 MachineInstr &I) const {
1723 if (!STI.canUseExtension(SPIRV::Extension::SPV_INTEL_variable_length_array))
1724 report_fatal_error(
1725 "llvm.stacksave intrinsic: this instruction requires the following "
1726 "SPIR-V extension: SPV_INTEL_variable_length_array",
1727 false);
1728 MachineBasicBlock &BB = *I.getParent();
1729 BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpSaveMemoryINTEL))
1730 .addDef(ResVReg)
1731 .addUse(GR.getSPIRVTypeID(ResType))
1732 .constrainAllUses(TII, TRI, RBI);
1733 return true;
1734}
1735
1736bool SPIRVInstructionSelector::selectStackRestore(MachineInstr &I) const {
1737 if (!STI.canUseExtension(SPIRV::Extension::SPV_INTEL_variable_length_array))
1738 report_fatal_error(
1739 "llvm.stackrestore intrinsic: this instruction requires the following "
1740 "SPIR-V extension: SPV_INTEL_variable_length_array",
1741 false);
1742 if (!I.getOperand(0).isReg())
1743 return false;
1744 MachineBasicBlock &BB = *I.getParent();
1745 BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpRestoreMemoryINTEL))
1746 .addUse(I.getOperand(0).getReg())
1747 .constrainAllUses(TII, TRI, RBI);
1748 return true;
1749}
1750
1751Register
1752SPIRVInstructionSelector::getOrCreateMemSetGlobal(MachineInstr &I) const {
1753 MachineIRBuilder MIRBuilder(I);
1754 assert(I.getOperand(1).isReg() && I.getOperand(2).isReg());
1755
1756 // TODO: check if we have such GV, add init, use buildGlobalVariable.
1757 unsigned Num = getIConstVal(I.getOperand(2).getReg(), MRI);
1758 Function &CurFunction = GR.CurMF->getFunction();
1759 Type *LLVMArrTy =
1760 ArrayType::get(IntegerType::get(CurFunction.getContext(), 8), Num);
1761 GlobalVariable *GV = new GlobalVariable(*CurFunction.getParent(), LLVMArrTy,
1762 true, GlobalValue::InternalLinkage,
1763 Constant::getNullValue(LLVMArrTy));
1764
1765 Type *ValTy = Type::getInt8Ty(I.getMF()->getFunction().getContext());
1766 Type *ArrTy = ArrayType::get(ValTy, Num);
1767 SPIRVTypeInst VarTy = GR.getOrCreateSPIRVPointerType(
1768 ArrTy, MIRBuilder, SPIRV::StorageClass::UniformConstant);
1769
1770 SPIRVTypeInst SpvArrTy = GR.getOrCreateSPIRVType(
1771 ArrTy, MIRBuilder, SPIRV::AccessQualifier::None, false);
1772
1773 unsigned Val = getIConstVal(I.getOperand(1).getReg(), MRI);
1774 Register Const = GR.getOrCreateConstIntArray(Val, Num, I, SpvArrTy, TII);
1775
1776 Register VarReg = MRI->createGenericVirtualRegister(LLT::scalar(64));
1777 auto MIBVar =
1778 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(SPIRV::OpVariable))
1779 .addDef(VarReg)
1780 .addUse(GR.getSPIRVTypeID(VarTy))
1781 .addImm(SPIRV::StorageClass::UniformConstant)
1782 .addUse(Const);
1783 MIBVar.constrainAllUses(TII, TRI, RBI);
1784
1785 GR.add(GV, MIBVar);
1786 GR.addGlobalObject(GV, GR.CurMF, VarReg);
1787
1788 buildOpDecorate(VarReg, I, TII, SPIRV::Decoration::Constant, {});
1789 return VarReg;
1790}
1791
1792bool SPIRVInstructionSelector::selectCopyMemory(MachineInstr &I,
1793 Register SrcReg) const {
1794 MachineBasicBlock &BB = *I.getParent();
1795 Register DstReg = I.getOperand(0).getReg();
1796 SPIRVTypeInst DstTy = GR.getSPIRVTypeForVReg(DstReg);
1797 SPIRVTypeInst SrcTy = GR.getSPIRVTypeForVReg(SrcReg);
1798 if (GR.getPointeeType(DstTy) != GR.getPointeeType(SrcTy))
1799 report_fatal_error("OpCopyMemory requires operands to have the same type");
1800 uint64_t CopySize = getIConstVal(I.getOperand(2).getReg(), MRI);
1801 SPIRVTypeInst PointeeTy = GR.getPointeeType(DstTy);
1802 const Type *LLVMPointeeTy = GR.getTypeForSPIRVType(PointeeTy);
1803 if (!LLVMPointeeTy)
1804 report_fatal_error(
1805 "Unable to determine pointee type size for OpCopyMemory");
1806 const DataLayout &DL = I.getMF()->getFunction().getDataLayout();
1807 if (CopySize != DL.getTypeStoreSize(const_cast<Type *>(LLVMPointeeTy)))
1808 report_fatal_error(
1809 "OpCopyMemory requires the size to match the pointee type size");
1810 auto MIB = BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpCopyMemory))
1811 .addUse(DstReg)
1812 .addUse(SrcReg);
1813 if (I.getNumMemOperands()) {
1814 MachineIRBuilder MIRBuilder(I);
1815 addMemoryOperands(*I.memoperands_begin(), MIB, MIRBuilder, GR);
1816 }
1817 MIB.constrainAllUses(TII, TRI, RBI);
1818 return true;
1819}
1820
1821bool SPIRVInstructionSelector::selectCopyMemorySized(MachineInstr &I,
1822 Register SrcReg) const {
1823 MachineBasicBlock &BB = *I.getParent();
1824 auto MIB = BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpCopyMemorySized))
1825 .addUse(I.getOperand(0).getReg())
1826 .addUse(SrcReg)
1827 .addUse(I.getOperand(2).getReg());
1828 if (I.getNumMemOperands()) {
1829 MachineIRBuilder MIRBuilder(I);
1830 addMemoryOperands(*I.memoperands_begin(), MIB, MIRBuilder, GR);
1831 }
1832 MIB.constrainAllUses(TII, TRI, RBI);
1833 return true;
1834}
1835
1836bool SPIRVInstructionSelector::selectMemOperation(Register ResVReg,
1837 MachineInstr &I) const {
1838 Register SrcReg = I.getOperand(1).getReg();
1839 if (I.getOpcode() == TargetOpcode::G_MEMSET) {
1840 Register VarReg = getOrCreateMemSetGlobal(I);
1841 if (!VarReg.isValid())
1842 return false;
1843 Type *ValTy = Type::getInt8Ty(I.getMF()->getFunction().getContext());
1844 SPIRVTypeInst SourceTy = GR.getOrCreateSPIRVPointerType(
1845 ValTy, I, SPIRV::StorageClass::UniformConstant);
1846 SrcReg = MRI->createGenericVirtualRegister(LLT::scalar(64));
1847 if (!selectOpWithSrcs(SrcReg, SourceTy, I, {VarReg}, SPIRV::OpBitcast))
1848 return false;
1849 }
1850 if (STI.isLogicalSPIRV()) {
1851 if (!selectCopyMemory(I, SrcReg))
1852 return false;
1853 } else {
1854 if (!selectCopyMemorySized(I, SrcReg))
1855 return false;
1856 }
1857 if (ResVReg.isValid() && ResVReg != I.getOperand(0).getReg())
1858 if (!BuildCOPY(ResVReg, I.getOperand(0).getReg(), I))
1859 return false;
1860 return true;
1861}
1862
1863bool SPIRVInstructionSelector::selectAtomicRMW(Register ResVReg,
1864 SPIRVTypeInst ResType,
1865 MachineInstr &I,
1866 unsigned NewOpcode,
1867 unsigned NegateOpcode) const {
1868 assert(I.hasOneMemOperand());
1869 const MachineMemOperand *MemOp = *I.memoperands_begin();
1870 uint32_t Scope = static_cast<uint32_t>(getMemScope(
1871 GR.CurMF->getFunction().getContext(), MemOp->getSyncScopeID()));
1872 Register ScopeReg = buildI32Constant(Scope, I);
1873
1874 Register Ptr = I.getOperand(1).getReg();
1875 // TODO: Changed as it's implemented in the translator. See test/atomicrmw.ll
1876 // auto ScSem =
1877 // getMemSemanticsForStorageClass(GR.getPointerStorageClass(Ptr));
1878 AtomicOrdering AO = MemOp->getSuccessOrdering();
1879 uint32_t MemSem = static_cast<uint32_t>(getMemSemantics(AO));
1880 Register MemSemReg = buildI32Constant(MemSem /*| ScSem*/, I);
1881
1882 Register ValueReg = I.getOperand(2).getReg();
1883 if (NegateOpcode != 0) {
1884 // Translation with negative value operand is requested
1885 Register TmpReg = createVirtualRegister(ResType, &GR, MRI, MRI->getMF());
1886 if (!selectOpWithSrcs(TmpReg, ResType, I, {ValueReg}, NegateOpcode))
1887 return false;
1888 ValueReg = TmpReg;
1889 }
1890
1891 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(NewOpcode))
1892 .addDef(ResVReg)
1893 .addUse(GR.getSPIRVTypeID(ResType))
1894 .addUse(Ptr)
1895 .addUse(ScopeReg)
1896 .addUse(MemSemReg)
1897 .addUse(ValueReg)
1898 .constrainAllUses(TII, TRI, RBI);
1899 return true;
1900}
1901
1902bool SPIRVInstructionSelector::selectUnmergeValues(MachineInstr &I) const {
1903 unsigned ArgI = I.getNumOperands() - 1;
1904 Register SrcReg =
1905 I.getOperand(ArgI).isReg() ? I.getOperand(ArgI).getReg() : Register(0);
1906 SPIRVTypeInst SrcType =
1907 SrcReg.isValid() ? GR.getSPIRVTypeForVReg(SrcReg) : nullptr;
1908 if (!SrcType || SrcType->getOpcode() != SPIRV::OpTypeVector)
1909 report_fatal_error(
1910 "cannot select G_UNMERGE_VALUES with a non-vector argument");
1911
1912 SPIRVTypeInst ScalarType =
1913 GR.getSPIRVTypeForVReg(SrcType->getOperand(1).getReg());
1914 MachineBasicBlock &BB = *I.getParent();
1915 unsigned CurrentIndex = 0;
1916 for (unsigned i = 0; i < I.getNumDefs(); ++i) {
1917 Register ResVReg = I.getOperand(i).getReg();
1918 SPIRVTypeInst ResType = GR.getSPIRVTypeForVReg(ResVReg);
1919 if (!ResType) {
1920 LLT ResLLT = MRI->getType(ResVReg);
1921 assert(ResLLT.isValid());
1922 if (ResLLT.isVector()) {
1923 ResType = GR.getOrCreateSPIRVVectorType(
1924 ScalarType, ResLLT.getNumElements(), I, TII);
1925 } else {
1926 ResType = ScalarType;
1927 }
1928 MRI->setRegClass(ResVReg, GR.getRegClass(ResType));
1929 GR.assignSPIRVTypeToVReg(ResType, ResVReg, *GR.CurMF);
1930 }
1931
1932 if (ResType->getOpcode() == SPIRV::OpTypeVector) {
1933 Register UndefReg = GR.getOrCreateUndef(I, SrcType, TII);
1934 auto MIB =
1935 BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpVectorShuffle))
1936 .addDef(ResVReg)
1937 .addUse(GR.getSPIRVTypeID(ResType))
1938 .addUse(SrcReg)
1939 .addUse(UndefReg);
1940 unsigned NumElements = GR.getScalarOrVectorComponentCount(ResType);
1941 for (unsigned j = 0; j < NumElements; ++j) {
1942 MIB.addImm(CurrentIndex + j);
1943 }
1944 CurrentIndex += NumElements;
1945 MIB.constrainAllUses(TII, TRI, RBI);
1946 } else {
1947 auto MIB =
1948 BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpCompositeExtract))
1949 .addDef(ResVReg)
1950 .addUse(GR.getSPIRVTypeID(ResType))
1951 .addUse(SrcReg)
1952 .addImm(CurrentIndex);
1953 CurrentIndex++;
1954 MIB.constrainAllUses(TII, TRI, RBI);
1955 }
1956 }
1957 return true;
1958}
1959
1960bool SPIRVInstructionSelector::selectFence(MachineInstr &I) const {
1961 AtomicOrdering AO = AtomicOrdering(I.getOperand(0).getImm());
1962 uint32_t MemSem = static_cast<uint32_t>(getMemSemantics(AO));
1963 Register MemSemReg = buildI32Constant(MemSem, I);
1964 SyncScope::ID Ord = SyncScope::ID(I.getOperand(1).getImm());
1965 uint32_t Scope = static_cast<uint32_t>(
1966 getMemScope(GR.CurMF->getFunction().getContext(), Ord));
1967 Register ScopeReg = buildI32Constant(Scope, I);
1968 MachineBasicBlock &BB = *I.getParent();
1969 BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpMemoryBarrier))
1970 .addUse(ScopeReg)
1971 .addUse(MemSemReg)
1972 .constrainAllUses(TII, TRI, RBI);
1973 return true;
1974}
1975
1976bool SPIRVInstructionSelector::selectOverflowArith(Register ResVReg,
1977 SPIRVTypeInst ResType,
1978 MachineInstr &I,
1979 unsigned Opcode) const {
1980 Type *ResTy = nullptr;
1981 StringRef ResName;
1982 if (!GR.findValueAttrs(&I, ResTy, ResName))
1983 report_fatal_error(
1984 "Not enough info to select the arithmetic with overflow instruction");
1985 if (!ResTy || !ResTy->isStructTy())
1986 report_fatal_error("Expect struct type result for the arithmetic "
1987 "with overflow instruction");
1988 // "Result Type must be from OpTypeStruct. The struct must have two members,
1989 // and the two members must be the same type."
1990 Type *ResElemTy = cast<StructType>(ResTy)->getElementType(0);
1991 ResTy = StructType::get(ResElemTy, ResElemTy);
1992 // Build SPIR-V types and constant(s) if needed.
1993 MachineIRBuilder MIRBuilder(I);
1994 SPIRVTypeInst StructType = GR.getOrCreateSPIRVType(
1995 ResTy, MIRBuilder, SPIRV::AccessQualifier::ReadWrite, false);
1996 assert(I.getNumDefs() > 1 && "Not enought operands");
1997 SPIRVTypeInst BoolType = GR.getOrCreateSPIRVBoolType(I, TII);
1998 unsigned N = GR.getScalarOrVectorComponentCount(ResType);
1999 if (N > 1)
2000 BoolType = GR.getOrCreateSPIRVVectorType(BoolType, N, I, TII);
2001 Register BoolTypeReg = GR.getSPIRVTypeID(BoolType);
2002 Register ZeroReg = buildZerosVal(ResType, I);
2003 // A new virtual register to store the result struct.
2004 Register StructVReg = MRI->createGenericVirtualRegister(LLT::scalar(64));
2005 MRI->setRegClass(StructVReg, &SPIRV::IDRegClass);
2006 // Build the result name if needed.
2007 if (ResName.size() > 0)
2008 buildOpName(StructVReg, ResName, MIRBuilder);
2009 // Build the arithmetic with overflow instruction.
2010 MachineBasicBlock &BB = *I.getParent();
2011 auto MIB =
2012 BuildMI(BB, MIRBuilder.getInsertPt(), I.getDebugLoc(), TII.get(Opcode))
2013 .addDef(StructVReg)
2014 .addUse(GR.getSPIRVTypeID(StructType));
2015 for (unsigned i = I.getNumDefs(); i < I.getNumOperands(); ++i)
2016 MIB.addUse(I.getOperand(i).getReg());
2017 MIB.constrainAllUses(TII, TRI, RBI);
2018 // Build instructions to extract fields of the instruction's result.
2019 // A new virtual register to store the higher part of the result struct.
2020 Register HigherVReg = MRI->createGenericVirtualRegister(LLT::scalar(64));
2021 MRI->setRegClass(HigherVReg, &SPIRV::iIDRegClass);
2022 for (unsigned i = 0; i < I.getNumDefs(); ++i) {
2023 auto MIB =
2024 BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpCompositeExtract))
2025 .addDef(i == 1 ? HigherVReg : I.getOperand(i).getReg())
2026 .addUse(GR.getSPIRVTypeID(ResType))
2027 .addUse(StructVReg)
2028 .addImm(i);
2029 MIB.constrainAllUses(TII, TRI, RBI);
2030 }
2031 // Build boolean value from the higher part.
2032 BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpINotEqual))
2033 .addDef(I.getOperand(1).getReg())
2034 .addUse(BoolTypeReg)
2035 .addUse(HigherVReg)
2036 .addUse(ZeroReg)
2037 .constrainAllUses(TII, TRI, RBI);
2038 return true;
2039}
2040
2041bool SPIRVInstructionSelector::selectAtomicCmpXchg(Register ResVReg,
2042 SPIRVTypeInst ResType,
2043 MachineInstr &I) const {
2044 Register ScopeReg;
2045 Register MemSemEqReg;
2046 Register MemSemNeqReg;
2047 Register Ptr = I.getOperand(2).getReg();
2048 if (!isa<GIntrinsic>(I)) {
2049 assert(I.hasOneMemOperand());
2050 const MachineMemOperand *MemOp = *I.memoperands_begin();
2051 unsigned Scope = static_cast<uint32_t>(getMemScope(
2052 GR.CurMF->getFunction().getContext(), MemOp->getSyncScopeID()));
2053 ScopeReg = buildI32Constant(Scope, I);
2054
2055 unsigned ScSem = static_cast<uint32_t>(
2056 getMemSemanticsForStorageClass(GR.getPointerStorageClass(Ptr)));
2057 AtomicOrdering AO = MemOp->getSuccessOrdering();
2058 unsigned MemSemEq = static_cast<uint32_t>(getMemSemantics(AO)) | ScSem;
2059 Register MemSemEqReg = buildI32Constant(MemSemEq, I);
2060 AtomicOrdering FO = MemOp->getFailureOrdering();
2061 unsigned MemSemNeq = static_cast<uint32_t>(getMemSemantics(FO)) | ScSem;
2062 if (MemSemEq == MemSemNeq)
2063 MemSemNeqReg = MemSemEqReg;
2064 else {
2065 MemSemNeqReg = buildI32Constant(MemSemEq, I);
2066 }
2067 } else {
2068 ScopeReg = I.getOperand(5).getReg();
2069 MemSemEqReg = I.getOperand(6).getReg();
2070 MemSemNeqReg = I.getOperand(7).getReg();
2071 }
2072
2073 Register Cmp = I.getOperand(3).getReg();
2074 Register Val = I.getOperand(4).getReg();
2075 SPIRVTypeInst SpvValTy = GR.getSPIRVTypeForVReg(Val);
2076 Register ACmpRes = createVirtualRegister(SpvValTy, &GR, MRI, *I.getMF());
2077 const DebugLoc &DL = I.getDebugLoc();
2078 BuildMI(*I.getParent(), I, DL, TII.get(SPIRV::OpAtomicCompareExchange))
2079 .addDef(ACmpRes)
2080 .addUse(GR.getSPIRVTypeID(SpvValTy))
2081 .addUse(Ptr)
2082 .addUse(ScopeReg)
2083 .addUse(MemSemEqReg)
2084 .addUse(MemSemNeqReg)
2085 .addUse(Val)
2086 .addUse(Cmp)
2087 .constrainAllUses(TII, TRI, RBI);
2088 SPIRVTypeInst BoolTy = GR.getOrCreateSPIRVBoolType(I, TII);
2089 Register CmpSuccReg = createVirtualRegister(BoolTy, &GR, MRI, *I.getMF());
2090 BuildMI(*I.getParent(), I, DL, TII.get(SPIRV::OpIEqual))
2091 .addDef(CmpSuccReg)
2092 .addUse(GR.getSPIRVTypeID(BoolTy))
2093 .addUse(ACmpRes)
2094 .addUse(Cmp)
2095 .constrainAllUses(TII, TRI, RBI);
2096 Register TmpReg = createVirtualRegister(ResType, &GR, MRI, *I.getMF());
2097 BuildMI(*I.getParent(), I, DL, TII.get(SPIRV::OpCompositeInsert))
2098 .addDef(TmpReg)
2099 .addUse(GR.getSPIRVTypeID(ResType))
2100 .addUse(ACmpRes)
2101 .addUse(GR.getOrCreateUndef(I, ResType, TII))
2102 .addImm(0)
2103 .constrainAllUses(TII, TRI, RBI);
2104 BuildMI(*I.getParent(), I, DL, TII.get(SPIRV::OpCompositeInsert))
2105 .addDef(ResVReg)
2106 .addUse(GR.getSPIRVTypeID(ResType))
2107 .addUse(CmpSuccReg)
2108 .addUse(TmpReg)
2109 .addImm(1)
2110 .constrainAllUses(TII, TRI, RBI);
2111 return true;
2112}
2113
2114static bool isUSMStorageClass(SPIRV::StorageClass::StorageClass SC) {
2115 switch (SC) {
2116 case SPIRV::StorageClass::DeviceOnlyINTEL:
2117 case SPIRV::StorageClass::HostOnlyINTEL:
2118 return true;
2119 default:
2120 return false;
2121 }
2122}
2123
2124// Returns true ResVReg is referred only from global vars and OpName's.
2125static bool isASCastInGVar(MachineRegisterInfo *MRI, Register ResVReg) {
2126 bool IsGRef = false;
2127 bool IsAllowedRefs =
2128 llvm::all_of(MRI->use_instructions(ResVReg), [&IsGRef](auto const &It) {
2129 unsigned Opcode = It.getOpcode();
2130 if (Opcode == SPIRV::OpConstantComposite ||
2131 Opcode == SPIRV::OpVariable ||
2132 isSpvIntrinsic(It, Intrinsic::spv_init_global))
2133 return IsGRef = true;
2134 return Opcode == SPIRV::OpName;
2135 });
2136 return IsAllowedRefs && IsGRef;
2137}
2138
2139Register SPIRVInstructionSelector::getUcharPtrTypeReg(
2140 MachineInstr &I, SPIRV::StorageClass::StorageClass SC) const {
2141 return GR.getSPIRVTypeID(GR.getOrCreateSPIRVPointerType(
2142 Type::getInt8Ty(I.getMF()->getFunction().getContext()), I, SC));
2143}
2144
2145MachineInstrBuilder
2146SPIRVInstructionSelector::buildSpecConstantOp(MachineInstr &I, Register Dest,
2147 Register Src, Register DestType,
2148 uint32_t Opcode) const {
2149 return BuildMI(*I.getParent(), I, I.getDebugLoc(),
2150 TII.get(SPIRV::OpSpecConstantOp))
2151 .addDef(Dest)
2152 .addUse(DestType)
2153 .addImm(Opcode)
2154 .addUse(Src);
2155}
2156
2157MachineInstrBuilder
2158SPIRVInstructionSelector::buildConstGenericPtr(MachineInstr &I, Register SrcPtr,
2159 SPIRVTypeInst SrcPtrTy) const {
2160 SPIRVTypeInst GenericPtrTy =
2161 GR.changePointerStorageClass(SrcPtrTy, SPIRV::StorageClass::Generic, I);
2162 Register Tmp = MRI->createVirtualRegister(&SPIRV::pIDRegClass);
2163 MRI->setType(Tmp, LLT::pointer(storageClassToAddressSpace(
2164 SPIRV::StorageClass::Generic),
2165 GR.getPointerSize()));
2166 MachineFunction *MF = I.getParent()->getParent();
2167 GR.assignSPIRVTypeToVReg(GenericPtrTy, Tmp, *MF);
2168 MachineInstrBuilder MIB = buildSpecConstantOp(
2169 I, Tmp, SrcPtr, GR.getSPIRVTypeID(GenericPtrTy),
2170 static_cast<uint32_t>(SPIRV::Opcode::PtrCastToGeneric));
2171 GR.add(MIB.getInstr(), MIB);
2172 return MIB;
2173}
2174
2175// In SPIR-V address space casting can only happen to and from the Generic
2176// storage class. We can also only cast Workgroup, CrossWorkgroup, or Function
2177// pointers to and from Generic pointers. As such, we can convert e.g. from
2178// Workgroup to Function by going via a Generic pointer as an intermediary. All
2179// other combinations can only be done by a bitcast, and are probably not safe.
2180bool SPIRVInstructionSelector::selectAddrSpaceCast(Register ResVReg,
2181 SPIRVTypeInst ResType,
2182 MachineInstr &I) const {
2183 MachineBasicBlock &BB = *I.getParent();
2184 const DebugLoc &DL = I.getDebugLoc();
2185
2186 Register SrcPtr = I.getOperand(1).getReg();
2187 SPIRVTypeInst SrcPtrTy = GR.getSPIRVTypeForVReg(SrcPtr);
2188
2189 // don't generate a cast for a null that may be represented by OpTypeInt
2190 if (SrcPtrTy->getOpcode() != SPIRV::OpTypePointer ||
2191 ResType->getOpcode() != SPIRV::OpTypePointer)
2192 return BuildCOPY(ResVReg, SrcPtr, I);
2193
2194 SPIRV::StorageClass::StorageClass SrcSC = GR.getPointerStorageClass(SrcPtrTy);
2195 SPIRV::StorageClass::StorageClass DstSC = GR.getPointerStorageClass(ResType);
2196
2197 if (isASCastInGVar(MRI, ResVReg)) {
2198 // AddrSpaceCast uses within OpVariable and OpConstantComposite instructions
2199 // are expressed by OpSpecConstantOp with an Opcode.
2200 // TODO: maybe insert a check whether the Kernel capability was declared and
2201 // so PtrCastToGeneric/GenericCastToPtr are available.
2202 unsigned SpecOpcode =
2203 DstSC == SPIRV::StorageClass::Generic && isGenericCastablePtr(SrcSC)
2204 ? static_cast<uint32_t>(SPIRV::Opcode::PtrCastToGeneric)
2205 : (SrcSC == SPIRV::StorageClass::Generic &&
2206 isGenericCastablePtr(DstSC)
2207 ? static_cast<uint32_t>(SPIRV::Opcode::GenericCastToPtr)
2208 : 0);
2209 // TODO: OpConstantComposite expects i8*, so we are forced to forget a
2210 // correct value of ResType and use general i8* instead. Maybe this should
2211 // be addressed in the emit-intrinsic step to infer a correct
2212 // OpConstantComposite type.
2213 if (SpecOpcode) {
2214 buildSpecConstantOp(I, ResVReg, SrcPtr, getUcharPtrTypeReg(I, DstSC),
2215 SpecOpcode)
2216 .constrainAllUses(TII, TRI, RBI);
2217 } else if (isGenericCastablePtr(SrcSC) && isGenericCastablePtr(DstSC)) {
2218 MachineInstrBuilder MIB = buildConstGenericPtr(I, SrcPtr, SrcPtrTy);
2219 MIB.constrainAllUses(TII, TRI, RBI);
2220 buildSpecConstantOp(
2221 I, ResVReg, MIB->getOperand(0).getReg(), getUcharPtrTypeReg(I, DstSC),
2222 static_cast<uint32_t>(SPIRV::Opcode::GenericCastToPtr))
2223 .constrainAllUses(TII, TRI, RBI);
2224 }
2225 return true;
2226 }
2227
2228 // don't generate a cast between identical storage classes
2229 if (SrcSC == DstSC)
2230 return BuildCOPY(ResVReg, SrcPtr, I);
2231
2232 if ((SrcSC == SPIRV::StorageClass::Function &&
2233 DstSC == SPIRV::StorageClass::Private) ||
2234 (DstSC == SPIRV::StorageClass::Function &&
2235 SrcSC == SPIRV::StorageClass::Private))
2236 return BuildCOPY(ResVReg, SrcPtr, I);
2237
2238 // Casting from an eligible pointer to Generic.
2239 if (DstSC == SPIRV::StorageClass::Generic && isGenericCastablePtr(SrcSC))
2240 return selectUnOp(ResVReg, ResType, I, SPIRV::OpPtrCastToGeneric);
2241 // Casting from Generic to an eligible pointer.
2242 if (SrcSC == SPIRV::StorageClass::Generic && isGenericCastablePtr(DstSC))
2243 return selectUnOp(ResVReg, ResType, I, SPIRV::OpGenericCastToPtr);
2244 // Casting between 2 eligible pointers using Generic as an intermediary.
2245 if (isGenericCastablePtr(SrcSC) && isGenericCastablePtr(DstSC)) {
2246 SPIRVTypeInst GenericPtrTy =
2247 GR.changePointerStorageClass(SrcPtrTy, SPIRV::StorageClass::Generic, I);
2248 Register Tmp = createVirtualRegister(GenericPtrTy, &GR, MRI, MRI->getMF());
2249 BuildMI(BB, I, DL, TII.get(SPIRV::OpPtrCastToGeneric))
2250 .addDef(Tmp)
2251 .addUse(GR.getSPIRVTypeID(GenericPtrTy))
2252 .addUse(SrcPtr)
2253 .constrainAllUses(TII, TRI, RBI);
2254 BuildMI(BB, I, DL, TII.get(SPIRV::OpGenericCastToPtr))
2255 .addDef(ResVReg)
2256 .addUse(GR.getSPIRVTypeID(ResType))
2257 .addUse(Tmp)
2258 .constrainAllUses(TII, TRI, RBI);
2259 return true;
2260 }
2261
2262 // Check if instructions from the SPV_INTEL_usm_storage_classes extension may
2263 // be applied
2264 if (isUSMStorageClass(SrcSC) && DstSC == SPIRV::StorageClass::CrossWorkgroup)
2265 return selectUnOp(ResVReg, ResType, I,
2266 SPIRV::OpPtrCastToCrossWorkgroupINTEL);
2267 if (SrcSC == SPIRV::StorageClass::CrossWorkgroup && isUSMStorageClass(DstSC))
2268 return selectUnOp(ResVReg, ResType, I,
2269 SPIRV::OpCrossWorkgroupCastToPtrINTEL);
2270 if (isUSMStorageClass(SrcSC) && DstSC == SPIRV::StorageClass::Generic)
2271 return selectUnOp(ResVReg, ResType, I, SPIRV::OpPtrCastToGeneric);
2272 if (SrcSC == SPIRV::StorageClass::Generic && isUSMStorageClass(DstSC))
2273 return selectUnOp(ResVReg, ResType, I, SPIRV::OpGenericCastToPtr);
2274
2275 // Bitcast for pointers requires that the address spaces must match
2276 return false;
2277}
2278
2279static unsigned getFCmpOpcode(unsigned PredNum) {
2280 auto Pred = static_cast<CmpInst::Predicate>(PredNum);
2281 switch (Pred) {
2282 case CmpInst::FCMP_OEQ:
2283 return SPIRV::OpFOrdEqual;
2284 case CmpInst::FCMP_OGE:
2285 return SPIRV::OpFOrdGreaterThanEqual;
2286 case CmpInst::FCMP_OGT:
2287 return SPIRV::OpFOrdGreaterThan;
2288 case CmpInst::FCMP_OLE:
2289 return SPIRV::OpFOrdLessThanEqual;
2290 case CmpInst::FCMP_OLT:
2291 return SPIRV::OpFOrdLessThan;
2292 case CmpInst::FCMP_ONE:
2293 return SPIRV::OpFOrdNotEqual;
2294 case CmpInst::FCMP_ORD:
2295 return SPIRV::OpOrdered;
2296 case CmpInst::FCMP_UEQ:
2297 return SPIRV::OpFUnordEqual;
2298 case CmpInst::FCMP_UGE:
2299 return SPIRV::OpFUnordGreaterThanEqual;
2300 case CmpInst::FCMP_UGT:
2301 return SPIRV::OpFUnordGreaterThan;
2302 case CmpInst::FCMP_ULE:
2303 return SPIRV::OpFUnordLessThanEqual;
2304 case CmpInst::FCMP_ULT:
2305 return SPIRV::OpFUnordLessThan;
2306 case CmpInst::FCMP_UNE:
2307 return SPIRV::OpFUnordNotEqual;
2308 case CmpInst::FCMP_UNO:
2309 return SPIRV::OpUnordered;
2310 default:
2311 llvm_unreachable("Unknown predicate type for FCmp");
2312 }
2313}
2314
2315static unsigned getICmpOpcode(unsigned PredNum) {
2316 auto Pred = static_cast<CmpInst::Predicate>(PredNum);
2317 switch (Pred) {
2318 case CmpInst::ICMP_EQ:
2319 return SPIRV::OpIEqual;
2320 case CmpInst::ICMP_NE:
2321 return SPIRV::OpINotEqual;
2322 case CmpInst::ICMP_SGE:
2323 return SPIRV::OpSGreaterThanEqual;
2324 case CmpInst::ICMP_SGT:
2325 return SPIRV::OpSGreaterThan;
2326 case CmpInst::ICMP_SLE:
2327 return SPIRV::OpSLessThanEqual;
2328 case CmpInst::ICMP_SLT:
2329 return SPIRV::OpSLessThan;
2330 case CmpInst::ICMP_UGE:
2331 return SPIRV::OpUGreaterThanEqual;
2332 case CmpInst::ICMP_UGT:
2333 return SPIRV::OpUGreaterThan;
2334 case CmpInst::ICMP_ULE:
2335 return SPIRV::OpULessThanEqual;
2336 case CmpInst::ICMP_ULT:
2337 return SPIRV::OpULessThan;
2338 default:
2339 llvm_unreachable("Unknown predicate type for ICmp");
2340 }
2341}
2342
2343static unsigned getPtrCmpOpcode(unsigned Pred) {
2344 switch (static_cast<CmpInst::Predicate>(Pred)) {
2345 case CmpInst::ICMP_EQ:
2346 return SPIRV::OpPtrEqual;
2347 case CmpInst::ICMP_NE:
2348 return SPIRV::OpPtrNotEqual;
2349 default:
2350 llvm_unreachable("Unknown predicate type for pointer comparison");
2351 }
2352}
2353
2354// Return the logical operation, or abort if none exists.
2355static unsigned getBoolCmpOpcode(unsigned PredNum) {
2356 auto Pred = static_cast<CmpInst::Predicate>(PredNum);
2357 switch (Pred) {
2358 case CmpInst::ICMP_EQ:
2359 return SPIRV::OpLogicalEqual;
2360 case CmpInst::ICMP_NE:
2361 return SPIRV::OpLogicalNotEqual;
2362 default:
2363 llvm_unreachable("Unknown predicate type for Bool comparison");
2364 }
2365}
2366
2367static APFloat getZeroFP(const Type *LLVMFloatTy) {
2368 if (!LLVMFloatTy)
2369 return APFloat::getZero(APFloat::IEEEsingle());
2370 switch (LLVMFloatTy->getScalarType()->getTypeID()) {
2371 case Type::HalfTyID:
2372 return APFloat::getZero(APFloat::IEEEhalf());
2373 default:
2374 case Type::FloatTyID:
2375 return APFloat::getZero(APFloat::IEEEsingle());
2376 case Type::DoubleTyID:
2377 return APFloat::getZero(APFloat::IEEEdouble());
2378 }
2379}
2380
2381static APFloat getOneFP(const Type *LLVMFloatTy) {
2382 if (!LLVMFloatTy)
2383 return APFloat::getOne(APFloat::IEEEsingle());
2384 switch (LLVMFloatTy->getScalarType()->getTypeID()) {
2385 case Type::HalfTyID:
2386 return APFloat::getOne(APFloat::IEEEhalf());
2387 default:
2388 case Type::FloatTyID:
2389 return APFloat::getOne(APFloat::IEEEsingle());
2390 case Type::DoubleTyID:
2391 return APFloat::getOne(APFloat::IEEEdouble());
2392 }
2393}
2394
2395bool SPIRVInstructionSelector::selectAnyOrAll(Register ResVReg,
2396 SPIRVTypeInst ResType,
2397 MachineInstr &I,
2398 unsigned OpAnyOrAll) const {
2399 assert(I.getNumOperands() == 3);
2400 assert(I.getOperand(2).isReg());
2401 MachineBasicBlock &BB = *I.getParent();
2402 Register InputRegister = I.getOperand(2).getReg();
2403 SPIRVTypeInst InputType = GR.getSPIRVTypeForVReg(InputRegister);
2404
2405 if (!InputType)
2406 report_fatal_error("Input Type could not be determined.");
2407
2408 bool IsBoolTy = GR.isScalarOrVectorOfType(InputRegister, SPIRV::OpTypeBool);
2409 bool IsVectorTy = InputType->getOpcode() == SPIRV::OpTypeVector;
2410 if (IsBoolTy && !IsVectorTy) {
2411 assert(ResVReg == I.getOperand(0).getReg());
2412 return BuildCOPY(ResVReg, InputRegister, I);
2413 }
2414
2415 bool IsFloatTy = GR.isScalarOrVectorOfType(InputRegister, SPIRV::OpTypeFloat);
2416 unsigned SpirvNotEqualId =
2417 IsFloatTy ? SPIRV::OpFOrdNotEqual : SPIRV::OpINotEqual;
2418 SPIRVTypeInst SpvBoolScalarTy = GR.getOrCreateSPIRVBoolType(I, TII);
2419 SPIRVTypeInst SpvBoolTy = SpvBoolScalarTy;
2420 Register NotEqualReg = ResVReg;
2421
2422 if (IsVectorTy) {
2423 NotEqualReg =
2424 IsBoolTy ? InputRegister
2425 : createVirtualRegister(SpvBoolTy, &GR, MRI, MRI->getMF());
2426 const unsigned NumElts = InputType->getOperand(2).getImm();
2427 SpvBoolTy = GR.getOrCreateSPIRVVectorType(SpvBoolTy, NumElts, I, TII);
2428 }
2429
2430 if (!IsBoolTy) {
2431 Register ConstZeroReg =
2432 IsFloatTy ? buildZerosValF(InputType, I) : buildZerosVal(InputType, I);
2433
2434 BuildMI(BB, I, I.getDebugLoc(), TII.get(SpirvNotEqualId))
2435 .addDef(NotEqualReg)
2436 .addUse(GR.getSPIRVTypeID(SpvBoolTy))
2437 .addUse(InputRegister)
2438 .addUse(ConstZeroReg)
2439 .constrainAllUses(TII, TRI, RBI);
2440 }
2441
2442 if (IsVectorTy)
2443 BuildMI(BB, I, I.getDebugLoc(), TII.get(OpAnyOrAll))
2444 .addDef(ResVReg)
2445 .addUse(GR.getSPIRVTypeID(SpvBoolScalarTy))
2446 .addUse(NotEqualReg)
2447 .constrainAllUses(TII, TRI, RBI);
2448 return true;
2449}
2450
2451bool SPIRVInstructionSelector::selectAll(Register ResVReg,
2452 SPIRVTypeInst ResType,
2453 MachineInstr &I) const {
2454 return selectAnyOrAll(ResVReg, ResType, I, SPIRV::OpAll);
2455}
2456
2457bool SPIRVInstructionSelector::selectAny(Register ResVReg,
2458 SPIRVTypeInst ResType,
2459 MachineInstr &I) const {
2460 return selectAnyOrAll(ResVReg, ResType, I, SPIRV::OpAny);
2461}
2462
2463// Select the OpDot instruction for the given float dot
2464bool SPIRVInstructionSelector::selectFloatDot(Register ResVReg,
2465 SPIRVTypeInst ResType,
2466 MachineInstr &I) const {
2467 assert(I.getNumOperands() == 4);
2468 assert(I.getOperand(2).isReg());
2469 assert(I.getOperand(3).isReg());
2470
2471 [[maybe_unused]] SPIRVTypeInst VecType =
2472 GR.getSPIRVTypeForVReg(I.getOperand(2).getReg());
2473
2474 assert(VecType->getOpcode() == SPIRV::OpTypeVector &&
2475 GR.getScalarOrVectorComponentCount(VecType) > 1 &&
2476 "dot product requires a vector of at least 2 components");
2477
2478 [[maybe_unused]] SPIRVTypeInst EltType =
2479 GR.getSPIRVTypeForVReg(VecType->getOperand(1).getReg());
2480
2481 assert(EltType->getOpcode() == SPIRV::OpTypeFloat);
2482
2483 MachineBasicBlock &BB = *I.getParent();
2484 BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpDot))
2485 .addDef(ResVReg)
2486 .addUse(GR.getSPIRVTypeID(ResType))
2487 .addUse(I.getOperand(2).getReg())
2488 .addUse(I.getOperand(3).getReg())
2489 .constrainAllUses(TII, TRI, RBI);
2490 return true;
2491}
2492
2493bool SPIRVInstructionSelector::selectIntegerDot(Register ResVReg,
2494 SPIRVTypeInst ResType,
2495 MachineInstr &I,
2496 bool Signed) const {
2497 assert(I.getNumOperands() == 4);
2498 assert(I.getOperand(2).isReg());
2499 assert(I.getOperand(3).isReg());
2500 MachineBasicBlock &BB = *I.getParent();
2501
2502 auto DotOp = Signed ? SPIRV::OpSDot : SPIRV::OpUDot;
2503 BuildMI(BB, I, I.getDebugLoc(), TII.get(DotOp))
2504 .addDef(ResVReg)
2505 .addUse(GR.getSPIRVTypeID(ResType))
2506 .addUse(I.getOperand(2).getReg())
2507 .addUse(I.getOperand(3).getReg())
2508 .constrainAllUses(TII, TRI, RBI);
2509 return true;
2510}
2511
2512// Since pre-1.6 SPIRV has no integer dot implementation,
2513// expand by piecewise multiplying and adding the results
2514bool SPIRVInstructionSelector::selectIntegerDotExpansion(
2515 Register ResVReg, SPIRVTypeInst ResType, MachineInstr &I) const {
2516 assert(I.getNumOperands() == 4);
2517 assert(I.getOperand(2).isReg());
2518 assert(I.getOperand(3).isReg());
2519 MachineBasicBlock &BB = *I.getParent();
2520
2521 // Multiply the vectors, then sum the results
2522 Register Vec0 = I.getOperand(2).getReg();
2523 Register Vec1 = I.getOperand(3).getReg();
2524 Register TmpVec = MRI->createVirtualRegister(GR.getRegClass(ResType));
2525 SPIRVTypeInst VecType = GR.getSPIRVTypeForVReg(Vec0);
2526
2527 BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpIMulV))
2528 .addDef(TmpVec)
2529 .addUse(GR.getSPIRVTypeID(VecType))
2530 .addUse(Vec0)
2531 .addUse(Vec1)
2532 .constrainAllUses(TII, TRI, RBI);
2533
2534 assert(VecType->getOpcode() == SPIRV::OpTypeVector &&
2535 GR.getScalarOrVectorComponentCount(VecType) > 1 &&
2536 "dot product requires a vector of at least 2 components");
2537
2538 Register Res = MRI->createVirtualRegister(GR.getRegClass(ResType));
2539 BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpCompositeExtract))
2540 .addDef(Res)
2541 .addUse(GR.getSPIRVTypeID(ResType))
2542 .addUse(TmpVec)
2543 .addImm(0)
2544 .constrainAllUses(TII, TRI, RBI);
2545
2546 for (unsigned i = 1; i < GR.getScalarOrVectorComponentCount(VecType); i++) {
2547 Register Elt = MRI->createVirtualRegister(GR.getRegClass(ResType));
2548
2549 BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpCompositeExtract))
2550 .addDef(Elt)
2551 .addUse(GR.getSPIRVTypeID(ResType))
2552 .addUse(TmpVec)
2553 .addImm(i)
2554 .constrainAllUses(TII, TRI, RBI);
2555
2556 Register Sum = i < GR.getScalarOrVectorComponentCount(VecType) - 1
2557 ? MRI->createVirtualRegister(GR.getRegClass(ResType))
2558 : ResVReg;
2559
2560 BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpIAddS))
2561 .addDef(Sum)
2562 .addUse(GR.getSPIRVTypeID(ResType))
2563 .addUse(Res)
2564 .addUse(Elt)
2565 .constrainAllUses(TII, TRI, RBI);
2566 Res = Sum;
2567 }
2568
2569 return true;
2570}
2571
2572bool SPIRVInstructionSelector::selectOpIsInf(Register ResVReg,
2573 SPIRVTypeInst ResType,
2574 MachineInstr &I) const {
2575 MachineBasicBlock &BB = *I.getParent();
2576 BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpIsInf))
2577 .addDef(ResVReg)
2578 .addUse(GR.getSPIRVTypeID(ResType))
2579 .addUse(I.getOperand(2).getReg())
2580 .constrainAllUses(TII, TRI, RBI);
2581 return true;
2582}
2583
2584bool SPIRVInstructionSelector::selectOpIsNan(Register ResVReg,
2585 SPIRVTypeInst ResType,
2586 MachineInstr &I) const {
2587 MachineBasicBlock &BB = *I.getParent();
2588 BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpIsNan))
2589 .addDef(ResVReg)
2590 .addUse(GR.getSPIRVTypeID(ResType))
2591 .addUse(I.getOperand(2).getReg())
2592 .constrainAllUses(TII, TRI, RBI);
2593 return true;
2594}
2595
2596template <bool Signed>
2597bool SPIRVInstructionSelector::selectDot4AddPacked(Register ResVReg,
2598 SPIRVTypeInst ResType,
2599 MachineInstr &I) const {
2600 assert(I.getNumOperands() == 5);
2601 assert(I.getOperand(2).isReg());
2602 assert(I.getOperand(3).isReg());
2603 assert(I.getOperand(4).isReg());
2604 MachineBasicBlock &BB = *I.getParent();
2605
2606 Register Acc = I.getOperand(2).getReg();
2607 Register X = I.getOperand(3).getReg();
2608 Register Y = I.getOperand(4).getReg();
2609
2610 auto DotOp = Signed ? SPIRV::OpSDot : SPIRV::OpUDot;
2611 Register Dot = MRI->createVirtualRegister(GR.getRegClass(ResType));
2612 auto MIB = BuildMI(BB, I, I.getDebugLoc(), TII.get(DotOp))
2613 .addDef(Dot)
2614 .addUse(GR.getSPIRVTypeID(ResType))
2615 .addUse(X)
2616 .addUse(Y);
2617 MIB.addImm(SPIRV::BuiltIn::PackedVectorFormat4x8Bit);
2618 MIB.constrainAllUses(TII, TRI, RBI);
2619
2620 BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpIAddS))
2621 .addDef(ResVReg)
2622 .addUse(GR.getSPIRVTypeID(ResType))
2623 .addUse(Dot)
2624 .addUse(Acc)
2625 .constrainAllUses(TII, TRI, RBI);
2626 return true;
2627}
2628
2629// Since pre-1.6 SPIRV has no DotProductInput4x8BitPacked implementation,
2630// extract the elements of the packed inputs, multiply them and add the result
2631// to the accumulator.
2632template <bool Signed>
2633bool SPIRVInstructionSelector::selectDot4AddPackedExpansion(
2634 Register ResVReg, SPIRVTypeInst ResType, MachineInstr &I) const {
2635 assert(I.getNumOperands() == 5);
2636 assert(I.getOperand(2).isReg());
2637 assert(I.getOperand(3).isReg());
2638 assert(I.getOperand(4).isReg());
2639 MachineBasicBlock &BB = *I.getParent();
2640
2641 Register Acc = I.getOperand(2).getReg();
2642 Register X = I.getOperand(3).getReg();
2643 Register Y = I.getOperand(4).getReg();
2644
2645 SPIRVTypeInst EltType = GR.getOrCreateSPIRVIntegerType(8, I, TII);
2646 auto ExtractOp =
2647 Signed ? SPIRV::OpBitFieldSExtract : SPIRV::OpBitFieldUExtract;
2648
2649 bool ZeroAsNull = !STI.isShader();
2650 // Extract the i8 element, multiply and add it to the accumulator
2651 for (unsigned i = 0; i < 4; i++) {
2652 // A[i]
2653 Register AElt = MRI->createVirtualRegister(&SPIRV::IDRegClass);
2654 BuildMI(BB, I, I.getDebugLoc(), TII.get(ExtractOp))
2655 .addDef(AElt)
2656 .addUse(GR.getSPIRVTypeID(ResType))
2657 .addUse(X)
2658 .addUse(GR.getOrCreateConstInt(i * 8, I, EltType, TII, ZeroAsNull))
2659 .addUse(GR.getOrCreateConstInt(8, I, EltType, TII, ZeroAsNull))
2660 .constrainAllUses(TII, TRI, RBI);
2661
2662 // B[i]
2663 Register BElt = MRI->createVirtualRegister(&SPIRV::IDRegClass);
2664 BuildMI(BB, I, I.getDebugLoc(), TII.get(ExtractOp))
2665 .addDef(BElt)
2666 .addUse(GR.getSPIRVTypeID(ResType))
2667 .addUse(Y)
2668 .addUse(GR.getOrCreateConstInt(i * 8, I, EltType, TII, ZeroAsNull))
2669 .addUse(GR.getOrCreateConstInt(8, I, EltType, TII, ZeroAsNull))
2670 .constrainAllUses(TII, TRI, RBI);
2671
2672 // A[i] * B[i]
2673 Register Mul = MRI->createVirtualRegister(&SPIRV::IDRegClass);
2674 BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpIMulS))
2675 .addDef(Mul)
2676 .addUse(GR.getSPIRVTypeID(ResType))
2677 .addUse(AElt)
2678 .addUse(BElt)
2679 .constrainAllUses(TII, TRI, RBI);
2680
2681 // Discard 24 highest-bits so that stored i32 register is i8 equivalent
2682 Register MaskMul = MRI->createVirtualRegister(&SPIRV::IDRegClass);
2683 BuildMI(BB, I, I.getDebugLoc(), TII.get(ExtractOp))
2684 .addDef(MaskMul)
2685 .addUse(GR.getSPIRVTypeID(ResType))
2686 .addUse(Mul)
2687 .addUse(GR.getOrCreateConstInt(0, I, EltType, TII, ZeroAsNull))
2688 .addUse(GR.getOrCreateConstInt(8, I, EltType, TII, ZeroAsNull))
2689 .constrainAllUses(TII, TRI, RBI);
2690
2691 // Acc = Acc + A[i] * B[i]
2692 Register Sum =
2693 i < 3 ? MRI->createVirtualRegister(&SPIRV::IDRegClass) : ResVReg;
2694 BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpIAddS))
2695 .addDef(Sum)
2696 .addUse(GR.getSPIRVTypeID(ResType))
2697 .addUse(Acc)
2698 .addUse(MaskMul)
2699 .constrainAllUses(TII, TRI, RBI);
2700
2701 Acc = Sum;
2702 }
2703
2704 return true;
2705}
2706
2707/// Transform saturate(x) to clamp(x, 0.0f, 1.0f) as SPIRV
2708/// does not have a saturate builtin.
2709bool SPIRVInstructionSelector::selectSaturate(Register ResVReg,
2710 SPIRVTypeInst ResType,
2711 MachineInstr &I) const {
2712 assert(I.getNumOperands() == 3);
2713 assert(I.getOperand(2).isReg());
2714 MachineBasicBlock &BB = *I.getParent();
2715 Register VZero = buildZerosValF(ResType, I);
2716 Register VOne = buildOnesValF(ResType, I);
2717
2718 BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpExtInst))
2719 .addDef(ResVReg)
2720 .addUse(GR.getSPIRVTypeID(ResType))
2721 .addImm(static_cast<uint32_t>(SPIRV::InstructionSet::GLSL_std_450))
2722 .addImm(GL::FClamp)
2723 .addUse(I.getOperand(2).getReg())
2724 .addUse(VZero)
2725 .addUse(VOne)
2726 .constrainAllUses(TII, TRI, RBI);
2727 return true;
2728}
2729
2730bool SPIRVInstructionSelector::selectSign(Register ResVReg,
2731 SPIRVTypeInst ResType,
2732 MachineInstr &I) const {
2733 assert(I.getNumOperands() == 3);
2734 assert(I.getOperand(2).isReg());
2735 MachineBasicBlock &BB = *I.getParent();
2736 Register InputRegister = I.getOperand(2).getReg();
2737 SPIRVTypeInst InputType = GR.getSPIRVTypeForVReg(InputRegister);
2738 auto &DL = I.getDebugLoc();
2739
2740 if (!InputType)
2741 report_fatal_error("Input Type could not be determined.");
2742
2743 bool IsFloatTy = GR.isScalarOrVectorOfType(InputRegister, SPIRV::OpTypeFloat);
2744
2745 unsigned SignBitWidth = GR.getScalarOrVectorBitWidth(InputType);
2746 unsigned ResBitWidth = GR.getScalarOrVectorBitWidth(ResType);
2747
2748 bool NeedsConversion = IsFloatTy || SignBitWidth != ResBitWidth;
2749
2750 auto SignOpcode = IsFloatTy ? GL::FSign : GL::SSign;
2751 Register SignReg = NeedsConversion
2752 ? MRI->createVirtualRegister(&SPIRV::IDRegClass)
2753 : ResVReg;
2754
2755 BuildMI(BB, I, DL, TII.get(SPIRV::OpExtInst))
2756 .addDef(SignReg)
2757 .addUse(GR.getSPIRVTypeID(InputType))
2758 .addImm(static_cast<uint32_t>(SPIRV::InstructionSet::GLSL_std_450))
2759 .addImm(SignOpcode)
2760 .addUse(InputRegister)
2761 .constrainAllUses(TII, TRI, RBI);
2762
2763 if (NeedsConversion) {
2764 auto ConvertOpcode = IsFloatTy ? SPIRV::OpConvertFToS : SPIRV::OpSConvert;
2765 BuildMI(*I.getParent(), I, DL, TII.get(ConvertOpcode))
2766 .addDef(ResVReg)
2767 .addUse(GR.getSPIRVTypeID(ResType))
2768 .addUse(SignReg)
2769 .constrainAllUses(TII, TRI, RBI);
2770 }
2771
2772 return true;
2773}
2774
2775bool SPIRVInstructionSelector::selectWaveOpInst(Register ResVReg,
2776 SPIRVTypeInst ResType,
2777 MachineInstr &I,
2778 unsigned Opcode) const {
2779 MachineBasicBlock &BB = *I.getParent();
2780 SPIRVTypeInst IntTy = GR.getOrCreateSPIRVIntegerType(32, I, TII);
2781
2782 auto BMI = BuildMI(BB, I, I.getDebugLoc(), TII.get(Opcode))
2783 .addDef(ResVReg)
2784 .addUse(GR.getSPIRVTypeID(ResType))
2785 .addUse(GR.getOrCreateConstInt(SPIRV::Scope::Subgroup, I,
2786 IntTy, TII, !STI.isShader()));
2787
2788 for (unsigned J = 2; J < I.getNumOperands(); J++) {
2789 BMI.addUse(I.getOperand(J).getReg());
2790 }
2791
2792 BMI.constrainAllUses(TII, TRI, RBI);
2793 return true;
2794}
2795
2796bool SPIRVInstructionSelector::selectWaveActiveCountBits(
2797 Register ResVReg, SPIRVTypeInst ResType, MachineInstr &I) const {
2798
2799 SPIRVTypeInst IntTy = GR.getOrCreateSPIRVIntegerType(32, I, TII);
2800 SPIRVTypeInst BallotType = GR.getOrCreateSPIRVVectorType(IntTy, 4, I, TII);
2801 Register BallotReg = MRI->createVirtualRegister(GR.getRegClass(BallotType));
2802 if (!selectWaveOpInst(BallotReg, BallotType, I,
2803 SPIRV::OpGroupNonUniformBallot))
2804 return false;
2805
2806 MachineBasicBlock &BB = *I.getParent();
2807 BuildMI(BB, I, I.getDebugLoc(),
2808 TII.get(SPIRV::OpGroupNonUniformBallotBitCount))
2809 .addDef(ResVReg)
2810 .addUse(GR.getSPIRVTypeID(ResType))
2811 .addUse(GR.getOrCreateConstInt(SPIRV::Scope::Subgroup, I, IntTy, TII,
2812 !STI.isShader()))
2813 .addImm(SPIRV::GroupOperation::Reduce)
2814 .addUse(BallotReg)
2815 .constrainAllUses(TII, TRI, RBI);
2816
2817 return true;
2818}
2819
2820bool SPIRVInstructionSelector::selectWavePrefixBitCount(Register ResVReg,
2821 SPIRVTypeInst ResType,
2822 MachineInstr &I) const {
2823
2824 assert(I.getNumOperands() == 3);
2825
2826 auto Op = I.getOperand(2);
2827 assert(Op.isReg());
2828
2829 MachineBasicBlock &BB = *I.getParent();
2830 DebugLoc DL = I.getDebugLoc();
2831
2832 Register InputRegister = Op.getReg();
2833 SPIRVTypeInst InputType = GR.getSPIRVTypeForVReg(InputRegister);
2834
2835 if (!InputType)
2836 report_fatal_error("Input Type could not be determined.");
2837
2838 if (InputType->getOpcode() != SPIRV::OpTypeBool)
2839 report_fatal_error("WavePrefixBitCount requires boolean input");
2840
2841 // Types
2842 SPIRVTypeInst Int32Ty = GR.getOrCreateSPIRVIntegerType(32, I, TII);
2843
2844 // Ballot result type: vector<uint32>
2845 // Match DXC: %v4uint for Subgroup size
2846 SPIRVTypeInst BallotTy = GR.getOrCreateSPIRVVectorType(Int32Ty, 4, I, TII);
2847
2848 // Create a vreg for the ballot result
2849 Register BallotVReg = MRI->createVirtualRegister(&SPIRV::IDRegClass);
2850
2851 // 1. OpGroupNonUniformBallot
2852 BuildMI(BB, I, DL, TII.get(SPIRV::OpGroupNonUniformBallot))
2853 .addDef(BallotVReg)
2854 .addUse(GR.getSPIRVTypeID(BallotTy))
2855 .addUse(GR.getOrCreateConstInt(SPIRV::Scope::Subgroup, I, Int32Ty, TII))
2856 .addUse(InputRegister)
2857 .constrainAllUses(TII, TRI, RBI);
2858
2859 // 2. OpGroupNonUniformBallotBitCount
2860 BuildMI(BB, I, DL, TII.get(SPIRV::OpGroupNonUniformBallotBitCount))
2861 .addDef(ResVReg)
2862 .addUse(GR.getSPIRVTypeID(ResType))
2863 .addUse(GR.getOrCreateConstInt(SPIRV::Scope::Subgroup, I, Int32Ty, TII))
2864 .addImm(SPIRV::GroupOperation::ExclusiveScan)
2865 .addUse(BallotVReg)
2866 .constrainAllUses(TII, TRI, RBI);
2867
2868 return true;
2869}
2870
2871bool SPIRVInstructionSelector::selectWaveReduceMax(Register ResVReg,
2872 SPIRVTypeInst ResType,
2873 MachineInstr &I,
2874 bool IsUnsigned) const {
2875 return selectWaveReduce(
2876 ResVReg, ResType, I, IsUnsigned,
2877 [&](Register InputRegister, bool IsUnsigned) {
2878 const bool IsFloatTy =
2879 GR.isScalarOrVectorOfType(InputRegister, SPIRV::OpTypeFloat);
2880 const unsigned IntOp = IsUnsigned ? SPIRV::OpGroupNonUniformUMax
2881 : SPIRV::OpGroupNonUniformSMax;
2882 return IsFloatTy ? SPIRV::OpGroupNonUniformFMax : IntOp;
2883 });
2884}
2885
2886bool SPIRVInstructionSelector::selectWaveReduceMin(Register ResVReg,
2887 SPIRVTypeInst ResType,
2888 MachineInstr &I,
2889 bool IsUnsigned) const {
2890 return selectWaveReduce(
2891 ResVReg, ResType, I, IsUnsigned,
2892 [&](Register InputRegister, bool IsUnsigned) {
2893 const bool IsFloatTy =
2894 GR.isScalarOrVectorOfType(InputRegister, SPIRV::OpTypeFloat);
2895 const unsigned IntOp = IsUnsigned ? SPIRV::OpGroupNonUniformUMin
2896 : SPIRV::OpGroupNonUniformSMin;
2897 return IsFloatTy ? SPIRV::OpGroupNonUniformFMin : IntOp;
2898 });
2899}
2900
2901bool SPIRVInstructionSelector::selectWaveReduceSum(Register ResVReg,
2902 SPIRVTypeInst ResType,
2903 MachineInstr &I) const {
2904 return selectWaveReduce(ResVReg, ResType, I, /*IsUnsigned*/ false,
2905 [&](Register InputRegister, bool IsUnsigned) {
2906 bool IsFloatTy = GR.isScalarOrVectorOfType(
2907 InputRegister, SPIRV::OpTypeFloat);
2908 return IsFloatTy ? SPIRV::OpGroupNonUniformFAdd
2909 : SPIRV::OpGroupNonUniformIAdd;
2910 });
2911}
2912
2913template <typename PickOpcodeFn>
2914bool SPIRVInstructionSelector::selectWaveReduce(
2915 Register ResVReg, SPIRVTypeInst ResType, MachineInstr &I, bool IsUnsigned,
2916 PickOpcodeFn &&PickOpcode) const {
2917 assert(I.getNumOperands() == 3);
2918 assert(I.getOperand(2).isReg());
2919 MachineBasicBlock &BB = *I.getParent();
2920 Register InputRegister = I.getOperand(2).getReg();
2921 SPIRVTypeInst InputType = GR.getSPIRVTypeForVReg(InputRegister);
2922
2923 if (!InputType)
2924 report_fatal_error("Input Type could not be determined.");
2925
2926 SPIRVTypeInst IntTy = GR.getOrCreateSPIRVIntegerType(32, I, TII);
2927 const unsigned Opcode = PickOpcode(InputRegister, IsUnsigned);
2928 BuildMI(BB, I, I.getDebugLoc(), TII.get(Opcode))
2929 .addDef(ResVReg)
2930 .addUse(GR.getSPIRVTypeID(ResType))
2931 .addUse(GR.getOrCreateConstInt(SPIRV::Scope::Subgroup, I, IntTy, TII,
2932 !STI.isShader()))
2933 .addImm(SPIRV::GroupOperation::Reduce)
2934 .addUse(I.getOperand(2).getReg())
2935 .constrainAllUses(TII, TRI, RBI);
2936 return true;
2937}
2938
2939bool SPIRVInstructionSelector::selectWaveExclusiveScanSum(
2940 Register ResVReg, SPIRVTypeInst ResType, MachineInstr &I) const {
2941 return selectWaveExclusiveScan(ResVReg, ResType, I, /*IsUnsigned*/ false,
2942 [&](Register InputRegister, bool IsUnsigned) {
2943 bool IsFloatTy = GR.isScalarOrVectorOfType(
2944 InputRegister, SPIRV::OpTypeFloat);
2945 return IsFloatTy
2946 ? SPIRV::OpGroupNonUniformFAdd
2947 : SPIRV::OpGroupNonUniformIAdd;
2948 });
2949}
2950
2951bool SPIRVInstructionSelector::selectWaveExclusiveScanProduct(
2952 Register ResVReg, SPIRVTypeInst ResType, MachineInstr &I) const {
2953 return selectWaveExclusiveScan(ResVReg, ResType, I, /*IsUnsigned*/ false,
2954 [&](Register InputRegister, bool IsUnsigned) {
2955 bool IsFloatTy = GR.isScalarOrVectorOfType(
2956 InputRegister, SPIRV::OpTypeFloat);
2957 return IsFloatTy
2958 ? SPIRV::OpGroupNonUniformFMul
2959 : SPIRV::OpGroupNonUniformIMul;
2960 });
2961}
2962
2963template <typename PickOpcodeFn>
2964bool SPIRVInstructionSelector::selectWaveExclusiveScan(
2965 Register ResVReg, SPIRVTypeInst ResType, MachineInstr &I, bool IsUnsigned,
2966 PickOpcodeFn &&PickOpcode) const {
2967 assert(I.getNumOperands() == 3);
2968 assert(I.getOperand(2).isReg());
2969 MachineBasicBlock &BB = *I.getParent();
2970 Register InputRegister = I.getOperand(2).getReg();
2971 SPIRVTypeInst InputType = GR.getSPIRVTypeForVReg(InputRegister);
2972
2973 if (!InputType)
2974 report_fatal_error("Input Type could not be determined.");
2975
2976 SPIRVTypeInst IntTy = GR.getOrCreateSPIRVIntegerType(32, I, TII);
2977 const unsigned Opcode = PickOpcode(InputRegister, IsUnsigned);
2978 BuildMI(BB, I, I.getDebugLoc(), TII.get(Opcode))
2979 .addDef(ResVReg)
2980 .addUse(GR.getSPIRVTypeID(ResType))
2981 .addUse(GR.getOrCreateConstInt(SPIRV::Scope::Subgroup, I, IntTy, TII,
2982 !STI.isShader()))
2983 .addImm(SPIRV::GroupOperation::ExclusiveScan)
2984 .addUse(I.getOperand(2).getReg())
2985 .constrainAllUses(TII, TRI, RBI);
2986 return true;
2987}
2988
2989bool SPIRVInstructionSelector::selectBitreverse(Register ResVReg,
2990 SPIRVTypeInst ResType,
2991 MachineInstr &I) const {
2992 MachineBasicBlock &BB = *I.getParent();
2993 BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpBitReverse))
2994 .addDef(ResVReg)
2995 .addUse(GR.getSPIRVTypeID(ResType))
2996 .addUse(I.getOperand(1).getReg())
2997 .constrainAllUses(TII, TRI, RBI);
2998 return true;
2999}
3000
3001bool SPIRVInstructionSelector::selectFreeze(Register ResVReg,
3002 SPIRVTypeInst ResType,
3003 MachineInstr &I) const {
3004 // There is no way to implement `freeze` correctly without support on SPIR-V
3005 // standard side, but we may at least address a simple (static) case when
3006 // undef/poison value presence is obvious. The main benefit of even
3007 // incomplete `freeze` support is preventing of translation from crashing due
3008 // to lack of support on legalization and instruction selection steps.
3009 if (!I.getOperand(0).isReg() || !I.getOperand(1).isReg())
3010 return false;
3011 Register OpReg = I.getOperand(1).getReg();
3012 if (MachineInstr *Def = MRI->getVRegDef(OpReg)) {
3013 if (Def->getOpcode() == TargetOpcode::COPY)
3014 Def = MRI->getVRegDef(Def->getOperand(1).getReg());
3015 Register Reg;
3016 switch (Def->getOpcode()) {
3017 case SPIRV::ASSIGN_TYPE:
3018 if (MachineInstr *AssignToDef =
3019 MRI->getVRegDef(Def->getOperand(1).getReg())) {
3020 if (AssignToDef->getOpcode() == TargetOpcode::G_IMPLICIT_DEF)
3021 Reg = Def->getOperand(2).getReg();
3022 }
3023 break;
3024 case SPIRV::OpUndef:
3025 Reg = Def->getOperand(1).getReg();
3026 break;
3027 }
3028 unsigned DestOpCode;
3029 if (Reg.isValid()) {
3030 DestOpCode = SPIRV::OpConstantNull;
3031 } else {
3032 DestOpCode = TargetOpcode::COPY;
3033 Reg = OpReg;
3034 }
3035 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(DestOpCode))
3036 .addDef(I.getOperand(0).getReg())
3037 .addUse(Reg)
3038 .constrainAllUses(TII, TRI, RBI);
3039 return true;
3040 }
3041 return false;
3042}
3043
3044bool SPIRVInstructionSelector::selectBuildVector(Register ResVReg,
3045 SPIRVTypeInst ResType,
3046 MachineInstr &I) const {
3047 unsigned N = 0;
3048 if (ResType->getOpcode() == SPIRV::OpTypeVector)
3049 N = GR.getScalarOrVectorComponentCount(ResType);
3050 else if (ResType->getOpcode() == SPIRV::OpTypeArray)
3051 N = getArrayComponentCount(MRI, ResType);
3052 else
3053 report_fatal_error("Cannot select G_BUILD_VECTOR with a non-vector result");
3054 if (I.getNumExplicitOperands() - I.getNumExplicitDefs() != N)
3055 report_fatal_error("G_BUILD_VECTOR and the result type are inconsistent");
3056
3057 // check if we may construct a constant vector
3058 bool IsConst = true;
3059 for (unsigned i = I.getNumExplicitDefs();
3060 i < I.getNumExplicitOperands() && IsConst; ++i)
3061 if (!isConstReg(MRI, I.getOperand(i).getReg()))
3062 IsConst = false;
3063
3064 if (!IsConst && N < 2)
3065 report_fatal_error(
3066 "There must be at least two constituent operands in a vector");
3067
3068 MRI->setRegClass(ResVReg, GR.getRegClass(ResType));
3069 auto MIB = BuildMI(*I.getParent(), I, I.getDebugLoc(),
3070 TII.get(IsConst ? SPIRV::OpConstantComposite
3071 : SPIRV::OpCompositeConstruct))
3072 .addDef(ResVReg)
3073 .addUse(GR.getSPIRVTypeID(ResType));
3074 for (unsigned i = I.getNumExplicitDefs(); i < I.getNumExplicitOperands(); ++i)
3075 MIB.addUse(I.getOperand(i).getReg());
3076 MIB.constrainAllUses(TII, TRI, RBI);
3077 return true;
3078}
3079
3080bool SPIRVInstructionSelector::selectSplatVector(Register ResVReg,
3081 SPIRVTypeInst ResType,
3082 MachineInstr &I) const {
3083 unsigned N = 0;
3084 if (ResType->getOpcode() == SPIRV::OpTypeVector)
3085 N = GR.getScalarOrVectorComponentCount(ResType);
3086 else if (ResType->getOpcode() == SPIRV::OpTypeArray)
3087 N = getArrayComponentCount(MRI, ResType);
3088 else
3089 report_fatal_error("Cannot select G_SPLAT_VECTOR with a non-vector result");
3090
3091 unsigned OpIdx = I.getNumExplicitDefs();
3092 if (!I.getOperand(OpIdx).isReg())
3093 report_fatal_error("Unexpected argument in G_SPLAT_VECTOR");
3094
3095 // check if we may construct a constant vector
3096 Register OpReg = I.getOperand(OpIdx).getReg();
3097 bool IsConst = isConstReg(MRI, OpReg);
3098
3099 if (!IsConst && N < 2)
3100 report_fatal_error(
3101 "There must be at least two constituent operands in a vector");
3102
3103 MRI->setRegClass(ResVReg, GR.getRegClass(ResType));
3104 auto MIB = BuildMI(*I.getParent(), I, I.getDebugLoc(),
3105 TII.get(IsConst ? SPIRV::OpConstantComposite
3106 : SPIRV::OpCompositeConstruct))
3107 .addDef(ResVReg)
3108 .addUse(GR.getSPIRVTypeID(ResType));
3109 for (unsigned i = 0; i < N; ++i)
3110 MIB.addUse(OpReg);
3111 MIB.constrainAllUses(TII, TRI, RBI);
3112 return true;
3113}
3114
3115bool SPIRVInstructionSelector::selectDiscard(Register ResVReg,
3116 SPIRVTypeInst ResType,
3117 MachineInstr &I) const {
3118
3119 unsigned Opcode;
3120
3121 if (STI.canUseExtension(
3122 SPIRV::Extension::SPV_EXT_demote_to_helper_invocation) ||
3123 STI.isAtLeastSPIRVVer(llvm::VersionTuple(1, 6))) {
3124 Opcode = SPIRV::OpDemoteToHelperInvocation;
3125 } else {
3126 Opcode = SPIRV::OpKill;
3127 // OpKill must be the last operation of any basic block.
3128 if (MachineInstr *NextI = I.getNextNode()) {
3129 GR.invalidateMachineInstr(NextI);
3130 NextI->eraseFromParent();
3131 }
3132 }
3133
3134 MachineBasicBlock &BB = *I.getParent();
3135 BuildMI(BB, I, I.getDebugLoc(), TII.get(Opcode))
3136 .constrainAllUses(TII, TRI, RBI);
3137 return true;
3138}
3139
3140bool SPIRVInstructionSelector::selectCmp(Register ResVReg,
3141 SPIRVTypeInst ResType, unsigned CmpOpc,
3142 MachineInstr &I) const {
3143 Register Cmp0 = I.getOperand(2).getReg();
3144 Register Cmp1 = I.getOperand(3).getReg();
3145 assert(GR.getSPIRVTypeForVReg(Cmp0)->getOpcode() ==
3146 GR.getSPIRVTypeForVReg(Cmp1)->getOpcode() &&
3147 "CMP operands should have the same type");
3148 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(CmpOpc))
3149 .addDef(ResVReg)
3150 .addUse(GR.getSPIRVTypeID(ResType))
3151 .addUse(Cmp0)
3152 .addUse(Cmp1)
3153 .setMIFlags(I.getFlags())
3154 .constrainAllUses(TII, TRI, RBI);
3155 return true;
3156}
3157
3158bool SPIRVInstructionSelector::selectICmp(Register ResVReg,
3159 SPIRVTypeInst ResType,
3160 MachineInstr &I) const {
3161 auto Pred = I.getOperand(1).getPredicate();
3162 unsigned CmpOpc;
3163
3164 Register CmpOperand = I.getOperand(2).getReg();
3165 if (GR.isScalarOfType(CmpOperand, SPIRV::OpTypePointer))
3166 CmpOpc = getPtrCmpOpcode(Pred);
3167 else if (GR.isScalarOrVectorOfType(CmpOperand, SPIRV::OpTypeBool))
3168 CmpOpc = getBoolCmpOpcode(Pred);
3169 else
3170 CmpOpc = getICmpOpcode(Pred);
3171 return selectCmp(ResVReg, ResType, CmpOpc, I);
3172}
3173
3174Register
3175SPIRVInstructionSelector::buildI32Constant(uint32_t Val, MachineInstr &I,
3176 SPIRVTypeInst ResType) const {
3177 Type *LLVMTy = IntegerType::get(GR.CurMF->getFunction().getContext(), 32);
3178 SPIRVTypeInst SpvI32Ty =
3179 ResType ? ResType : GR.getOrCreateSPIRVIntegerType(32, I, TII);
3180 // Find a constant in DT or build a new one.
3181 auto ConstInt = ConstantInt::get(LLVMTy, Val);
3182 Register NewReg = GR.find(ConstInt, GR.CurMF);
3183 if (!NewReg.isValid()) {
3184 NewReg = MRI->createGenericVirtualRegister(LLT::scalar(64));
3185 MachineBasicBlock &BB = *I.getParent();
3186 MachineInstr *MI =
3187 Val == 0
3188 ? BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpConstantNull))
3189 .addDef(NewReg)
3190 .addUse(GR.getSPIRVTypeID(SpvI32Ty))
3191 : BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpConstantI))
3192 .addDef(NewReg)
3193 .addUse(GR.getSPIRVTypeID(SpvI32Ty))
3194 .addImm(APInt(32, Val).getZExtValue());
3195 constrainSelectedInstRegOperands(*MI, TII, TRI, RBI);
3196 GR.add(ConstInt, MI);
3197 }
3198 return NewReg;
3199}
3200
3201bool SPIRVInstructionSelector::selectFCmp(Register ResVReg,
3202 SPIRVTypeInst ResType,
3203 MachineInstr &I) const {
3204 unsigned CmpOp = getFCmpOpcode(I.getOperand(1).getPredicate());
3205 return selectCmp(ResVReg, ResType, CmpOp, I);
3206}
3207
3208bool SPIRVInstructionSelector::selectExp10(Register ResVReg,
3209 SPIRVTypeInst ResType,
3210 MachineInstr &I) const {
3211 if (STI.canUseExtInstSet(SPIRV::InstructionSet::OpenCL_std)) {
3212 return selectExtInst(ResVReg, ResType, I, CL::exp10);
3213 }
3214
3215 if (STI.canUseExtInstSet(SPIRV::InstructionSet::GLSL_std_450)) {
3216 /// There is no exp10 in GLSL. Use exp10(x) = exp2(x * log2(10)) instead
3217 /// log2(10) ~= 3.3219280948874l
3218
3219 if (ResType->getOpcode() != SPIRV::OpTypeVector &&
3220 ResType->getOpcode() != SPIRV::OpTypeFloat)
3221 return false;
3222
3223 MachineIRBuilder MIRBuilder(I);
3224
3225 SPIRVTypeInst SpirvScalarType = ResType->getOpcode() == SPIRV::OpTypeVector
3226 ? SPIRVTypeInst(GR.getSPIRVTypeForVReg(
3227 ResType->getOperand(1).getReg()))
3228 : ResType;
3229
3230 assert(SpirvScalarType->getOperand(1).getImm() == 32 &&
3231 "only float operands supported by GLSL extended math");
3232
3233 Register ConstReg = GR.buildConstantFP(APFloat(3.3219280948874f),
3234 MIRBuilder, SpirvScalarType);
3235 Register ArgReg = MRI->createVirtualRegister(GR.getRegClass(ResType));
3236 auto Opcode = ResType->getOpcode() == SPIRV::OpTypeVector
3237 ? SPIRV::OpVectorTimesScalar
3238 : SPIRV::OpFMulS;
3239
3240 if (!selectOpWithSrcs(ArgReg, ResType, I,
3241 {I.getOperand(1).getReg(), ConstReg}, Opcode))
3242 return false;
3243 if (!selectExtInst(ResVReg, ResType, I,
3244 {{SPIRV::InstructionSet::GLSL_std_450, GL::Exp2}}, false,
3245 false, {ArgReg}))
3246 return false;
3247
3248 return true;
3249 }
3250
3251 return false;
3252}
3253
3254Register SPIRVInstructionSelector::buildZerosVal(SPIRVTypeInst ResType,
3255 MachineInstr &I) const {
3256 // OpenCL uses nulls for Zero. In HLSL we don't use null constants.
3257 bool ZeroAsNull = !STI.isShader();
3258 if (ResType->getOpcode() == SPIRV::OpTypeVector)
3259 return GR.getOrCreateConstVector(0UL, I, ResType, TII, ZeroAsNull);
3260 return GR.getOrCreateConstInt(0, I, ResType, TII, ZeroAsNull);
3261}
3262
3263bool SPIRVInstructionSelector::isScalarOrVectorIntConstantZero(
3264 Register Reg) const {
3265 SPIRVTypeInst Type = GR.getSPIRVTypeForVReg(Reg);
3266 if (!Type)
3267 return false;
3268 SPIRVTypeInst CompType = GR.getScalarOrVectorComponentType(Type);
3269 if (!CompType || CompType->getOpcode() != SPIRV::OpTypeInt)
3270 return false;
3271
3272 auto IsZero = [this](Register Reg) {
3273 MachineInstr *Def = getDefInstrMaybeConstant(Reg, MRI);
3274 if (!Def)
3275 return false;
3276
3277 if (Def->getOpcode() == SPIRV::OpConstantNull)
3278 return true;
3279
3280 if (Def->getOpcode() == TargetOpcode::G_CONSTANT ||
3281 Def->getOpcode() == SPIRV::OpConstantI)
3282 return getIConstVal(Reg, MRI) == 0;
3283
3284 return false;
3285 };
3286
3287 if (IsZero(Reg))
3288 return true;
3289
3290 MachineInstr *Def = MRI->getVRegDef(Reg);
3291 if (!Def)
3292 return false;
3293
3294 if (Def->getOpcode() == TargetOpcode::G_BUILD_VECTOR ||
3295 (Def->getOpcode() == TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS &&
3296 cast<GIntrinsic>(Def)->getIntrinsicID() ==
3297 Intrinsic::spv_const_composite)) {
3298 unsigned StartOp = Def->getOpcode() == TargetOpcode::G_BUILD_VECTOR ? 1 : 2;
3299 for (unsigned i = StartOp; i < Def->getNumOperands(); ++i) {
3300 if (!IsZero(Def->getOperand(i).getReg()))
3301 return false;
3302 }
3303 return true;
3304 }
3305
3306 return false;
3307}
3308
3309Register SPIRVInstructionSelector::buildZerosValF(SPIRVTypeInst ResType,
3310 MachineInstr &I) const {
3311 // OpenCL uses nulls for Zero. In HLSL we don't use null constants.
3312 bool ZeroAsNull = !STI.isShader();
3313 APFloat VZero = getZeroFP(GR.getTypeForSPIRVType(ResType));
3314 if (ResType->getOpcode() == SPIRV::OpTypeVector)
3315 return GR.getOrCreateConstVector(VZero, I, ResType, TII, ZeroAsNull);
3316 return GR.getOrCreateConstFP(VZero, I, ResType, TII, ZeroAsNull);
3317}
3318
3319Register SPIRVInstructionSelector::buildOnesValF(SPIRVTypeInst ResType,
3320 MachineInstr &I) const {
3321 // OpenCL uses nulls for Zero. In HLSL we don't use null constants.
3322 bool ZeroAsNull = !STI.isShader();
3323 APFloat VOne = getOneFP(GR.getTypeForSPIRVType(ResType));
3324 if (ResType->getOpcode() == SPIRV::OpTypeVector)
3325 return GR.getOrCreateConstVector(VOne, I, ResType, TII, ZeroAsNull);
3326 return GR.getOrCreateConstFP(VOne, I, ResType, TII, ZeroAsNull);
3327}
3328
3329Register SPIRVInstructionSelector::buildOnesVal(bool AllOnes,
3330 SPIRVTypeInst ResType,
3331 MachineInstr &I) const {
3332 unsigned BitWidth = GR.getScalarOrVectorBitWidth(ResType);
3333 APInt One =
3334 AllOnes ? APInt::getAllOnes(BitWidth) : APInt::getOneBitSet(BitWidth, 0);
3335 if (ResType->getOpcode() == SPIRV::OpTypeVector)
3336 return GR.getOrCreateConstVector(One, I, ResType, TII);
3337 return GR.getOrCreateConstInt(One, I, ResType, TII);
3338}
3339
3340bool SPIRVInstructionSelector::selectSelect(Register ResVReg,
3341 SPIRVTypeInst ResType,
3342 MachineInstr &I) const {
3343 Register SelectFirstArg = I.getOperand(2).getReg();
3344 Register SelectSecondArg = I.getOperand(3).getReg();
3345 assert(ResType == GR.getSPIRVTypeForVReg(SelectFirstArg) &&
3346 ResType == GR.getSPIRVTypeForVReg(SelectSecondArg));
3347
3348 bool IsFloatTy =
3349 GR.isScalarOrVectorOfType(SelectFirstArg, SPIRV::OpTypeFloat);
3350 bool IsPtrTy =
3351 GR.isScalarOrVectorOfType(SelectFirstArg, SPIRV::OpTypePointer);
3352 bool IsVectorTy = GR.getSPIRVTypeForVReg(SelectFirstArg)->getOpcode() ==
3353 SPIRV::OpTypeVector;
3354
3355 bool IsScalarBool =
3356 GR.isScalarOfType(I.getOperand(1).getReg(), SPIRV::OpTypeBool);
3357 unsigned Opcode;
3358 if (IsVectorTy) {
3359 if (IsFloatTy) {
3360 Opcode = IsScalarBool ? SPIRV::OpSelectVFSCond : SPIRV::OpSelectVFVCond;
3361 } else if (IsPtrTy) {
3362 Opcode = IsScalarBool ? SPIRV::OpSelectVPSCond : SPIRV::OpSelectVPVCond;
3363 } else {
3364 Opcode = IsScalarBool ? SPIRV::OpSelectVISCond : SPIRV::OpSelectVIVCond;
3365 }
3366 } else {
3367 if (IsFloatTy) {
3368 Opcode = IsScalarBool ? SPIRV::OpSelectSFSCond : SPIRV::OpSelectVFVCond;
3369 } else if (IsPtrTy) {
3370 Opcode = IsScalarBool ? SPIRV::OpSelectSPSCond : SPIRV::OpSelectVPVCond;
3371 } else {
3372 Opcode = IsScalarBool ? SPIRV::OpSelectSISCond : SPIRV::OpSelectVIVCond;
3373 }
3374 }
3375 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(Opcode))
3376 .addDef(ResVReg)
3377 .addUse(GR.getSPIRVTypeID(ResType))
3378 .addUse(I.getOperand(1).getReg())
3379 .addUse(SelectFirstArg)
3380 .addUse(SelectSecondArg)
3381 .constrainAllUses(TII, TRI, RBI);
3382 return true;
3383}
3384
3385bool SPIRVInstructionSelector::selectSelectDefaultArgs(Register ResVReg,
3386 SPIRVTypeInst ResType,
3387 MachineInstr &I,
3388 bool IsSigned) const {
3389 // To extend a bool, we need to use OpSelect between constants.
3390 Register ZeroReg = buildZerosVal(ResType, I);
3391 Register OneReg = buildOnesVal(IsSigned, ResType, I);
3392 bool IsScalarBool =
3393 GR.isScalarOfType(I.getOperand(1).getReg(), SPIRV::OpTypeBool);
3394 unsigned Opcode =
3395 IsScalarBool ? SPIRV::OpSelectSISCond : SPIRV::OpSelectVIVCond;
3396 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(Opcode))
3397 .addDef(ResVReg)
3398 .addUse(GR.getSPIRVTypeID(ResType))
3399 .addUse(I.getOperand(1).getReg())
3400 .addUse(OneReg)
3401 .addUse(ZeroReg)
3402 .constrainAllUses(TII, TRI, RBI);
3403 return true;
3404}
3405
3406bool SPIRVInstructionSelector::selectIToF(Register ResVReg,
3407 SPIRVTypeInst ResType,
3408 MachineInstr &I, bool IsSigned,
3409 unsigned Opcode) const {
3410 Register SrcReg = I.getOperand(1).getReg();
3411 // We can convert bool value directly to float type without OpConvert*ToF,
3412 // however the translator generates OpSelect+OpConvert*ToF, so we do the same.
3413 if (GR.isScalarOrVectorOfType(I.getOperand(1).getReg(), SPIRV::OpTypeBool)) {
3414 unsigned BitWidth = GR.getScalarOrVectorBitWidth(ResType);
3415 SPIRVTypeInst TmpType = GR.getOrCreateSPIRVIntegerType(BitWidth, I, TII);
3416 if (ResType->getOpcode() == SPIRV::OpTypeVector) {
3417 const unsigned NumElts = ResType->getOperand(2).getImm();
3418 TmpType = GR.getOrCreateSPIRVVectorType(TmpType, NumElts, I, TII);
3419 }
3420 SrcReg = createVirtualRegister(TmpType, &GR, MRI, MRI->getMF());
3421 selectSelectDefaultArgs(SrcReg, TmpType, I, false);
3422 }
3423 return selectOpWithSrcs(ResVReg, ResType, I, {SrcReg}, Opcode);
3424}
3425
3426bool SPIRVInstructionSelector::selectExt(Register ResVReg,
3427 SPIRVTypeInst ResType, MachineInstr &I,
3428 bool IsSigned) const {
3429 Register SrcReg = I.getOperand(1).getReg();
3430 if (GR.isScalarOrVectorOfType(SrcReg, SPIRV::OpTypeBool))
3431 return selectSelectDefaultArgs(ResVReg, ResType, I, IsSigned);
3432
3433 SPIRVTypeInst SrcType = GR.getSPIRVTypeForVReg(SrcReg);
3434 if (ResType == SrcType)
3435 return BuildCOPY(ResVReg, SrcReg, I);
3436
3437 unsigned Opcode = IsSigned ? SPIRV::OpSConvert : SPIRV::OpUConvert;
3438 return selectUnOp(ResVReg, ResType, I, Opcode);
3439}
3440
3441bool SPIRVInstructionSelector::selectSUCmp(Register ResVReg,
3442 SPIRVTypeInst ResType,
3443 MachineInstr &I,
3444 bool IsSigned) const {
3445 MachineIRBuilder MIRBuilder(I);
3446 MachineRegisterInfo *MRI = MIRBuilder.getMRI();
3447 MachineBasicBlock &BB = *I.getParent();
3448 // Ensure we have bool.
3449 SPIRVTypeInst BoolType = GR.getOrCreateSPIRVBoolType(I, TII);
3450 unsigned N = GR.getScalarOrVectorComponentCount(ResType);
3451 if (N > 1)
3452 BoolType = GR.getOrCreateSPIRVVectorType(BoolType, N, I, TII);
3453 Register BoolTypeReg = GR.getSPIRVTypeID(BoolType);
3454 // Build less-than-equal and less-than.
3455 // TODO: replace with one-liner createVirtualRegister() from
3456 // llvm/lib/Target/SPIRV/SPIRVUtils.cpp when PR #116609 is merged.
3457 Register IsLessEqReg = MRI->createVirtualRegister(GR.getRegClass(ResType));
3458 MRI->setType(IsLessEqReg, LLT::scalar(64));
3459 GR.assignSPIRVTypeToVReg(ResType, IsLessEqReg, MIRBuilder.getMF());
3460 BuildMI(BB, I, I.getDebugLoc(),
3461 TII.get(IsSigned ? SPIRV::OpSLessThanEqual : SPIRV::OpULessThanEqual))
3462 .addDef(IsLessEqReg)
3463 .addUse(BoolTypeReg)
3464 .addUse(I.getOperand(1).getReg())
3465 .addUse(I.getOperand(2).getReg())
3466 .constrainAllUses(TII, TRI, RBI);
3467 Register IsLessReg = MRI->createVirtualRegister(GR.getRegClass(ResType));
3468 MRI->setType(IsLessReg, LLT::scalar(64));
3469 GR.assignSPIRVTypeToVReg(ResType, IsLessReg, MIRBuilder.getMF());
3470 BuildMI(BB, I, I.getDebugLoc(),
3471 TII.get(IsSigned ? SPIRV::OpSLessThan : SPIRV::OpULessThan))
3472 .addDef(IsLessReg)
3473 .addUse(BoolTypeReg)
3474 .addUse(I.getOperand(1).getReg())
3475 .addUse(I.getOperand(2).getReg())
3476 .constrainAllUses(TII, TRI, RBI);
3477 // Build selects.
3478 Register ResTypeReg = GR.getSPIRVTypeID(ResType);
3479 Register NegOneOrZeroReg =
3480 MRI->createVirtualRegister(GR.getRegClass(ResType));
3481 MRI->setType(NegOneOrZeroReg, LLT::scalar(64));
3482 GR.assignSPIRVTypeToVReg(ResType, NegOneOrZeroReg, MIRBuilder.getMF());
3483 unsigned SelectOpcode =
3484 N > 1 ? SPIRV::OpSelectVIVCond : SPIRV::OpSelectSISCond;
3485 BuildMI(BB, I, I.getDebugLoc(), TII.get(SelectOpcode))
3486 .addDef(NegOneOrZeroReg)
3487 .addUse(ResTypeReg)
3488 .addUse(IsLessReg)
3489 .addUse(buildOnesVal(true, ResType, I)) // -1
3490 .addUse(buildZerosVal(ResType, I))
3491 .constrainAllUses(TII, TRI, RBI);
3492 BuildMI(BB, I, I.getDebugLoc(), TII.get(SelectOpcode))
3493 .addDef(ResVReg)
3494 .addUse(ResTypeReg)
3495 .addUse(IsLessEqReg)
3496 .addUse(NegOneOrZeroReg) // -1 or 0
3497 .addUse(buildOnesVal(false, ResType, I))
3498 .constrainAllUses(TII, TRI, RBI);
3499 return true;
3500}
3501
3502bool SPIRVInstructionSelector::selectIntToBool(Register IntReg,
3503 Register ResVReg,
3504 MachineInstr &I,
3505 SPIRVTypeInst IntTy,
3506 SPIRVTypeInst BoolTy) const {
3507 // To truncate to a bool, we use OpBitwiseAnd 1 and OpINotEqual to zero.
3508 Register BitIntReg = createVirtualRegister(IntTy, &GR, MRI, MRI->getMF());
3509 bool IsVectorTy = IntTy->getOpcode() == SPIRV::OpTypeVector;
3510 unsigned Opcode = IsVectorTy ? SPIRV::OpBitwiseAndV : SPIRV::OpBitwiseAndS;
3511 Register Zero = buildZerosVal(IntTy, I);
3512 Register One = buildOnesVal(false, IntTy, I);
3513 MachineBasicBlock &BB = *I.getParent();
3514 BuildMI(BB, I, I.getDebugLoc(), TII.get(Opcode))
3515 .addDef(BitIntReg)
3516 .addUse(GR.getSPIRVTypeID(IntTy))
3517 .addUse(IntReg)
3518 .addUse(One)
3519 .constrainAllUses(TII, TRI, RBI);
3520 BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpINotEqual))
3521 .addDef(ResVReg)
3522 .addUse(GR.getSPIRVTypeID(BoolTy))
3523 .addUse(BitIntReg)
3524 .addUse(Zero)
3525 .constrainAllUses(TII, TRI, RBI);
3526 return true;
3527}
3528
3529bool SPIRVInstructionSelector::selectTrunc(Register ResVReg,
3530 SPIRVTypeInst ResType,
3531 MachineInstr &I) const {
3532 Register IntReg = I.getOperand(1).getReg();
3533 const SPIRVTypeInst ArgType = GR.getSPIRVTypeForVReg(IntReg);
3534 if (GR.isScalarOrVectorOfType(ResVReg, SPIRV::OpTypeBool))
3535 return selectIntToBool(IntReg, ResVReg, I, ArgType, ResType);
3536 if (ArgType == ResType)
3537 return BuildCOPY(ResVReg, IntReg, I);
3538 bool IsSigned = GR.isScalarOrVectorSigned(ResType);
3539 unsigned Opcode = IsSigned ? SPIRV::OpSConvert : SPIRV::OpUConvert;
3540 return selectUnOp(ResVReg, ResType, I, Opcode);
3541}
3542
3543bool SPIRVInstructionSelector::selectConst(Register ResVReg,
3544 SPIRVTypeInst ResType,
3545 MachineInstr &I) const {
3546 unsigned Opcode = I.getOpcode();
3547 unsigned TpOpcode = ResType->getOpcode();
3548 Register Reg;
3549 if (TpOpcode == SPIRV::OpTypePointer || TpOpcode == SPIRV::OpTypeEvent) {
3550 assert(Opcode == TargetOpcode::G_CONSTANT &&
3551 I.getOperand(1).getCImm()->isZero());
3552 MachineBasicBlock &DepMBB = I.getMF()->front();
3553 MachineIRBuilder MIRBuilder(DepMBB, DepMBB.getFirstNonPHI());
3554 Reg = GR.getOrCreateConstNullPtr(MIRBuilder, ResType);
3555 } else if (Opcode == TargetOpcode::G_FCONSTANT) {
3556 Reg = GR.getOrCreateConstFP(I.getOperand(1).getFPImm()->getValue(), I,
3557 ResType, TII, !STI.isShader());
3558 } else {
3559 Reg = GR.getOrCreateConstInt(I.getOperand(1).getCImm()->getValue(), I,
3560 ResType, TII, !STI.isShader());
3561 }
3562 return Reg == ResVReg ? true : BuildCOPY(ResVReg, Reg, I);
3563}
3564
3565bool SPIRVInstructionSelector::selectOpUndef(Register ResVReg,
3566 SPIRVTypeInst ResType,
3567 MachineInstr &I) const {
3568 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(SPIRV::OpUndef))
3569 .addDef(ResVReg)
3570 .addUse(GR.getSPIRVTypeID(ResType))
3571 .constrainAllUses(TII, TRI, RBI);
3572 return true;
3573}
3574
3575bool SPIRVInstructionSelector::selectInsertVal(Register ResVReg,
3576 SPIRVTypeInst ResType,
3577 MachineInstr &I) const {
3578 MachineBasicBlock &BB = *I.getParent();
3579 auto MIB = BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpCompositeInsert))
3580 .addDef(ResVReg)
3581 .addUse(GR.getSPIRVTypeID(ResType))
3582 // object to insert
3583 .addUse(I.getOperand(3).getReg())
3584 // composite to insert into
3585 .addUse(I.getOperand(2).getReg());
3586 for (unsigned i = 4; i < I.getNumOperands(); i++)
3587 MIB.addImm(foldImm(I.getOperand(i), MRI));
3588 MIB.constrainAllUses(TII, TRI, RBI);
3589 return true;
3590}
3591
3592bool SPIRVInstructionSelector::selectExtractVal(Register ResVReg,
3593 SPIRVTypeInst ResType,
3594 MachineInstr &I) const {
3595 Type *MaybeResTy = nullptr;
3596 StringRef ResName;
3597 if (GR.findValueAttrs(&I, MaybeResTy, ResName) &&
3598 MaybeResTy != GR.getTypeForSPIRVType(ResType)) {
3599 assert((!MaybeResTy || MaybeResTy->isAggregateType()) &&
3600 "Expected aggregate type for extractv instruction");
3601 ResType = GR.getOrCreateSPIRVType(MaybeResTy, I,
3602 SPIRV::AccessQualifier::ReadWrite, false);
3603 GR.assignSPIRVTypeToVReg(ResType, ResVReg, *I.getMF());
3604 }
3605 MachineBasicBlock &BB = *I.getParent();
3606 auto MIB = BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpCompositeExtract))
3607 .addDef(ResVReg)
3608 .addUse(GR.getSPIRVTypeID(ResType))
3609 .addUse(I.getOperand(2).getReg());
3610 for (unsigned i = 3; i < I.getNumOperands(); i++)
3611 MIB.addImm(foldImm(I.getOperand(i), MRI));
3612 MIB.constrainAllUses(TII, TRI, RBI);
3613 return true;
3614}
3615
3616bool SPIRVInstructionSelector::selectInsertElt(Register ResVReg,
3617 SPIRVTypeInst ResType,
3618 MachineInstr &I) const {
3619 if (getImm(I.getOperand(4), MRI))
3620 return selectInsertVal(ResVReg, ResType, I);
3621 MachineBasicBlock &BB = *I.getParent();
3622 BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpVectorInsertDynamic))
3623 .addDef(ResVReg)
3624 .addUse(GR.getSPIRVTypeID(ResType))
3625 .addUse(I.getOperand(2).getReg())
3626 .addUse(I.getOperand(3).getReg())
3627 .addUse(I.getOperand(4).getReg())
3628 .constrainAllUses(TII, TRI, RBI);
3629 return true;
3630}
3631
3632bool SPIRVInstructionSelector::selectExtractElt(Register ResVReg,
3633 SPIRVTypeInst ResType,
3634 MachineInstr &I) const {
3635 if (getImm(I.getOperand(3), MRI))
3636 return selectExtractVal(ResVReg, ResType, I);
3637 MachineBasicBlock &BB = *I.getParent();
3638 BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpVectorExtractDynamic))
3639 .addDef(ResVReg)
3640 .addUse(GR.getSPIRVTypeID(ResType))
3641 .addUse(I.getOperand(2).getReg())
3642 .addUse(I.getOperand(3).getReg())
3643 .constrainAllUses(TII, TRI, RBI);
3644 return true;
3645}
3646
3647bool SPIRVInstructionSelector::selectGEP(Register ResVReg,
3648 SPIRVTypeInst ResType,
3649 MachineInstr &I) const {
3650 const bool IsGEPInBounds = I.getOperand(2).getImm();
3651
3652 // OpAccessChain could be used for OpenCL, but the SPIRV-LLVM Translator only
3653 // relies on PtrAccessChain, so we'll try not to deviate. For Vulkan however,
3654 // we have to use Op[InBounds]AccessChain.
3655 const unsigned Opcode = STI.isLogicalSPIRV()
3656 ? (IsGEPInBounds ? SPIRV::OpInBoundsAccessChain
3657 : SPIRV::OpAccessChain)
3658 : (IsGEPInBounds ? SPIRV::OpInBoundsPtrAccessChain
3659 : SPIRV::OpPtrAccessChain);
3660
3661 auto Res = BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(Opcode))
3662 .addDef(ResVReg)
3663 .addUse(GR.getSPIRVTypeID(ResType))
3664 // Object to get a pointer to.
3665 .addUse(I.getOperand(3).getReg());
3666 assert(
3667 (Opcode == SPIRV::OpPtrAccessChain ||
3668 Opcode == SPIRV::OpInBoundsPtrAccessChain ||
3669 (getImm(I.getOperand(4), MRI) && foldImm(I.getOperand(4), MRI) == 0)) &&
3670 "Cannot translate GEP to OpAccessChain. First index must be 0.");
3671
3672 // Adding indices.
3673 const unsigned StartingIndex =
3674 (Opcode == SPIRV::OpAccessChain || Opcode == SPIRV::OpInBoundsAccessChain)
3675 ? 5
3676 : 4;
3677 for (unsigned i = StartingIndex; i < I.getNumExplicitOperands(); ++i)
3678 Res.addUse(I.getOperand(i).getReg());
3679 Res.constrainAllUses(TII, TRI, RBI);
3680 return true;
3681}
3682
3683// Maybe wrap a value into OpSpecConstantOp
3684bool SPIRVInstructionSelector::wrapIntoSpecConstantOp(
3685 MachineInstr &I, SmallVector<Register> &CompositeArgs) const {
3686 unsigned Lim = I.getNumExplicitOperands();
3687 for (unsigned i = I.getNumExplicitDefs() + 1; i < Lim; ++i) {
3688 Register OpReg = I.getOperand(i).getReg();
3689 MachineInstr *OpDefine = MRI->getVRegDef(OpReg);
3690 SPIRVTypeInst OpType = GR.getSPIRVTypeForVReg(OpReg);
3691 if (!OpDefine || !OpType || isConstReg(MRI, OpDefine) ||
3692 OpDefine->getOpcode() == TargetOpcode::G_ADDRSPACE_CAST ||
3693 OpDefine->getOpcode() == TargetOpcode::G_INTTOPTR ||
3694 GR.isAggregateType(OpType)) {
3695 // The case of G_ADDRSPACE_CAST inside spv_const_composite() is processed
3696 // by selectAddrSpaceCast(), and G_INTTOPTR is processed by selectUnOp()
3697 CompositeArgs.push_back(OpReg);
3698 continue;
3699 }
3700 MachineFunction *MF = I.getMF();
3701 Register WrapReg = GR.find(OpDefine, MF);
3702 if (WrapReg.isValid()) {
3703 CompositeArgs.push_back(WrapReg);
3704 continue;
3705 }
3706 // Create a new register for the wrapper
3707 WrapReg = MRI->createVirtualRegister(GR.getRegClass(OpType));
3708 CompositeArgs.push_back(WrapReg);
3709 // Decorate the wrapper register and generate a new instruction
3710 MRI->setType(WrapReg, LLT::pointer(0, 64));
3711 GR.assignSPIRVTypeToVReg(OpType, WrapReg, *MF);
3712 auto MIB = BuildMI(*I.getParent(), I, I.getDebugLoc(),
3713 TII.get(SPIRV::OpSpecConstantOp))
3714 .addDef(WrapReg)
3715 .addUse(GR.getSPIRVTypeID(OpType))
3716 .addImm(static_cast<uint32_t>(SPIRV::Opcode::Bitcast))
3717 .addUse(OpReg);
3718 GR.add(OpDefine, MIB);
3719 MIB.constrainAllUses(TII, TRI, RBI);
3720 }
3721 return true;
3722}
3723
3724bool SPIRVInstructionSelector::selectDerivativeInst(
3725 Register ResVReg, SPIRVTypeInst ResType, MachineInstr &I,
3726 const unsigned DPdOpCode) const {
3727 // TODO: This should check specifically for Fragment Execution Model, but STI
3728 // doesn't provide that information yet. See #167562
3729 errorIfInstrOutsideShader(I);
3730
3731 // If the arg/result types are half then we need to wrap the instr in
3732 // conversions to float
3733 // This case occurs because a half arg/result is legal in HLSL but not spirv.
3734 Register SrcReg = I.getOperand(2).getReg();
3735 SPIRVTypeInst SrcType = GR.getSPIRVTypeForVReg(SrcReg);
3736 unsigned BitWidth = std::min(GR.getScalarOrVectorBitWidth(SrcType),
3737 GR.getScalarOrVectorBitWidth(ResType));
3738 if (BitWidth == 32)
3739 return BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(DPdOpCode))
3740 .addDef(ResVReg)
3741 .addUse(GR.getSPIRVTypeID(ResType))
3742 .addUse(I.getOperand(2).getReg());
3743
3744 MachineIRBuilder MIRBuilder(I);
3745 unsigned componentCount = GR.getScalarOrVectorComponentCount(SrcType);
3746 SPIRVTypeInst F32ConvertTy = GR.getOrCreateSPIRVFloatType(32, I, TII);
3747 if (componentCount != 1)
3748 F32ConvertTy = GR.getOrCreateSPIRVVectorType(F32ConvertTy, componentCount,
3749 MIRBuilder, false);
3750
3751 const TargetRegisterClass *RegClass = GR.getRegClass(SrcType);
3752 Register ConvertToVReg = MRI->createVirtualRegister(RegClass);
3753 Register DpdOpVReg = MRI->createVirtualRegister(RegClass);
3754
3755 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(SPIRV::OpFConvert))
3756 .addDef(ConvertToVReg)
3757 .addUse(GR.getSPIRVTypeID(F32ConvertTy))
3758 .addUse(SrcReg)
3759 .constrainAllUses(TII, TRI, RBI);
3760 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(DPdOpCode))
3761 .addDef(DpdOpVReg)
3762 .addUse(GR.getSPIRVTypeID(F32ConvertTy))
3763 .addUse(ConvertToVReg)
3764 .constrainAllUses(TII, TRI, RBI);
3765 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(SPIRV::OpFConvert))
3766 .addDef(ResVReg)
3767 .addUse(GR.getSPIRVTypeID(ResType))
3768 .addUse(DpdOpVReg)
3769 .constrainAllUses(TII, TRI, RBI);
3770 return true;
3771}
3772
3773bool SPIRVInstructionSelector::selectIntrinsic(Register ResVReg,
3774 SPIRVTypeInst ResType,
3775 MachineInstr &I) const {
3776 MachineBasicBlock &BB = *I.getParent();
3777 Intrinsic::ID IID = cast<GIntrinsic>(I).getIntrinsicID();
3778 switch (IID) {
3779 case Intrinsic::spv_load:
3780 return selectLoad(ResVReg, ResType, I);
3781 case Intrinsic::spv_store:
3782 return selectStore(I);
3783 case Intrinsic::spv_extractv:
3784 return selectExtractVal(ResVReg, ResType, I);
3785 case Intrinsic::spv_insertv:
3786 return selectInsertVal(ResVReg, ResType, I);
3787 case Intrinsic::spv_extractelt:
3788 return selectExtractElt(ResVReg, ResType, I);
3789 case Intrinsic::spv_insertelt:
3790 return selectInsertElt(ResVReg, ResType, I);
3791 case Intrinsic::spv_gep:
3792 return selectGEP(ResVReg, ResType, I);
3793 case Intrinsic::spv_bitcast: {
3794 Register OpReg = I.getOperand(2).getReg();
3795 SPIRVTypeInst OpType =
3796 OpReg.isValid() ? GR.getSPIRVTypeForVReg(OpReg) : nullptr;
3797 if (!GR.isBitcastCompatible(ResType, OpType))
3798 report_fatal_error("incompatible result and operand types in a bitcast");
3799 return selectOpWithSrcs(ResVReg, ResType, I, {OpReg}, SPIRV::OpBitcast);
3800 }
3801 case Intrinsic::spv_unref_global:
3802 case Intrinsic::spv_init_global: {
3803 MachineInstr *MI = MRI->getVRegDef(I.getOperand(1).getReg());
3804 MachineInstr *Init = I.getNumExplicitOperands() > 2
3805 ? MRI->getVRegDef(I.getOperand(2).getReg())
3806 : nullptr;
3807 assert(MI);
3808 Register GVarVReg = MI->getOperand(0).getReg();
3809 if (!selectGlobalValue(GVarVReg, *MI, Init))
3810 return false;
3811 // We violate SSA form by inserting OpVariable and still having a gMIR
3812 // instruction %vreg = G_GLOBAL_VALUE @gvar. We need to fix this by erasing
3813 // the duplicated definition.
3814 if (MI->getOpcode() == TargetOpcode::G_GLOBAL_VALUE) {
3815 GR.invalidateMachineInstr(MI);
3816 MI->eraseFromParent();
3817 }
3818 return true;
3819 }
3820 case Intrinsic::spv_undef: {
3821 auto MIB = BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpUndef))
3822 .addDef(ResVReg)
3823 .addUse(GR.getSPIRVTypeID(ResType));
3824 MIB.constrainAllUses(TII, TRI, RBI);
3825 return true;
3826 }
3827 case Intrinsic::spv_const_composite: {
3828 // If no values are attached, the composite is null constant.
3829 bool IsNull = I.getNumExplicitDefs() + 1 == I.getNumExplicitOperands();
3830 SmallVector<Register> CompositeArgs;
3831 MRI->setRegClass(ResVReg, GR.getRegClass(ResType));
3832
3833 // skip type MD node we already used when generated assign.type for this
3834 if (!IsNull) {
3835 if (!wrapIntoSpecConstantOp(I, CompositeArgs))
3836 return false;
3837 MachineIRBuilder MIR(I);
3838 SmallVector<MachineInstr *, 4> Instructions = createContinuedInstructions(
3839 MIR, SPIRV::OpConstantComposite, 3,
3840 SPIRV::OpConstantCompositeContinuedINTEL, CompositeArgs, ResVReg,
3841 GR.getSPIRVTypeID(ResType));
3842 for (auto *Instr : Instructions) {
3843 Instr->setDebugLoc(I.getDebugLoc());
3844 constrainSelectedInstRegOperands(*Instr, TII, TRI, RBI);
3845 }
3846 return true;
3847 } else {
3848 auto MIB = BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpConstantNull))
3849 .addDef(ResVReg)
3850 .addUse(GR.getSPIRVTypeID(ResType));
3851 MIB.constrainAllUses(TII, TRI, RBI);
3852 return true;
3853 }
3854 }
3855 case Intrinsic::spv_assign_name: {
3856 auto MIB = BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpName));
3857 MIB.addUse(I.getOperand(I.getNumExplicitDefs() + 1).getReg());
3858 for (unsigned i = I.getNumExplicitDefs() + 2;
3859 i < I.getNumExplicitOperands(); ++i) {
3860 MIB.addImm(I.getOperand(i).getImm());
3861 }
3862 MIB.constrainAllUses(TII, TRI, RBI);
3863 return true;
3864 }
3865 case Intrinsic::spv_switch: {
3866 auto MIB = BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpSwitch));
3867 for (unsigned i = 1; i < I.getNumExplicitOperands(); ++i) {
3868 if (I.getOperand(i).isReg())
3869 MIB.addReg(I.getOperand(i).getReg());
3870 else if (I.getOperand(i).isCImm())
3871 addNumImm(I.getOperand(i).getCImm()->getValue(), MIB);
3872 else if (I.getOperand(i).isMBB())
3873 MIB.addMBB(I.getOperand(i).getMBB());
3874 else
3875 llvm_unreachable("Unexpected OpSwitch operand");
3876 }
3877 MIB.constrainAllUses(TII, TRI, RBI);
3878 return true;
3879 }
3880 case Intrinsic::spv_loop_merge: {
3881 auto MIB = BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpLoopMerge));
3882 for (unsigned i = 1; i < I.getNumExplicitOperands(); ++i) {
3883 if (I.getOperand(i).isMBB())
3884 MIB.addMBB(I.getOperand(i).getMBB());
3885 else
3886 MIB.addImm(foldImm(I.getOperand(i), MRI));
3887 }
3888 MIB.constrainAllUses(TII, TRI, RBI);
3889 return true;
3890 }
3891 case Intrinsic::spv_loop_control_intel: {
3892 auto MIB =
3893 BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpLoopControlINTEL));
3894 for (unsigned J = 1; J < I.getNumExplicitOperands(); ++J)
3895 MIB.addImm(foldImm(I.getOperand(J), MRI));
3896 MIB.constrainAllUses(TII, TRI, RBI);
3897 return true;
3898 }
3899 case Intrinsic::spv_selection_merge: {
3900 auto MIB =
3901 BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpSelectionMerge));
3902 assert(I.getOperand(1).isMBB() &&
3903 "operand 1 to spv_selection_merge must be a basic block");
3904 MIB.addMBB(I.getOperand(1).getMBB());
3905 MIB.addImm(getSelectionOperandForImm(I.getOperand(2).getImm()));
3906 MIB.constrainAllUses(TII, TRI, RBI);
3907 return true;
3908 }
3909 case Intrinsic::spv_cmpxchg:
3910 return selectAtomicCmpXchg(ResVReg, ResType, I);
3911 case Intrinsic::spv_unreachable:
3912 BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpUnreachable))
3913 .constrainAllUses(TII, TRI, RBI);
3914 return true;
3915 case Intrinsic::spv_alloca:
3916 return selectFrameIndex(ResVReg, ResType, I);
3917 case Intrinsic::spv_alloca_array:
3918 return selectAllocaArray(ResVReg, ResType, I);
3919 case Intrinsic::spv_assume:
3920 if (STI.canUseExtension(SPIRV::Extension::SPV_KHR_expect_assume)) {
3921 BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpAssumeTrueKHR))
3922 .addUse(I.getOperand(1).getReg())
3923 .constrainAllUses(TII, TRI, RBI);
3924 return true;
3925 }
3926 break;
3927 case Intrinsic::spv_expect:
3928 if (STI.canUseExtension(SPIRV::Extension::SPV_KHR_expect_assume)) {
3929 BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpExpectKHR))
3930 .addDef(ResVReg)
3931 .addUse(GR.getSPIRVTypeID(ResType))
3932 .addUse(I.getOperand(2).getReg())
3933 .addUse(I.getOperand(3).getReg())
3934 .constrainAllUses(TII, TRI, RBI);
3935 return true;
3936 }
3937 break;
3938 case Intrinsic::arithmetic_fence:
3939 if (STI.canUseExtension(SPIRV::Extension::SPV_EXT_arithmetic_fence)) {
3940 BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpArithmeticFenceEXT))
3941 .addDef(ResVReg)
3942 .addUse(GR.getSPIRVTypeID(ResType))
3943 .addUse(I.getOperand(2).getReg())
3944 .constrainAllUses(TII, TRI, RBI);
3945 return true;
3946 } else
3947 return BuildCOPY(ResVReg, I.getOperand(2).getReg(), I);
3948 break;
3949 case Intrinsic::spv_thread_id:
3950 // The HLSL SV_DispatchThreadID semantic is lowered to llvm.spv.thread.id
3951 // intrinsic in LLVM IR for SPIR-V backend.
3952 //
3953 // In SPIR-V backend, llvm.spv.thread.id is now correctly translated to a
3954 // `GlobalInvocationId` builtin variable
3955 return loadVec3BuiltinInputID(SPIRV::BuiltIn::GlobalInvocationId, ResVReg,
3956 ResType, I);
3957 case Intrinsic::spv_thread_id_in_group:
3958 // The HLSL SV_GroupThreadId semantic is lowered to
3959 // llvm.spv.thread.id.in.group intrinsic in LLVM IR for SPIR-V backend.
3960 //
3961 // In SPIR-V backend, llvm.spv.thread.id.in.group is now correctly
3962 // translated to a `LocalInvocationId` builtin variable
3963 return loadVec3BuiltinInputID(SPIRV::BuiltIn::LocalInvocationId, ResVReg,
3964 ResType, I);
3965 case Intrinsic::spv_group_id:
3966 // The HLSL SV_GroupId semantic is lowered to
3967 // llvm.spv.group.id intrinsic in LLVM IR for SPIR-V backend.
3968 //
3969 // In SPIR-V backend, llvm.spv.group.id is now translated to a `WorkgroupId`
3970 // builtin variable
3971 return loadVec3BuiltinInputID(SPIRV::BuiltIn::WorkgroupId, ResVReg, ResType,
3972 I);
3973 case Intrinsic::spv_flattened_thread_id_in_group:
3974 // The HLSL SV_GroupIndex semantic is lowered to
3975 // llvm.spv.flattened.thread.id.in.group() intrinsic in LLVM IR for SPIR-V
3976 // backend.
3977 //
3978 // In SPIR-V backend, llvm.spv.flattened.thread.id.in.group is translated to
3979 // a `LocalInvocationIndex` builtin variable
3980 return loadBuiltinInputID(SPIRV::BuiltIn::LocalInvocationIndex, ResVReg,
3981 ResType, I);
3982 case Intrinsic::spv_workgroup_size:
3983 return loadVec3BuiltinInputID(SPIRV::BuiltIn::WorkgroupSize, ResVReg,
3984 ResType, I);
3985 case Intrinsic::spv_global_size:
3986 return loadVec3BuiltinInputID(SPIRV::BuiltIn::GlobalSize, ResVReg, ResType,
3987 I);
3988 case Intrinsic::spv_global_offset:
3989 return loadVec3BuiltinInputID(SPIRV::BuiltIn::GlobalOffset, ResVReg,
3990 ResType, I);
3991 case Intrinsic::spv_num_workgroups:
3992 return loadVec3BuiltinInputID(SPIRV::BuiltIn::NumWorkgroups, ResVReg,
3993 ResType, I);
3994 case Intrinsic::spv_subgroup_size:
3995 return loadBuiltinInputID(SPIRV::BuiltIn::SubgroupSize, ResVReg, ResType,
3996 I);
3997 case Intrinsic::spv_num_subgroups:
3998 return loadBuiltinInputID(SPIRV::BuiltIn::NumSubgroups, ResVReg, ResType,
3999 I);
4000 case Intrinsic::spv_subgroup_id:
4001 return loadBuiltinInputID(SPIRV::BuiltIn::SubgroupId, ResVReg, ResType, I);
4002 case Intrinsic::spv_subgroup_local_invocation_id:
4003 return loadBuiltinInputID(SPIRV::BuiltIn::SubgroupLocalInvocationId,
4004 ResVReg, ResType, I);
4005 case Intrinsic::spv_subgroup_max_size:
4006 return loadBuiltinInputID(SPIRV::BuiltIn::SubgroupMaxSize, ResVReg, ResType,
4007 I);
4008 case Intrinsic::spv_fdot:
4009 return selectFloatDot(ResVReg, ResType, I);
4010 case Intrinsic::spv_udot:
4011 case Intrinsic::spv_sdot:
4012 if (STI.canUseExtension(SPIRV::Extension::SPV_KHR_integer_dot_product) ||
4013 STI.isAtLeastSPIRVVer(VersionTuple(1, 6)))
4014 return selectIntegerDot(ResVReg, ResType, I,
4015 /*Signed=*/IID == Intrinsic::spv_sdot);
4016 return selectIntegerDotExpansion(ResVReg, ResType, I);
4017 case Intrinsic::spv_dot4add_i8packed:
4018 if (STI.canUseExtension(SPIRV::Extension::SPV_KHR_integer_dot_product) ||
4019 STI.isAtLeastSPIRVVer(VersionTuple(1, 6)))
4020 return selectDot4AddPacked<true>(ResVReg, ResType, I);
4021 return selectDot4AddPackedExpansion<true>(ResVReg, ResType, I);
4022 case Intrinsic::spv_dot4add_u8packed:
4023 if (STI.canUseExtension(SPIRV::Extension::SPV_KHR_integer_dot_product) ||
4024 STI.isAtLeastSPIRVVer(VersionTuple(1, 6)))
4025 return selectDot4AddPacked<false>(ResVReg, ResType, I);
4026 return selectDot4AddPackedExpansion<false>(ResVReg, ResType, I);
4027 case Intrinsic::spv_all:
4028 return selectAll(ResVReg, ResType, I);
4029 case Intrinsic::spv_any:
4030 return selectAny(ResVReg, ResType, I);
4031 case Intrinsic::spv_cross:
4032 return selectExtInst(ResVReg, ResType, I, CL::cross, GL::Cross);
4033 case Intrinsic::spv_distance:
4034 return selectExtInst(ResVReg, ResType, I, CL::distance, GL::Distance);
4035 case Intrinsic::spv_lerp:
4036 return selectExtInst(ResVReg, ResType, I, CL::mix, GL::FMix);
4037 case Intrinsic::spv_length:
4038 return selectExtInst(ResVReg, ResType, I, CL::length, GL::Length);
4039 case Intrinsic::spv_degrees:
4040 return selectExtInst(ResVReg, ResType, I, CL::degrees, GL::Degrees);
4041 case Intrinsic::spv_faceforward:
4042 return selectExtInst(ResVReg, ResType, I, GL::FaceForward);
4043 case Intrinsic::spv_frac:
4044 return selectExtInst(ResVReg, ResType, I, CL::fract, GL::Fract);
4045 case Intrinsic::spv_isinf:
4046 return selectOpIsInf(ResVReg, ResType, I);
4047 case Intrinsic::spv_isnan:
4048 return selectOpIsNan(ResVReg, ResType, I);
4049 case Intrinsic::spv_normalize:
4050 return selectExtInst(ResVReg, ResType, I, CL::normalize, GL::Normalize);
4051 case Intrinsic::spv_refract:
4052 return selectExtInst(ResVReg, ResType, I, GL::Refract);
4053 case Intrinsic::spv_reflect:
4054 return selectExtInst(ResVReg, ResType, I, GL::Reflect);
4055 case Intrinsic::spv_rsqrt:
4056 return selectExtInst(ResVReg, ResType, I, CL::rsqrt, GL::InverseSqrt);
4057 case Intrinsic::spv_sign:
4058 return selectSign(ResVReg, ResType, I);
4059 case Intrinsic::spv_smoothstep:
4060 return selectExtInst(ResVReg, ResType, I, CL::smoothstep, GL::SmoothStep);
4061 case Intrinsic::spv_firstbituhigh: // There is no CL equivalent of FindUMsb
4062 return selectFirstBitHigh(ResVReg, ResType, I, /*IsSigned=*/false);
4063 case Intrinsic::spv_firstbitshigh: // There is no CL equivalent of FindSMsb
4064 return selectFirstBitHigh(ResVReg, ResType, I, /*IsSigned=*/true);
4065 case Intrinsic::spv_firstbitlow: // There is no CL equivlent of FindILsb
4066 return selectFirstBitLow(ResVReg, ResType, I);
4067 case Intrinsic::spv_group_memory_barrier_with_group_sync: {
4068 Register MemSemReg =
4069 buildI32Constant(SPIRV::MemorySemantics::SequentiallyConsistent, I);
4070 Register ScopeReg = buildI32Constant(SPIRV::Scope::Workgroup, I);
4071 MachineBasicBlock &BB = *I.getParent();
4072 BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpControlBarrier))
4073 .addUse(ScopeReg)
4074 .addUse(ScopeReg)
4075 .addUse(MemSemReg)
4076 .constrainAllUses(TII, TRI, RBI);
4077 return true;
4078 }
4079 case Intrinsic::spv_generic_cast_to_ptr_explicit: {
4080 Register PtrReg = I.getOperand(I.getNumExplicitDefs() + 1).getReg();
4081 SPIRV::StorageClass::StorageClass ResSC =
4082 GR.getPointerStorageClass(ResType);
4083 if (!isGenericCastablePtr(ResSC))
4084 report_fatal_error("The target storage class is not castable from the "
4085 "Generic storage class");
4086 BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpGenericCastToPtrExplicit))
4087 .addDef(ResVReg)
4088 .addUse(GR.getSPIRVTypeID(ResType))
4089 .addUse(PtrReg)
4090 .addImm(ResSC)
4091 .constrainAllUses(TII, TRI, RBI);
4092 return true;
4093 }
4094 case Intrinsic::spv_lifetime_start:
4095 case Intrinsic::spv_lifetime_end: {
4096 unsigned Op = IID == Intrinsic::spv_lifetime_start ? SPIRV::OpLifetimeStart
4097 : SPIRV::OpLifetimeStop;
4098 int64_t Size = I.getOperand(I.getNumExplicitDefs() + 1).getImm();
4099 Register PtrReg = I.getOperand(I.getNumExplicitDefs() + 2).getReg();
4100 if (Size == -1)
4101 Size = 0;
4102 BuildMI(BB, I, I.getDebugLoc(), TII.get(Op))
4103 .addUse(PtrReg)
4104 .addImm(Size)
4105 .constrainAllUses(TII, TRI, RBI);
4106 return true;
4107 }
4108 case Intrinsic::spv_saturate:
4109 return selectSaturate(ResVReg, ResType, I);
4110 case Intrinsic::spv_nclamp:
4111 return selectExtInst(ResVReg, ResType, I, CL::fclamp, GL::NClamp);
4112 case Intrinsic::spv_uclamp:
4113 return selectExtInst(ResVReg, ResType, I, CL::u_clamp, GL::UClamp);
4114 case Intrinsic::spv_sclamp:
4115 return selectExtInst(ResVReg, ResType, I, CL::s_clamp, GL::SClamp);
4116 case Intrinsic::spv_subgroup_prefix_bit_count:
4117 return selectWavePrefixBitCount(ResVReg, ResType, I);
4118 case Intrinsic::spv_wave_active_countbits:
4119 return selectWaveActiveCountBits(ResVReg, ResType, I);
4120 case Intrinsic::spv_wave_all:
4121 return selectWaveOpInst(ResVReg, ResType, I, SPIRV::OpGroupNonUniformAll);
4122 case Intrinsic::spv_wave_any:
4123 return selectWaveOpInst(ResVReg, ResType, I, SPIRV::OpGroupNonUniformAny);
4124 case Intrinsic::spv_subgroup_ballot:
4125 return selectWaveOpInst(ResVReg, ResType, I,
4126 SPIRV::OpGroupNonUniformBallot);
4127 case Intrinsic::spv_wave_is_first_lane:
4128 return selectWaveOpInst(ResVReg, ResType, I, SPIRV::OpGroupNonUniformElect);
4129 case Intrinsic::spv_wave_reduce_umax:
4130 return selectWaveReduceMax(ResVReg, ResType, I, /*IsUnsigned*/ true);
4131 case Intrinsic::spv_wave_reduce_max:
4132 return selectWaveReduceMax(ResVReg, ResType, I, /*IsUnsigned*/ false);
4133 case Intrinsic::spv_wave_reduce_umin:
4134 return selectWaveReduceMin(ResVReg, ResType, I, /*IsUnsigned*/ true);
4135 case Intrinsic::spv_wave_reduce_min:
4136 return selectWaveReduceMin(ResVReg, ResType, I, /*IsUnsigned*/ false);
4137 case Intrinsic::spv_wave_reduce_sum:
4138 return selectWaveReduceSum(ResVReg, ResType, I);
4139 case Intrinsic::spv_wave_readlane:
4140 return selectWaveOpInst(ResVReg, ResType, I,
4141 SPIRV::OpGroupNonUniformShuffle);
4142 case Intrinsic::spv_wave_prefix_sum:
4143 return selectWaveExclusiveScanSum(ResVReg, ResType, I);
4144 case Intrinsic::spv_wave_prefix_product:
4145 return selectWaveExclusiveScanProduct(ResVReg, ResType, I);
4146 case Intrinsic::spv_step:
4147 return selectExtInst(ResVReg, ResType, I, CL::step, GL::Step);
4148 case Intrinsic::spv_radians:
4149 return selectExtInst(ResVReg, ResType, I, CL::radians, GL::Radians);
4150 // Discard intrinsics which we do not expect to actually represent code after
4151 // lowering or intrinsics which are not implemented but should not crash when
4152 // found in a customer's LLVM IR input.
4153 case Intrinsic::instrprof_increment:
4154 case Intrinsic::instrprof_increment_step:
4155 case Intrinsic::instrprof_value_profile:
4156 break;
4157 // Discard internal intrinsics.
4158 case Intrinsic::spv_value_md:
4159 break;
4160 case Intrinsic::spv_resource_handlefrombinding: {
4161 return selectHandleFromBinding(ResVReg, ResType, I);
4162 }
4163 case Intrinsic::spv_resource_counterhandlefrombinding:
4164 return selectCounterHandleFromBinding(ResVReg, ResType, I);
4165 case Intrinsic::spv_resource_updatecounter:
4166 return selectUpdateCounter(ResVReg, ResType, I);
4167 case Intrinsic::spv_resource_store_typedbuffer: {
4168 return selectImageWriteIntrinsic(I);
4169 }
4170 case Intrinsic::spv_resource_load_typedbuffer: {
4171 return selectReadImageIntrinsic(ResVReg, ResType, I);
4172 }
4173 case Intrinsic::spv_resource_sample:
4174 case Intrinsic::spv_resource_sample_clamp:
4175 return selectSampleBasicIntrinsic(ResVReg, ResType, I);
4176 case Intrinsic::spv_resource_samplebias:
4177 case Intrinsic::spv_resource_samplebias_clamp:
4178 return selectSampleBiasIntrinsic(ResVReg, ResType, I);
4179 case Intrinsic::spv_resource_samplegrad:
4180 case Intrinsic::spv_resource_samplegrad_clamp:
4181 return selectSampleGradIntrinsic(ResVReg, ResType, I);
4182 case Intrinsic::spv_resource_samplelevel:
4183 return selectSampleLevelIntrinsic(ResVReg, ResType, I);
4184 case Intrinsic::spv_resource_samplecmp:
4185 case Intrinsic::spv_resource_samplecmp_clamp:
4186 return selectSampleCmpIntrinsic(ResVReg, ResType, I);
4187 case Intrinsic::spv_resource_samplecmplevelzero:
4188 return selectSampleCmpLevelZeroIntrinsic(ResVReg, ResType, I);
4189 case Intrinsic::spv_resource_gather:
4190 case Intrinsic::spv_resource_gather_cmp:
4191 return selectGatherIntrinsic(ResVReg, ResType, I);
4192 case Intrinsic::spv_resource_getpointer: {
4193 return selectResourceGetPointer(ResVReg, ResType, I);
4194 }
4195 case Intrinsic::spv_pushconstant_getpointer: {
4196 return selectPushConstantGetPointer(ResVReg, ResType, I);
4197 }
4198 case Intrinsic::spv_discard: {
4199 return selectDiscard(ResVReg, ResType, I);
4200 }
4201 case Intrinsic::spv_resource_nonuniformindex: {
4202 return selectResourceNonUniformIndex(ResVReg, ResType, I);
4203 }
4204 case Intrinsic::spv_unpackhalf2x16: {
4205 return selectExtInst(ResVReg, ResType, I, GL::UnpackHalf2x16);
4206 }
4207 case Intrinsic::spv_packhalf2x16: {
4208 return selectExtInst(ResVReg, ResType, I, GL::PackHalf2x16);
4209 }
4210 case Intrinsic::spv_ddx:
4211 return selectDerivativeInst(ResVReg, ResType, I, SPIRV::OpDPdx);
4212 case Intrinsic::spv_ddy:
4213 return selectDerivativeInst(ResVReg, ResType, I, SPIRV::OpDPdy);
4214 case Intrinsic::spv_ddx_coarse:
4215 return selectDerivativeInst(ResVReg, ResType, I, SPIRV::OpDPdxCoarse);
4216 case Intrinsic::spv_ddy_coarse:
4217 return selectDerivativeInst(ResVReg, ResType, I, SPIRV::OpDPdyCoarse);
4218 case Intrinsic::spv_ddx_fine:
4219 return selectDerivativeInst(ResVReg, ResType, I, SPIRV::OpDPdxFine);
4220 case Intrinsic::spv_ddy_fine:
4221 return selectDerivativeInst(ResVReg, ResType, I, SPIRV::OpDPdyFine);
4222 case Intrinsic::spv_fwidth:
4223 return selectDerivativeInst(ResVReg, ResType, I, SPIRV::OpFwidth);
4224 default: {
4225 std::string DiagMsg;
4226 raw_string_ostream OS(DiagMsg);
4227 I.print(OS);
4228 DiagMsg = "Intrinsic selection not implemented: " + DiagMsg;
4229 report_fatal_error(DiagMsg.c_str(), false);
4230 }
4231 }
4232 return true;
4233}
4234
4235bool SPIRVInstructionSelector::selectHandleFromBinding(Register &ResVReg,
4236 SPIRVTypeInst ResType,
4237 MachineInstr &I) const {
4238 // The images need to be loaded in the same basic block as their use. We defer
4239 // loading the image to the intrinsic that uses it.
4240 if (ResType->getOpcode() == SPIRV::OpTypeImage)
4241 return true;
4242
4243 return loadHandleBeforePosition(ResVReg, GR.getSPIRVTypeForVReg(ResVReg),
4244 *cast<GIntrinsic>(&I), I);
4245}
4246
4247bool SPIRVInstructionSelector::selectCounterHandleFromBinding(
4248 Register &ResVReg, SPIRVTypeInst ResType, MachineInstr &I) const {
4249 auto &Intr = cast<GIntrinsic>(I);
4250 assert(Intr.getIntrinsicID() ==
4251 Intrinsic::spv_resource_counterhandlefrombinding);
4252
4253 // Extract information from the intrinsic call.
4254 Register MainHandleReg = Intr.getOperand(2).getReg();
4255 auto *MainHandleDef = cast<GIntrinsic>(getVRegDef(*MRI, MainHandleReg));
4256 assert(MainHandleDef->getIntrinsicID() ==
4257 Intrinsic::spv_resource_handlefrombinding);
4258
4259 uint32_t Set = getIConstVal(Intr.getOperand(4).getReg(), MRI);
4260 uint32_t Binding = getIConstVal(Intr.getOperand(3).getReg(), MRI);
4261 uint32_t ArraySize = getIConstVal(MainHandleDef->getOperand(4).getReg(), MRI);
4262 Register IndexReg = MainHandleDef->getOperand(5).getReg();
4263 std::string CounterName =
4264 getStringValueFromReg(MainHandleDef->getOperand(6).getReg(), *MRI) +
4265 ".counter";
4266
4267 // Create the counter variable.
4268 MachineIRBuilder MIRBuilder(I);
4269 Register CounterVarReg =
4270 buildPointerToResource(SPIRVTypeInst(GR.getPointeeType(ResType)),
4271 GR.getPointerStorageClass(ResType), Set, Binding,
4272 ArraySize, IndexReg, CounterName, MIRBuilder);
4273
4274 return BuildCOPY(ResVReg, CounterVarReg, I);
4275}
4276
4277bool SPIRVInstructionSelector::selectUpdateCounter(Register &ResVReg,
4278 SPIRVTypeInst ResType,
4279 MachineInstr &I) const {
4280 auto &Intr = cast<GIntrinsic>(I);
4281 assert(Intr.getIntrinsicID() == Intrinsic::spv_resource_updatecounter);
4282
4283 Register CounterHandleReg = Intr.getOperand(2).getReg();
4284 Register IncrReg = Intr.getOperand(3).getReg();
4285
4286 // The counter handle is a pointer to the counter variable (which is a struct
4287 // containing an i32). We need to get a pointer to that i32 member to do the
4288 // atomic operation.
4289#ifndef NDEBUG
4290 SPIRVTypeInst CounterVarType = GR.getSPIRVTypeForVReg(CounterHandleReg);
4291 SPIRVTypeInst CounterVarPointeeType = GR.getPointeeType(CounterVarType);
4292 assert(CounterVarPointeeType &&
4293 CounterVarPointeeType->getOpcode() == SPIRV::OpTypeStruct &&
4294 "Counter variable must be a struct");
4295 assert(GR.getPointerStorageClass(CounterVarType) ==
4296 SPIRV::StorageClass::StorageBuffer &&
4297 "Counter variable must be in the storage buffer storage class");
4298 assert(CounterVarPointeeType->getNumOperands() == 2 &&
4299 "Counter variable must have exactly 1 member in the struct");
4300 const SPIRVTypeInst MemberType =
4301 GR.getSPIRVTypeForVReg(CounterVarPointeeType->getOperand(1).getReg());
4302 assert(MemberType->getOpcode() == SPIRV::OpTypeInt &&
4303 "Counter variable struct must have a single i32 member");
4304#endif
4305
4306 // The struct has a single i32 member.
4307 MachineIRBuilder MIRBuilder(I);
4308 const Type *LLVMIntType =
4309 Type::getInt32Ty(I.getMF()->getFunction().getContext());
4310
4311 SPIRVTypeInst IntPtrType = GR.getOrCreateSPIRVPointerType(
4312 LLVMIntType, MIRBuilder, SPIRV::StorageClass::StorageBuffer);
4313
4314 Register Zero = buildI32Constant(0, I);
4315
4316 Register PtrToCounter =
4317 MRI->createVirtualRegister(GR.getRegClass(IntPtrType));
4318 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(SPIRV::OpAccessChain))
4319 .addDef(PtrToCounter)
4320 .addUse(GR.getSPIRVTypeID(IntPtrType))
4321 .addUse(CounterHandleReg)
4322 .addUse(Zero)
4323 .constrainAllUses(TII, TRI, RBI);
4324
4325 // For UAV/SSBO counters, the scope is Device. The counter variable is not
4326 // used as a flag. So the memory semantics can be None.
4327 Register Scope = buildI32Constant(SPIRV::Scope::Device, I);
4328 Register Semantics = buildI32Constant(SPIRV::MemorySemantics::None, I);
4329
4330 int64_t IncrVal = getIConstValSext(IncrReg, MRI);
4331 Register Incr = buildI32Constant(static_cast<uint32_t>(IncrVal), I);
4332
4333 Register AtomicRes = MRI->createVirtualRegister(GR.getRegClass(ResType));
4334 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(SPIRV::OpAtomicIAdd))
4335 .addDef(AtomicRes)
4336 .addUse(GR.getSPIRVTypeID(ResType))
4337 .addUse(PtrToCounter)
4338 .addUse(Scope)
4339 .addUse(Semantics)
4340 .addUse(Incr)
4341 .constrainAllUses(TII, TRI, RBI);
4342 if (IncrVal >= 0) {
4343 return BuildCOPY(ResVReg, AtomicRes, I);
4344 }
4345
4346 // In HLSL, IncrementCounter returns the value *before* the increment, while
4347 // DecrementCounter returns the value *after* the decrement. Both are lowered
4348 // to the same atomic intrinsic which returns the value *before* the
4349 // operation. So for decrements (negative IncrVal), we must subtract the
4350 // increment value from the result to get the post-decrement value.
4351 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(SPIRV::OpIAddS))
4352 .addDef(ResVReg)
4353 .addUse(GR.getSPIRVTypeID(ResType))
4354 .addUse(AtomicRes)
4355 .addUse(Incr)
4356 .constrainAllUses(TII, TRI, RBI);
4357 return true;
4358}
4359bool SPIRVInstructionSelector::selectReadImageIntrinsic(Register &ResVReg,
4360 SPIRVTypeInst ResType,
4361 MachineInstr &I) const {
4362
4363 // If the load of the image is in a different basic block, then
4364 // this will generate invalid code. A proper solution is to move
4365 // the OpLoad from selectHandleFromBinding here. However, to do
4366 // that we will need to change the return type of the intrinsic.
4367 // We will do that when we can, but for now trying to move forward with other
4368 // issues.
4369 Register ImageReg = I.getOperand(2).getReg();
4370 auto *ImageDef = cast<GIntrinsic>(getVRegDef(*MRI, ImageReg));
4371 Register NewImageReg = MRI->createVirtualRegister(MRI->getRegClass(ImageReg));
4372 if (!loadHandleBeforePosition(NewImageReg, GR.getSPIRVTypeForVReg(ImageReg),
4373 *ImageDef, I)) {
4374 return false;
4375 }
4376
4377 Register IdxReg = I.getOperand(3).getReg();
4378 DebugLoc Loc = I.getDebugLoc();
4379 MachineInstr &Pos = I;
4380
4381 return generateImageReadOrFetch(ResVReg, ResType, NewImageReg, IdxReg, Loc,
4382 Pos);
4383}
4384
4385bool SPIRVInstructionSelector::generateSampleImage(
4386 Register ResVReg, SPIRVTypeInst ResType, Register ImageReg,
4387 Register SamplerReg, Register CoordinateReg, const ImageOperands &ImOps,
4388 DebugLoc Loc, MachineInstr &Pos) const {
4389 auto *ImageDef = cast<GIntrinsic>(getVRegDef(*MRI, ImageReg));
4390 Register NewImageReg = MRI->createVirtualRegister(MRI->getRegClass(ImageReg));
4391 if (!loadHandleBeforePosition(NewImageReg, GR.getSPIRVTypeForVReg(ImageReg),
4392 *ImageDef, Pos)) {
4393 return false;
4394 }
4395
4396 auto *SamplerDef = cast<GIntrinsic>(getVRegDef(*MRI, SamplerReg));
4397 Register NewSamplerReg =
4398 MRI->createVirtualRegister(MRI->getRegClass(SamplerReg));
4399 if (!loadHandleBeforePosition(NewSamplerReg,
4400 GR.getSPIRVTypeForVReg(SamplerReg), *SamplerDef,
4401 Pos)) {
4402 return false;
4403 }
4404
4405 MachineIRBuilder MIRBuilder(Pos);
4406 SPIRVTypeInst SampledImageType = GR.getOrCreateOpTypeSampledImage(
4407 GR.getSPIRVTypeForVReg(ImageReg), MIRBuilder);
4408 Register SampledImageReg =
4409 MRI->createVirtualRegister(GR.getRegClass(SampledImageType));
4410
4411 BuildMI(*Pos.getParent(), Pos, Loc, TII.get(SPIRV::OpSampledImage))
4412 .addDef(SampledImageReg)
4413 .addUse(GR.getSPIRVTypeID(SampledImageType))
4414 .addUse(NewImageReg)
4415 .addUse(NewSamplerReg)
4416 .constrainAllUses(TII, TRI, RBI);
4417
4418 bool IsExplicitLod = ImOps.GradX.has_value() || ImOps.GradY.has_value() ||
4419 ImOps.Lod.has_value();
4420 unsigned Opcode = IsExplicitLod ? SPIRV::OpImageSampleExplicitLod
4421 : SPIRV::OpImageSampleImplicitLod;
4422 if (ImOps.Compare)
4423 Opcode = IsExplicitLod ? SPIRV::OpImageSampleDrefExplicitLod
4424 : SPIRV::OpImageSampleDrefImplicitLod;
4425
4426 auto MIB = BuildMI(*Pos.getParent(), Pos, Loc, TII.get(Opcode))
4427 .addDef(ResVReg)
4428 .addUse(GR.getSPIRVTypeID(ResType))
4429 .addUse(SampledImageReg)
4430 .addUse(CoordinateReg);
4431
4432 if (ImOps.Compare)
4433 MIB.addUse(*ImOps.Compare);
4434
4435 uint32_t ImageOperands = 0;
4436 if (ImOps.Bias)
4437 ImageOperands |= SPIRV::ImageOperand::Bias;
4438 if (ImOps.Lod)
4439 ImageOperands |= SPIRV::ImageOperand::Lod;
4440 if (ImOps.GradX && ImOps.GradY)
4441 ImageOperands |= SPIRV::ImageOperand::Grad;
4442 if (ImOps.Offset && !isScalarOrVectorIntConstantZero(*ImOps.Offset)) {
4443 if (isConstReg(MRI, *ImOps.Offset))
4444 ImageOperands |= SPIRV::ImageOperand::ConstOffset;
4445 else {
4446 Pos.emitGenericError(
4447 "Non-constant offsets are not supported in sample instructions.");
4448 }
4449 }
4450 if (ImOps.MinLod)
4451 ImageOperands |= SPIRV::ImageOperand::MinLod;
4452
4453 if (ImageOperands != 0) {
4454 MIB.addImm(ImageOperands);
4455 if (ImageOperands & SPIRV::ImageOperand::Bias)
4456 MIB.addUse(*ImOps.Bias);
4457 if (ImageOperands & SPIRV::ImageOperand::Lod)
4458 MIB.addUse(*ImOps.Lod);
4459 if (ImageOperands & SPIRV::ImageOperand::Grad) {
4460 MIB.addUse(*ImOps.GradX);
4461 MIB.addUse(*ImOps.GradY);
4462 }
4463 if (ImageOperands &
4464 (SPIRV::ImageOperand::ConstOffset | SPIRV::ImageOperand::Offset))
4465 MIB.addUse(*ImOps.Offset);
4466 if (ImageOperands & SPIRV::ImageOperand::MinLod)
4467 MIB.addUse(*ImOps.MinLod);
4468 }
4469
4470 MIB.constrainAllUses(TII, TRI, RBI);
4471 return true;
4472}
4473
4474bool SPIRVInstructionSelector::selectSampleBasicIntrinsic(
4475 Register &ResVReg, SPIRVTypeInst ResType, MachineInstr &I) const {
4476 Register ImageReg = I.getOperand(2).getReg();
4477 Register SamplerReg = I.getOperand(3).getReg();
4478 Register CoordinateReg = I.getOperand(4).getReg();
4479 ImageOperands ImOps;
4480 if (I.getNumOperands() > 5)
4481 ImOps.Offset = I.getOperand(5).getReg();
4482 if (I.getNumOperands() > 6)
4483 ImOps.MinLod = I.getOperand(6).getReg();
4484 return generateSampleImage(ResVReg, ResType, ImageReg, SamplerReg,
4485 CoordinateReg, ImOps, I.getDebugLoc(), I);
4486}
4487
4488bool SPIRVInstructionSelector::selectSampleBiasIntrinsic(
4489 Register &ResVReg, SPIRVTypeInst ResType, MachineInstr &I) const {
4490 Register ImageReg = I.getOperand(2).getReg();
4491 Register SamplerReg = I.getOperand(3).getReg();
4492 Register CoordinateReg = I.getOperand(4).getReg();
4493 ImageOperands ImOps;
4494 ImOps.Bias = I.getOperand(5).getReg();
4495 if (I.getNumOperands() > 6)
4496 ImOps.Offset = I.getOperand(6).getReg();
4497 if (I.getNumOperands() > 7)
4498 ImOps.MinLod = I.getOperand(7).getReg();
4499 return generateSampleImage(ResVReg, ResType, ImageReg, SamplerReg,
4500 CoordinateReg, ImOps, I.getDebugLoc(), I);
4501}
4502
4503bool SPIRVInstructionSelector::selectSampleGradIntrinsic(
4504 Register &ResVReg, SPIRVTypeInst ResType, MachineInstr &I) const {
4505 Register ImageReg = I.getOperand(2).getReg();
4506 Register SamplerReg = I.getOperand(3).getReg();
4507 Register CoordinateReg = I.getOperand(4).getReg();
4508 ImageOperands ImOps;
4509 ImOps.GradX = I.getOperand(5).getReg();
4510 ImOps.GradY = I.getOperand(6).getReg();
4511 if (I.getNumOperands() > 7)
4512 ImOps.Offset = I.getOperand(7).getReg();
4513 if (I.getNumOperands() > 8)
4514 ImOps.MinLod = I.getOperand(8).getReg();
4515 return generateSampleImage(ResVReg, ResType, ImageReg, SamplerReg,
4516 CoordinateReg, ImOps, I.getDebugLoc(), I);
4517}
4518
4519bool SPIRVInstructionSelector::selectSampleLevelIntrinsic(
4520 Register &ResVReg, SPIRVTypeInst ResType, MachineInstr &I) const {
4521 Register ImageReg = I.getOperand(2).getReg();
4522 Register SamplerReg = I.getOperand(3).getReg();
4523 Register CoordinateReg = I.getOperand(4).getReg();
4524 ImageOperands ImOps;
4525 ImOps.Lod = I.getOperand(5).getReg();
4526 if (I.getNumOperands() > 6)
4527 ImOps.Offset = I.getOperand(6).getReg();
4528 return generateSampleImage(ResVReg, ResType, ImageReg, SamplerReg,
4529 CoordinateReg, ImOps, I.getDebugLoc(), I);
4530}
4531
4532bool SPIRVInstructionSelector::selectSampleCmpIntrinsic(Register &ResVReg,
4533 SPIRVTypeInst ResType,
4534 MachineInstr &I) const {
4535 Register ImageReg = I.getOperand(2).getReg();
4536 Register SamplerReg = I.getOperand(3).getReg();
4537 Register CoordinateReg = I.getOperand(4).getReg();
4538 ImageOperands ImOps;
4539 ImOps.Compare = I.getOperand(5).getReg();
4540 if (I.getNumOperands() > 6)
4541 ImOps.Offset = I.getOperand(6).getReg();
4542 if (I.getNumOperands() > 7)
4543 ImOps.MinLod = I.getOperand(7).getReg();
4544 return generateSampleImage(ResVReg, ResType, ImageReg, SamplerReg,
4545 CoordinateReg, ImOps, I.getDebugLoc(), I);
4546}
4547
4548bool SPIRVInstructionSelector::selectSampleCmpLevelZeroIntrinsic(
4549 Register &ResVReg, SPIRVTypeInst ResType, MachineInstr &I) const {
4550 Register ImageReg = I.getOperand(2).getReg();
4551 Register SamplerReg = I.getOperand(3).getReg();
4552 Register CoordinateReg = I.getOperand(4).getReg();
4553 ImageOperands ImOps;
4554 ImOps.Compare = I.getOperand(5).getReg();
4555 if (I.getNumOperands() > 6)
4556 ImOps.Offset = I.getOperand(6).getReg();
4557 SPIRVTypeInst FloatTy = GR.getOrCreateSPIRVFloatType(32, I, TII);
4558 ImOps.Lod = GR.getOrCreateConstFP(APFloat(0.0f), I, FloatTy, TII);
4559 return generateSampleImage(ResVReg, ResType, ImageReg, SamplerReg,
4560 CoordinateReg, ImOps, I.getDebugLoc(), I);
4561}
4562
4563bool SPIRVInstructionSelector::selectGatherIntrinsic(Register &ResVReg,
4564 SPIRVTypeInst ResType,
4565 MachineInstr &I) const {
4566 Register ImageReg = I.getOperand(2).getReg();
4567 Register SamplerReg = I.getOperand(3).getReg();
4568 Register CoordinateReg = I.getOperand(4).getReg();
4569 SPIRVTypeInst ImageType = GR.getSPIRVTypeForVReg(ImageReg);
4570 assert(ImageType && ImageType->getOpcode() == SPIRV::OpTypeImage &&
4571 "ImageReg is not an image type.");
4572
4573 Register ComponentOrCompareReg;
4574 Register OffsetReg;
4575
4576 ComponentOrCompareReg = I.getOperand(5).getReg();
4577 OffsetReg = I.getOperand(6).getReg();
4578 auto *ImageDef = cast<GIntrinsic>(getVRegDef(*MRI, ImageReg));
4579 Register NewImageReg = MRI->createVirtualRegister(MRI->getRegClass(ImageReg));
4580 if (!loadHandleBeforePosition(NewImageReg, ImageType, *ImageDef, I)) {
4581 return false;
4582 }
4583
4584 auto Dim = static_cast<SPIRV::Dim::Dim>(ImageType->getOperand(2).getImm());
4585 if (Dim != SPIRV::Dim::DIM_2D && Dim != SPIRV::Dim::DIM_Cube &&
4586 Dim != SPIRV::Dim::DIM_Rect) {
4587 I.emitGenericError(
4588 "Gather operations are only supported for 2D, Cube, and Rect images.");
4589 return false;
4590 }
4591
4592 auto *SamplerDef = cast<GIntrinsic>(getVRegDef(*MRI, SamplerReg));
4593 Register NewSamplerReg =
4594 MRI->createVirtualRegister(MRI->getRegClass(SamplerReg));
4595 if (!loadHandleBeforePosition(
4596 NewSamplerReg, GR.getSPIRVTypeForVReg(SamplerReg), *SamplerDef, I)) {
4597 return false;
4598 }
4599
4600 MachineIRBuilder MIRBuilder(I);
4601 SPIRVTypeInst SampledImageType =
4602 GR.getOrCreateOpTypeSampledImage(ImageType, MIRBuilder);
4603 Register SampledImageReg =
4604 MRI->createVirtualRegister(GR.getRegClass(SampledImageType));
4605
4606 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(SPIRV::OpSampledImage))
4607 .addDef(SampledImageReg)
4608 .addUse(GR.getSPIRVTypeID(SampledImageType))
4609 .addUse(NewImageReg)
4610 .addUse(NewSamplerReg)
4611 .constrainAllUses(TII, TRI, RBI);
4612
4613 auto IntrId = cast<GIntrinsic>(I).getIntrinsicID();
4614 bool IsGatherCmp = IntrId == Intrinsic::spv_resource_gather_cmp;
4615 unsigned Opcode =
4616 IsGatherCmp ? SPIRV::OpImageDrefGather : SPIRV::OpImageGather;
4617
4618 auto MIB = BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(Opcode))
4619 .addDef(ResVReg)
4620 .addUse(GR.getSPIRVTypeID(ResType))
4621 .addUse(SampledImageReg)
4622 .addUse(CoordinateReg)
4623 .addUse(ComponentOrCompareReg);
4624
4625 uint32_t ImageOperands = 0;
4626 if (OffsetReg && !isScalarOrVectorIntConstantZero(OffsetReg)) {
4627 if (Dim == SPIRV::Dim::DIM_Cube) {
4628 I.emitGenericError(
4629 "Gather operations with offset are not supported for Cube images.");
4630 return false;
4631 }
4632 if (isConstReg(MRI, OffsetReg))
4633 ImageOperands |= SPIRV::ImageOperand::ConstOffset;
4634 else {
4635 ImageOperands |= SPIRV::ImageOperand::Offset;
4636 }
4637 }
4638
4639 if (ImageOperands != 0) {
4640 MIB.addImm(ImageOperands);
4641 if (ImageOperands &
4642 (SPIRV::ImageOperand::ConstOffset | SPIRV::ImageOperand::Offset))
4643 MIB.addUse(OffsetReg);
4644 }
4645
4646 MIB.constrainAllUses(TII, TRI, RBI);
4647 return true;
4648}
4649
4650bool SPIRVInstructionSelector::generateImageReadOrFetch(
4651 Register &ResVReg, SPIRVTypeInst ResType, Register ImageReg,
4652 Register IdxReg, DebugLoc Loc, MachineInstr &Pos) const {
4653 SPIRVTypeInst ImageType = GR.getSPIRVTypeForVReg(ImageReg);
4654 assert(ImageType && ImageType->getOpcode() == SPIRV::OpTypeImage &&
4655 "ImageReg is not an image type.");
4656
4657 bool IsSignedInteger =
4658 sampledTypeIsSignedInteger(GR.getTypeForSPIRVType(ImageType));
4659 // Check if the "sampled" operand of the image type is 1.
4660 // https://registry.khronos.org/SPIR-V/specs/unified1/SPIRV.html#OpImageFetch
4661 auto SampledOp = ImageType->getOperand(6);
4662 bool IsFetch = (SampledOp.getImm() == 1);
4663
4664 uint64_t ResultSize = GR.getScalarOrVectorComponentCount(ResType);
4665 if (ResultSize == 4) {
4666 auto BMI =
4667 BuildMI(*Pos.getParent(), Pos, Loc,
4668 TII.get(IsFetch ? SPIRV::OpImageFetch : SPIRV::OpImageRead))
4669 .addDef(ResVReg)
4670 .addUse(GR.getSPIRVTypeID(ResType))
4671 .addUse(ImageReg)
4672 .addUse(IdxReg);
4673
4674 if (IsSignedInteger)
4675 BMI.addImm(0x1000); // SignExtend
4676 BMI.constrainAllUses(TII, TRI, RBI);
4677 return true;
4678 }
4679
4680 SPIRVTypeInst ReadType = widenTypeToVec4(ResType, Pos);
4681 Register ReadReg = MRI->createVirtualRegister(GR.getRegClass(ReadType));
4682 auto BMI =
4683 BuildMI(*Pos.getParent(), Pos, Loc,
4684 TII.get(IsFetch ? SPIRV::OpImageFetch : SPIRV::OpImageRead))
4685 .addDef(ReadReg)
4686 .addUse(GR.getSPIRVTypeID(ReadType))
4687 .addUse(ImageReg)
4688 .addUse(IdxReg);
4689 if (IsSignedInteger)
4690 BMI.addImm(0x1000); // SignExtend
4691 BMI.constrainAllUses(TII, TRI, RBI);
4692
4693 if (ResultSize == 1) {
4694 BuildMI(*Pos.getParent(), Pos, Loc, TII.get(SPIRV::OpCompositeExtract))
4695 .addDef(ResVReg)
4696 .addUse(GR.getSPIRVTypeID(ResType))
4697 .addUse(ReadReg)
4698 .addImm(0)
4699 .constrainAllUses(TII, TRI, RBI);
4700 return true;
4701 }
4702 return extractSubvector(ResVReg, ResType, ReadReg, Pos);
4703}
4704
4705bool SPIRVInstructionSelector::selectResourceGetPointer(Register &ResVReg,
4706 SPIRVTypeInst ResType,
4707 MachineInstr &I) const {
4708 Register ResourcePtr = I.getOperand(2).getReg();
4709 SPIRVTypeInst RegType = GR.getSPIRVTypeForVReg(ResourcePtr, I.getMF());
4710 if (RegType->getOpcode() == SPIRV::OpTypeImage) {
4711 // For texel buffers, the index into the image is part of the OpImageRead or
4712 // OpImageWrite instructions. So we will do nothing in this case. This
4713 // intrinsic will be combined with the load or store when selecting the load
4714 // or store.
4715 return true;
4716 }
4717
4718 assert(ResType->getOpcode() == SPIRV::OpTypePointer);
4719 MachineIRBuilder MIRBuilder(I);
4720
4721 Register IndexReg = I.getOperand(3).getReg();
4722 Register ZeroReg =
4723 buildZerosVal(GR.getOrCreateSPIRVIntegerType(32, I, TII), I);
4724 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(SPIRV::OpAccessChain))
4725 .addDef(ResVReg)
4726 .addUse(GR.getSPIRVTypeID(ResType))
4727 .addUse(ResourcePtr)
4728 .addUse(ZeroReg)
4729 .addUse(IndexReg)
4730 .constrainAllUses(TII, TRI, RBI);
4731 return true;
4732}
4733
4734bool SPIRVInstructionSelector::selectPushConstantGetPointer(
4735 Register &ResVReg, SPIRVTypeInst ResType, MachineInstr &I) const {
4736 MRI->replaceRegWith(ResVReg, I.getOperand(2).getReg());
4737 return true;
4738}
4739
4740bool SPIRVInstructionSelector::selectResourceNonUniformIndex(
4741 Register &ResVReg, SPIRVTypeInst ResType, MachineInstr &I) const {
4742 Register ObjReg = I.getOperand(2).getReg();
4743 if (!BuildCOPY(ResVReg, ObjReg, I))
4744 return false;
4745
4746 buildOpDecorate(ResVReg, I, TII, SPIRV::Decoration::NonUniformEXT, {});
4747 // Check for the registers that use the index marked as non-uniform
4748 // and recursively mark them as non-uniform.
4749 // Per the spec, it's necessary that the final argument used for
4750 // load/store/sample/atomic must be decorated, so we need to propagate the
4751 // decoration through access chains and copies.
4752 // https://docs.vulkan.org/samples/latest/samples/extensions/descriptor_indexing/README.html#_when_to_use_non_uniform_indexing_qualifier
4753 decorateUsesAsNonUniform(ResVReg);
4754 return true;
4755}
4756
4757void SPIRVInstructionSelector::decorateUsesAsNonUniform(
4758 Register &NonUniformReg) const {
4759 llvm::SmallVector<Register> WorkList = {NonUniformReg};
4760 while (WorkList.size() > 0) {
4761 Register CurrentReg = WorkList.back();
4762 WorkList.pop_back();
4763
4764 bool IsDecorated = false;
4765 for (MachineInstr &Use : MRI->use_instructions(CurrentReg)) {
4766 if (Use.getOpcode() == SPIRV::OpDecorate &&
4767 Use.getOperand(1).getImm() == SPIRV::Decoration::NonUniformEXT) {
4768 IsDecorated = true;
4769 continue;
4770 }
4771 // Check if the instruction has the result register and add it to the
4772 // worklist.
4773 if (Use.getOperand(0).isReg() && Use.getOperand(0).isDef()) {
4774 Register ResultReg = Use.getOperand(0).getReg();
4775 if (ResultReg == CurrentReg)
4776 continue;
4777 WorkList.push_back(ResultReg);
4778 }
4779 }
4780
4781 if (!IsDecorated) {
4782 buildOpDecorate(CurrentReg, *MRI->getVRegDef(CurrentReg), TII,
4783 SPIRV::Decoration::NonUniformEXT, {});
4784 }
4785 }
4786}
4787
4788bool SPIRVInstructionSelector::extractSubvector(
4789 Register &ResVReg, SPIRVTypeInst ResType, Register &ReadReg,
4790 MachineInstr &InsertionPoint) const {
4791 SPIRVTypeInst InputType = GR.getResultType(ReadReg);
4792 [[maybe_unused]] uint64_t InputSize =
4793 GR.getScalarOrVectorComponentCount(InputType);
4794 uint64_t ResultSize = GR.getScalarOrVectorComponentCount(ResType);
4795 assert(InputSize > 1 && "The input must be a vector.");
4796 assert(ResultSize > 1 && "The result must be a vector.");
4797 assert(ResultSize < InputSize &&
4798 "Cannot extract more element than there are in the input.");
4799 SmallVector<Register> ComponentRegisters;
4800 SPIRVTypeInst ScalarType = GR.getScalarOrVectorComponentType(ResType);
4801 const TargetRegisterClass *ScalarRegClass = GR.getRegClass(ScalarType);
4802 for (uint64_t I = 0; I < ResultSize; I++) {
4803 Register ComponentReg = MRI->createVirtualRegister(ScalarRegClass);
4804 BuildMI(*InsertionPoint.getParent(), InsertionPoint,
4805 InsertionPoint.getDebugLoc(), TII.get(SPIRV::OpCompositeExtract))
4806 .addDef(ComponentReg)
4807 .addUse(ScalarType->getOperand(0).getReg())
4808 .addUse(ReadReg)
4809 .addImm(I)
4810 .constrainAllUses(TII, TRI, RBI);
4811 ComponentRegisters.emplace_back(ComponentReg);
4812 }
4813
4814 MachineInstrBuilder MIB = BuildMI(*InsertionPoint.getParent(), InsertionPoint,
4815 InsertionPoint.getDebugLoc(),
4816 TII.get(SPIRV::OpCompositeConstruct))
4817 .addDef(ResVReg)
4818 .addUse(GR.getSPIRVTypeID(ResType));
4819
4820 for (Register ComponentReg : ComponentRegisters)
4821 MIB.addUse(ComponentReg);
4822 MIB.constrainAllUses(TII, TRI, RBI);
4823 return true;
4824}
4825
4826bool SPIRVInstructionSelector::selectImageWriteIntrinsic(
4827 MachineInstr &I) const {
4828 // If the load of the image is in a different basic block, then
4829 // this will generate invalid code. A proper solution is to move
4830 // the OpLoad from selectHandleFromBinding here. However, to do
4831 // that we will need to change the return type of the intrinsic.
4832 // We will do that when we can, but for now trying to move forward with other
4833 // issues.
4834 Register ImageReg = I.getOperand(1).getReg();
4835 auto *ImageDef = cast<GIntrinsic>(getVRegDef(*MRI, ImageReg));
4836 Register NewImageReg = MRI->createVirtualRegister(MRI->getRegClass(ImageReg));
4837 if (!loadHandleBeforePosition(NewImageReg, GR.getSPIRVTypeForVReg(ImageReg),
4838 *ImageDef, I)) {
4839 return false;
4840 }
4841
4842 Register CoordinateReg = I.getOperand(2).getReg();
4843 Register DataReg = I.getOperand(3).getReg();
4844 assert(GR.getResultType(DataReg)->getOpcode() == SPIRV::OpTypeVector);
4845 assert(GR.getScalarOrVectorComponentCount(GR.getResultType(DataReg)) == 4);
4846 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(SPIRV::OpImageWrite))
4847 .addUse(NewImageReg)
4848 .addUse(CoordinateReg)
4849 .addUse(DataReg)
4850 .constrainAllUses(TII, TRI, RBI);
4851 return true;
4852}
4853
4854Register SPIRVInstructionSelector::buildPointerToResource(
4855 SPIRVTypeInst SpirvResType, SPIRV::StorageClass::StorageClass SC,
4856 uint32_t Set, uint32_t Binding, uint32_t ArraySize, Register IndexReg,
4857 StringRef Name, MachineIRBuilder MIRBuilder) const {
4858 const Type *ResType = GR.getTypeForSPIRVType(SpirvResType);
4859 if (ArraySize == 1) {
4860 SPIRVTypeInst PtrType =
4861 GR.getOrCreateSPIRVPointerType(ResType, MIRBuilder, SC);
4862 assert(GR.getPointeeType(PtrType) == SpirvResType &&
4863 "SpirvResType did not have an explicit layout.");
4864 return GR.getOrCreateGlobalVariableWithBinding(PtrType, Set, Binding, Name,
4865 MIRBuilder);
4866 }
4867
4868 const Type *VarType = ArrayType::get(const_cast<Type *>(ResType), ArraySize);
4869 SPIRVTypeInst VarPointerType =
4870 GR.getOrCreateSPIRVPointerType(VarType, MIRBuilder, SC);
4871 Register VarReg = GR.getOrCreateGlobalVariableWithBinding(
4872 VarPointerType, Set, Binding, Name, MIRBuilder);
4873
4874 SPIRVTypeInst ResPointerType =
4875 GR.getOrCreateSPIRVPointerType(ResType, MIRBuilder, SC);
4876 Register AcReg = MRI->createVirtualRegister(GR.getRegClass(ResPointerType));
4877
4878 MIRBuilder.buildInstr(SPIRV::OpAccessChain)
4879 .addDef(AcReg)
4880 .addUse(GR.getSPIRVTypeID(ResPointerType))
4881 .addUse(VarReg)
4882 .addUse(IndexReg);
4883
4884 return AcReg;
4885}
4886
4887bool SPIRVInstructionSelector::selectFirstBitSet16(
4888 Register ResVReg, SPIRVTypeInst ResType, MachineInstr &I,
4889 unsigned ExtendOpcode, unsigned BitSetOpcode) const {
4890 Register ExtReg = MRI->createVirtualRegister(GR.getRegClass(ResType));
4891 if (!selectOpWithSrcs(ExtReg, ResType, I, {I.getOperand(2).getReg()},
4892 ExtendOpcode))
4893 return false;
4894
4895 return selectFirstBitSet32(ResVReg, ResType, I, ExtReg, BitSetOpcode);
4896}
4897
4898bool SPIRVInstructionSelector::selectFirstBitSet32(
4899 Register ResVReg, SPIRVTypeInst ResType, MachineInstr &I, Register SrcReg,
4900 unsigned BitSetOpcode) const {
4901 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(SPIRV::OpExtInst))
4902 .addDef(ResVReg)
4903 .addUse(GR.getSPIRVTypeID(ResType))
4904 .addImm(static_cast<uint32_t>(SPIRV::InstructionSet::GLSL_std_450))
4905 .addImm(BitSetOpcode)
4906 .addUse(SrcReg)
4907 .constrainAllUses(TII, TRI, RBI);
4908 return true;
4909}
4910
4911bool SPIRVInstructionSelector::selectFirstBitSet64Overflow(
4912 Register ResVReg, SPIRVTypeInst ResType, MachineInstr &I, Register SrcReg,
4913 unsigned BitSetOpcode, bool SwapPrimarySide) const {
4914
4915 // SPIR-V allow vectors of size 2,3,4 only. Calling with a larger vectors
4916 // requires creating a param register and return register with an invalid
4917 // vector size. If that is resolved, then this function can be used for
4918 // vectors of any component size.
4919 unsigned ComponentCount = GR.getScalarOrVectorComponentCount(ResType);
4920 assert(ComponentCount < 5 && "Vec 5+ will generate invalid SPIR-V ops");
4921
4922 MachineIRBuilder MIRBuilder(I);
4923 SPIRVTypeInst BaseType = GR.retrieveScalarOrVectorIntType(ResType);
4924 SPIRVTypeInst I64Type = GR.getOrCreateSPIRVIntegerType(64, MIRBuilder);
4925 SPIRVTypeInst I64x2Type =
4926 GR.getOrCreateSPIRVVectorType(I64Type, 2, MIRBuilder, false);
4927 SPIRVTypeInst Vec2ResType =
4928 GR.getOrCreateSPIRVVectorType(BaseType, 2, MIRBuilder, false);
4929
4930 std::vector<Register> PartialRegs;
4931
4932 // Loops 0, 2, 4, ... but stops one loop early when ComponentCount is odd
4933 unsigned CurrentComponent = 0;
4934 for (; CurrentComponent + 1 < ComponentCount; CurrentComponent += 2) {
4935 // This register holds the firstbitX result for each of the i64x2 vectors
4936 // extracted from SrcReg
4937 Register BitSetResult =
4938 MRI->createVirtualRegister(GR.getRegClass(I64x2Type));
4939
4940 auto MIB = BuildMI(*I.getParent(), I, I.getDebugLoc(),
4941 TII.get(SPIRV::OpVectorShuffle))
4942 .addDef(BitSetResult)
4943 .addUse(GR.getSPIRVTypeID(I64x2Type))
4944 .addUse(SrcReg)
4945 .addUse(SrcReg)
4946 .addImm(CurrentComponent)
4947 .addImm(CurrentComponent + 1);
4948
4949 MIB.constrainAllUses(TII, TRI, RBI);
4950
4951 Register SubVecBitSetReg =
4952 MRI->createVirtualRegister(GR.getRegClass(Vec2ResType));
4953
4954 if (!selectFirstBitSet64(SubVecBitSetReg, Vec2ResType, I, BitSetResult,
4955 BitSetOpcode, SwapPrimarySide))
4956 return false;
4957
4958 PartialRegs.push_back(SubVecBitSetReg);
4959 }
4960
4961 // On odd component counts we need to handle one more component
4962 if (CurrentComponent != ComponentCount) {
4963 bool ZeroAsNull = !STI.isShader();
4964 Register FinalElemReg = MRI->createVirtualRegister(GR.getRegClass(I64Type));
4965 Register ConstIntLastIdx = GR.getOrCreateConstInt(
4966 ComponentCount - 1, I, BaseType, TII, ZeroAsNull);
4967
4968 if (!selectOpWithSrcs(FinalElemReg, I64Type, I, {SrcReg, ConstIntLastIdx},
4969 SPIRV::OpVectorExtractDynamic))
4970 return false;
4971
4972 Register FinalElemBitSetReg =
4973 MRI->createVirtualRegister(GR.getRegClass(BaseType));
4974
4975 if (!selectFirstBitSet64(FinalElemBitSetReg, BaseType, I, FinalElemReg,
4976 BitSetOpcode, SwapPrimarySide))
4977 return false;
4978
4979 PartialRegs.push_back(FinalElemBitSetReg);
4980 }
4981
4982 // Join all the resulting registers back into the return type in order
4983 // (ie i32x2, i32x2, i32x1 -> i32x5)
4984 return selectOpWithSrcs(ResVReg, ResType, I, std::move(PartialRegs),
4985 SPIRV::OpCompositeConstruct);
4986}
4987
4988bool SPIRVInstructionSelector::selectFirstBitSet64(
4989 Register ResVReg, SPIRVTypeInst ResType, MachineInstr &I, Register SrcReg,
4990 unsigned BitSetOpcode, bool SwapPrimarySide) const {
4991 unsigned ComponentCount = GR.getScalarOrVectorComponentCount(ResType);
4992 SPIRVTypeInst BaseType = GR.retrieveScalarOrVectorIntType(ResType);
4993 bool ZeroAsNull = !STI.isShader();
4994 Register ConstIntZero =
4995 GR.getOrCreateConstInt(0, I, BaseType, TII, ZeroAsNull);
4996 Register ConstIntOne =
4997 GR.getOrCreateConstInt(1, I, BaseType, TII, ZeroAsNull);
4998
4999 // SPIRV doesn't support vectors with more than 4 components. Since the
5000 // algoritm below converts i64 -> i32x2 and i64x4 -> i32x8 it can only
5001 // operate on vectors with 2 or less components. When largers vectors are
5002 // seen. Split them, recurse, then recombine them.
5003 if (ComponentCount > 2) {
5004 return selectFirstBitSet64Overflow(ResVReg, ResType, I, SrcReg,
5005 BitSetOpcode, SwapPrimarySide);
5006 }
5007
5008 // 1. Split int64 into 2 pieces using a bitcast
5009 MachineIRBuilder MIRBuilder(I);
5010 SPIRVTypeInst PostCastType = GR.getOrCreateSPIRVVectorType(
5011 BaseType, 2 * ComponentCount, MIRBuilder, false);
5012 Register BitcastReg =
5013 MRI->createVirtualRegister(GR.getRegClass(PostCastType));
5014
5015 if (!selectOpWithSrcs(BitcastReg, PostCastType, I, {SrcReg},
5016 SPIRV::OpBitcast))
5017 return false;
5018
5019 // 2. Find the first set bit from the primary side for all the pieces in #1
5020 Register FBSReg = MRI->createVirtualRegister(GR.getRegClass(PostCastType));
5021 if (!selectFirstBitSet32(FBSReg, PostCastType, I, BitcastReg, BitSetOpcode))
5022 return false;
5023
5024 // 3. Split result vector into high bits and low bits
5025 Register HighReg = MRI->createVirtualRegister(GR.getRegClass(ResType));
5026 Register LowReg = MRI->createVirtualRegister(GR.getRegClass(ResType));
5027
5028 bool IsScalarRes = ResType->getOpcode() != SPIRV::OpTypeVector;
5029 if (IsScalarRes) {
5030 // if scalar do a vector extract
5031 if (!selectOpWithSrcs(HighReg, ResType, I, {FBSReg, ConstIntZero},
5032 SPIRV::OpVectorExtractDynamic))
5033 return false;
5034 if (!selectOpWithSrcs(LowReg, ResType, I, {FBSReg, ConstIntOne},
5035 SPIRV::OpVectorExtractDynamic))
5036 return false;
5037 } else {
5038 // if vector do a shufflevector
5039 auto MIB = BuildMI(*I.getParent(), I, I.getDebugLoc(),
5040 TII.get(SPIRV::OpVectorShuffle))
5041 .addDef(HighReg)
5042 .addUse(GR.getSPIRVTypeID(ResType))
5043 .addUse(FBSReg)
5044 // Per the spec, repeat the vector if only one vec is needed
5045 .addUse(FBSReg);
5046
5047 // high bits are stored in even indexes. Extract them from FBSReg
5048 for (unsigned J = 0; J < ComponentCount * 2; J += 2) {
5049 MIB.addImm(J);
5050 }
5051
5052 MIB.constrainAllUses(TII, TRI, RBI);
5053
5054 MIB = BuildMI(*I.getParent(), I, I.getDebugLoc(),
5055 TII.get(SPIRV::OpVectorShuffle))
5056 .addDef(LowReg)
5057 .addUse(GR.getSPIRVTypeID(ResType))
5058 .addUse(FBSReg)
5059 // Per the spec, repeat the vector if only one vec is needed
5060 .addUse(FBSReg);
5061
5062 // low bits are stored in odd indexes. Extract them from FBSReg
5063 for (unsigned J = 1; J < ComponentCount * 2; J += 2) {
5064 MIB.addImm(J);
5065 }
5066 MIB.constrainAllUses(TII, TRI, RBI);
5067 }
5068
5069 // 4. Check the result. When primary bits == -1 use secondary, otherwise use
5070 // primary
5071 SPIRVTypeInst BoolType = GR.getOrCreateSPIRVBoolType(I, TII);
5072 Register NegOneReg;
5073 Register Reg0;
5074 Register Reg32;
5075 unsigned SelectOp;
5076 unsigned AddOp;
5077
5078 if (IsScalarRes) {
5079 NegOneReg =
5080 GR.getOrCreateConstInt((unsigned)-1, I, ResType, TII, ZeroAsNull);
5081 Reg0 = GR.getOrCreateConstInt(0, I, ResType, TII, ZeroAsNull);
5082 Reg32 = GR.getOrCreateConstInt(32, I, ResType, TII, ZeroAsNull);
5083 SelectOp = SPIRV::OpSelectSISCond;
5084 AddOp = SPIRV::OpIAddS;
5085 } else {
5086 BoolType = GR.getOrCreateSPIRVVectorType(BoolType, ComponentCount,
5087 MIRBuilder, false);
5088 NegOneReg =
5089 GR.getOrCreateConstVector((unsigned)-1, I, ResType, TII, ZeroAsNull);
5090 Reg0 = GR.getOrCreateConstVector(0, I, ResType, TII, ZeroAsNull);
5091 Reg32 = GR.getOrCreateConstVector(32, I, ResType, TII, ZeroAsNull);
5092 SelectOp = SPIRV::OpSelectVIVCond;
5093 AddOp = SPIRV::OpIAddV;
5094 }
5095
5096 Register PrimaryReg = HighReg;
5097 Register SecondaryReg = LowReg;
5098 Register PrimaryShiftReg = Reg32;
5099 Register SecondaryShiftReg = Reg0;
5100
5101 // By default the emitted opcodes check for the set bit from the MSB side.
5102 // Setting SwapPrimarySide checks the set bit from the LSB side
5103 if (SwapPrimarySide) {
5104 PrimaryReg = LowReg;
5105 SecondaryReg = HighReg;
5106 PrimaryShiftReg = Reg0;
5107 SecondaryShiftReg = Reg32;
5108 }
5109
5110 // Check if the primary bits are == -1
5111 Register BReg = MRI->createVirtualRegister(GR.getRegClass(BoolType));
5112 if (!selectOpWithSrcs(BReg, BoolType, I, {PrimaryReg, NegOneReg},
5113 SPIRV::OpIEqual))
5114 return false;
5115
5116 // Select secondary bits if true in BReg, otherwise primary bits
5117 Register TmpReg = MRI->createVirtualRegister(GR.getRegClass(ResType));
5118 if (!selectOpWithSrcs(TmpReg, ResType, I, {BReg, SecondaryReg, PrimaryReg},
5119 SelectOp))
5120 return false;
5121
5122 // 5. Add 32 when high bits are used, otherwise 0 for low bits
5123 Register ValReg = MRI->createVirtualRegister(GR.getRegClass(ResType));
5124 if (!selectOpWithSrcs(ValReg, ResType, I,
5125 {BReg, SecondaryShiftReg, PrimaryShiftReg}, SelectOp))
5126 return false;
5127
5128 return selectOpWithSrcs(ResVReg, ResType, I, {ValReg, TmpReg}, AddOp);
5129}
5130
5131bool SPIRVInstructionSelector::selectFirstBitHigh(Register ResVReg,
5132 SPIRVTypeInst ResType,
5133 MachineInstr &I,
5134 bool IsSigned) const {
5135 // FindUMsb and FindSMsb intrinsics only support 32 bit integers
5136 Register OpReg = I.getOperand(2).getReg();
5137 SPIRVTypeInst OpType = GR.getSPIRVTypeForVReg(OpReg);
5138 // zero or sign extend
5139 unsigned ExtendOpcode = IsSigned ? SPIRV::OpSConvert : SPIRV::OpUConvert;
5140 unsigned BitSetOpcode = IsSigned ? GL::FindSMsb : GL::FindUMsb;
5141
5142 switch (GR.getScalarOrVectorBitWidth(OpType)) {
5143 case 16:
5144 return selectFirstBitSet16(ResVReg, ResType, I, ExtendOpcode, BitSetOpcode);
5145 case 32:
5146 return selectFirstBitSet32(ResVReg, ResType, I, OpReg, BitSetOpcode);
5147 case 64:
5148 return selectFirstBitSet64(ResVReg, ResType, I, OpReg, BitSetOpcode,
5149 /*SwapPrimarySide=*/false);
5150 default:
5151 report_fatal_error(
5152 "spv_firstbituhigh and spv_firstbitshigh only support 16,32,64 bits.");
5153 }
5154}
5155
5156bool SPIRVInstructionSelector::selectFirstBitLow(Register ResVReg,
5157 SPIRVTypeInst ResType,
5158 MachineInstr &I) const {
5159 // FindILsb intrinsic only supports 32 bit integers
5160 Register OpReg = I.getOperand(2).getReg();
5161 SPIRVTypeInst OpType = GR.getSPIRVTypeForVReg(OpReg);
5162 // OpUConvert treats the operand bits as an unsigned i16 and zero extends it
5163 // to an unsigned i32. As this leaves all the least significant bits unchanged
5164 // so the first set bit from the LSB side doesn't change.
5165 unsigned ExtendOpcode = SPIRV::OpUConvert;
5166 unsigned BitSetOpcode = GL::FindILsb;
5167
5168 switch (GR.getScalarOrVectorBitWidth(OpType)) {
5169 case 16:
5170 return selectFirstBitSet16(ResVReg, ResType, I, ExtendOpcode, BitSetOpcode);
5171 case 32:
5172 return selectFirstBitSet32(ResVReg, ResType, I, OpReg, BitSetOpcode);
5173 case 64:
5174 return selectFirstBitSet64(ResVReg, ResType, I, OpReg, BitSetOpcode,
5175 /*SwapPrimarySide=*/true);
5176 default:
5177 report_fatal_error("spv_firstbitlow only supports 16,32,64 bits.");
5178 }
5179}
5180
5181bool SPIRVInstructionSelector::selectAllocaArray(Register ResVReg,
5182 SPIRVTypeInst ResType,
5183 MachineInstr &I) const {
5184 // there was an allocation size parameter to the allocation instruction
5185 // that is not 1
5186 MachineBasicBlock &BB = *I.getParent();
5187 BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpVariableLengthArrayINTEL))
5188 .addDef(ResVReg)
5189 .addUse(GR.getSPIRVTypeID(ResType))
5190 .addUse(I.getOperand(2).getReg())
5191 .constrainAllUses(TII, TRI, RBI);
5192 if (!STI.isShader()) {
5193 unsigned Alignment = I.getOperand(3).getImm();
5194 buildOpDecorate(ResVReg, I, TII, SPIRV::Decoration::Alignment, {Alignment});
5195 }
5196 return true;
5197}
5198
5199bool SPIRVInstructionSelector::selectFrameIndex(Register ResVReg,
5200 SPIRVTypeInst ResType,
5201 MachineInstr &I) const {
5202 // Change order of instructions if needed: all OpVariable instructions in a
5203 // function must be the first instructions in the first block
5204 auto It = getOpVariableMBBIt(I);
5205 BuildMI(*It->getParent(), It, It->getDebugLoc(), TII.get(SPIRV::OpVariable))
5206 .addDef(ResVReg)
5207 .addUse(GR.getSPIRVTypeID(ResType))
5208 .addImm(static_cast<uint32_t>(SPIRV::StorageClass::Function))
5209 .constrainAllUses(TII, TRI, RBI);
5210 if (!STI.isShader()) {
5211 unsigned Alignment = I.getOperand(2).getImm();
5212 buildOpDecorate(ResVReg, *It, TII, SPIRV::Decoration::Alignment,
5213 {Alignment});
5214 }
5215 return true;
5216}
5217
5218bool SPIRVInstructionSelector::selectBranch(MachineInstr &I) const {
5219 // InstructionSelector walks backwards through the instructions. We can use
5220 // both a G_BR and a G_BRCOND to create an OpBranchConditional. We hit G_BR
5221 // first, so can generate an OpBranchConditional here. If there is no
5222 // G_BRCOND, we just use OpBranch for a regular unconditional branch.
5223 const MachineInstr *PrevI = I.getPrevNode();
5224 MachineBasicBlock &MBB = *I.getParent();
5225 if (PrevI != nullptr && PrevI->getOpcode() == TargetOpcode::G_BRCOND) {
5226 BuildMI(MBB, I, I.getDebugLoc(), TII.get(SPIRV::OpBranchConditional))
5227 .addUse(PrevI->getOperand(0).getReg())
5228 .addMBB(PrevI->getOperand(1).getMBB())
5229 .addMBB(I.getOperand(0).getMBB())
5230 .constrainAllUses(TII, TRI, RBI);
5231 return true;
5232 }
5233 BuildMI(MBB, I, I.getDebugLoc(), TII.get(SPIRV::OpBranch))
5234 .addMBB(I.getOperand(0).getMBB())
5235 .constrainAllUses(TII, TRI, RBI);
5236 return true;
5237}
5238
5239bool SPIRVInstructionSelector::selectBranchCond(MachineInstr &I) const {
5240 // InstructionSelector walks backwards through the instructions. For an
5241 // explicit conditional branch with no fallthrough, we use both a G_BR and a
5242 // G_BRCOND to create an OpBranchConditional. We should hit G_BR first, and
5243 // generate the OpBranchConditional in selectBranch above.
5244 //
5245 // If an OpBranchConditional has been generated, we simply return, as the work
5246 // is alread done. If there is no OpBranchConditional, LLVM must be relying on
5247 // implicit fallthrough to the next basic block, so we need to create an
5248 // OpBranchConditional with an explicit "false" argument pointing to the next
5249 // basic block that LLVM would fall through to.
5250 const MachineInstr *NextI = I.getNextNode();
5251 // Check if this has already been successfully selected.
5252 if (NextI != nullptr && NextI->getOpcode() == SPIRV::OpBranchConditional)
5253 return true;
5254 // Must be relying on implicit block fallthrough, so generate an
5255 // OpBranchConditional with the "next" basic block as the "false" target.
5256 MachineBasicBlock &MBB = *I.getParent();
5257 unsigned NextMBBNum = MBB.getNextNode()->getNumber();
5258 MachineBasicBlock *NextMBB = I.getMF()->getBlockNumbered(NextMBBNum);
5259 BuildMI(MBB, I, I.getDebugLoc(), TII.get(SPIRV::OpBranchConditional))
5260 .addUse(I.getOperand(0).getReg())
5261 .addMBB(I.getOperand(1).getMBB())
5262 .addMBB(NextMBB)
5263 .constrainAllUses(TII, TRI, RBI);
5264 return true;
5265}
5266
5267bool SPIRVInstructionSelector::selectPhi(Register ResVReg,
5268 MachineInstr &I) const {
5269 auto MIB =
5270 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(TargetOpcode::PHI))
5271 .addDef(ResVReg);
5272 const unsigned NumOps = I.getNumOperands();
5273 for (unsigned i = 1; i < NumOps; i += 2) {
5274 MIB.addUse(I.getOperand(i + 0).getReg());
5275 MIB.addMBB(I.getOperand(i + 1).getMBB());
5276 }
5277 MIB.constrainAllUses(TII, TRI, RBI);
5278 return true;
5279}
5280
5281bool SPIRVInstructionSelector::selectGlobalValue(
5282 Register ResVReg, MachineInstr &I, const MachineInstr *Init) const {
5283 // FIXME: don't use MachineIRBuilder here, replace it with BuildMI.
5284 MachineIRBuilder MIRBuilder(I);
5285 const GlobalValue *GV = I.getOperand(1).getGlobal();
5286 Type *GVType = toTypedPointer(GR.getDeducedGlobalValueType(GV));
5287
5288 std::string GlobalIdent;
5289 if (!GV->hasName()) {
5290 unsigned &ID = UnnamedGlobalIDs[GV];
5291 if (ID == 0)
5292 ID = UnnamedGlobalIDs.size();
5293 GlobalIdent = "__unnamed_" + Twine(ID).str();
5294 } else {
5295 GlobalIdent = GV->getName();
5296 }
5297
5298 // Behaviour of functions as operands depends on availability of the
5299 // corresponding extension (SPV_INTEL_function_pointers):
5300 // - If there is an extension to operate with functions as operands:
5301 // We create a proper constant operand and evaluate a correct type for a
5302 // function pointer.
5303 // - Without the required extension:
5304 // We have functions as operands in tests with blocks of instruction e.g. in
5305 // transcoding/global_block.ll. These operands are not used and should be
5306 // substituted by zero constants. Their type is expected to be always
5307 // OpTypePointer Function %uchar.
5308 if (isa<Function>(GV)) {
5309 const Constant *ConstVal = GV;
5310 MachineBasicBlock &BB = *I.getParent();
5311 Register NewReg = GR.find(ConstVal, GR.CurMF);
5312 if (!NewReg.isValid()) {
5313 Register NewReg = ResVReg;
5314 const Function *GVFun =
5315 STI.canUseExtension(SPIRV::Extension::SPV_INTEL_function_pointers)
5316 ? dyn_cast<Function>(GV)
5317 : nullptr;
5318 SPIRVTypeInst ResType = GR.getOrCreateSPIRVPointerType(
5319 GVType, I,
5320 GVFun ? SPIRV::StorageClass::CodeSectionINTEL
5321 : addressSpaceToStorageClass(GV->getAddressSpace(), STI));
5322 if (GVFun) {
5323 // References to a function via function pointers generate virtual
5324 // registers without a definition. We will resolve it later, during
5325 // module analysis stage.
5326 Register ResTypeReg = GR.getSPIRVTypeID(ResType);
5327 MachineRegisterInfo *MRI = MIRBuilder.getMRI();
5328 Register FuncVReg =
5329 MRI->createGenericVirtualRegister(GR.getRegType(ResType));
5330 MRI->setRegClass(FuncVReg, &SPIRV::pIDRegClass);
5331 MachineInstrBuilder MIB1 =
5332 BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpUndef))
5333 .addDef(FuncVReg)
5334 .addUse(ResTypeReg);
5335 MachineInstrBuilder MIB2 =
5336 BuildMI(BB, I, I.getDebugLoc(),
5337 TII.get(SPIRV::OpConstantFunctionPointerINTEL))
5338 .addDef(NewReg)
5339 .addUse(ResTypeReg)
5340 .addUse(FuncVReg);
5341 GR.add(ConstVal, MIB2);
5342 // mapping the function pointer to the used Function
5343 GR.recordFunctionPointer(&MIB2.getInstr()->getOperand(2), GVFun);
5344 MIB1.constrainAllUses(TII, TRI, RBI);
5345 MIB2.constrainAllUses(TII, TRI, RBI);
5346 return true;
5347 }
5348 MachineInstrBuilder MIB3 =
5349 BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpConstantNull))
5350 .addDef(NewReg)
5351 .addUse(GR.getSPIRVTypeID(ResType));
5352 GR.add(ConstVal, MIB3);
5353 MIB3.constrainAllUses(TII, TRI, RBI);
5354 return true;
5355 }
5356 assert(NewReg != ResVReg);
5357 return BuildCOPY(ResVReg, NewReg, I);
5358 }
5359 auto GlobalVar = cast<GlobalVariable>(GV);
5360 assert(GlobalVar->getName() != "llvm.global.annotations");
5361
5362 // Skip empty declaration for GVs with initializers till we get the decl with
5363 // passed initializer.
5364 if (hasInitializer(GlobalVar) && !Init)
5365 return true;
5366
5367 const std::optional<SPIRV::LinkageType::LinkageType> LnkType =
5368 getSpirvLinkageTypeFor(STI, *GV);
5369
5370 const unsigned AddrSpace = GV->getAddressSpace();
5371 SPIRV::StorageClass::StorageClass StorageClass =
5372 addressSpaceToStorageClass(AddrSpace, STI);
5373 SPIRVTypeInst ResType =
5374 GR.getOrCreateSPIRVPointerType(GVType, I, StorageClass);
5375 Register Reg = GR.buildGlobalVariable(
5376 ResVReg, ResType, GlobalIdent, GV, StorageClass, Init,
5377 GlobalVar->isConstant(), LnkType, MIRBuilder, true);
5378 // TODO: For AMDGCN, we pipe externally_initialized through via
5379 // HostAccessINTEL, with ReadWrite (3) access, which is we then handle during
5380 // reverse translation. We should remove this once SPIR-V gains the ability to
5381 // express the concept.
5382 if (GlobalVar->isExternallyInitialized() &&
5383 STI.getTargetTriple().getVendor() == Triple::AMD) {
5384 constexpr unsigned ReadWriteINTEL = 3u;
5385 buildOpDecorate(Reg, MIRBuilder, SPIRV::Decoration::HostAccessINTEL,
5386 {ReadWriteINTEL});
5387 MachineInstrBuilder MIB(*MF, --MIRBuilder.getInsertPt());
5388 addStringImm(GV->getName(), MIB);
5389 }
5390 return Reg.isValid();
5391}
5392
5393bool SPIRVInstructionSelector::selectLog10(Register ResVReg,
5394 SPIRVTypeInst ResType,
5395 MachineInstr &I) const {
5396 if (STI.canUseExtInstSet(SPIRV::InstructionSet::OpenCL_std)) {
5397 return selectExtInst(ResVReg, ResType, I, CL::log10);
5398 }
5399
5400 // There is no log10 instruction in the GLSL Extended Instruction set, so it
5401 // is implemented as:
5402 // log10(x) = log2(x) * (1 / log2(10))
5403 // = log2(x) * 0.30103
5404
5405 MachineIRBuilder MIRBuilder(I);
5406 MachineBasicBlock &BB = *I.getParent();
5407
5408 // Build log2(x).
5409 Register VarReg = MRI->createVirtualRegister(GR.getRegClass(ResType));
5410 BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpExtInst))
5411 .addDef(VarReg)
5412 .addUse(GR.getSPIRVTypeID(ResType))
5413 .addImm(static_cast<uint32_t>(SPIRV::InstructionSet::GLSL_std_450))
5414 .addImm(GL::Log2)
5415 .add(I.getOperand(1))
5416 .constrainAllUses(TII, TRI, RBI);
5417
5418 // Build 0.30103.
5419 assert(ResType->getOpcode() == SPIRV::OpTypeVector ||
5420 ResType->getOpcode() == SPIRV::OpTypeFloat);
5421 // TODO: Add matrix implementation once supported by the HLSL frontend.
5422 SPIRVTypeInst SpirvScalarType = ResType->getOpcode() == SPIRV::OpTypeVector
5423 ? SPIRVTypeInst(GR.getSPIRVTypeForVReg(
5424 ResType->getOperand(1).getReg()))
5425 : ResType;
5426 Register ScaleReg =
5427 GR.buildConstantFP(APFloat(0.30103f), MIRBuilder, SpirvScalarType);
5428
5429 // Multiply log2(x) by 0.30103 to get log10(x) result.
5430 auto Opcode = ResType->getOpcode() == SPIRV::OpTypeVector
5431 ? SPIRV::OpVectorTimesScalar
5432 : SPIRV::OpFMulS;
5433 BuildMI(BB, I, I.getDebugLoc(), TII.get(Opcode))
5434 .addDef(ResVReg)
5435 .addUse(GR.getSPIRVTypeID(ResType))
5436 .addUse(VarReg)
5437 .addUse(ScaleReg)
5438 .constrainAllUses(TII, TRI, RBI);
5439 return true;
5440}
5441
5442bool SPIRVInstructionSelector::selectModf(Register ResVReg,
5443 SPIRVTypeInst ResType,
5444 MachineInstr &I) const {
5445 // llvm.modf has a single arg --the number to be decomposed-- and returns a
5446 // struct { restype, restype }, while OpenCLLIB::modf has two args --the
5447 // number to be decomposed and a pointer--, returns the fractional part and
5448 // the integral part is stored in the pointer argument. Therefore, we can't
5449 // use directly the OpenCLLIB::modf intrinsic. However, we can do some
5450 // scaffolding to make it work. The idea is to create an alloca instruction
5451 // to get a ptr, pass this ptr to OpenCL::modf, and then load the value
5452 // from this ptr to place it in the struct. llvm.modf returns the fractional
5453 // part as the first element of the result, and the integral part as the
5454 // second element of the result.
5455
5456 // At this point, the return type is not a struct anymore, but rather two
5457 // independent elements of SPIRVResType. We can get each independent element
5458 // from I.getDefs() or I.getOperands().
5459 if (STI.canUseExtInstSet(SPIRV::InstructionSet::OpenCL_std)) {
5460 MachineIRBuilder MIRBuilder(I);
5461 // Get pointer type for alloca variable.
5462 const SPIRVTypeInst PtrType = GR.getOrCreateSPIRVPointerType(
5463 ResType, MIRBuilder, SPIRV::StorageClass::Function);
5464 // Create new register for the pointer type of alloca variable.
5465 Register PtrTyReg =
5466 MIRBuilder.getMRI()->createVirtualRegister(&SPIRV::iIDRegClass);
5467 MIRBuilder.getMRI()->setType(
5468 PtrTyReg,
5469 LLT::pointer(storageClassToAddressSpace(SPIRV::StorageClass::Function),
5470 GR.getPointerSize()));
5471
5472 // Assign SPIR-V type of the pointer type of the alloca variable to the
5473 // new register.
5474 GR.assignSPIRVTypeToVReg(PtrType, PtrTyReg, MIRBuilder.getMF());
5475 MachineBasicBlock &EntryBB = I.getMF()->front();
5476 MachineBasicBlock::iterator VarPos =
5477 getFirstValidInstructionInsertPoint(EntryBB);
5478 auto AllocaMIB =
5479 BuildMI(EntryBB, VarPos, I.getDebugLoc(), TII.get(SPIRV::OpVariable))
5480 .addDef(PtrTyReg)
5481 .addUse(GR.getSPIRVTypeID(PtrType))
5482 .addImm(static_cast<uint32_t>(SPIRV::StorageClass::Function));
5483 Register Variable = AllocaMIB->getOperand(0).getReg();
5484
5485 MachineBasicBlock &BB = *I.getParent();
5486 // Create the OpenCLLIB::modf instruction.
5487 auto MIB =
5488 BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpExtInst))
5489 .addDef(ResVReg)
5490 .addUse(GR.getSPIRVTypeID(ResType))
5491 .addImm(static_cast<uint32_t>(SPIRV::InstructionSet::OpenCL_std))
5492 .addImm(CL::modf)
5493 .setMIFlags(I.getFlags())
5494 .add(I.getOperand(I.getNumExplicitDefs())) // Floating point value.
5495 .addUse(Variable); // Pointer to integral part.
5496 // Assign the integral part stored in the ptr to the second element of the
5497 // result.
5498 Register IntegralPartReg = I.getOperand(1).getReg();
5499 if (IntegralPartReg.isValid()) {
5500 // Load the value from the pointer to integral part.
5501 auto LoadMIB = BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpLoad))
5502 .addDef(IntegralPartReg)
5503 .addUse(GR.getSPIRVTypeID(ResType))
5504 .addUse(Variable);
5505 LoadMIB.constrainAllUses(TII, TRI, RBI);
5506 return true;
5507 }
5508
5509 MIB.constrainAllUses(TII, TRI, RBI);
5510 return true;
5511 } else if (STI.canUseExtInstSet(SPIRV::InstructionSet::GLSL_std_450)) {
5512 assert(false && "GLSL::Modf is deprecated.");
5513 // FIXME: GL::Modf is deprecated, use Modfstruct instead.
5514 return false;
5515 }
5516 return false;
5517}
5518
5519// Generate the instructions to load 3-element vector builtin input
5520// IDs/Indices.
5521// Like: GlobalInvocationId, LocalInvocationId, etc....
5522
5523bool SPIRVInstructionSelector::loadVec3BuiltinInputID(
5524 SPIRV::BuiltIn::BuiltIn BuiltInValue, Register ResVReg,
5525 SPIRVTypeInst ResType, MachineInstr &I) const {
5526 MachineIRBuilder MIRBuilder(I);
5527 const SPIRVTypeInst Vec3Ty =
5528 GR.getOrCreateSPIRVVectorType(ResType, 3, MIRBuilder, false);
5529 const SPIRVTypeInst PtrType = GR.getOrCreateSPIRVPointerType(
5530 Vec3Ty, MIRBuilder, SPIRV::StorageClass::Input);
5531
5532 // Create new register for the input ID builtin variable.
5533 Register NewRegister =
5534 MIRBuilder.getMRI()->createVirtualRegister(&SPIRV::iIDRegClass);
5535 MIRBuilder.getMRI()->setType(NewRegister, LLT::pointer(0, 64));
5536 GR.assignSPIRVTypeToVReg(PtrType, NewRegister, MIRBuilder.getMF());
5537
5538 // Build global variable with the necessary decorations for the input ID
5539 // builtin variable.
5540 Register Variable = GR.buildGlobalVariable(
5541 NewRegister, PtrType, getLinkStringForBuiltIn(BuiltInValue), nullptr,
5542 SPIRV::StorageClass::Input, nullptr, true, std::nullopt, MIRBuilder,
5543 false);
5544
5545 // Create new register for loading value.
5546 MachineRegisterInfo *MRI = MIRBuilder.getMRI();
5547 Register LoadedRegister = MRI->createVirtualRegister(&SPIRV::iIDRegClass);
5548 MIRBuilder.getMRI()->setType(LoadedRegister, LLT::pointer(0, 64));
5549 GR.assignSPIRVTypeToVReg(Vec3Ty, LoadedRegister, MIRBuilder.getMF());
5550
5551 // Load v3uint value from the global variable.
5552 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(SPIRV::OpLoad))
5553 .addDef(LoadedRegister)
5554 .addUse(GR.getSPIRVTypeID(Vec3Ty))
5555 .addUse(Variable);
5556
5557 // Get the input ID index. Expecting operand is a constant immediate value,
5558 // wrapped in a type assignment.
5559 assert(I.getOperand(2).isReg());
5560 const uint32_t ThreadId = foldImm(I.getOperand(2), MRI);
5561
5562 // Extract the input ID from the loaded vector value.
5563 MachineBasicBlock &BB = *I.getParent();
5564 auto MIB = BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpCompositeExtract))
5565 .addDef(ResVReg)
5566 .addUse(GR.getSPIRVTypeID(ResType))
5567 .addUse(LoadedRegister)
5568 .addImm(ThreadId);
5569 MIB.constrainAllUses(TII, TRI, RBI);
5570 return true;
5571}
5572
5573// Generate the instructions to load 32-bit integer builtin input IDs/Indices.
5574// Like LocalInvocationIndex
5575bool SPIRVInstructionSelector::loadBuiltinInputID(
5576 SPIRV::BuiltIn::BuiltIn BuiltInValue, Register ResVReg,
5577 SPIRVTypeInst ResType, MachineInstr &I) const {
5578 MachineIRBuilder MIRBuilder(I);
5579 const SPIRVTypeInst PtrType = GR.getOrCreateSPIRVPointerType(
5580 ResType, MIRBuilder, SPIRV::StorageClass::Input);
5581
5582 // Create new register for the input ID builtin variable.
5583 Register NewRegister =
5584 MIRBuilder.getMRI()->createVirtualRegister(GR.getRegClass(PtrType));
5585 MIRBuilder.getMRI()->setType(
5586 NewRegister,
5587 LLT::pointer(storageClassToAddressSpace(SPIRV::StorageClass::Input),
5588 GR.getPointerSize()));
5589 GR.assignSPIRVTypeToVReg(PtrType, NewRegister, MIRBuilder.getMF());
5590
5591 // Build global variable with the necessary decorations for the input ID
5592 // builtin variable.
5593 Register Variable = GR.buildGlobalVariable(
5594 NewRegister, PtrType, getLinkStringForBuiltIn(BuiltInValue), nullptr,
5595 SPIRV::StorageClass::Input, nullptr, true, std::nullopt, MIRBuilder,
5596 false);
5597
5598 // Load uint value from the global variable.
5599 auto MIB = BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(SPIRV::OpLoad))
5600 .addDef(ResVReg)
5601 .addUse(GR.getSPIRVTypeID(ResType))
5602 .addUse(Variable);
5603
5604 MIB.constrainAllUses(TII, TRI, RBI);
5605 return true;
5606}
5607
5608SPIRVTypeInst SPIRVInstructionSelector::widenTypeToVec4(SPIRVTypeInst Type,
5609 MachineInstr &I) const {
5610 MachineIRBuilder MIRBuilder(I);
5611 if (Type->getOpcode() != SPIRV::OpTypeVector)
5612 return GR.getOrCreateSPIRVVectorType(Type, 4, MIRBuilder, false);
5613
5614 uint64_t VectorSize = Type->getOperand(2).getImm();
5615 if (VectorSize == 4)
5616 return Type;
5617
5618 Register ScalarTypeReg = Type->getOperand(1).getReg();
5619 const SPIRVTypeInst ScalarType = GR.getSPIRVTypeForVReg(ScalarTypeReg);
5620 return GR.getOrCreateSPIRVVectorType(ScalarType, 4, MIRBuilder, false);
5621}
5622
5623bool SPIRVInstructionSelector::loadHandleBeforePosition(
5624 Register &HandleReg, SPIRVTypeInst ResType, GIntrinsic &HandleDef,
5625 MachineInstr &Pos) const {
5626
5627 assert(HandleDef.getIntrinsicID() ==
5628 Intrinsic::spv_resource_handlefrombinding);
5629 uint32_t Set = foldImm(HandleDef.getOperand(2), MRI);
5630 uint32_t Binding = foldImm(HandleDef.getOperand(3), MRI);
5631 uint32_t ArraySize = foldImm(HandleDef.getOperand(4), MRI);
5632 Register IndexReg = HandleDef.getOperand(5).getReg();
5633 std::string Name =
5634 getStringValueFromReg(HandleDef.getOperand(6).getReg(), *MRI);
5635
5636 bool IsStructuredBuffer = ResType->getOpcode() == SPIRV::OpTypePointer;
5637 MachineIRBuilder MIRBuilder(HandleDef);
5638 SPIRVTypeInst VarType = ResType;
5639 SPIRV::StorageClass::StorageClass SC = SPIRV::StorageClass::UniformConstant;
5640
5641 if (IsStructuredBuffer) {
5642 VarType = GR.getPointeeType(ResType);
5643 SC = GR.getPointerStorageClass(ResType);
5644 }
5645
5646 Register VarReg =
5647 buildPointerToResource(SPIRVTypeInst(VarType), SC, Set, Binding,
5648 ArraySize, IndexReg, Name, MIRBuilder);
5649
5650 // The handle for the buffer is the pointer to the resource. For an image, the
5651 // handle is the image object. So images get an extra load.
5652 uint32_t LoadOpcode =
5653 IsStructuredBuffer ? SPIRV::OpCopyObject : SPIRV::OpLoad;
5654 GR.assignSPIRVTypeToVReg(ResType, HandleReg, *Pos.getMF());
5655 BuildMI(*Pos.getParent(), Pos, HandleDef.getDebugLoc(), TII.get(LoadOpcode))
5656 .addDef(HandleReg)
5657 .addUse(GR.getSPIRVTypeID(ResType))
5658 .addUse(VarReg)
5659 .constrainAllUses(TII, TRI, RBI);
5660 return true;
5661}
5662
5663void SPIRVInstructionSelector::errorIfInstrOutsideShader(
5664 MachineInstr &I) const {
5665 if (!STI.isShader()) {
5666 std::string DiagMsg;
5667 raw_string_ostream OS(DiagMsg);
5668 I.print(OS, true, false, false, false);
5669 DiagMsg += " is only supported in shaders.\n";
5670 report_fatal_error(DiagMsg.c_str(), false);
5671 }
5672}
5673
5674namespace llvm {
5675InstructionSelector *
5676createSPIRVInstructionSelector(const SPIRVTargetMachine &TM,
5677 const SPIRVSubtarget &Subtarget,
5678 const RegisterBankInfo &RBI) {
5679 return new SPIRVInstructionSelector(TM, Subtarget, RBI);
5680}
5681} // namespace llvm
MRI
unsigned const MachineRegisterInfo * MRI
Definition AArch64AdvSIMDScalarPass.cpp:103
UseMI
MachineInstrBuilder & UseMI
Definition AArch64ExpandPseudoInsts.cpp:120
GET_GLOBALISEL_PREDICATES_INIT
#define GET_GLOBALISEL_PREDICATES_INIT
GET_GLOBALISEL_TEMPORARIES_INIT
#define GET_GLOBALISEL_TEMPORARIES_INIT
Generic
@ Generic
Definition AArch64MCAsmInfo.cpp:24
assert
assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")
APFloat.h
This file declares a class to represent arbitrary precision floating point values and provide a varie...
selectUnmergeValues
static bool selectUnmergeValues(MachineInstrBuilder &MIB, const ARMBaseInstrInfo &TII, MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI)
Definition ARMInstructionSelector.cpp:264
MBB
MachineBasicBlock & MBB
Definition ARMSLSHardening.cpp:71
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition ARMSLSHardening.cpp:73
true
basic Basic Alias true
Definition BasicAliasAnalysis.cpp:2036
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
Binding
DXIL Resource Implicit Binding
Definition DXILResourceImplicitBinding.cpp:185
DEBUG_TYPE
#define DEBUG_TYPE
Definition GenericCycleImpl.h:31
GenericMachineInstrs.h
Declares convenience wrapper classes for interpreting MachineInstr instances as specific generic oper...
TII
const HexagonInstrInfo * TII
Definition HexagonCopyToCombine.cpp:118
MI
IRTranslator LLVM IR MI
Definition IRTranslator.cpp:110
LLVMIntType
LLVMTypeRef LLVMIntType(unsigned NumBits)
Definition Core.cpp:717
NumOps
const size_t AbstractManglingParser< Derived, Alloc >::NumOps
Definition ItaniumDemangle.h:3452
I
#define I(x, y, z)
Definition MD5.cpp:57
Reg
Register Reg
Definition MachineSink.cpp:2119
TRI
Register const TargetRegisterInfo * TRI
Definition MachineSink.cpp:2120
Register
Promote Memory to Register
Definition Mem2Reg.cpp:110
OpIdx
MachineInstr unsigned OpIdx
Definition NVPTXPrologEpilogPass.cpp:56
II
uint64_t IntrinsicInst * II
Definition NVVMIntrRange.cpp:46
getName
static StringRef getName(Value *V)
Definition ProvenanceAnalysisEvaluator.cpp:20
getFCmpOpcode
static unsigned getFCmpOpcode(CmpInst::Predicate Pred, unsigned Size)
Definition RISCVInstructionSelector.cpp:1782
getOneFP
static APFloat getOneFP(const Type *LLVMFloatTy)
Definition SPIRVInstructionSelector.cpp:2381
isUSMStorageClass
static bool isUSMStorageClass(SPIRV::StorageClass::StorageClass SC)
Definition SPIRVInstructionSelector.cpp:2114
isASCastInGVar
static bool isASCastInGVar(MachineRegisterInfo *MRI, Register ResVReg)
Definition SPIRVInstructionSelector.cpp:2125
mayApplyGenericSelection
static bool mayApplyGenericSelection(unsigned Opcode)
Definition SPIRVInstructionSelector.cpp:862
getZeroFP
static APFloat getZeroFP(const Type *LLVMFloatTy)
Definition SPIRVInstructionSelector.cpp:2367
ExtInstList
std::vector< std::pair< SPIRV::InstructionSet::InstructionSet, uint32_t > > ExtInstList
Definition SPIRVInstructionSelector.cpp:42
intrinsicHasSideEffects
static bool intrinsicHasSideEffects(Intrinsic::ID ID)
Definition SPIRVInstructionSelector.cpp:579
getBoolCmpOpcode
static unsigned getBoolCmpOpcode(unsigned PredNum)
Definition SPIRVInstructionSelector.cpp:2355
getICmpOpcode
static unsigned getICmpOpcode(unsigned PredNum)
Definition SPIRVInstructionSelector.cpp:2315
isOpcodeWithNoSideEffects
static bool isOpcodeWithNoSideEffects(unsigned Opcode)
Definition SPIRVInstructionSelector.cpp:645
addMemoryOperands
static void addMemoryOperands(MachineMemOperand *MemOp, MachineInstrBuilder &MIB, MachineIRBuilder &MIRBuilder, SPIRVGlobalRegistry &GR)
Definition SPIRVInstructionSelector.cpp:1571
isConstReg
static bool isConstReg(MachineRegisterInfo *MRI, MachineInstr *OpDef)
Definition SPIRVInstructionSelector.cpp:514
getPtrCmpOpcode
static unsigned getPtrCmpOpcode(unsigned Pred)
Definition SPIRVInstructionSelector.cpp:2343
isDead
bool isDead(const MachineInstr &MI, const MachineRegisterInfo &MRI)
Definition SPIRVInstructionSelector.cpp:679
SPIRV
spirv structurize SPIRV
Definition SPIRVStructurizer.cpp:1222
BaseType
BaseType
A given derived pointer can have multiple base pointers through phi/selects.
Definition SafepointIRVerifier.cpp:311
StringExtras.h
This file contains some functions that are useful when dealing with strings.
LLVM_DEBUG
#define LLVM_DEBUG(...)
Definition Debug.h:114
Y
static TableGen::Emitter::Opt Y("gen-skeleton-entry", EmitSkeleton, "Generate example skeleton entry")
X
static TableGen::Emitter::OptClass< SkeletonEmitter > X("gen-skeleton-class", "Generate example skeleton class")
Mul
BinaryOperator * Mul
Definition X86PartialReduction.cpp:75
llvm::APFloatBase::IEEEsingle
static const fltSemantics & IEEEsingle()
Definition APFloat.h:296
llvm::APFloatBase::IEEEdouble
static const fltSemantics & IEEEdouble()
Definition APFloat.h:297
llvm::APFloatBase::IEEEhalf
static const fltSemantics & IEEEhalf()
Definition APFloat.h:294
llvm::APFloat::getOne
static APFloat getOne(const fltSemantics &Sem, bool Negative=false)
Factory for Positive and Negative One.
Definition APFloat.h:1139
llvm::APFloat::getZero
static APFloat getZero(const fltSemantics &Sem, bool Negative=false)
Factory for Positive and Negative Zero.
Definition APFloat.h:1130
llvm::APInt::getAllOnes
static APInt getAllOnes(unsigned numBits)
Return an APInt of a specified width with all bits set.
Definition APInt.h:235
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition ArrayRef.h:40
llvm::BlockFrequencyInfo
BlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate IR basic block frequen...
Definition BlockFrequencyInfo.h:38
llvm::CmpInst::Predicate
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition InstrTypes.h:676
llvm::CmpInst::FCMP_OEQ
@ FCMP_OEQ
0 0 0 1 True if ordered and equal
Definition InstrTypes.h:679
llvm::CmpInst::ICMP_SLT
@ ICMP_SLT
signed less than
Definition InstrTypes.h:705
llvm::CmpInst::ICMP_SLE
@ ICMP_SLE
signed less or equal
Definition InstrTypes.h:706
llvm::CmpInst::FCMP_OLT
@ FCMP_OLT
0 1 0 0 True if ordered and less than
Definition InstrTypes.h:682
llvm::CmpInst::FCMP_ULE
@ FCMP_ULE
1 1 0 1 True if unordered, less than, or equal
Definition InstrTypes.h:691
llvm::CmpInst::FCMP_OGT
@ FCMP_OGT
0 0 1 0 True if ordered and greater than
Definition InstrTypes.h:680
llvm::CmpInst::FCMP_OGE
@ FCMP_OGE
0 0 1 1 True if ordered and greater than or equal
Definition InstrTypes.h:681
llvm::CmpInst::ICMP_UGE
@ ICMP_UGE
unsigned greater or equal
Definition InstrTypes.h:700
llvm::CmpInst::ICMP_UGT
@ ICMP_UGT
unsigned greater than
Definition InstrTypes.h:699
llvm::CmpInst::ICMP_SGT
@ ICMP_SGT
signed greater than
Definition InstrTypes.h:703
llvm::CmpInst::FCMP_ULT
@ FCMP_ULT
1 1 0 0 True if unordered or less than
Definition InstrTypes.h:690
llvm::CmpInst::FCMP_ONE
@ FCMP_ONE
0 1 1 0 True if ordered and operands are unequal
Definition InstrTypes.h:684
llvm::CmpInst::FCMP_UEQ
@ FCMP_UEQ
1 0 0 1 True if unordered or equal
Definition InstrTypes.h:687
llvm::CmpInst::ICMP_ULT
@ ICMP_ULT
unsigned less than
Definition InstrTypes.h:701
llvm::CmpInst::FCMP_UGT
@ FCMP_UGT
1 0 1 0 True if unordered or greater than
Definition InstrTypes.h:688
llvm::CmpInst::FCMP_OLE
@ FCMP_OLE
0 1 0 1 True if ordered and less than or equal
Definition InstrTypes.h:683
llvm::CmpInst::FCMP_ORD
@ FCMP_ORD
0 1 1 1 True if ordered (no nans)
Definition InstrTypes.h:685
llvm::CmpInst::ICMP_NE
@ ICMP_NE
not equal
Definition InstrTypes.h:698
llvm::CmpInst::ICMP_SGE
@ ICMP_SGE
signed greater or equal
Definition InstrTypes.h:704
llvm::CmpInst::FCMP_UNE
@ FCMP_UNE
1 1 1 0 True if unordered or not equal
Definition InstrTypes.h:692
llvm::CmpInst::ICMP_ULE
@ ICMP_ULE
unsigned less or equal
Definition InstrTypes.h:702
llvm::CmpInst::FCMP_UGE
@ FCMP_UGE
1 0 1 1 True if unordered, greater than, or equal
Definition InstrTypes.h:689
llvm::CmpInst::FCMP_UNO
@ FCMP_UNO
1 0 0 0 True if unordered: isnan(X) | isnan(Y)
Definition InstrTypes.h:686
llvm::Constant::getNullValue
static LLVM_ABI Constant * getNullValue(Type *Ty)
Constructor to create a '0' constant of arbitrary type.
Definition Constants.cpp:374
llvm::DenseMapBase::size
unsigned size() const
Definition DenseMap.h:110
llvm::Function::getContext
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function.
Definition Function.cpp:358
llvm::GIntrinsic::getIntrinsicID
Intrinsic::ID getIntrinsicID() const
Definition GenericMachineInstrs.h:531
llvm::GlobalValue::getAddressSpace
unsigned getAddressSpace() const
Definition GlobalValue.h:207
llvm::GlobalValue::getParent
Module * getParent()
Get the module that this global value is contained inside of...
Definition GlobalValue.h:663
llvm::GlobalValue::InternalLinkage
@ InternalLinkage
Rename collisions when linking (static functions).
Definition GlobalValue.h:60
llvm::IntegerType::get
static LLVM_ABI IntegerType * get(LLVMContext &C, unsigned NumBits)
This static method is the primary way of constructing an IntegerType.
Definition Type.cpp:318
llvm::LLT::isScalar
constexpr bool isScalar() const
Definition LowLevelType.h:147
llvm::LLT::scalar
static constexpr LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
Definition LowLevelType.h:43
llvm::LLT::isValid
constexpr bool isValid() const
Definition LowLevelType.h:146
llvm::LLT::getNumElements
constexpr uint16_t getNumElements() const
Returns the number of elements in a vector LLT.
Definition LowLevelType.h:160
llvm::LLT::isVector
constexpr bool isVector() const
Definition LowLevelType.h:149
llvm::LLT::pointer
static constexpr LLT pointer(unsigned AddressSpace, unsigned SizeInBits)
Get a low-level pointer in the given address space.
Definition LowLevelType.h:58
llvm::LLT::isPointer
constexpr bool isPointer() const
Definition LowLevelType.h:150
llvm::LLT::fixed_vector
static constexpr LLT fixed_vector(unsigned NumElements, unsigned ScalarSizeInBits)
Get a low-level fixed-width vector of some number of elements and element width.
Definition LowLevelType.h:101
llvm::MachineBasicBlock::getNumber
int getNumber() const
MachineBasicBlocks are uniquely numbered at the function level, unless they're not in a MachineFuncti...
Definition MachineBasicBlock.h:1283
llvm::MachineBasicBlock::getFirstNonPHI
LLVM_ABI iterator getFirstNonPHI()
Returns a pointer to the first instruction in this block that is not a PHINode instruction.
Definition MachineBasicBlock.cpp:200
llvm::MachineBasicBlock::getParent
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
Definition MachineBasicBlock.h:331
llvm::MachineBasicBlock::iterator
MachineInstrBundleIterator< MachineInstr > iterator
Definition MachineBasicBlock.h:349
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition MachineFunction.h:786
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition MachineFunction.h:747
llvm::MachineIRBuilder
Helper class to build MachineInstr.
Definition MachineIRBuilder.h:237
llvm::MachineIRBuilder::getInsertPt
MachineBasicBlock::iterator getInsertPt()
Current insertion point for new instructions.
Definition MachineIRBuilder.h:335
llvm::MachineIRBuilder::buildInstr
MachineInstrBuilder buildInstr(unsigned Opcode)
Build and insert <empty> = Opcode <empty>.
Definition MachineIRBuilder.h:423
llvm::MachineIRBuilder::getMF
MachineFunction & getMF()
Getter for the function we currently build.
Definition MachineIRBuilder.h:289
llvm::MachineIRBuilder::getMRI
MachineRegisterInfo * getMRI()
Getter for MRI.
Definition MachineIRBuilder.h:311
llvm::MachineInstrBuilder::constrainAllUses
void constrainAllUses(const TargetInstrInfo &TII, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI) const
Definition MachineInstrBuilder.h:441
llvm::MachineInstrBuilder::addUse
const MachineInstrBuilder & addUse(Register RegNo, RegState Flags={}, unsigned SubReg=0) const
Add a virtual register use operand.
Definition MachineInstrBuilder.h:225
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(Register RegNo, RegState Flags={}, unsigned SubReg=0) const
Add a new virtual register operand.
Definition MachineInstrBuilder.h:199
llvm::MachineInstrBuilder::addImm
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Definition MachineInstrBuilder.h:233
llvm::MachineInstrBuilder::add
const MachineInstrBuilder & add(const MachineOperand &MO) const
Definition MachineInstrBuilder.h:326
llvm::MachineInstrBuilder::addMBB
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
Definition MachineInstrBuilder.h:248
llvm::MachineInstrBuilder::addDef
const MachineInstrBuilder & addDef(Register RegNo, RegState Flags={}, unsigned SubReg=0) const
Add a virtual register definition operand.
Definition MachineInstrBuilder.h:218
llvm::MachineInstrBuilder::setMIFlags
const MachineInstrBuilder & setMIFlags(unsigned Flags) const
Definition MachineInstrBuilder.h:379
llvm::MachineInstrBuilder::getInstr
MachineInstr * getInstr() const
If conversion operators fail, use this method to get the MachineInstr explicitly.
Definition MachineInstrBuilder.h:191
llvm::MachineInstr
Representation of each machine instruction.
Definition MachineInstr.h:72
llvm::MachineInstr::getOpcode
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition MachineInstr.h:599
llvm::MachineInstr::getParent
const MachineBasicBlock * getParent() const
Definition MachineInstr.h:371
llvm::MachineInstr::getNumOperands
unsigned getNumOperands() const
Retuns the total number of operands.
Definition MachineInstr.h:602
llvm::MachineInstr::getNumExplicitDefs
LLVM_ABI unsigned getNumExplicitDefs() const
Returns the number of non-implicit definitions.
Definition MachineInstr.cpp:869
llvm::MachineInstr::emitGenericError
LLVM_ABI void emitGenericError(const Twine &ErrMsg) const
Definition MachineInstr.cpp:2374
llvm::MachineInstr::getMF
LLVM_ABI const MachineFunction * getMF() const
Return the function that contains the basic block that this instruction belongs to.
Definition MachineInstr.cpp:786
llvm::MachineInstr::getDebugLoc
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition MachineInstr.h:523
llvm::MachineInstr::getOperand
const MachineOperand & getOperand(unsigned i) const
Definition MachineInstr.h:607
llvm::MachineMemOperand
A description of a memory reference used in the backend.
Definition MachineMemOperand.h:130
llvm::MachineMemOperand::MOVolatile
@ MOVolatile
The memory access is volatile.
Definition MachineMemOperand.h:141
llvm::MachineMemOperand::MONonTemporal
@ MONonTemporal
The memory access is non-temporal.
Definition MachineMemOperand.h:143
llvm::MachineOperand::getImm
int64_t getImm() const
Definition MachineOperand.h:560
llvm::MachineOperand::isReg
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Definition MachineOperand.h:331
llvm::MachineOperand::getMBB
MachineBasicBlock * getMBB() const
Definition MachineOperand.h:575
llvm::MachineOperand::getReg
Register getReg() const
getReg - Returns the register number.
Definition MachineOperand.h:372
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition MachineRegisterInfo.h:53
llvm::MachineRegisterInfo::use_instr_iterator
defusechain_instr_iterator< true, false, false, true > use_instr_iterator
use_instr_iterator/use_instr_begin/use_instr_end - Walk all uses of the specified register,...
Definition MachineRegisterInfo.h:478
llvm::MachineRegisterInfo::def_instr_iterator
defusechain_instr_iterator< false, true, false, true > def_instr_iterator
def_instr_iterator/def_instr_begin/def_instr_end - Walk all defs of the specified register,...
Definition MachineRegisterInfo.h:399
llvm::MachineRegisterInfo::createVirtualRegister
LLVM_ABI Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
Definition MachineRegisterInfo.cpp:154
llvm::MachineRegisterInfo::setType
LLVM_ABI void setType(Register VReg, LLT Ty)
Set the low-level type of VReg to Ty.
Definition MachineRegisterInfo.cpp:185
llvm::ProfileSummaryInfo
Analysis providing profile information.
Definition ProfileSummaryInfo.h:42
llvm::RegisterBankInfo
Holds all the information related to register banks.
Definition RegisterBankInfo.h:40
llvm::Register
Wrapper class representing virtual and physical registers.
Definition Register.h:20
llvm::Register::isValid
constexpr bool isValid() const
Definition Register.h:112
llvm::Register::isPhysical
constexpr bool isPhysical() const
Return true if the specified register number is in the physical register namespace.
Definition Register.h:83
llvm::SPIRVGlobalRegistry::isScalarOrVectorSigned
bool isScalarOrVectorSigned(SPIRVTypeInst Type) const
Definition SPIRVGlobalRegistry.cpp:1443
llvm::SPIRVGlobalRegistry::getOrCreateOpTypeSampledImage
SPIRVTypeInst getOrCreateOpTypeSampledImage(SPIRVTypeInst ImageType, MachineIRBuilder &MIRBuilder)
Definition SPIRVGlobalRegistry.cpp:1691
llvm::SPIRVGlobalRegistry::assignSPIRVTypeToVReg
void assignSPIRVTypeToVReg(SPIRVTypeInst Type, Register VReg, const MachineFunction &MF)
Definition SPIRVGlobalRegistry.cpp:130
llvm::SPIRVGlobalRegistry::getRegClass
const TargetRegisterClass * getRegClass(SPIRVTypeInst SpvType) const
Definition SPIRVGlobalRegistry.cpp:2050
llvm::SPIRVGlobalRegistry::getOrAddMemAliasingINTELInst
MachineInstr * getOrAddMemAliasingINTELInst(MachineIRBuilder &MIRBuilder, const MDNode *AliasingListMD)
Definition SPIRVGlobalRegistry.cpp:2115
llvm::SPIRVGlobalRegistry::isAggregateType
bool isAggregateType(SPIRVTypeInst Type) const
Definition SPIRVGlobalRegistry.h:371
llvm::SPIRVGlobalRegistry::getScalarOrVectorBitWidth
unsigned getScalarOrVectorBitWidth(SPIRVTypeInst Type) const
Definition SPIRVGlobalRegistry.cpp:1408
llvm::SPIRVGlobalRegistry::getOrCreateSPIRVIntegerType
SPIRVTypeInst getOrCreateSPIRVIntegerType(unsigned BitWidth, MachineIRBuilder &MIRBuilder)
Definition SPIRVGlobalRegistry.cpp:1821
llvm::SPIRVGlobalRegistry::getOrCreateSPIRVVectorType
SPIRVTypeInst getOrCreateSPIRVVectorType(SPIRVTypeInst BaseType, unsigned NumElements, MachineIRBuilder &MIRBuilder, bool EmitIR)
Definition SPIRVGlobalRegistry.cpp:1920
llvm::SPIRVGlobalRegistry::buildGlobalVariable
Register buildGlobalVariable(Register Reg, SPIRVTypeInst BaseType, StringRef Name, const GlobalValue *GV, SPIRV::StorageClass::StorageClass Storage, const MachineInstr *Init, bool IsConst, const std::optional< SPIRV::LinkageType::LinkageType > &LinkageType, MachineIRBuilder &MIRBuilder, bool IsInstSelector)
Definition SPIRVGlobalRegistry.cpp:780
llvm::SPIRVGlobalRegistry::getResultType
SPIRVTypeInst getResultType(Register VReg, MachineFunction *MF=nullptr)
Definition SPIRVGlobalRegistry.cpp:1291
llvm::SPIRVGlobalRegistry::getScalarOrVectorComponentCount
unsigned getScalarOrVectorComponentCount(Register VReg) const
Definition SPIRVGlobalRegistry.cpp:1381
llvm::SPIRVGlobalRegistry::getTypeForSPIRVType
const Type * getTypeForSPIRVType(SPIRVTypeInst Ty) const
Definition SPIRVGlobalRegistry.h:324
llvm::SPIRVGlobalRegistry::isBitcastCompatible
bool isBitcastCompatible(SPIRVTypeInst Type1, SPIRVTypeInst Type2) const
Definition SPIRVGlobalRegistry.cpp:1459
llvm::SPIRVGlobalRegistry::getOrCreateConstFP
Register getOrCreateConstFP(APFloat Val, MachineInstr &I, SPIRVTypeInst SpvType, const SPIRVInstrInfo &TII, bool ZeroAsNull=true)
Definition SPIRVGlobalRegistry.cpp:334
llvm::SPIRVGlobalRegistry::getRegType
LLT getRegType(SPIRVTypeInst SpvType) const
Definition SPIRVGlobalRegistry.cpp:2077
llvm::SPIRVGlobalRegistry::invalidateMachineInstr
void invalidateMachineInstr(MachineInstr *MI)
Definition SPIRVGlobalRegistry.cpp:233
llvm::SPIRVGlobalRegistry::getOrCreateSPIRVBoolType
SPIRVTypeInst getOrCreateSPIRVBoolType(MachineIRBuilder &MIRBuilder, bool EmitIR)
Definition SPIRVGlobalRegistry.cpp:1895
llvm::SPIRVGlobalRegistry::getOrCreateSPIRVPointerType
SPIRVTypeInst getOrCreateSPIRVPointerType(const Type *BaseType, MachineIRBuilder &MIRBuilder, SPIRV::StorageClass::StorageClass SC)
Definition SPIRVGlobalRegistry.cpp:1958
llvm::SPIRVGlobalRegistry::isScalarOfType
bool isScalarOfType(Register VReg, unsigned TypeOpcode) const
Definition SPIRVGlobalRegistry.cpp:1346
llvm::SPIRVGlobalRegistry::getSPIRVTypeID
Register getSPIRVTypeID(SPIRVTypeInst SpirvType) const
Definition SPIRVGlobalRegistry.cpp:1122
llvm::SPIRVGlobalRegistry::getOrCreateConstInt
Register getOrCreateConstInt(uint64_t Val, MachineInstr &I, SPIRVTypeInst SpvType, const SPIRVInstrInfo &TII, bool ZeroAsNull=true)
Definition SPIRVGlobalRegistry.cpp:387
llvm::SPIRVGlobalRegistry::getOrCreateConstIntArray
Register getOrCreateConstIntArray(uint64_t Val, size_t Num, MachineInstr &I, SPIRVTypeInst SpvType, const SPIRVInstrInfo &TII)
Definition SPIRVGlobalRegistry.cpp:646
llvm::SPIRVGlobalRegistry::findValueAttrs
bool findValueAttrs(const MachineInstr *Key, Type *&Ty, StringRef &Name)
Definition SPIRVGlobalRegistry.h:176
llvm::SPIRVGlobalRegistry::retrieveScalarOrVectorIntType
SPIRVTypeInst retrieveScalarOrVectorIntType(SPIRVTypeInst Type) const
Definition SPIRVGlobalRegistry.cpp:1437
llvm::SPIRVGlobalRegistry::getOrCreateGlobalVariableWithBinding
Register getOrCreateGlobalVariableWithBinding(SPIRVTypeInst VarType, uint32_t Set, uint32_t Binding, StringRef Name, MachineIRBuilder &MIRBuilder)
Definition SPIRVGlobalRegistry.cpp:885
llvm::SPIRVGlobalRegistry::changePointerStorageClass
SPIRVTypeInst changePointerStorageClass(SPIRVTypeInst PtrType, SPIRV::StorageClass::StorageClass SC, MachineInstr &I)
Definition SPIRVGlobalRegistry.cpp:1969
llvm::SPIRVGlobalRegistry::getOrCreateConstVector
Register getOrCreateConstVector(uint64_t Val, MachineInstr &I, SPIRVTypeInst SpvType, const SPIRVInstrInfo &TII, bool ZeroAsNull=true)
Definition SPIRVGlobalRegistry.cpp:597
llvm::SPIRVGlobalRegistry::buildConstantFP
Register buildConstantFP(APFloat Val, MachineIRBuilder &MIRBuilder, SPIRVTypeInst SpvType=nullptr)
Definition SPIRVGlobalRegistry.cpp:501
llvm::SPIRVGlobalRegistry::addGlobalObject
void addGlobalObject(const Value *V, const MachineFunction *MF, Register R)
Definition SPIRVGlobalRegistry.h:122
llvm::SPIRVGlobalRegistry::getScalarOrVectorComponentType
SPIRVTypeInst getScalarOrVectorComponentType(SPIRVTypeInst Type) const
Definition SPIRVGlobalRegistry.cpp:1395
llvm::SPIRVGlobalRegistry::recordFunctionPointer
void recordFunctionPointer(const MachineOperand *MO, const Function *F)
Definition SPIRVGlobalRegistry.h:259
llvm::SPIRVGlobalRegistry::getOrCreateSPIRVFloatType
SPIRVTypeInst getOrCreateSPIRVFloatType(unsigned BitWidth, MachineInstr &I, const SPIRVInstrInfo &TII)
Definition SPIRVGlobalRegistry.cpp:1874
llvm::SPIRVGlobalRegistry::getPointeeType
SPIRVTypeInst getPointeeType(SPIRVTypeInst PtrType)
Definition SPIRVGlobalRegistry.cpp:1448
llvm::SPIRVGlobalRegistry::getOrCreateSPIRVType
SPIRVTypeInst getOrCreateSPIRVType(const Type *Type, MachineInstr &I, SPIRV::AccessQualifier::AccessQualifier AQ, bool EmitIR)
Definition SPIRVGlobalRegistry.h:310
llvm::SPIRVGlobalRegistry::isScalarOrVectorOfType
bool isScalarOrVectorOfType(Register VReg, unsigned TypeOpcode) const
Definition SPIRVGlobalRegistry.cpp:1353
llvm::SPIRVGlobalRegistry::setCurrentFunc
MachineFunction * setCurrentFunc(MachineFunction &MF)
Definition SPIRVGlobalRegistry.h:364
llvm::SPIRVGlobalRegistry::getOrCreateConstNullPtr
Register getOrCreateConstNullPtr(MachineIRBuilder &MIRBuilder, SPIRVTypeInst SpvType)
Definition SPIRVGlobalRegistry.cpp:729
llvm::SPIRVGlobalRegistry::getSPIRVTypeForVReg
SPIRVTypeInst getSPIRVTypeForVReg(Register VReg, const MachineFunction *MF=nullptr) const
Definition SPIRVGlobalRegistry.cpp:1280
llvm::SPIRVGlobalRegistry::getDeducedGlobalValueType
Type * getDeducedGlobalValueType(const GlobalValue *Global)
Definition SPIRVGlobalRegistry.h:212
llvm::SPIRVGlobalRegistry::getOrCreateUndef
Register getOrCreateUndef(MachineInstr &I, SPIRVTypeInst SpvType, const SPIRVInstrInfo &TII)
Definition SPIRVGlobalRegistry.cpp:2016
llvm::SPIRVGlobalRegistry::getPointerStorageClass
SPIRV::StorageClass::StorageClass getPointerStorageClass(Register VReg) const
Definition SPIRVGlobalRegistry.cpp:1479
llvm::SPIRVIRMapping::erase
bool erase(const MachineInstr *MI)
Definition SPIRVIRMapping.h:211
llvm::SPIRVIRMapping::add
bool add(SPIRV::IRHandle Handle, const MachineInstr *MI)
Definition SPIRVIRMapping.h:189
llvm::SPIRVIRMapping::find
Register find(SPIRV::IRHandle Handle, const MachineFunction *MF)
Definition SPIRVIRMapping.h:235
llvm::SPIRVSubtarget::isPhysicalSPIRV
bool isPhysicalSPIRV() const
Definition SPIRVSubtarget.h:93
llvm::SPIRVSubtarget::isAtLeastSPIRVVer
bool isAtLeastSPIRVVer(VersionTuple VerToCompareTo) const
Definition SPIRVSubtarget.cpp:142
llvm::SPIRVSubtarget::canUseExtInstSet
bool canUseExtInstSet(SPIRV::InstructionSet::InstructionSet E) const
Definition SPIRVSubtarget.cpp:129
llvm::SPIRVSubtarget::isLogicalSPIRV
bool isLogicalSPIRV() const
Definition SPIRVSubtarget.h:90
llvm::SPIRVSubtarget::canUseExtension
bool canUseExtension(SPIRV::Extension::Extension E) const
Definition SPIRVSubtarget.cpp:125
llvm::SmallPtrSetImpl::insert
std::pair< iterator, bool > insert(PtrType Ptr)
Inserts Ptr if and only if there is no element in the container equal to Ptr.
Definition SmallPtrSet.h:389
llvm::SmallPtrSetImpl::contains
bool contains(ConstPtrType Ptr) const
Definition SmallPtrSet.h:461
llvm::SmallPtrSet
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements.
Definition SmallPtrSet.h:527
llvm::SmallVectorImpl::emplace_back
reference emplace_back(ArgTypes &&... Args)
Definition SmallVector.h:946
llvm::SmallVectorTemplateBase::push_back
void push_back(const T &Elt)
Definition SmallVector.h:419
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition SmallVector.h:1205
llvm::StringRef::size
constexpr size_t size() const
size - Get the string size.
Definition StringRef.h:143
llvm::StructType::get
static LLVM_ABI StructType * get(LLVMContext &Context, ArrayRef< Type * > Elements, bool isPacked=false)
This static method is the primary way to create a literal StructType.
Definition Type.cpp:413
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition Type.h:45
llvm::Type::HalfTyID
@ HalfTyID
16-bit floating point type
Definition Type.h:56
llvm::Type::FloatTyID
@ FloatTyID
32-bit floating point type
Definition Type.h:58
llvm::Type::DoubleTyID
@ DoubleTyID
64-bit floating point type
Definition Type.h:59
llvm::Type::getScalarType
Type * getScalarType() const
If this is a vector type, return the element type, otherwise return 'this'.
Definition Type.h:352
llvm::Type::isStructTy
bool isStructTy() const
True if this is an instance of StructType.
Definition Type.h:261
llvm::Type::isAggregateType
bool isAggregateType() const
Return true if the type is an aggregate type.
Definition Type.h:304
llvm::Type::getTypeID
TypeID getTypeID() const
Return the type id for the type.
Definition Type.h:136
llvm::User::getOperand
Value * getOperand(unsigned i) const
Definition User.h:207
llvm::Value::hasName
bool hasName() const
Definition Value.h:262
llvm::Value::getName
LLVM_ABI StringRef getName() const
Return a constant reference to the value's name.
Definition Value.cpp:322
llvm::ilist_node_with_parent::getNextNode
NodeTy * getNextNode()
Get the next node, or nullptr for the list tail.
Definition ilist_node.h:348
uint32_t
uint64_t
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition ErrorHandling.h:164
llvm::AMDGPU::HSAMD::Kernel::Arg::Key::IsConst
constexpr char IsConst[]
Key for Kernel::Arg::Metadata::mIsConst.
Definition AMDGPUMetadata.h:197
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition CallingConv.h:24
llvm::dwarf_linker::DebugSectionKind::DebugLoc
@ DebugLoc
Definition DWARFLinkerBase.h:34
llvm::rdf::Def
NodeAddr< DefNode * > Def
Definition RDFGraph.h:384
llvm::rdf::Instr
NodeAddr< InstrNode * > Instr
Definition RDFGraph.h:389
llvm::rdf::Use
NodeAddr< UseNode * > Use
Definition RDFGraph.h:385
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition Types.h:26
llvm::buildOpName
void buildOpName(Register Target, const StringRef &Name, MachineIRBuilder &MIRBuilder)
Definition SPIRVUtils.cpp:187
llvm::Offset
@ Offset
Definition DWP.cpp:532
llvm::all_of
bool all_of(R &&range, UnaryPredicate P)
Provide wrappers to std::all_of which take ranges instead of having to pass begin/end explicitly.
Definition STLExtras.h:1739
llvm::getIConstValSext
int64_t getIConstValSext(Register ConstReg, const MachineRegisterInfo *MRI)
Definition SPIRVUtils.cpp:464
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition MachineInstrBuilder.h:449
llvm::isTypeFoldingSupported
bool isTypeFoldingSupported(unsigned Opcode)
Definition SPIRVUtils.cpp:1064
llvm::dyn_cast
decltype(auto) dyn_cast(const From &Val)
dyn_cast<X> - Return the argument parameter cast to the specified type.
Definition Casting.h:643
llvm::Int32Ty
FunctionAddr VTableAddr uintptr_t uintptr_t Int32Ty
Definition InstrProf.h:296
llvm::addNumImm
void addNumImm(const APInt &Imm, MachineInstrBuilder &MIB)
Definition SPIRVUtils.cpp:156
llvm::salvageDebugInfo
LLVM_ABI void salvageDebugInfo(const MachineRegisterInfo &MRI, MachineInstr &MI)
Assuming the instruction MI is going to be deleted, attempt to salvage debug users of MI by writing t...
Definition Utils.cpp:1730
llvm::constrainSelectedInstRegOperands
LLVM_ABI void constrainSelectedInstRegOperands(MachineInstr &I, const TargetInstrInfo &TII, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI)
Mutate the newly-selected instruction I to constrain its (possibly generic) virtual register operands...
Definition Utils.cpp:155
llvm::isPreISelGenericOpcode
bool isPreISelGenericOpcode(unsigned Opcode)
Check whether the given Opcode is a generic opcode that is not supposed to appear after ISel.
Definition TargetOpcodes.h:30
llvm::createVirtualRegister
Register createVirtualRegister(SPIRVTypeInst SpvType, SPIRVGlobalRegistry *GR, MachineRegisterInfo *MRI, const MachineFunction &MF)
Definition SPIRVUtils.cpp:890
llvm::getArrayComponentCount
unsigned getArrayComponentCount(const MachineRegisterInfo *MRI, const MachineInstr *ResType)
Definition SPIRVUtils.cpp:1101
llvm::getIConstVal
uint64_t getIConstVal(Register ConstReg, const MachineRegisterInfo *MRI)
Definition SPIRVUtils.cpp:458
llvm::createContinuedInstructions
SmallVector< MachineInstr *, 4 > createContinuedInstructions(MachineIRBuilder &MIRBuilder, unsigned Opcode, unsigned MinWC, unsigned ContinuedOpcode, ArrayRef< Register > Args, Register ReturnRegister, Register TypeID)
Definition SPIRVUtils.cpp:955
llvm::getMemSemanticsForStorageClass
SPIRV::MemorySemantics::MemorySemantics getMemSemanticsForStorageClass(SPIRV::StorageClass::StorageClass SC)
Definition SPIRVUtils.cpp:373
llvm::storageClassToAddressSpace
constexpr unsigned storageClassToAddressSpace(SPIRV::StorageClass::StorageClass SC)
Definition SPIRVUtils.h:247
llvm::getFirstValidInstructionInsertPoint
MachineBasicBlock::iterator getFirstValidInstructionInsertPoint(MachineBasicBlock &BB)
Definition SPIRVUtils.cpp:1107
llvm::buildOpDecorate
void buildOpDecorate(Register Reg, MachineIRBuilder &MIRBuilder, SPIRV::Decoration::Decoration Dec, const std::vector< uint32_t > &DecArgs, StringRef StrImm)
Definition SPIRVUtils.cpp:214
llvm::getOpVariableMBBIt
MachineBasicBlock::iterator getOpVariableMBBIt(MachineInstr &I)
Definition SPIRVUtils.cpp:299
llvm::getImm
MachineInstr * getImm(const MachineOperand &MO, const MachineRegisterInfo *MRI)
Definition SPIRVUtils.cpp:1082
llvm::toTypedPointer
Type * toTypedPointer(Type *Ty)
Definition SPIRVUtils.h:461
llvm::dbgs
LLVM_ABI raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition Debug.cpp:207
llvm::report_fatal_error
LLVM_ABI void report_fatal_error(Error Err, bool gen_crash_diag=true)
Definition Error.cpp:163
llvm::isGenericCastablePtr
constexpr bool isGenericCastablePtr(SPIRV::StorageClass::StorageClass SC)
Definition SPIRVUtils.h:232
llvm::SmallVector
class LLVM_GSL_OWNER SmallVector
Forward declaration of SmallVector so that calculateSmallVectorDefaultInlinedElements can reference s...
Definition SmallVector.h:1131
llvm::passCopy
MachineInstr * passCopy(MachineInstr *Def, const MachineRegisterInfo *MRI)
Definition SPIRVUtils.cpp:1069
llvm::isa
bool isa(const From &Val)
isa<X> - Return true if the parameter to the template is an instance of one of the template type argu...
Definition Casting.h:547
llvm::getSpirvLinkageTypeFor
std::optional< SPIRV::LinkageType::LinkageType > getSpirvLinkageTypeFor(const SPIRVSubtarget &ST, const GlobalValue &GV)
Definition SPIRVUtils.cpp:1199
llvm::errs
LLVM_ABI raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.
Definition raw_ostream.cpp:904
llvm::addressSpaceToStorageClass
SPIRV::StorageClass::StorageClass addressSpaceToStorageClass(unsigned AddrSpace, const SPIRVSubtarget &STI)
Definition SPIRVUtils.cpp:333
llvm::AtomicOrdering
AtomicOrdering
Atomic ordering for LLVM's memory model.
Definition AtomicOrdering.h:56
llvm::getMemScope
SPIRV::Scope::Scope getMemScope(LLVMContext &Ctx, SyncScope::ID Id)
Definition SPIRVUtils.cpp:409
llvm::createSPIRVInstructionSelector
InstructionSelector * createSPIRVInstructionSelector(const SPIRVTargetMachine &TM, const SPIRVSubtarget &Subtarget, const RegisterBankInfo &RBI)
Definition SPIRVInstructionSelector.cpp:5676
llvm::getStringValueFromReg
std::string getStringValueFromReg(Register Reg, MachineRegisterInfo &MRI)
Definition SPIRVUtils.cpp:146
llvm::foldImm
int64_t foldImm(const MachineOperand &MO, const MachineRegisterInfo *MRI)
Definition SPIRVUtils.cpp:1091
llvm::Op
DWARFExpression::Operation Op
Definition DWARFExpressionPrinter.cpp:22
llvm::ArrayRef
ArrayRef(const T &OneElt) -> ArrayRef< T >
llvm::getDefInstrMaybeConstant
MachineInstr * getDefInstrMaybeConstant(Register &ConstReg, const MachineRegisterInfo *MRI)
Definition SPIRVUtils.cpp:435
llvm::BitWidth
constexpr unsigned BitWidth
Definition BitmaskEnum.h:219
llvm::cast
decltype(auto) cast(const From &Val)
cast<X> - Return the argument parameter cast to the specified type.
Definition Casting.h:559
llvm::hasInitializer
bool hasInitializer(const GlobalVariable *GV)
Definition SPIRVUtils.h:349
llvm::addStringImm
void addStringImm(const StringRef &Str, MCInst &Inst)
Definition SPIRVUtils.cpp:117
llvm::getVRegDef
MachineInstr * getVRegDef(MachineRegisterInfo &MRI, Register Reg)
Definition SPIRVUtils.cpp:843
llvm::getMemSemantics
SPIRV::MemorySemantics::MemorySemantics getMemSemantics(AtomicOrdering Ord)
Definition SPIRVUtils.cpp:391
llvm::getLinkStringForBuiltIn
std::string getLinkStringForBuiltIn(SPIRV::BuiltIn::BuiltIn BuiltInValue)
Definition SPIRVBaseInfo.cpp:202
llvm::isTriviallyDead
LLVM_ABI bool isTriviallyDead(const MachineInstr &MI, const MachineRegisterInfo &MRI)
Check whether an instruction MI is dead: it only defines dead virtual registers, and doesn't have oth...
Definition Utils.cpp:221
N
#define N
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