41 TargetOpcode::G_CONSTANT,
42 TargetOpcode::G_FCONSTANT,
49 TargetOpcode::G_SELECT,
50 TargetOpcode::G_EXTRACT_VECTOR_ELT,
58 using namespace TargetOpcode;
61 GR = ST.getSPIRVGlobalRegistry();
99 const unsigned PSize = ST.getPointerSize();
110 auto allPtrsScalarsAndVectors = {
111 p0, p1, p2, p3, p4, p5, p6, s1, s8, s16,
112 s32, s64, v2s1, v2s8, v2s16, v2s32, v2s64, v3s1, v3s8, v3s16,
113 v3s32, v3s64, v4s1, v4s8, v4s16, v4s32, v4s64, v8s1, v8s8, v8s16,
114 v8s32, v8s64, v16s1, v16s8, v16s16, v16s32, v16s64};
116 auto allVectors = {v2s1, v2s8, v2s16, v2s32, v2s64, v3s1, v3s8,
117 v3s16, v3s32, v3s64, v4s1, v4s8, v4s16, v4s32,
118 v4s64, v8s1, v8s8, v8s16, v8s32, v8s64, v16s1,
119 v16s8, v16s16, v16s32, v16s64};
121 auto allScalarsAndVectors = {
122 s1, s8, s16, s32, s64, v2s1, v2s8, v2s16, v2s32, v2s64,
123 v3s1, v3s8, v3s16, v3s32, v3s64, v4s1, v4s8, v4s16, v4s32, v4s64,
124 v8s1, v8s8, v8s16, v8s32, v8s64, v16s1, v16s8, v16s16, v16s32, v16s64};
126 auto allIntScalarsAndVectors = {s8, s16, s32, s64, v2s8, v2s16,
127 v2s32, v2s64, v3s8, v3s16, v3s32, v3s64,
128 v4s8, v4s16, v4s32, v4s64, v8s8, v8s16,
129 v8s32, v8s64, v16s8, v16s16, v16s32, v16s64};
131 auto allBoolScalarsAndVectors = {s1, v2s1, v3s1, v4s1, v8s1, v16s1};
133 auto allIntScalars = {s8, s16, s32, s64};
135 auto allFloatScalars = {s16, s32, s64};
137 auto allFloatScalarsAndVectors = {
138 s16, s32, s64, v2s16, v2s32, v2s64, v3s16, v3s32, v3s64,
139 v4s16, v4s32, v4s64, v8s16, v8s32, v8s64, v16s16, v16s32, v16s64};
141 auto allFloatAndIntScalarsAndPtrs = {s8, s16, s32, s64, p0, p1,
144 auto allPtrs = {p0, p1, p2, p3, p4, p5, p6};
145 auto allWritablePtrs = {p0, p1, p3, p4, p5, p6};
154 {G_BUILD_VECTOR, G_SHUFFLE_VECTOR, G_SPLAT_VECTOR})
159 {G_VECREDUCE_SMIN, G_VECREDUCE_SMAX, G_VECREDUCE_UMIN, G_VECREDUCE_UMAX,
160 G_VECREDUCE_ADD, G_VECREDUCE_MUL, G_VECREDUCE_FMUL, G_VECREDUCE_FMIN,
161 G_VECREDUCE_FMAX, G_VECREDUCE_FMINIMUM, G_VECREDUCE_FMAXIMUM,
162 G_VECREDUCE_OR, G_VECREDUCE_AND, G_VECREDUCE_XOR})
163 .legalFor(allVectors)
191 .legalForCartesianProduct(allIntScalarsAndVectors,
192 allFloatScalarsAndVectors);
195 .legalForCartesianProduct(allFloatScalarsAndVectors,
196 allScalarsAndVectors);
199 .legalFor(allIntScalarsAndVectors);
202 allIntScalarsAndVectors, allIntScalarsAndVectors);
208 typeInSet(1, allPtrsScalarsAndVectors)));
219 allPtrs, allIntScalars);
225 typeInSet(1, allPtrsScalarsAndVectors)));
229 typeInSet(1, allFloatScalarsAndVectors)));
232 G_ATOMICRMW_MAX, G_ATOMICRMW_MIN,
233 G_ATOMICRMW_SUB, G_ATOMICRMW_XOR,
234 G_ATOMICRMW_UMAX, G_ATOMICRMW_UMIN})
235 .legalForCartesianProduct(allIntScalars, allWritablePtrs);
238 {G_ATOMICRMW_FADD, G_ATOMICRMW_FSUB, G_ATOMICRMW_FMIN, G_ATOMICRMW_FMAX})
239 .legalForCartesianProduct(allFloatScalars, allWritablePtrs);
253 .legalForCartesianProduct(allScalarsAndVectors);
257 .legalForCartesianProduct(allFloatScalarsAndVectors);
296 G_INTRINSIC_ROUNDEVEN})
297 .legalFor(allFloatScalarsAndVectors);
301 allFloatScalarsAndVectors);
304 allFloatScalarsAndVectors, allIntScalarsAndVectors);
306 if (ST.canUseExtInstSet(SPIRV::InstructionSet::OpenCL_std)) {
308 {G_CTTZ, G_CTTZ_ZERO_UNDEF, G_CTLZ, G_CTLZ_ZERO_UNDEF})
309 .legalForCartesianProduct(allIntScalarsAndVectors,
310 allIntScalarsAndVectors);
317 .legalFor(allIntScalarsAndVectors);
321 verify(*ST.getInstrInfo());
328 Register ConvReg =
MRI.createGenericVirtualRegister(ConvTy);
339 auto Opc =
MI.getOpcode();
342 assert(Opc == TargetOpcode::G_ICMP);
344 auto &Op0 =
MI.getOperand(2);
345 auto &Op1 =
MI.getOperand(3);
352 MRI.getType(Reg0).isPointer() &&
MRI.getType(Reg1).isPointer()) {
unsigned const MachineRegisterInfo * MRI
static void scalarize(BinaryOperator *BO, SmallVectorImpl< BinaryOperator * > &Replace)
This file declares the MachineIRBuilder class.
const SmallVectorImpl< MachineOperand > & Cond
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool isTypeFoldingSupported(unsigned Opcode)
static const std::set< unsigned > TypeFoldingSupportingOpcs
static Register convertPtrToInt(Register Reg, LLT ConvTy, SPIRVType *SpirvType, LegalizerHelper &Helper, MachineRegisterInfo &MRI, SPIRVGlobalRegistry *GR)
bool isTypeFoldingSupported(unsigned Opcode)
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
static IntegerType * get(LLVMContext &C, unsigned NumBits)
This static method is the primary way of constructing an IntegerType.
static constexpr LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
static constexpr LLT pointer(unsigned AddressSpace, unsigned SizeInBits)
Get a low-level pointer in the given address space.
static constexpr LLT fixed_vector(unsigned NumElements, unsigned ScalarSizeInBits)
Get a low-level fixed-width vector of some number of elements and element width.
void computeTables()
Compute any ancillary tables needed to quickly decide how an operation should be handled.
LegalizeRuleSet & legalFor(std::initializer_list< LLT > Types)
The instruction is legal when type index 0 is any type in the given list.
LegalizeRuleSet & lower()
The instruction is lowered.
LegalizeRuleSet & custom()
Unconditionally custom lower.
LegalizeRuleSet & alwaysLegal()
LegalizeRuleSet & customIf(LegalityPredicate Predicate)
LegalizeRuleSet & scalarize(unsigned TypeIdx)
LegalizeRuleSet & legalForCartesianProduct(std::initializer_list< LLT > Types)
The instruction is legal when type indexes 0 and 1 are both in the given list.
LegalizeRuleSet & legalIf(LegalityPredicate Predicate)
The instruction is legal if predicate is true.
MachineIRBuilder & MIRBuilder
Expose MIRBuilder so clients can set their own RecordInsertInstruction functions.
LegalizeRuleSet & getActionDefinitionsBuilder(unsigned Opcode)
Get the action definition builder for the given opcode.
const LegacyLegalizerInfo & getLegacyLegalizerInfo() const
MachineInstrBuilder buildInstr(unsigned Opcode)
Build and insert <empty> = Opcode <empty>.
MachineFunction & getMF()
Getter for the function we currently build.
const MachineInstrBuilder & addUse(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register use operand.
const MachineInstrBuilder & addDef(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register definition operand.
Representation of each machine instruction.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Wrapper class representing virtual and physical registers.
SPIRVType * getSPIRVTypeForVReg(Register VReg, const MachineFunction *MF=nullptr) const
SPIRVType * getOrCreateSPIRVType(const Type *Type, MachineIRBuilder &MIRBuilder, SPIRV::AccessQualifier::AccessQualifier AQ=SPIRV::AccessQualifier::ReadWrite, bool EmitIR=true)
void assignSPIRVTypeToVReg(SPIRVType *Type, Register VReg, MachineFunction &MF)
SPIRVLegalizerInfo(const SPIRVSubtarget &ST)
bool legalizeCustom(LegalizerHelper &Helper, MachineInstr &MI, LostDebugLocObserver &LocObserver) const override
Called for instructions with the Custom LegalizationAction.
unsigned getPointerSize() const
bool canDirectlyComparePointers() const
The instances of the Type class are immutable: once they are created, they are never changed.
LegalityPredicate typeInSet(unsigned TypeIdx, std::initializer_list< LLT > TypesInit)
True iff the given type index is one of the specified types.
Predicate all(Predicate P0, Predicate P1)
True iff P0 and P1 are true.
This is an optimization pass for GlobalISel generic memory operations.