LLVM 22.0.0git
MachineRegisterInfo.h
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1//===- llvm/CodeGen/MachineRegisterInfo.h -----------------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the MachineRegisterInfo class.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_CODEGEN_MACHINEREGISTERINFO_H
14#define LLVM_CODEGEN_MACHINEREGISTERINFO_H
15
16#include "llvm/ADT/ArrayRef.h"
17#include "llvm/ADT/BitVector.h"
18#include "llvm/ADT/IndexedMap.h"
22#include "llvm/ADT/StringSet.h"
32#include "llvm/MC/LaneBitmask.h"
34#include <cassert>
35#include <cstddef>
36#include <cstdint>
37#include <iterator>
38#include <memory>
39#include <utility>
40#include <vector>
41
42namespace llvm {
43
44class PSetIterator;
45
46/// Convenient type to represent either a register class or a register bank.
49
50/// MachineRegisterInfo - Keep track of information for virtual and physical
51/// registers, including vreg register classes, use/def chains for registers,
52/// etc.
54public:
56 virtual void anchor();
57
58 public:
59 virtual ~Delegate() = default;
60
63 Register SrcReg) {
65 }
66 };
67
68private:
70 SmallPtrSet<Delegate *, 1> TheDelegates;
71
72 /// True if subregister liveness is tracked.
73 const bool TracksSubRegLiveness;
74
75 /// VRegInfo - Information we keep for each virtual register.
76 ///
77 /// Each element in this list contains the register class of the vreg and the
78 /// start of the use/def list for the register.
82
83 /// Map for recovering vreg name from vreg number.
84 /// This map is used by the MIR Printer.
86
87 /// StringSet that is used to unique vreg names.
88 StringSet<> VRegNames;
89
90 /// The flag is true upon \p UpdatedCSRs initialization
91 /// and false otherwise.
92 bool IsUpdatedCSRsInitialized = false;
93
94 /// Contains the updated callee saved register list.
95 /// As opposed to the static list defined in register info,
96 /// all registers that were disabled are removed from the list.
98
99 /// RegAllocHints - This vector records register allocation hints for
100 /// virtual registers. For each virtual register, it keeps a pair of hint
101 /// type and hints vector making up the allocation hints. Only the first
102 /// hint may be target specific, and in that case this is reflected by the
103 /// first member of the pair being non-zero. If the hinted register is
104 /// virtual, it means the allocator should prefer the physical register
105 /// allocated to it if any.
108 RegAllocHints;
109
110 /// PhysRegUseDefLists - This is an array of the head of the use/def list for
111 /// physical registers.
112 std::unique_ptr<MachineOperand *[]> PhysRegUseDefLists;
113
114 /// getRegUseDefListHead - Return the head pointer for the register use/def
115 /// list for the specified virtual or physical register.
116 MachineOperand *&getRegUseDefListHead(Register RegNo) {
117 if (RegNo.isVirtual())
118 return VRegInfo[RegNo.id()].second;
119 return PhysRegUseDefLists[RegNo.id()];
120 }
121
122 MachineOperand *getRegUseDefListHead(Register RegNo) const {
123 if (RegNo.isVirtual())
124 return VRegInfo[RegNo.id()].second;
125 return PhysRegUseDefLists[RegNo.id()];
126 }
127
128 /// Get the next element in the use-def chain.
129 static MachineOperand *getNextOperandForReg(const MachineOperand *MO) {
130 assert(MO && MO->isReg() && "This is not a register operand!");
131 return MO->Contents.Reg.Next;
132 }
133
134 /// UsedPhysRegMask - Additional used physregs including aliases.
135 /// This bit vector represents all the registers clobbered by function calls.
136 BitVector UsedPhysRegMask;
137
138 /// ReservedRegs - This is a bit vector of reserved registers. The target
139 /// may change its mind about which registers should be reserved. This
140 /// vector is the frozen set of reserved registers when register allocation
141 /// started.
142 BitVector ReservedRegs;
143
144 using VRegToTypeMap = IndexedMap<LLT, VirtReg2IndexFunctor>;
145 /// Map generic virtual registers to their low-level type.
146 VRegToTypeMap VRegToType;
147
148 /// Keep track of the physical registers that are live in to the function.
149 /// Live in values are typically arguments in registers. LiveIn values are
150 /// allowed to have virtual registers associated with them, stored in the
151 /// second element.
152 std::vector<std::pair<MCRegister, Register>> LiveIns;
153
154public:
155 LLVM_ABI explicit MachineRegisterInfo(MachineFunction *MF);
158
160 return MF->getSubtarget().getRegisterInfo();
161 }
162
163 void resetDelegate(Delegate *delegate) {
164 // Ensure another delegate does not take over unless the current
165 // delegate first unattaches itself.
166 assert(TheDelegates.count(delegate) &&
167 "Only an existing delegate can perform reset!");
168 TheDelegates.erase(delegate);
169 }
170
171 void addDelegate(Delegate *delegate) {
172 assert(delegate && !TheDelegates.count(delegate) &&
173 "Attempted to add null delegate, or to change it without "
174 "first resetting it!");
175
176 TheDelegates.insert(delegate);
177 }
178
180 for (auto *TheDelegate : TheDelegates)
181 TheDelegate->MRI_NoteNewVirtualRegister(Reg);
182 }
183
185 for (auto *TheDelegate : TheDelegates)
186 TheDelegate->MRI_NoteCloneVirtualRegister(NewReg, SrcReg);
187 }
188
189 const MachineFunction &getMF() const { return *MF; }
190
191 //===--------------------------------------------------------------------===//
192 // Function State
193 //===--------------------------------------------------------------------===//
194
195 // isSSA - Returns true when the machine function is in SSA form. Early
196 // passes require the machine function to be in SSA form where every virtual
197 // register has a single defining instruction.
198 //
199 // The TwoAddressInstructionPass and PHIElimination passes take the machine
200 // function out of SSA form when they introduce multiple defs per virtual
201 // register.
202 bool isSSA() const { return MF->getProperties().hasIsSSA(); }
203
204 // leaveSSA - Indicates that the machine function is no longer in SSA form.
205 void leaveSSA() { MF->getProperties().resetIsSSA(); }
206
207 /// tracksLiveness - Returns true when tracking register liveness accurately.
208 /// (see MachineFUnctionProperties::Property description for details)
209 bool tracksLiveness() const {
210 return MF->getProperties().hasTracksLiveness();
211 }
212
213 /// invalidateLiveness - Indicates that register liveness is no longer being
214 /// tracked accurately.
215 ///
216 /// This should be called by late passes that invalidate the liveness
217 /// information.
218 void invalidateLiveness() { MF->getProperties().resetTracksLiveness(); }
219
220 /// Returns true if liveness for register class @p RC should be tracked at
221 /// the subregister level.
226 assert(VReg.isVirtual() && "Must pass a VReg");
227 const TargetRegisterClass *RC = getRegClassOrNull(VReg);
228 return LLVM_LIKELY(RC) ? shouldTrackSubRegLiveness(*RC) : false;
229 }
231 return TracksSubRegLiveness;
232 }
233
234 //===--------------------------------------------------------------------===//
235 // Register Info
236 //===--------------------------------------------------------------------===//
237
238 /// Returns true if the updated CSR list was initialized and false otherwise.
239 bool isUpdatedCSRsInitialized() const { return IsUpdatedCSRsInitialized; }
240
241 /// Disables the register from the list of CSRs.
242 /// I.e. the register will not appear as part of the CSR mask.
243 /// \see UpdatedCalleeSavedRegs.
245
246 /// Returns list of callee saved registers.
247 /// The function returns the updated CSR list (after taking into account
248 /// registers that are disabled from the CSR list).
250
251 /// Sets the updated Callee Saved Registers list.
252 /// Notice that it will override ant previously disabled/saved CSRs.
254
255 // Strictly for use by MachineInstr.cpp.
257
258 // Strictly for use by MachineInstr.cpp.
260
261 // Strictly for use by MachineInstr.cpp.
263 unsigned NumOps);
264
265 /// Verify the sanity of the use list for Reg.
267
268 /// Verify the use list of all registers.
269 LLVM_ABI void verifyUseLists() const;
270
271 /// reg_begin/reg_end - Provide iteration support to walk over all definitions
272 /// and uses of a register within the MachineFunction that corresponds to this
273 /// MachineRegisterInfo object.
274 template <bool Uses, bool Defs, bool SkipDebug, bool ByOperand, bool ByInstr>
276 template <bool Uses, bool Defs, bool SkipDebug, bool ByInstr>
278
279 // Make it a friend so it can access getNextOperandForReg().
280 template <bool, bool, bool, bool, bool> friend class defusechain_iterator;
281 template <bool, bool, bool, bool> friend class defusechain_instr_iterator;
282
283 /// reg_iterator/reg_begin/reg_end - Walk all defs and uses of the specified
284 /// register.
287 return reg_iterator(getRegUseDefListHead(RegNo));
288 }
289 static reg_iterator reg_end() { return reg_iterator(nullptr); }
290
294
295 /// reg_instr_iterator/reg_instr_begin/reg_instr_end - Walk all defs and uses
296 /// of the specified register, stepping by MachineInstr.
298 defusechain_instr_iterator<true, true, false, /*ByInstr=*/true>;
300 return reg_instr_iterator(getRegUseDefListHead(RegNo));
301 }
303 return reg_instr_iterator(nullptr);
304 }
305
310
311 /// reg_bundle_iterator/reg_bundle_begin/reg_bundle_end - Walk all defs and uses
312 /// of the specified register, stepping by bundle.
314 defusechain_instr_iterator<true, true, false, /*ByInstr=*/false>;
316 return reg_bundle_iterator(getRegUseDefListHead(RegNo));
317 }
319 return reg_bundle_iterator(nullptr);
320 }
321
325
326 /// reg_empty - Return true if there are no instructions using or defining the
327 /// specified register (it may be live-in).
328 bool reg_empty(Register RegNo) const { return reg_begin(RegNo) == reg_end(); }
329
330 /// reg_nodbg_iterator/reg_nodbg_begin/reg_nodbg_end - Walk all defs and uses
331 /// of the specified register, skipping those marked as Debug.
335 return reg_nodbg_iterator(getRegUseDefListHead(RegNo));
336 }
338 return reg_nodbg_iterator(nullptr);
339 }
340
345
346 /// reg_instr_nodbg_iterator/reg_instr_nodbg_begin/reg_instr_nodbg_end - Walk
347 /// all defs and uses of the specified register, stepping by MachineInstr,
348 /// skipping those marked as Debug.
350 defusechain_instr_iterator<true, true, true, /*ByInstr=*/true>;
352 return reg_instr_nodbg_iterator(getRegUseDefListHead(RegNo));
353 }
357
362
363 /// reg_bundle_nodbg_iterator/reg_bundle_nodbg_begin/reg_bundle_nodbg_end - Walk
364 /// all defs and uses of the specified register, stepping by bundle,
365 /// skipping those marked as Debug.
367 defusechain_instr_iterator<true, true, true, /*ByInstr=*/false>;
369 return reg_bundle_nodbg_iterator(getRegUseDefListHead(RegNo));
370 }
374
379
380 /// reg_nodbg_empty - Return true if the only instructions using or defining
381 /// Reg are Debug instructions.
382 bool reg_nodbg_empty(Register RegNo) const {
383 return reg_nodbg_begin(RegNo) == reg_nodbg_end();
384 }
385
386 /// def_iterator/def_begin/def_end - Walk all defs of the specified register.
389 return def_iterator(getRegUseDefListHead(RegNo));
390 }
391 static def_iterator def_end() { return def_iterator(nullptr); }
392
396
397 /// def_instr_iterator/def_instr_begin/def_instr_end - Walk all defs of the
398 /// specified register, stepping by MachineInst.
400 defusechain_instr_iterator<false, true, false, /*ByInstr=*/true>;
402 return def_instr_iterator(getRegUseDefListHead(RegNo));
403 }
405 return def_instr_iterator(nullptr);
406 }
407
412
413 /// def_bundle_iterator/def_bundle_begin/def_bundle_end - Walk all defs of the
414 /// specified register, stepping by bundle.
416 defusechain_instr_iterator<false, true, false, /*ByInstr=*/false>;
418 return def_bundle_iterator(getRegUseDefListHead(RegNo));
419 }
421 return def_bundle_iterator(nullptr);
422 }
423
427
428 /// def_empty - Return true if there are no instructions defining the
429 /// specified register (it may be live-in).
430 bool def_empty(Register RegNo) const { return def_begin(RegNo) == def_end(); }
431
433 return VReg2Name.inBounds(Reg) ? StringRef(VReg2Name[Reg]) : "";
434 }
435
437 assert((Name.empty() || !VRegNames.contains(Name)) &&
438 "Named VRegs Must be Unique.");
439 if (!Name.empty()) {
440 VRegNames.insert(Name);
441 VReg2Name.grow(Reg);
442 VReg2Name[Reg] = Name.str();
443 }
444 }
445
446 /// Return true if there is exactly one operand defining the specified
447 /// register.
448 bool hasOneDef(Register RegNo) const {
449 return hasSingleElement(def_operands(RegNo));
450 }
451
452 /// Returns the defining operand if there is exactly one operand defining the
453 /// specified register, otherwise nullptr.
456 if (DI == def_end()) // No defs.
457 return nullptr;
458
459 def_iterator OneDef = DI;
460 if (++DI == def_end())
461 return &*OneDef;
462 return nullptr; // Multiple defs.
463 }
464
465 /// use_iterator/use_begin/use_end - Walk all uses of the specified register.
468 return use_iterator(getRegUseDefListHead(RegNo));
469 }
470 static use_iterator use_end() { return use_iterator(nullptr); }
471
475
476 /// use_instr_iterator/use_instr_begin/use_instr_end - Walk all uses of the
477 /// specified register, stepping by MachineInstr.
479 defusechain_instr_iterator<true, false, false, /*ByInstr=*/true>;
481 return use_instr_iterator(getRegUseDefListHead(RegNo));
482 }
484 return use_instr_iterator(nullptr);
485 }
486
491
492 /// use_bundle_iterator/use_bundle_begin/use_bundle_end - Walk all uses of the
493 /// specified register, stepping by bundle.
495 defusechain_instr_iterator<true, false, false, /*ByInstr=*/false>;
497 return use_bundle_iterator(getRegUseDefListHead(RegNo));
498 }
500 return use_bundle_iterator(nullptr);
501 }
502
506
507 /// use_empty - Return true if there are no instructions using the specified
508 /// register.
509 bool use_empty(Register RegNo) const { return use_begin(RegNo) == use_end(); }
510
511 /// hasOneUse - Return true if there is exactly one instruction using the
512 /// specified register.
513 bool hasOneUse(Register RegNo) const {
514 return hasSingleElement(use_operands(RegNo));
515 }
516
517 /// use_nodbg_iterator/use_nodbg_begin/use_nodbg_end - Walk all uses of the
518 /// specified register, skipping those marked as Debug.
522 return use_nodbg_iterator(getRegUseDefListHead(RegNo));
523 }
525 return use_nodbg_iterator(nullptr);
526 }
527
532
533 /// use_instr_nodbg_iterator/use_instr_nodbg_begin/use_instr_nodbg_end - Walk
534 /// all uses of the specified register, stepping by MachineInstr, skipping
535 /// those marked as Debug.
537 defusechain_instr_iterator<true, false, true, /*ByInstr=*/true>;
539 return use_instr_nodbg_iterator(getRegUseDefListHead(RegNo));
540 }
544
549
550 /// use_bundle_nodbg_iterator/use_bundle_nodbg_begin/use_bundle_nodbg_end - Walk
551 /// all uses of the specified register, stepping by bundle, skipping
552 /// those marked as Debug.
554 defusechain_instr_iterator<true, false, true, /*ByInstr=*/false>;
556 return use_bundle_nodbg_iterator(getRegUseDefListHead(RegNo));
557 }
561
566
567 /// use_nodbg_empty - Return true if there are no non-Debug instructions
568 /// using the specified register.
569 bool use_nodbg_empty(Register RegNo) const {
570 return use_nodbg_begin(RegNo) == use_nodbg_end();
571 }
572
573 /// hasOneNonDBGUse - Return true if there is exactly one non-Debug
574 /// use of the specified register.
575 LLVM_ABI bool hasOneNonDBGUse(Register RegNo) const;
576
577 /// hasOneNonDBGUse - Return true if there is exactly one non-Debug
578 /// instruction using the specified register. Said instruction may have
579 /// multiple uses.
580 LLVM_ABI bool hasOneNonDBGUser(Register RegNo) const;
581
582 /// If the register has a single non-Debug use, returns it; otherwise returns
583 /// nullptr.
585
586 /// If the register has a single non-Debug instruction using the specified
587 /// register, returns it; otherwise returns nullptr.
589
590 /// hasAtMostUses - Return true if the given register has at most \p MaxUsers
591 /// non-debug user instructions.
592 LLVM_ABI bool hasAtMostUserInstrs(Register Reg, unsigned MaxUsers) const;
593
594 /// replaceRegWith - Replace all instances of FromReg with ToReg in the
595 /// machine function. This is like llvm-level X->replaceAllUsesWith(Y),
596 /// except that it also changes any definitions of the register as well.
597 ///
598 /// Note that it is usually necessary to first constrain ToReg's register
599 /// class and register bank to match the FromReg constraints using one of the
600 /// methods:
601 ///
602 /// constrainRegClass(ToReg, getRegClass(FromReg))
603 /// constrainRegAttrs(ToReg, FromReg)
604 /// RegisterBankInfo::constrainGenericRegister(ToReg,
605 /// *MRI.getRegClass(FromReg), MRI)
606 ///
607 /// These functions will return a falsy result if the virtual registers have
608 /// incompatible constraints.
609 ///
610 /// Note that if ToReg is a physical register the function will replace and
611 /// apply sub registers to ToReg in order to obtain a final/proper physical
612 /// register.
613 LLVM_ABI void replaceRegWith(Register FromReg, Register ToReg);
614
615 /// getVRegDef - Return the machine instr that defines the specified virtual
616 /// register or null if none is found. This assumes that the code is in SSA
617 /// form, so there should only be one definition.
619
620 /// getUniqueVRegDef - Return the unique machine instr that defines the
621 /// specified virtual register or null if none is found. If there are
622 /// multiple definitions or no definition, return null.
624
625 /// clearKillFlags - Iterate over all the uses of the given register and
626 /// clear the kill flag from the MachineOperand. This function is used by
627 /// optimization passes which extend register lifetimes and need only
628 /// preserve conservative kill flag information.
630
631 LLVM_ABI void dumpUses(Register RegNo) const;
632
633 /// Returns true if PhysReg is unallocatable and constant throughout the
634 /// function. Writing to a constant register has no effect.
635 LLVM_ABI bool isConstantPhysReg(MCRegister PhysReg) const;
636
637 /// Get an iterator over the pressure sets affected by the given physical or
638 /// virtual register. If RegUnit is physical, it must be a register unit (from
639 /// MCRegUnitIterator).
641
642 //===--------------------------------------------------------------------===//
643 // Virtual Register Info
644 //===--------------------------------------------------------------------===//
645
646 /// Return the register class of the specified virtual register.
647 /// This shouldn't be used directly unless \p Reg has a register class.
648 /// \see getRegClassOrNull when this might happen.
650 assert(isa<const TargetRegisterClass *>(VRegInfo[Reg.id()].first) &&
651 "Register class not set, wrong accessor");
652 return cast<const TargetRegisterClass *>(VRegInfo[Reg.id()].first);
653 }
654
655 /// Return the register class of \p Reg, or null if Reg has not been assigned
656 /// a register class yet.
657 ///
658 /// \note A null register class can only happen when these two
659 /// conditions are met:
660 /// 1. Generic virtual registers are created.
661 /// 2. The machine function has not completely been through the
662 /// instruction selection process.
663 /// None of this condition is possible without GlobalISel for now.
664 /// In other words, if GlobalISel is not used or if the query happens after
665 /// the select pass, using getRegClass is safe.
667 const RegClassOrRegBank &Val = VRegInfo[Reg].first;
669 }
670
671 /// Return the register bank of \p Reg.
672 /// This shouldn't be used directly unless \p Reg has a register bank.
674 return cast<const RegisterBank *>(VRegInfo[Reg.id()].first);
675 }
676
677 /// Return the register bank of \p Reg, or null if Reg has not been assigned
678 /// a register bank or has been assigned a register class.
679 /// \note It is possible to get the register bank from the register class via
680 /// RegisterBankInfo::getRegBankFromRegClass.
682 const RegClassOrRegBank &Val = VRegInfo[Reg].first;
684 }
685
686 /// Return the register bank or register class of \p Reg.
687 /// \note Before the register bank gets assigned (i.e., before the
688 /// RegBankSelect pass) \p Reg may not have either.
690 return VRegInfo[Reg].first;
691 }
692
693 /// setRegClass - Set the register class of the specified virtual register.
695
696 /// Set the register bank to \p RegBank for \p Reg.
697 LLVM_ABI void setRegBank(Register Reg, const RegisterBank &RegBank);
698
700 const RegClassOrRegBank &RCOrRB){
701 VRegInfo[Reg].first = RCOrRB;
702 }
703
704 /// constrainRegClass - Constrain the register class of the specified virtual
705 /// register to be a common subclass of RC and the current register class,
706 /// but only if the new class has at least MinNumRegs registers. Return the
707 /// new register class, or NULL if no such class exists.
708 /// This should only be used when the constraint is known to be trivial, like
709 /// GR32 -> GR32_NOSP. Beware of increasing register pressure.
710 ///
711 /// \note Assumes that the register has a register class assigned.
712 /// Use RegisterBankInfo::constrainGenericRegister in GlobalISel's
713 /// InstructionSelect pass and constrainRegAttrs in every other pass,
714 /// including non-select passes of GlobalISel, instead.
717 unsigned MinNumRegs = 0);
718
719 /// Constrain the register class or the register bank of the virtual register
720 /// \p Reg (and low-level type) to be a common subclass or a common bank of
721 /// both registers provided respectively (and a common low-level type). Do
722 /// nothing if any of the attributes (classes, banks, or low-level types) of
723 /// the registers are deemed incompatible, or if the resulting register will
724 /// have a class smaller than before and of size less than \p MinNumRegs.
725 /// Return true if such register attributes exist, false otherwise.
726 ///
727 /// \note Use this method instead of constrainRegClass and
728 /// RegisterBankInfo::constrainGenericRegister everywhere but SelectionDAG
729 /// ISel / FastISel and GlobalISel's InstructionSelect pass respectively.
730 LLVM_ABI bool constrainRegAttrs(Register Reg, Register ConstrainingReg,
731 unsigned MinNumRegs = 0);
732
733 /// recomputeRegClass - Try to find a legal super-class of Reg's register
734 /// class that still satisfies the constraints from the instructions using
735 /// Reg. Returns true if Reg was upgraded.
736 ///
737 /// This method can be used after constraints have been removed from a
738 /// virtual register, for example after removing instructions or splitting
739 /// the live range.
741
742 /// createVirtualRegister - Create and return a new virtual register in the
743 /// function with the specified register class.
745 StringRef Name = "");
746
747 /// All attributes(register class or bank and low-level type) a virtual
748 /// register can have.
753
754 /// Returns register class or bank and low level type of \p Reg. Always safe
755 /// to use. Special values are returned when \p Reg does not have some of the
756 /// attributes.
760
761 /// Create and return a new virtual register in the function with the
762 /// specified register attributes(register class or bank and low level type).
763 LLVM_ABI Register createVirtualRegister(VRegAttrs RegAttr,
764 StringRef Name = "");
765
766 /// Create and return a new virtual register in the function with the same
767 /// attributes as the given register.
769
770 /// Get the low-level type of \p Reg or LLT{} if Reg is not a generic
771 /// (target independent) virtual register.
773 if (Reg.isVirtual() && VRegToType.inBounds(Reg))
774 return VRegToType[Reg];
775 return LLT{};
776 }
777
778 /// Set the low-level type of \p VReg to \p Ty.
779 LLVM_ABI void setType(Register VReg, LLT Ty);
780
781 /// Create and return a new generic virtual register with low-level
782 /// type \p Ty.
784
785 /// Remove all types associated to virtual registers (after instruction
786 /// selection and constraining of all generic virtual registers).
788
789 /// Creates a new virtual register that has no register class, register bank
790 /// or size assigned yet. This is only allowed to be used
791 /// temporarily while constructing machine instructions. Most operations are
792 /// undefined on an incomplete register until one of setRegClass(),
793 /// setRegBank() or setSize() has been called on it.
795
796 /// getNumVirtRegs - Return the number of virtual registers created.
797 unsigned getNumVirtRegs() const { return VRegInfo.size(); }
798
799 /// clearVirtRegs - Remove all virtual registers (after physreg assignment).
800 LLVM_ABI void clearVirtRegs();
801
802 /// setRegAllocationHint - Specify a register allocation hint for the
803 /// specified virtual register. This is typically used by target, and in case
804 /// of an earlier hint it will be overwritten.
805 void setRegAllocationHint(Register VReg, unsigned Type, Register PrefReg) {
806 assert(VReg.isVirtual());
807 RegAllocHints.grow(Register::index2VirtReg(getNumVirtRegs()));
808 auto &Hint = RegAllocHints[VReg];
809 Hint.first = Type;
810 Hint.second.clear();
811 Hint.second.push_back(PrefReg);
812 }
813
814 /// addRegAllocationHint - Add a register allocation hint to the hints
815 /// vector for VReg.
817 assert(VReg.isVirtual());
818 RegAllocHints.grow(Register::index2VirtReg(getNumVirtRegs()));
819 RegAllocHints[VReg].second.push_back(PrefReg);
820 }
821
822 /// Specify the preferred (target independent) register allocation hint for
823 /// the specified virtual register.
824 void setSimpleHint(Register VReg, Register PrefReg) {
825 setRegAllocationHint(VReg, /*Type=*/0, PrefReg);
826 }
827
829 assert (!RegAllocHints[VReg].first &&
830 "Expected to clear a non-target hint!");
831 if (RegAllocHints.inBounds(VReg))
832 RegAllocHints[VReg].second.clear();
833 }
834
835 /// getRegAllocationHint - Return the register allocation hint for the
836 /// specified virtual register. If there are many hints, this returns the
837 /// one with the greatest weight.
838 std::pair<unsigned, Register> getRegAllocationHint(Register VReg) const {
839 assert(VReg.isVirtual());
840 if (!RegAllocHints.inBounds(VReg))
841 return {0, Register()};
842 auto &Hint = RegAllocHints[VReg.id()];
843 Register BestHint = (Hint.second.size() ? Hint.second[0] : Register());
844 return {Hint.first, BestHint};
845 }
846
847 /// getSimpleHint - same as getRegAllocationHint except it will only return
848 /// a target independent hint.
850 assert(VReg.isVirtual());
851 std::pair<unsigned, Register> Hint = getRegAllocationHint(VReg);
852 return Hint.first ? Register() : Hint.second;
853 }
854
855 /// getRegAllocationHints - Return a reference to the vector of all
856 /// register allocation hints for VReg.
857 const std::pair<unsigned, SmallVector<Register, 4>> *
859 assert(VReg.isVirtual());
860 return RegAllocHints.inBounds(VReg) ? &RegAllocHints[VReg] : nullptr;
861 }
862
863 /// markUsesInDebugValueAsUndef - Mark every DBG_VALUE referencing the
864 /// specified register as undefined which causes the DBG_VALUE to be
865 /// deleted during LiveDebugVariables analysis.
867
868 /// updateDbgUsersToReg - Update a collection of debug instructions
869 /// to refer to the designated register.
872 // If this operand is a register, check whether it overlaps with OldReg.
873 // If it does, replace with NewReg.
874 auto UpdateOp = [this, &NewReg, &OldReg](MachineOperand &Op) {
875 if (Op.isReg() &&
876 getTargetRegisterInfo()->regsOverlap(Op.getReg(), OldReg))
877 Op.setReg(NewReg);
878 };
879
880 // Iterate through (possibly several) operands to DBG_VALUEs and update
881 // each. For DBG_PHIs, only one operand will be present.
882 for (MachineInstr *MI : Users) {
883 if (MI->isDebugValue()) {
884 for (auto &Op : MI->debug_operands())
885 UpdateOp(Op);
886 assert(MI->hasDebugOperandForReg(NewReg) &&
887 "Expected debug value to have some overlap with OldReg");
888 } else if (MI->isDebugPHI()) {
889 UpdateOp(MI->getOperand(0));
890 } else {
891 llvm_unreachable("Non-DBG_VALUE, Non-DBG_PHI debug instr updated");
892 }
893 }
894 }
895
896 /// Return true if the specified register is modified in this function.
897 /// This checks that no defining machine operands exist for the register or
898 /// any of its aliases. Definitions found on functions marked noreturn are
899 /// ignored, to consider them pass 'true' for optional parameter
900 /// SkipNoReturnDef. The register is also considered modified when it is set
901 /// in the UsedPhysRegMask.
903 bool SkipNoReturnDef = false) const;
904
905 /// Return true if the specified register is modified or read in this
906 /// function. This checks that no machine operands exist for the register or
907 /// any of its aliases. If SkipRegMaskTest is false, the register is
908 /// considered used when it is set in the UsedPhysRegMask.
909 LLVM_ABI bool isPhysRegUsed(MCRegister PhysReg,
910 bool SkipRegMaskTest = false) const;
911
912 /// addPhysRegsUsedFromRegMask - Mark any registers not in RegMask as used.
913 /// This corresponds to the bit mask attached to register mask operands.
915 UsedPhysRegMask.setBitsNotInMask(RegMask);
916 }
917
918 const BitVector &getUsedPhysRegsMask() const { return UsedPhysRegMask; }
919
920 //===--------------------------------------------------------------------===//
921 // Reserved Register Info
922 //===--------------------------------------------------------------------===//
923 //
924 // The set of reserved registers must be invariant during register
925 // allocation. For example, the target cannot suddenly decide it needs a
926 // frame pointer when the register allocator has already used the frame
927 // pointer register for something else.
928 //
929 // These methods can be used by target hooks like hasFP() to avoid changing
930 // the reserved register set during register allocation.
931
932 /// freezeReservedRegs - Called by the register allocator to freeze the set
933 /// of reserved registers before allocation begins.
935
936 /// reserveReg -- Mark a register as reserved so checks like isAllocatable
937 /// will not suggest using it. This should not be used during the middle
938 /// of a function walk, or when liveness info is available.
941 "Reserved registers haven't been frozen yet. ");
942 MCRegAliasIterator R(PhysReg, TRI, true);
943
944 for (; R.isValid(); ++R)
945 ReservedRegs.set((*R).id());
946 }
947
948 /// reservedRegsFrozen - Returns true after freezeReservedRegs() was called
949 /// to ensure the set of reserved registers stays constant.
950 bool reservedRegsFrozen() const {
951 return !ReservedRegs.empty();
952 }
953
954 /// canReserveReg - Returns true if PhysReg can be used as a reserved
955 /// register. Any register can be reserved before freezeReservedRegs() is
956 /// called.
957 bool canReserveReg(MCRegister PhysReg) const {
958 return !reservedRegsFrozen() || ReservedRegs.test(PhysReg.id());
959 }
960
961 /// getReservedRegs - Returns a reference to the frozen set of reserved
962 /// registers. This method should always be preferred to calling
963 /// TRI::getReservedRegs() when possible.
964 const BitVector &getReservedRegs() const {
966 "Reserved registers haven't been frozen yet. "
967 "Use TRI::getReservedRegs().");
968 return ReservedRegs;
969 }
970
971 /// isReserved - Returns true when PhysReg is a reserved register.
972 ///
973 /// Reserved registers may belong to an allocatable register class, but the
974 /// target has explicitly requested that they are not used.
975 bool isReserved(MCRegister PhysReg) const {
976 return getReservedRegs().test(PhysReg.id());
977 }
978
979 /// Returns true when the given register unit is considered reserved.
980 ///
981 /// Register units are considered reserved when for at least one of their
982 /// root registers, the root register and all super registers are reserved.
983 /// This currently iterates the register hierarchy and may be slower than
984 /// expected.
985 LLVM_ABI bool isReservedRegUnit(unsigned Unit) const;
986
987 /// isAllocatable - Returns true when PhysReg belongs to an allocatable
988 /// register class and it hasn't been reserved.
989 ///
990 /// Allocatable registers may show up in the allocation order of some virtual
991 /// register, so a register allocator needs to track its liveness and
992 /// availability.
993 bool isAllocatable(MCRegister PhysReg) const {
994 return getTargetRegisterInfo()->isInAllocatableClass(PhysReg) &&
995 !isReserved(PhysReg);
996 }
997
998 //===--------------------------------------------------------------------===//
999 // LiveIn Management
1000 //===--------------------------------------------------------------------===//
1001
1002 /// addLiveIn - Add the specified register as a live-in. Note that it
1003 /// is an error to add the same register to the same set more than once.
1005 LiveIns.push_back(std::make_pair(Reg, vreg));
1006 }
1007
1008 // Iteration support for the live-ins set. It's kept in sorted order
1009 // by register number.
1011 std::vector<std::pair<MCRegister,Register>>::const_iterator;
1012 livein_iterator livein_begin() const { return LiveIns.begin(); }
1013 livein_iterator livein_end() const { return LiveIns.end(); }
1014 bool livein_empty() const { return LiveIns.empty(); }
1015
1017 return LiveIns;
1018 }
1019
1020 LLVM_ABI bool isLiveIn(Register Reg) const;
1021
1022 /// getLiveInPhysReg - If VReg is a live-in virtual register, return the
1023 /// corresponding live-in physical register.
1025
1026 /// getLiveInVirtReg - If PReg is a live-in physical register, return the
1027 /// corresponding live-in virtual register.
1029
1030 /// EmitLiveInCopies - Emit copies to initialize livein virtual registers
1031 /// into the given entry block.
1033 const TargetRegisterInfo &TRI,
1034 const TargetInstrInfo &TII);
1035
1036 /// Returns a mask covering all bits that can appear in lane masks of
1037 /// subregisters of the virtual register @p Reg.
1039
1040 /// defusechain_iterator - This class provides iterator support for machine
1041 /// operands in the function that use or define a specific register. If
1042 /// ReturnUses is true it returns uses of registers, if ReturnDefs is true it
1043 /// returns defs. If neither are true then you are silly and it always
1044 /// returns end(). If SkipDebug is true it skips uses marked Debug
1045 /// when incrementing.
1046 template <bool ReturnUses, bool ReturnDefs, bool SkipDebug, bool ByOperand,
1047 bool ByInstr>
1048 class defusechain_iterator {
1050 static_assert(!ByOperand || !ByInstr,
1051 "ByOperand and ByInstr are mutually exclusive");
1052
1053 public:
1054 using iterator_category = std::forward_iterator_tag;
1056 using difference_type = std::ptrdiff_t;
1059
1060 private:
1061 MachineOperand *Op = nullptr;
1062
1063 explicit defusechain_iterator(MachineOperand *op) : Op(op) {
1064 // If the first node isn't one we're interested in, advance to one that
1065 // we are interested in.
1066 if (op) {
1067 if ((!ReturnUses && op->isUse()) ||
1068 (!ReturnDefs && op->isDef()) ||
1069 (SkipDebug && op->isDebug()))
1070 advance();
1071 }
1072 }
1073
1074 void advance() {
1075 assert(Op && "Cannot increment end iterator!");
1076 Op = getNextOperandForReg(Op);
1077
1078 // All defs come before the uses, so stop def_iterator early.
1079 if (!ReturnUses) {
1080 if (Op) {
1081 if (Op->isUse())
1082 Op = nullptr;
1083 else
1084 assert(!Op->isDebug() && "Can't have debug defs");
1085 }
1086 } else {
1087 // If this is an operand we don't care about, skip it.
1088 while (Op && ((!ReturnDefs && Op->isDef()) ||
1089 (SkipDebug && Op->isDebug())))
1090 Op = getNextOperandForReg(Op);
1091 }
1092 }
1093
1094 public:
1096
1097 bool operator==(const defusechain_iterator &x) const {
1098 return Op == x.Op;
1099 }
1100 bool operator!=(const defusechain_iterator &x) const {
1101 return !operator==(x);
1102 }
1103
1104 // Iterator traversal: forward iteration only
1105 defusechain_iterator &operator++() { // Preincrement
1106 assert(Op && "Cannot increment end iterator!");
1107 if (ByOperand)
1108 advance();
1109 else if (ByInstr) {
1110 MachineInstr *P = Op->getParent();
1111 do {
1112 advance();
1113 } while (Op && Op->getParent() == P);
1114 } else {
1116 getBundleStart(Op->getParent()->getIterator());
1117 do {
1118 advance();
1119 } while (Op && getBundleStart(Op->getParent()->getIterator()) == P);
1120 }
1121
1122 return *this;
1123 }
1124 defusechain_iterator operator++(int) { // Postincrement
1125 defusechain_iterator tmp = *this; ++*this; return tmp;
1126 }
1127
1128 /// getOperandNo - Return the operand # of this MachineOperand in its
1129 /// MachineInstr.
1130 unsigned getOperandNo() const {
1131 assert(Op && "Cannot dereference end iterator!");
1132 return Op - &Op->getParent()->getOperand(0);
1133 }
1134
1135 // Retrieve a reference to the current operand.
1137 assert(Op && "Cannot dereference end iterator!");
1138 return *Op;
1139 }
1140
1142 assert(Op && "Cannot dereference end iterator!");
1143 return Op;
1144 }
1145 };
1146
1147 /// defusechain_iterator - This class provides iterator support for machine
1148 /// operands in the function that use or define a specific register. If
1149 /// ReturnUses is true it returns uses of registers, if ReturnDefs is true it
1150 /// returns defs. If neither are true then you are silly and it always
1151 /// returns end(). If SkipDebug is true it skips uses marked Debug
1152 /// when incrementing.
1153 template <bool ReturnUses, bool ReturnDefs, bool SkipDebug, bool ByInstr>
1154 class defusechain_instr_iterator {
1156
1157 public:
1158 using iterator_category = std::forward_iterator_tag;
1160 using difference_type = std::ptrdiff_t;
1163
1164 private:
1165 MachineOperand *Op = nullptr;
1166
1168 // If the first node isn't one we're interested in, advance to one that
1169 // we are interested in.
1170 if (op) {
1171 if ((!ReturnUses && op->isUse()) ||
1172 (!ReturnDefs && op->isDef()) ||
1173 (SkipDebug && op->isDebug()))
1174 advance();
1175 }
1176 }
1177
1178 void advance() {
1179 assert(Op && "Cannot increment end iterator!");
1180 Op = getNextOperandForReg(Op);
1181
1182 // All defs come before the uses, so stop def_iterator early.
1183 if (!ReturnUses) {
1184 if (Op) {
1185 if (Op->isUse())
1186 Op = nullptr;
1187 else
1188 assert(!Op->isDebug() && "Can't have debug defs");
1189 }
1190 } else {
1191 // If this is an operand we don't care about, skip it.
1192 while (Op && ((!ReturnDefs && Op->isDef()) ||
1193 (SkipDebug && Op->isDebug())))
1194 Op = getNextOperandForReg(Op);
1195 }
1196 }
1197
1198 public:
1200
1201 bool operator==(const defusechain_instr_iterator &x) const {
1202 return Op == x.Op;
1203 }
1204 bool operator!=(const defusechain_instr_iterator &x) const {
1205 return !operator==(x);
1206 }
1207
1208 // Iterator traversal: forward iteration only
1209 defusechain_instr_iterator &operator++() { // Preincrement
1210 assert(Op && "Cannot increment end iterator!");
1211 if (ByInstr) {
1212 MachineInstr *P = Op->getParent();
1213 do {
1214 advance();
1215 } while (Op && Op->getParent() == P);
1216 } else {
1218 getBundleStart(Op->getParent()->getIterator());
1219 do {
1220 advance();
1221 } while (Op && getBundleStart(Op->getParent()->getIterator()) == P);
1222 }
1223
1224 return *this;
1225 }
1226 defusechain_instr_iterator operator++(int) { // Postincrement
1227 defusechain_instr_iterator tmp = *this; ++*this; return tmp;
1228 }
1229
1230 // Retrieve a reference to the current operand.
1232 assert(Op && "Cannot dereference end iterator!");
1233 if (!ByInstr)
1234 return *getBundleStart(Op->getParent()->getIterator());
1235 return *Op->getParent();
1236 }
1237
1238 MachineInstr *operator->() const { return &operator*(); }
1239 };
1240};
1241
1242/// Iterate over the pressure sets affected by the given physical or virtual
1243/// register. If Reg is physical, it must be a register unit (from
1244/// MCRegUnitIterator).
1246 const int *PSet = nullptr;
1247 unsigned Weight = 0;
1248
1249public:
1250 PSetIterator() = default;
1251
1253 const TargetRegisterInfo *TRI = MRI->getTargetRegisterInfo();
1254 if (RegUnit.isVirtual()) {
1255 const TargetRegisterClass *RC = MRI->getRegClass(RegUnit);
1256 PSet = TRI->getRegClassPressureSets(RC);
1257 Weight = TRI->getRegClassWeight(RC).RegWeight;
1258 } else {
1259 PSet = TRI->getRegUnitPressureSets(RegUnit);
1260 Weight = TRI->getRegUnitWeight(RegUnit);
1261 }
1262 if (*PSet == -1)
1263 PSet = nullptr;
1264 }
1265
1266 bool isValid() const { return PSet; }
1267
1268 unsigned getWeight() const { return Weight; }
1269
1270 unsigned operator*() const { return *PSet; }
1271
1272 void operator++() {
1273 assert(isValid() && "Invalid PSetIterator.");
1274 ++PSet;
1275 if (*PSet == -1)
1276 PSet = nullptr;
1277 }
1278};
1279
1280inline PSetIterator
1282 return PSetIterator(RegUnit, this);
1283}
1284
1285} // end namespace llvm
1286
1287#endif // LLVM_CODEGEN_MACHINEREGISTERINFO_H
unsigned const MachineRegisterInfo * MRI
assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")
This file implements the BitVector class.
#define LLVM_ABI
Definition Compiler.h:213
#define LLVM_LIKELY(EXPR)
Definition Compiler.h:335
#define op(i)
const HexagonInstrInfo * TII
IRTranslator LLVM IR MI
iv Induction Variable Users
Definition IVUsers.cpp:48
This file implements an indexed map.
const size_t AbstractManglingParser< Derived, Alloc >::NumOps
A common definition of LaneBitmask for use in TableGen and CodeGen.
Register Reg
Register const TargetRegisterInfo * TRI
Promote Memory to Register
Definition Mem2Reg.cpp:110
#define P(N)
This file defines the PointerUnion class, which is a discriminated union of pointer types.
This file defines the SmallPtrSet class.
This file defines the SmallVector class.
StringSet - A set-like wrapper for the StringMap.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition ArrayRef.h:41
bool test(unsigned Idx) const
Definition BitVector.h:461
MCRegAliasIterator enumerates all registers aliasing Reg.
Wrapper class representing physical registers. Should be passed by value.
Definition MCRegister.h:33
constexpr unsigned id() const
Definition MCRegister.h:74
Instructions::iterator instr_iterator
Representation of each machine instruction.
MachineOperand class - Representation of each machine instruction operand.
virtual void MRI_NoteNewVirtualRegister(Register Reg)=0
virtual void MRI_NoteCloneVirtualRegister(Register NewReg, Register SrcReg)
defusechain_iterator - This class provides iterator support for machine operands in the function that...
bool operator==(const defusechain_instr_iterator &x) const
bool operator!=(const defusechain_instr_iterator &x) const
reg_begin/reg_end - Provide iteration support to walk over all definitions and uses of a register wit...
unsigned getOperandNo() const
getOperandNo - Return the operand # of this MachineOperand in its MachineInstr.
bool operator!=(const defusechain_iterator &x) const
bool operator==(const defusechain_iterator &x) const
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
LLVM_ABI void verifyUseList(Register Reg) const
Verify the sanity of the use list for Reg.
LLVM_ABI bool hasOneNonDBGUse(Register RegNo) const
hasOneNonDBGUse - Return true if there is exactly one non-Debug use of the specified register.
Register getSimpleHint(Register VReg) const
getSimpleHint - same as getRegAllocationHint except it will only return a target independent hint.
use_nodbg_iterator use_nodbg_begin(Register RegNo) const
reg_nodbg_iterator reg_nodbg_begin(Register RegNo) const
void insertVRegByName(StringRef Name, Register Reg)
iterator_range< reg_bundle_iterator > reg_bundles(Register Reg) const
defusechain_instr_iterator< true, false, true, true > use_instr_nodbg_iterator
use_instr_nodbg_iterator/use_instr_nodbg_begin/use_instr_nodbg_end - Walk all uses of the specified r...
LLVM_ABI void verifyUseLists() const
Verify the use list of all registers.
defusechain_instr_iterator< false, true, false, false > def_bundle_iterator
def_bundle_iterator/def_bundle_begin/def_bundle_end - Walk all defs of the specified register,...
VRegAttrs getVRegAttrs(Register Reg) const
Returns register class or bank and low level type of Reg.
static reg_iterator reg_end()
LLVM_ABI void markUsesInDebugValueAsUndef(Register Reg) const
markUsesInDebugValueAsUndef - Mark every DBG_VALUE referencing the specified register as undefined wh...
bool tracksLiveness() const
tracksLiveness - Returns true when tracking register liveness accurately.
defusechain_instr_iterator< true, false, false, true > use_instr_iterator
use_instr_iterator/use_instr_begin/use_instr_end - Walk all uses of the specified register,...
const BitVector & getUsedPhysRegsMask() const
iterator_range< reg_iterator > reg_operands(Register Reg) const
LLVM_ABI bool recomputeRegClass(Register Reg)
recomputeRegClass - Try to find a legal super-class of Reg's register class that still satisfies the ...
static reg_instr_nodbg_iterator reg_instr_nodbg_end()
reg_instr_iterator reg_instr_begin(Register RegNo) const
defusechain_instr_iterator< true, true, false, false > reg_bundle_iterator
reg_bundle_iterator/reg_bundle_begin/reg_bundle_end - Walk all defs and uses of the specified registe...
MachineRegisterInfo & operator=(const MachineRegisterInfo &)=delete
bool isUpdatedCSRsInitialized() const
Returns true if the updated CSR list was initialized and false otherwise.
LLVM_ABI void freezeReservedRegs()
freezeReservedRegs - Called by the register allocator to freeze the set of reserved registers before ...
defusechain_instr_iterator< true, false, true, false > use_bundle_nodbg_iterator
use_bundle_nodbg_iterator/use_bundle_nodbg_begin/use_bundle_nodbg_end - Walk all uses of the specifie...
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
static use_nodbg_iterator use_nodbg_end()
reg_bundle_nodbg_iterator reg_bundle_nodbg_begin(Register RegNo) const
defusechain_instr_iterator< true, true, true, false > reg_bundle_nodbg_iterator
reg_bundle_nodbg_iterator/reg_bundle_nodbg_begin/reg_bundle_nodbg_end - Walk all defs and uses of the...
LLVM_ABI void clearKillFlags(Register Reg) const
clearKillFlags - Iterate over all the uses of the given register and clear the kill flag from the Mac...
LLVM_ABI MachineRegisterInfo(MachineFunction *MF)
reg_iterator reg_begin(Register RegNo) const
defusechain_instr_iterator< true, true, true, true > reg_instr_nodbg_iterator
reg_instr_nodbg_iterator/reg_instr_nodbg_begin/reg_instr_nodbg_end - Walk all defs and uses of the sp...
LLVM_ABI MachineInstr * getVRegDef(Register Reg) const
getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...
iterator_range< def_instr_iterator > def_instructions(Register Reg) const
bool shouldTrackSubRegLiveness(Register VReg) const
iterator_range< use_nodbg_iterator > use_nodbg_operands(Register Reg) const
LLVM_ABI void EmitLiveInCopies(MachineBasicBlock *EntryMBB, const TargetRegisterInfo &TRI, const TargetInstrInfo &TII)
EmitLiveInCopies - Emit copies to initialize livein virtual registers into the given entry block.
static reg_instr_iterator reg_instr_end()
use_instr_iterator use_instr_begin(Register RegNo) const
bool use_nodbg_empty(Register RegNo) const
use_nodbg_empty - Return true if there are no non-Debug instructions using the specified register.
const RegClassOrRegBank & getRegClassOrRegBank(Register Reg) const
Return the register bank or register class of Reg.
LLVM_ABI MachineOperand * getOneNonDBGUse(Register RegNo) const
If the register has a single non-Debug use, returns it; otherwise returns nullptr.
iterator_range< reg_bundle_nodbg_iterator > reg_nodbg_bundles(Register Reg) const
bool isReserved(MCRegister PhysReg) const
isReserved - Returns true when PhysReg is a reserved register.
const RegisterBank * getRegBank(Register Reg) const
Return the register bank of Reg.
static def_instr_iterator def_instr_end()
LLVM_ABI void dumpUses(Register RegNo) const
LLVM_ABI void moveOperands(MachineOperand *Dst, MachineOperand *Src, unsigned NumOps)
Move NumOps operands from Src to Dst, updating use-def lists as needed.
MachineOperand * getOneDef(Register Reg) const
Returns the defining operand if there is exactly one operand defining the specified register,...
def_iterator def_begin(Register RegNo) const
defusechain_iterator< true, false, false, true, false > use_iterator
use_iterator/use_begin/use_end - Walk all uses of the specified register.
defusechain_instr_iterator< false, true, false, true > def_instr_iterator
def_instr_iterator/def_instr_begin/def_instr_end - Walk all defs of the specified register,...
static def_bundle_iterator def_bundle_end()
const BitVector & getReservedRegs() const
getReservedRegs - Returns a reference to the frozen set of reserved registers.
iterator_range< use_bundle_nodbg_iterator > use_nodbg_bundles(Register Reg) const
void setRegClassOrRegBank(Register Reg, const RegClassOrRegBank &RCOrRB)
LLVM_ABI Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
def_instr_iterator def_instr_begin(Register RegNo) const
LLT getType(Register Reg) const
Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register.
bool reservedRegsFrozen() const
reservedRegsFrozen - Returns true after freezeReservedRegs() was called to ensure the set of reserved...
bool def_empty(Register RegNo) const
def_empty - Return true if there are no instructions defining the specified register (it may be live-...
bool hasOneUse(Register RegNo) const
hasOneUse - Return true if there is exactly one instruction using the specified register.
void resetDelegate(Delegate *delegate)
LLVM_ABI bool isLiveIn(Register Reg) const
bool reg_nodbg_empty(Register RegNo) const
reg_nodbg_empty - Return true if the only instructions using or defining Reg are Debug instructions.
std::vector< std::pair< MCRegister, Register > >::const_iterator livein_iterator
static use_bundle_iterator use_bundle_end()
const RegisterBank * getRegBankOrNull(Register Reg) const
Return the register bank of Reg, or null if Reg has not been assigned a register bank or has been ass...
void invalidateLiveness()
invalidateLiveness - Indicates that register liveness is no longer being tracked accurately.
static reg_nodbg_iterator reg_nodbg_end()
use_instr_nodbg_iterator use_instr_nodbg_begin(Register RegNo) const
ArrayRef< std::pair< MCRegister, Register > > liveins() const
use_bundle_nodbg_iterator use_bundle_nodbg_begin(Register RegNo) const
LLVM_ABI bool hasAtMostUserInstrs(Register Reg, unsigned MaxUsers) const
hasAtMostUses - Return true if the given register has at most MaxUsers non-debug user instructions.
static use_instr_iterator use_instr_end()
LLVM_ABI bool hasOneNonDBGUser(Register RegNo) const
hasOneNonDBGUse - Return true if there is exactly one non-Debug instruction using the specified regis...
LLVM_ABI void clearVirtRegs()
clearVirtRegs - Remove all virtual registers (after physreg assignment).
LLVM_ABI Register createIncompleteVirtualRegister(StringRef Name="")
Creates a new virtual register that has no register class, register bank or size assigned yet.
bool shouldTrackSubRegLiveness(const TargetRegisterClass &RC) const
Returns true if liveness for register class RC should be tracked at the subregister level.
bool isAllocatable(MCRegister PhysReg) const
isAllocatable - Returns true when PhysReg belongs to an allocatable register class and it hasn't been...
LLVM_ABI void setRegBank(Register Reg, const RegisterBank &RegBank)
Set the register bank to RegBank for Reg.
defusechain_iterator< true, false, true, true, false > use_nodbg_iterator
use_nodbg_iterator/use_nodbg_begin/use_nodbg_end - Walk all uses of the specified register,...
defusechain_iterator< false, true, false, true, false > def_iterator
def_iterator/def_begin/def_end - Walk all defs of the specified register.
LLVM_ABI MCRegister getLiveInPhysReg(Register VReg) const
getLiveInPhysReg - If VReg is a live-in virtual register, return the corresponding live-in physical r...
LLVM_ABI const MCPhysReg * getCalleeSavedRegs() const
Returns list of callee saved registers.
std::pair< unsigned, Register > getRegAllocationHint(Register VReg) const
getRegAllocationHint - Return the register allocation hint for the specified virtual register.
iterator_range< use_instr_nodbg_iterator > use_nodbg_instructions(Register Reg) const
iterator_range< def_iterator > def_operands(Register Reg) const
LLVM_ABI void setType(Register VReg, LLT Ty)
Set the low-level type of VReg to Ty.
void setRegAllocationHint(Register VReg, unsigned Type, Register PrefReg)
setRegAllocationHint - Specify a register allocation hint for the specified virtual register.
void addDelegate(Delegate *delegate)
const MachineFunction & getMF() const
bool hasOneDef(Register RegNo) const
Return true if there is exactly one operand defining the specified register.
static reg_bundle_nodbg_iterator reg_bundle_nodbg_end()
LLVM_ABI void setRegClass(Register Reg, const TargetRegisterClass *RC)
setRegClass - Set the register class of the specified virtual register.
LLVM_ABI Register createGenericVirtualRegister(LLT Ty, StringRef Name="")
Create and return a new generic virtual register with low-level type Ty.
bool canReserveReg(MCRegister PhysReg) const
canReserveReg - Returns true if PhysReg can be used as a reserved register.
LLVM_ABI void clearVirtRegTypes()
Remove all types associated to virtual registers (after instruction selection and constraining of all...
LLVM_ABI Register getLiveInVirtReg(MCRegister PReg) const
getLiveInVirtReg - If PReg is a live-in physical register, return the corresponding live-in virtual r...
const TargetRegisterClass * getRegClassOrNull(Register Reg) const
Return the register class of Reg, or null if Reg has not been assigned a register class yet.
void setSimpleHint(Register VReg, Register PrefReg)
Specify the preferred (target independent) register allocation hint for the specified virtual registe...
static def_iterator def_end()
LLVM_ABI void disableCalleeSavedRegister(MCRegister Reg)
Disables the register from the list of CSRs.
use_bundle_iterator use_bundle_begin(Register RegNo) const
livein_iterator livein_end() const
reg_bundle_iterator reg_bundle_begin(Register RegNo) const
iterator_range< reg_instr_iterator > reg_instructions(Register Reg) const
void noteNewVirtualRegister(Register Reg)
static use_bundle_nodbg_iterator use_bundle_nodbg_end()
const std::pair< unsigned, SmallVector< Register, 4 > > * getRegAllocationHints(Register VReg) const
getRegAllocationHints - Return a reference to the vector of all register allocation hints for VReg.
LLVM_ABI void setCalleeSavedRegs(ArrayRef< MCPhysReg > CSRs)
Sets the updated Callee Saved Registers list.
static reg_bundle_iterator reg_bundle_end()
iterator_range< use_instr_iterator > use_instructions(Register Reg) const
void reserveReg(MCRegister PhysReg, const TargetRegisterInfo *TRI)
reserveReg – Mark a register as reserved so checks like isAllocatable will not suggest using it.
const TargetRegisterInfo * getTargetRegisterInfo() const
LLVM_ABI LaneBitmask getMaxLaneMaskForVReg(Register Reg) const
Returns a mask covering all bits that can appear in lane masks of subregisters of the virtual registe...
use_iterator use_begin(Register RegNo) const
void addRegAllocationHint(Register VReg, Register PrefReg)
addRegAllocationHint - Add a register allocation hint to the hints vector for VReg.
LLVM_ABI bool isConstantPhysReg(MCRegister PhysReg) const
Returns true if PhysReg is unallocatable and constant throughout the function.
iterator_range< reg_nodbg_iterator > reg_nodbg_operands(Register Reg) const
LLVM_ABI Register cloneVirtualRegister(Register VReg, StringRef Name="")
Create and return a new virtual register in the function with the same attributes as the given regist...
void addPhysRegsUsedFromRegMask(const uint32_t *RegMask)
addPhysRegsUsedFromRegMask - Mark any registers not in RegMask as used.
MachineRegisterInfo(const MachineRegisterInfo &)=delete
defusechain_instr_iterator< true, false, false, false > use_bundle_iterator
use_bundle_iterator/use_bundle_begin/use_bundle_end - Walk all uses of the specified register,...
static use_iterator use_end()
void addLiveIn(MCRegister Reg, Register vreg=Register())
addLiveIn - Add the specified register as a live-in.
PSetIterator getPressureSets(Register RegUnit) const
Get an iterator over the pressure sets affected by the given physical or virtual register.
LLVM_ABI bool constrainRegAttrs(Register Reg, Register ConstrainingReg, unsigned MinNumRegs=0)
Constrain the register class or the register bank of the virtual register Reg (and low-level type) to...
iterator_range< def_bundle_iterator > def_bundles(Register Reg) const
defusechain_instr_iterator< true, true, false, true > reg_instr_iterator
reg_instr_iterator/reg_instr_begin/reg_instr_end - Walk all defs and uses of the specified register,...
LLVM_ABI const TargetRegisterClass * constrainRegClass(Register Reg, const TargetRegisterClass *RC, unsigned MinNumRegs=0)
constrainRegClass - Constrain the register class of the specified virtual register to be a common sub...
void clearSimpleHint(Register VReg)
LLVM_ABI bool isReservedRegUnit(unsigned Unit) const
Returns true when the given register unit is considered reserved.
defusechain_iterator< true, true, false, true, false > reg_iterator
reg_iterator/reg_begin/reg_end - Walk all defs and uses of the specified register.
void noteCloneVirtualRegister(Register NewReg, Register SrcReg)
iterator_range< use_iterator > use_operands(Register Reg) const
livein_iterator livein_begin() const
reg_instr_nodbg_iterator reg_instr_nodbg_begin(Register RegNo) const
unsigned getNumVirtRegs() const
getNumVirtRegs - Return the number of virtual registers created.
iterator_range< reg_instr_nodbg_iterator > reg_nodbg_instructions(Register Reg) const
LLVM_ABI void removeRegOperandFromUseList(MachineOperand *MO)
Remove MO from its use-def list.
bool use_empty(Register RegNo) const
use_empty - Return true if there are no instructions using the specified register.
bool reg_empty(Register RegNo) const
reg_empty - Return true if there are no instructions using or defining the specified register (it may...
StringRef getVRegName(Register Reg) const
iterator_range< use_bundle_iterator > use_bundles(Register Reg) const
LLVM_ABI void replaceRegWith(Register FromReg, Register ToReg)
replaceRegWith - Replace all instances of FromReg with ToReg in the machine function.
LLVM_ABI bool isPhysRegModified(MCRegister PhysReg, bool SkipNoReturnDef=false) const
Return true if the specified register is modified in this function.
void updateDbgUsersToReg(MCRegister OldReg, MCRegister NewReg, ArrayRef< MachineInstr * > Users) const
updateDbgUsersToReg - Update a collection of debug instructions to refer to the designated register.
LLVM_ABI void addRegOperandToUseList(MachineOperand *MO)
Add MO to the linked list of operands for its register.
LLVM_ABI MachineInstr * getOneNonDBGUser(Register RegNo) const
If the register has a single non-Debug instruction using the specified register, returns it; otherwis...
LLVM_ABI MachineInstr * getUniqueVRegDef(Register Reg) const
getUniqueVRegDef - Return the unique machine instr that defines the specified virtual register or nul...
def_bundle_iterator def_bundle_begin(Register RegNo) const
static use_instr_nodbg_iterator use_instr_nodbg_end()
LLVM_ABI bool isPhysRegUsed(MCRegister PhysReg, bool SkipRegMaskTest=false) const
Return true if the specified register is modified or read in this function.
defusechain_iterator< true, true, true, true, false > reg_nodbg_iterator
reg_nodbg_iterator/reg_nodbg_begin/reg_nodbg_end - Walk all defs and uses of the specified register,...
Iterate over the pressure sets affected by the given physical or virtual register.
unsigned operator*() const
PSetIterator(Register RegUnit, const MachineRegisterInfo *MRI)
unsigned getWeight() const
PSetIterator()=default
A discriminated union of two or more pointer types, with the discriminator in the low bit of the poin...
This class implements the register bank concept.
Wrapper class representing virtual and physical registers.
Definition Register.h:19
static Register index2VirtReg(unsigned Index)
Convert a 0-based index to a virtual register number.
Definition Register.h:67
constexpr bool isVirtual() const
Return true if the specified register number is in the virtual register namespace.
Definition Register.h:74
constexpr unsigned id() const
Definition Register.h:95
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
StringRef - Represent a constant reference to a string, i.e.
Definition StringRef.h:55
StringSet - A wrapper for StringMap that provides set-like functionality.
Definition StringSet.h:25
TargetInstrInfo - Interface to description of machine instruction set.
const bool HasDisjunctSubRegs
Whether the class supports two (or more) disjunct subregister indices.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
bool isInAllocatableClass(MCRegister RegNo) const
Return true if the register is in the allocation of any register class.
The instances of the Type class are immutable: once they are created, they are never changed.
Definition Type.h:45
A range adaptor for a pair of iterators.
This provides a very simple, boring adaptor for a begin and end iterator into a range type.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
This is an optimization pass for GlobalISel generic memory operations.
MachineBasicBlock::instr_iterator getBundleStart(MachineBasicBlock::instr_iterator I)
Returns an iterator to the first instruction in the bundle containing I.
PointerUnion< const TargetRegisterClass *, const RegisterBank * > RegClassOrRegBank
Convenient type to represent either a register class or a register bank.
auto dyn_cast_if_present(const Y &Val)
dyn_cast_if_present<X> - Functionally identical to dyn_cast, except that a null (or none in the case ...
Definition Casting.h:738
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
bool hasSingleElement(ContainerTy &&C)
Returns true if the given container only contains a single element.
Definition STLExtras.h:314
bool isa(const From &Val)
isa<X> - Return true if the parameter to the template is an instance of one of the template type argu...
Definition Casting.h:548
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
Definition MCRegister.h:21
DWARFExpression::Operation Op
decltype(auto) cast(const From &Val)
cast<X> - Return the argument parameter cast to the specified type.
Definition Casting.h:565
All attributes(register class or bank and low-level type) a virtual register can have.