13#ifndef LLVM_CODEGEN_MACHINEREGISTERINFO_H
14#define LLVM_CODEGEN_MACHINEREGISTERINFO_H
56 virtual void anchor();
73 const bool TracksSubRegLiveness;
92 bool IsUpdatedCSRsInitialized =
false;
112 std::unique_ptr<MachineOperand *[]> PhysRegUseDefLists;
119 return PhysRegUseDefLists[RegNo.
id()];
122 MachineOperand *getRegUseDefListHead(
Register RegNo)
const {
123 if (RegNo.isVirtual())
124 return VRegInfo[RegNo.id()].second;
125 return PhysRegUseDefLists[RegNo.id()];
129 static MachineOperand *getNextOperandForReg(
const MachineOperand *MO) {
130 assert(MO && MO->isReg() &&
"This is not a register operand!");
131 return MO->Contents.Reg.Next;
136 BitVector UsedPhysRegMask;
142 BitVector ReservedRegs;
144 using VRegToTypeMap = IndexedMap<LLT, VirtReg2IndexFunctor>;
146 VRegToTypeMap VRegToType;
152 std::vector<std::pair<MCRegister, Register>> LiveIns;
160 return MF->getSubtarget().getRegisterInfo();
166 assert(TheDelegates.count(delegate) &&
167 "Only an existing delegate can perform reset!");
168 TheDelegates.erase(delegate);
172 assert(delegate && !TheDelegates.count(delegate) &&
173 "Attempted to add null delegate, or to change it without "
174 "first resetting it!");
176 TheDelegates.insert(delegate);
180 for (
auto *TheDelegate : TheDelegates)
181 TheDelegate->MRI_NoteNewVirtualRegister(
Reg);
185 for (
auto *TheDelegate : TheDelegates)
186 TheDelegate->MRI_NoteCloneVirtualRegister(NewReg, SrcReg);
202 bool isSSA()
const {
return MF->getProperties().hasIsSSA(); }
205 void leaveSSA() { MF->getProperties().resetIsSSA(); }
210 return MF->getProperties().hasTracksLiveness();
231 return TracksSubRegLiveness;
274 template <
bool Uses,
bool Defs,
bool SkipDebug,
bool ByOperand,
bool ByInstr>
276 template <
bool Uses,
bool Defs,
bool SkipDebug,
bool ByInstr>
437 assert((Name.empty() || !VRegNames.contains(Name)) &&
438 "Named VRegs Must be Unique.");
440 VRegNames.insert(Name);
442 VReg2Name[
Reg] = Name.str();
651 "Register class not set, wrong accessor");
690 return VRegInfo[
Reg].first;
701 VRegInfo[
Reg].first = RCOrRB;
717 unsigned MinNumRegs = 0);
731 unsigned MinNumRegs = 0);
773 if (
Reg.isVirtual() && VRegToType.inBounds(
Reg))
774 return VRegToType[
Reg];
808 auto &Hint = RegAllocHints[VReg];
811 Hint.second.push_back(PrefReg);
819 RegAllocHints[VReg].second.push_back(PrefReg);
829 assert (!RegAllocHints[VReg].first &&
830 "Expected to clear a non-target hint!");
831 if (RegAllocHints.inBounds(VReg))
832 RegAllocHints[VReg].second.clear();
840 if (!RegAllocHints.inBounds(VReg))
842 auto &Hint = RegAllocHints[VReg.
id()];
844 return {Hint.first, BestHint};
852 return Hint.first ?
Register() : Hint.second;
857 const std::pair<unsigned, SmallVector<Register, 4>> *
860 return RegAllocHints.inBounds(VReg) ? &RegAllocHints[VReg] :
nullptr;
883 if (
MI->isDebugValue()) {
884 for (
auto &
Op :
MI->debug_operands())
886 assert(
MI->hasDebugOperandForReg(NewReg) &&
887 "Expected debug value to have some overlap with OldReg");
888 }
else if (
MI->isDebugPHI()) {
889 UpdateOp(
MI->getOperand(0));
903 bool SkipNoReturnDef =
false)
const;
910 bool SkipRegMaskTest =
false)
const;
915 UsedPhysRegMask.setBitsNotInMask(RegMask);
941 "Reserved registers haven't been frozen yet. ");
944 for (; R.isValid(); ++R)
945 ReservedRegs.set((*R).id());
951 return !ReservedRegs.empty();
966 "Reserved registers haven't been frozen yet. "
967 "Use TRI::getReservedRegs().");
1005 LiveIns.push_back(std::make_pair(
Reg, vreg));
1046 template <
bool ReturnUses,
bool ReturnDefs,
bool SkipDebug,
bool ByOperand,
1048 class defusechain_iterator {
1050 static_assert(!ByOperand || !ByInstr,
1051 "ByOperand and ByInstr are mutually exclusive");
1067 if ((!ReturnUses &&
op->isUse()) ||
1068 (!ReturnDefs &&
op->isDef()) ||
1069 (SkipDebug &&
op->isDebug()))
1075 assert(
Op &&
"Cannot increment end iterator!");
1076 Op = getNextOperandForReg(
Op);
1084 assert(!
Op->isDebug() &&
"Can't have debug defs");
1088 while (
Op && ((!ReturnDefs &&
Op->isDef()) ||
1089 (SkipDebug &&
Op->isDebug())))
1090 Op = getNextOperandForReg(
Op);
1106 assert(Op &&
"Cannot increment end iterator!");
1113 }
while (Op && Op->getParent() ==
P);
1125 defusechain_iterator tmp = *
this; ++*
this;
return tmp;
1131 assert(Op &&
"Cannot dereference end iterator!");
1132 return Op - &Op->getParent()->getOperand(0);
1137 assert(Op &&
"Cannot dereference end iterator!");
1142 assert(Op &&
"Cannot dereference end iterator!");
1153 template <
bool ReturnUses,
bool ReturnDefs,
bool SkipDebug,
bool ByInstr>
1154 class defusechain_instr_iterator {
1171 if ((!ReturnUses &&
op->isUse()) ||
1172 (!ReturnDefs &&
op->isDef()) ||
1173 (SkipDebug &&
op->isDebug()))
1179 assert(
Op &&
"Cannot increment end iterator!");
1180 Op = getNextOperandForReg(
Op);
1188 assert(!
Op->isDebug() &&
"Can't have debug defs");
1192 while (
Op && ((!ReturnDefs &&
Op->isDef()) ||
1193 (SkipDebug &&
Op->isDebug())))
1194 Op = getNextOperandForReg(
Op);
1210 assert(Op &&
"Cannot increment end iterator!");
1215 }
while (Op && Op->getParent() ==
P);
1227 defusechain_instr_iterator tmp = *
this; ++*
this;
return tmp;
1232 assert(Op &&
"Cannot dereference end iterator!");
1235 return *Op->getParent();
1246 const int *PSet =
nullptr;
1247 unsigned Weight = 0;
1256 PSet =
TRI->getRegClassPressureSets(RC);
1257 Weight =
TRI->getRegClassWeight(RC).RegWeight;
1259 PSet =
TRI->getRegUnitPressureSets(RegUnit);
1260 Weight =
TRI->getRegUnitWeight(RegUnit);
unsigned const MachineRegisterInfo * MRI
assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")
This file implements the BitVector class.
#define LLVM_LIKELY(EXPR)
const HexagonInstrInfo * TII
iv Induction Variable Users
This file implements an indexed map.
const size_t AbstractManglingParser< Derived, Alloc >::NumOps
A common definition of LaneBitmask for use in TableGen and CodeGen.
Register const TargetRegisterInfo * TRI
Promote Memory to Register
This file defines the PointerUnion class, which is a discriminated union of pointer types.
This file defines the SmallPtrSet class.
This file defines the SmallVector class.
StringSet - A set-like wrapper for the StringMap.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
bool test(unsigned Idx) const
MCRegAliasIterator enumerates all registers aliasing Reg.
Wrapper class representing physical registers. Should be passed by value.
constexpr unsigned id() const
Instructions::iterator instr_iterator
Representation of each machine instruction.
MachineOperand class - Representation of each machine instruction operand.
virtual void MRI_NoteNewVirtualRegister(Register Reg)=0
virtual void MRI_NoteCloneVirtualRegister(Register NewReg, Register SrcReg)
virtual ~Delegate()=default
defusechain_iterator - This class provides iterator support for machine operands in the function that...
defusechain_instr_iterator()=default
bool operator==(const defusechain_instr_iterator &x) const
defusechain_instr_iterator operator++(int)
std::forward_iterator_tag iterator_category
MachineInstr & operator*() const
bool operator!=(const defusechain_instr_iterator &x) const
MachineInstr * operator->() const
std::ptrdiff_t difference_type
defusechain_instr_iterator & operator++()
friend class MachineRegisterInfo
reg_begin/reg_end - Provide iteration support to walk over all definitions and uses of a register wit...
defusechain_iterator operator++(int)
MachineOperand & operator*() const
unsigned getOperandNo() const
getOperandNo - Return the operand # of this MachineOperand in its MachineInstr.
std::ptrdiff_t difference_type
defusechain_iterator()=default
std::forward_iterator_tag iterator_category
bool operator!=(const defusechain_iterator &x) const
defusechain_iterator & operator++()
MachineOperand * operator->() const
MachineOperand value_type
friend class MachineRegisterInfo
bool operator==(const defusechain_iterator &x) const
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
LLVM_ABI void verifyUseList(Register Reg) const
Verify the sanity of the use list for Reg.
LLVM_ABI bool hasOneNonDBGUse(Register RegNo) const
hasOneNonDBGUse - Return true if there is exactly one non-Debug use of the specified register.
Register getSimpleHint(Register VReg) const
getSimpleHint - same as getRegAllocationHint except it will only return a target independent hint.
use_nodbg_iterator use_nodbg_begin(Register RegNo) const
reg_nodbg_iterator reg_nodbg_begin(Register RegNo) const
void insertVRegByName(StringRef Name, Register Reg)
iterator_range< reg_bundle_iterator > reg_bundles(Register Reg) const
defusechain_instr_iterator< true, false, true, true > use_instr_nodbg_iterator
use_instr_nodbg_iterator/use_instr_nodbg_begin/use_instr_nodbg_end - Walk all uses of the specified r...
LLVM_ABI void verifyUseLists() const
Verify the use list of all registers.
defusechain_instr_iterator< false, true, false, false > def_bundle_iterator
def_bundle_iterator/def_bundle_begin/def_bundle_end - Walk all defs of the specified register,...
bool livein_empty() const
VRegAttrs getVRegAttrs(Register Reg) const
Returns register class or bank and low level type of Reg.
static reg_iterator reg_end()
LLVM_ABI void markUsesInDebugValueAsUndef(Register Reg) const
markUsesInDebugValueAsUndef - Mark every DBG_VALUE referencing the specified register as undefined wh...
bool tracksLiveness() const
tracksLiveness - Returns true when tracking register liveness accurately.
defusechain_instr_iterator< true, false, false, true > use_instr_iterator
use_instr_iterator/use_instr_begin/use_instr_end - Walk all uses of the specified register,...
const BitVector & getUsedPhysRegsMask() const
iterator_range< reg_iterator > reg_operands(Register Reg) const
LLVM_ABI bool recomputeRegClass(Register Reg)
recomputeRegClass - Try to find a legal super-class of Reg's register class that still satisfies the ...
static reg_instr_nodbg_iterator reg_instr_nodbg_end()
reg_instr_iterator reg_instr_begin(Register RegNo) const
defusechain_instr_iterator< true, true, false, false > reg_bundle_iterator
reg_bundle_iterator/reg_bundle_begin/reg_bundle_end - Walk all defs and uses of the specified registe...
MachineRegisterInfo & operator=(const MachineRegisterInfo &)=delete
bool isUpdatedCSRsInitialized() const
Returns true if the updated CSR list was initialized and false otherwise.
LLVM_ABI void freezeReservedRegs()
freezeReservedRegs - Called by the register allocator to freeze the set of reserved registers before ...
defusechain_instr_iterator< true, false, true, false > use_bundle_nodbg_iterator
use_bundle_nodbg_iterator/use_bundle_nodbg_begin/use_bundle_nodbg_end - Walk all uses of the specifie...
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
static use_nodbg_iterator use_nodbg_end()
reg_bundle_nodbg_iterator reg_bundle_nodbg_begin(Register RegNo) const
defusechain_instr_iterator< true, true, true, false > reg_bundle_nodbg_iterator
reg_bundle_nodbg_iterator/reg_bundle_nodbg_begin/reg_bundle_nodbg_end - Walk all defs and uses of the...
LLVM_ABI void clearKillFlags(Register Reg) const
clearKillFlags - Iterate over all the uses of the given register and clear the kill flag from the Mac...
LLVM_ABI MachineRegisterInfo(MachineFunction *MF)
reg_iterator reg_begin(Register RegNo) const
defusechain_instr_iterator< true, true, true, true > reg_instr_nodbg_iterator
reg_instr_nodbg_iterator/reg_instr_nodbg_begin/reg_instr_nodbg_end - Walk all defs and uses of the sp...
LLVM_ABI MachineInstr * getVRegDef(Register Reg) const
getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...
iterator_range< def_instr_iterator > def_instructions(Register Reg) const
bool shouldTrackSubRegLiveness(Register VReg) const
iterator_range< use_nodbg_iterator > use_nodbg_operands(Register Reg) const
LLVM_ABI void EmitLiveInCopies(MachineBasicBlock *EntryMBB, const TargetRegisterInfo &TRI, const TargetInstrInfo &TII)
EmitLiveInCopies - Emit copies to initialize livein virtual registers into the given entry block.
static reg_instr_iterator reg_instr_end()
use_instr_iterator use_instr_begin(Register RegNo) const
bool subRegLivenessEnabled() const
friend class defusechain_iterator
bool use_nodbg_empty(Register RegNo) const
use_nodbg_empty - Return true if there are no non-Debug instructions using the specified register.
const RegClassOrRegBank & getRegClassOrRegBank(Register Reg) const
Return the register bank or register class of Reg.
LLVM_ABI MachineOperand * getOneNonDBGUse(Register RegNo) const
If the register has a single non-Debug use, returns it; otherwise returns nullptr.
iterator_range< reg_bundle_nodbg_iterator > reg_nodbg_bundles(Register Reg) const
bool isReserved(MCRegister PhysReg) const
isReserved - Returns true when PhysReg is a reserved register.
const RegisterBank * getRegBank(Register Reg) const
Return the register bank of Reg.
static def_instr_iterator def_instr_end()
LLVM_ABI void dumpUses(Register RegNo) const
LLVM_ABI void moveOperands(MachineOperand *Dst, MachineOperand *Src, unsigned NumOps)
Move NumOps operands from Src to Dst, updating use-def lists as needed.
MachineOperand * getOneDef(Register Reg) const
Returns the defining operand if there is exactly one operand defining the specified register,...
def_iterator def_begin(Register RegNo) const
defusechain_iterator< true, false, false, true, false > use_iterator
use_iterator/use_begin/use_end - Walk all uses of the specified register.
defusechain_instr_iterator< false, true, false, true > def_instr_iterator
def_instr_iterator/def_instr_begin/def_instr_end - Walk all defs of the specified register,...
static def_bundle_iterator def_bundle_end()
const BitVector & getReservedRegs() const
getReservedRegs - Returns a reference to the frozen set of reserved registers.
iterator_range< use_bundle_nodbg_iterator > use_nodbg_bundles(Register Reg) const
void setRegClassOrRegBank(Register Reg, const RegClassOrRegBank &RCOrRB)
LLVM_ABI Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
def_instr_iterator def_instr_begin(Register RegNo) const
LLT getType(Register Reg) const
Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register.
bool reservedRegsFrozen() const
reservedRegsFrozen - Returns true after freezeReservedRegs() was called to ensure the set of reserved...
bool def_empty(Register RegNo) const
def_empty - Return true if there are no instructions defining the specified register (it may be live-...
bool hasOneUse(Register RegNo) const
hasOneUse - Return true if there is exactly one instruction using the specified register.
void resetDelegate(Delegate *delegate)
LLVM_ABI bool isLiveIn(Register Reg) const
bool reg_nodbg_empty(Register RegNo) const
reg_nodbg_empty - Return true if the only instructions using or defining Reg are Debug instructions.
std::vector< std::pair< MCRegister, Register > >::const_iterator livein_iterator
static use_bundle_iterator use_bundle_end()
const RegisterBank * getRegBankOrNull(Register Reg) const
Return the register bank of Reg, or null if Reg has not been assigned a register bank or has been ass...
void invalidateLiveness()
invalidateLiveness - Indicates that register liveness is no longer being tracked accurately.
static reg_nodbg_iterator reg_nodbg_end()
use_instr_nodbg_iterator use_instr_nodbg_begin(Register RegNo) const
ArrayRef< std::pair< MCRegister, Register > > liveins() const
use_bundle_nodbg_iterator use_bundle_nodbg_begin(Register RegNo) const
LLVM_ABI bool hasAtMostUserInstrs(Register Reg, unsigned MaxUsers) const
hasAtMostUses - Return true if the given register has at most MaxUsers non-debug user instructions.
static use_instr_iterator use_instr_end()
LLVM_ABI bool hasOneNonDBGUser(Register RegNo) const
hasOneNonDBGUse - Return true if there is exactly one non-Debug instruction using the specified regis...
LLVM_ABI void clearVirtRegs()
clearVirtRegs - Remove all virtual registers (after physreg assignment).
LLVM_ABI Register createIncompleteVirtualRegister(StringRef Name="")
Creates a new virtual register that has no register class, register bank or size assigned yet.
bool shouldTrackSubRegLiveness(const TargetRegisterClass &RC) const
Returns true if liveness for register class RC should be tracked at the subregister level.
bool isAllocatable(MCRegister PhysReg) const
isAllocatable - Returns true when PhysReg belongs to an allocatable register class and it hasn't been...
LLVM_ABI void setRegBank(Register Reg, const RegisterBank &RegBank)
Set the register bank to RegBank for Reg.
defusechain_iterator< true, false, true, true, false > use_nodbg_iterator
use_nodbg_iterator/use_nodbg_begin/use_nodbg_end - Walk all uses of the specified register,...
defusechain_iterator< false, true, false, true, false > def_iterator
def_iterator/def_begin/def_end - Walk all defs of the specified register.
LLVM_ABI MCRegister getLiveInPhysReg(Register VReg) const
getLiveInPhysReg - If VReg is a live-in virtual register, return the corresponding live-in physical r...
LLVM_ABI const MCPhysReg * getCalleeSavedRegs() const
Returns list of callee saved registers.
std::pair< unsigned, Register > getRegAllocationHint(Register VReg) const
getRegAllocationHint - Return the register allocation hint for the specified virtual register.
iterator_range< use_instr_nodbg_iterator > use_nodbg_instructions(Register Reg) const
iterator_range< def_iterator > def_operands(Register Reg) const
LLVM_ABI void setType(Register VReg, LLT Ty)
Set the low-level type of VReg to Ty.
void setRegAllocationHint(Register VReg, unsigned Type, Register PrefReg)
setRegAllocationHint - Specify a register allocation hint for the specified virtual register.
void addDelegate(Delegate *delegate)
const MachineFunction & getMF() const
bool hasOneDef(Register RegNo) const
Return true if there is exactly one operand defining the specified register.
static reg_bundle_nodbg_iterator reg_bundle_nodbg_end()
LLVM_ABI void setRegClass(Register Reg, const TargetRegisterClass *RC)
setRegClass - Set the register class of the specified virtual register.
LLVM_ABI Register createGenericVirtualRegister(LLT Ty, StringRef Name="")
Create and return a new generic virtual register with low-level type Ty.
bool canReserveReg(MCRegister PhysReg) const
canReserveReg - Returns true if PhysReg can be used as a reserved register.
LLVM_ABI void clearVirtRegTypes()
Remove all types associated to virtual registers (after instruction selection and constraining of all...
LLVM_ABI Register getLiveInVirtReg(MCRegister PReg) const
getLiveInVirtReg - If PReg is a live-in physical register, return the corresponding live-in virtual r...
const TargetRegisterClass * getRegClassOrNull(Register Reg) const
Return the register class of Reg, or null if Reg has not been assigned a register class yet.
void setSimpleHint(Register VReg, Register PrefReg)
Specify the preferred (target independent) register allocation hint for the specified virtual registe...
static def_iterator def_end()
LLVM_ABI void disableCalleeSavedRegister(MCRegister Reg)
Disables the register from the list of CSRs.
use_bundle_iterator use_bundle_begin(Register RegNo) const
livein_iterator livein_end() const
reg_bundle_iterator reg_bundle_begin(Register RegNo) const
iterator_range< reg_instr_iterator > reg_instructions(Register Reg) const
void noteNewVirtualRegister(Register Reg)
static use_bundle_nodbg_iterator use_bundle_nodbg_end()
const std::pair< unsigned, SmallVector< Register, 4 > > * getRegAllocationHints(Register VReg) const
getRegAllocationHints - Return a reference to the vector of all register allocation hints for VReg.
LLVM_ABI void setCalleeSavedRegs(ArrayRef< MCPhysReg > CSRs)
Sets the updated Callee Saved Registers list.
static reg_bundle_iterator reg_bundle_end()
iterator_range< use_instr_iterator > use_instructions(Register Reg) const
void reserveReg(MCRegister PhysReg, const TargetRegisterInfo *TRI)
reserveReg – Mark a register as reserved so checks like isAllocatable will not suggest using it.
const TargetRegisterInfo * getTargetRegisterInfo() const
LLVM_ABI LaneBitmask getMaxLaneMaskForVReg(Register Reg) const
Returns a mask covering all bits that can appear in lane masks of subregisters of the virtual registe...
use_iterator use_begin(Register RegNo) const
void addRegAllocationHint(Register VReg, Register PrefReg)
addRegAllocationHint - Add a register allocation hint to the hints vector for VReg.
LLVM_ABI bool isConstantPhysReg(MCRegister PhysReg) const
Returns true if PhysReg is unallocatable and constant throughout the function.
iterator_range< reg_nodbg_iterator > reg_nodbg_operands(Register Reg) const
LLVM_ABI Register cloneVirtualRegister(Register VReg, StringRef Name="")
Create and return a new virtual register in the function with the same attributes as the given regist...
void addPhysRegsUsedFromRegMask(const uint32_t *RegMask)
addPhysRegsUsedFromRegMask - Mark any registers not in RegMask as used.
MachineRegisterInfo(const MachineRegisterInfo &)=delete
defusechain_instr_iterator< true, false, false, false > use_bundle_iterator
use_bundle_iterator/use_bundle_begin/use_bundle_end - Walk all uses of the specified register,...
static use_iterator use_end()
void addLiveIn(MCRegister Reg, Register vreg=Register())
addLiveIn - Add the specified register as a live-in.
PSetIterator getPressureSets(Register RegUnit) const
Get an iterator over the pressure sets affected by the given physical or virtual register.
LLVM_ABI bool constrainRegAttrs(Register Reg, Register ConstrainingReg, unsigned MinNumRegs=0)
Constrain the register class or the register bank of the virtual register Reg (and low-level type) to...
iterator_range< def_bundle_iterator > def_bundles(Register Reg) const
defusechain_instr_iterator< true, true, false, true > reg_instr_iterator
reg_instr_iterator/reg_instr_begin/reg_instr_end - Walk all defs and uses of the specified register,...
LLVM_ABI const TargetRegisterClass * constrainRegClass(Register Reg, const TargetRegisterClass *RC, unsigned MinNumRegs=0)
constrainRegClass - Constrain the register class of the specified virtual register to be a common sub...
void clearSimpleHint(Register VReg)
LLVM_ABI bool isReservedRegUnit(unsigned Unit) const
Returns true when the given register unit is considered reserved.
defusechain_iterator< true, true, false, true, false > reg_iterator
reg_iterator/reg_begin/reg_end - Walk all defs and uses of the specified register.
void noteCloneVirtualRegister(Register NewReg, Register SrcReg)
iterator_range< use_iterator > use_operands(Register Reg) const
livein_iterator livein_begin() const
friend class defusechain_instr_iterator
reg_instr_nodbg_iterator reg_instr_nodbg_begin(Register RegNo) const
unsigned getNumVirtRegs() const
getNumVirtRegs - Return the number of virtual registers created.
iterator_range< reg_instr_nodbg_iterator > reg_nodbg_instructions(Register Reg) const
LLVM_ABI void removeRegOperandFromUseList(MachineOperand *MO)
Remove MO from its use-def list.
bool use_empty(Register RegNo) const
use_empty - Return true if there are no instructions using the specified register.
bool reg_empty(Register RegNo) const
reg_empty - Return true if there are no instructions using or defining the specified register (it may...
StringRef getVRegName(Register Reg) const
iterator_range< use_bundle_iterator > use_bundles(Register Reg) const
LLVM_ABI void replaceRegWith(Register FromReg, Register ToReg)
replaceRegWith - Replace all instances of FromReg with ToReg in the machine function.
LLVM_ABI bool isPhysRegModified(MCRegister PhysReg, bool SkipNoReturnDef=false) const
Return true if the specified register is modified in this function.
void updateDbgUsersToReg(MCRegister OldReg, MCRegister NewReg, ArrayRef< MachineInstr * > Users) const
updateDbgUsersToReg - Update a collection of debug instructions to refer to the designated register.
LLVM_ABI void addRegOperandToUseList(MachineOperand *MO)
Add MO to the linked list of operands for its register.
LLVM_ABI MachineInstr * getOneNonDBGUser(Register RegNo) const
If the register has a single non-Debug instruction using the specified register, returns it; otherwis...
LLVM_ABI MachineInstr * getUniqueVRegDef(Register Reg) const
getUniqueVRegDef - Return the unique machine instr that defines the specified virtual register or nul...
def_bundle_iterator def_bundle_begin(Register RegNo) const
static use_instr_nodbg_iterator use_instr_nodbg_end()
LLVM_ABI bool isPhysRegUsed(MCRegister PhysReg, bool SkipRegMaskTest=false) const
Return true if the specified register is modified or read in this function.
defusechain_iterator< true, true, true, true, false > reg_nodbg_iterator
reg_nodbg_iterator/reg_nodbg_begin/reg_nodbg_end - Walk all defs and uses of the specified register,...
Iterate over the pressure sets affected by the given physical or virtual register.
unsigned operator*() const
PSetIterator(Register RegUnit, const MachineRegisterInfo *MRI)
unsigned getWeight() const
A discriminated union of two or more pointer types, with the discriminator in the low bit of the poin...
This class implements the register bank concept.
Wrapper class representing virtual and physical registers.
static Register index2VirtReg(unsigned Index)
Convert a 0-based index to a virtual register number.
constexpr bool isVirtual() const
Return true if the specified register number is in the virtual register namespace.
constexpr unsigned id() const
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
StringRef - Represent a constant reference to a string, i.e.
StringSet - A wrapper for StringMap that provides set-like functionality.
TargetInstrInfo - Interface to description of machine instruction set.
const bool HasDisjunctSubRegs
Whether the class supports two (or more) disjunct subregister indices.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
bool isInAllocatableClass(MCRegister RegNo) const
Return true if the register is in the allocation of any register class.
The instances of the Type class are immutable: once they are created, they are never changed.
A range adaptor for a pair of iterators.
This provides a very simple, boring adaptor for a begin and end iterator into a range type.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
This is an optimization pass for GlobalISel generic memory operations.
MachineBasicBlock::instr_iterator getBundleStart(MachineBasicBlock::instr_iterator I)
Returns an iterator to the first instruction in the bundle containing I.
PointerUnion< const TargetRegisterClass *, const RegisterBank * > RegClassOrRegBank
Convenient type to represent either a register class or a register bank.
auto dyn_cast_if_present(const Y &Val)
dyn_cast_if_present<X> - Functionally identical to dyn_cast, except that a null (or none in the case ...
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
bool hasSingleElement(ContainerTy &&C)
Returns true if the given container only contains a single element.
bool isa(const From &Val)
isa<X> - Return true if the parameter to the template is an instance of one of the template type argu...
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
DWARFExpression::Operation Op
decltype(auto) cast(const From &Val)
cast<X> - Return the argument parameter cast to the specified type.
All attributes(register class or bank and low-level type) a virtual register can have.