TargetInstrInfo - Interface to description of machine instruction set. More...
#include "llvm/CodeGen/TargetInstrInfo.h"
Classes | |
| struct | MachineBranchPredicate |
| Represents a predicate at the MachineFunction level. More... | |
| class | PipelinerLoopInfo |
| Object returned by analyzeLoopForPipelining. More... | |
| struct | RegSubRegPair |
| A pair composed of a register and a sub-register index. More... | |
| struct | RegSubRegPairAndIdx |
| A pair composed of a pair of a register and a sub-register index, and another sub-register index. More... | |
Public Member Functions | |
| TargetInstrInfo (const TargetInstrInfo &)=delete | |
| TargetInstrInfo & | operator= (const TargetInstrInfo &)=delete |
| virtual | ~TargetInstrInfo () |
| int16_t | getOpRegClassID (const MCOperandInfo &OpInfo) const |
| virtual const TargetRegisterClass * | getRegClass (const MCInstrDesc &MCID, unsigned OpNum, const TargetRegisterInfo *TRI) const |
| Given a machine instruction descriptor, returns the register class constraint for OpNum, or NULL. | |
| virtual bool | isGlobalMemoryObject (const MachineInstr *MI) const |
| Returns true if MI is an instruction we are unable to reason about (like a call or something with unmodeled side effects). | |
| bool | isTriviallyReMaterializable (const MachineInstr &MI) const |
| Return true if the instruction is trivially rematerializable, meaning it has no side effects and requires no operands that aren't always available. | |
| virtual bool | isIgnorableUse (const MachineOperand &MO) const |
Given MO is a PhysReg use return if it can be ignored for the purpose of instruction rematerialization or sinking. | |
| virtual bool | isSafeToSink (MachineInstr &MI, MachineBasicBlock *SuccToSinkTo, MachineCycleInfo *CI) const |
| virtual bool | shouldBreakCriticalEdgeToSink (MachineInstr &MI) const |
| For a "cheap" instruction which doesn't enable additional sinking, should MachineSink break a critical edge to sink it anyways? | |
| unsigned | getCallFrameSetupOpcode () const |
| These methods return the opcode of the frame setup/destroy instructions if they exist (-1 otherwise). | |
| unsigned | getCallFrameDestroyOpcode () const |
| bool | isFrameInstr (const MachineInstr &I) const |
| Returns true if the argument is a frame pseudo instruction. | |
| bool | isFrameSetup (const MachineInstr &I) const |
| Returns true if the argument is a frame setup pseudo instruction. | |
| int64_t | getFrameSize (const MachineInstr &I) const |
| Returns size of the frame associated with the given frame instruction. | |
| int64_t | getFrameTotalSize (const MachineInstr &I) const |
| Returns the total frame size, which is made up of the space set up inside the pair of frame start-stop instructions and the space that is set up prior to the pair. | |
| unsigned | getCatchReturnOpcode () const |
| unsigned | getReturnOpcode () const |
| virtual int | getSPAdjust (const MachineInstr &MI) const |
| Returns the actual stack pointer adjustment made by an instruction as part of a call sequence. | |
| virtual bool | isCoalescableExtInstr (const MachineInstr &MI, Register &SrcReg, Register &DstReg, unsigned &SubIdx) const |
| Return true if the instruction is a "coalescable" extension instruction. | |
| virtual Register | isLoadFromStackSlot (const MachineInstr &MI, int &FrameIndex) const |
| If the specified machine instruction is a direct load from a stack slot, return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot. | |
| virtual Register | isLoadFromStackSlot (const MachineInstr &MI, int &FrameIndex, TypeSize &MemBytes) const |
| Optional extension of isLoadFromStackSlot that returns the number of bytes loaded from the stack. | |
| virtual Register | isLoadFromStackSlotPostFE (const MachineInstr &MI, int &FrameIndex) const |
| Check for post-frame ptr elimination stack locations as well. | |
| virtual bool | hasLoadFromStackSlot (const MachineInstr &MI, SmallVectorImpl< const MachineMemOperand * > &Accesses) const |
| If the specified machine instruction has a load from a stack slot, return true along with the FrameIndices of the loaded stack slot and the machine mem operands containing the reference. | |
| virtual Register | isStoreToStackSlot (const MachineInstr &MI, int &FrameIndex) const |
| If the specified machine instruction is a direct store to a stack slot, return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot. | |
| virtual Register | isStoreToStackSlot (const MachineInstr &MI, int &FrameIndex, TypeSize &MemBytes) const |
| Optional extension of isStoreToStackSlot that returns the number of bytes stored to the stack. | |
| virtual Register | isStoreToStackSlotPostFE (const MachineInstr &MI, int &FrameIndex) const |
| Check for post-frame ptr elimination stack locations as well. | |
| virtual bool | hasStoreToStackSlot (const MachineInstr &MI, SmallVectorImpl< const MachineMemOperand * > &Accesses) const |
| If the specified machine instruction has a store to a stack slot, return true along with the FrameIndices of the loaded stack slot and the machine mem operands containing the reference. | |
| virtual bool | isStackSlotCopy (const MachineInstr &MI, int &DestFrameIndex, int &SrcFrameIndex) const |
| Return true if the specified machine instruction is a copy of one stack slot to another and has no other effect. | |
| virtual bool | getStackSlotRange (const TargetRegisterClass *RC, unsigned SubIdx, unsigned &Size, unsigned &Offset, const MachineFunction &MF) const |
| Compute the size in bytes and offset within a stack slot of a spilled register or subregister. | |
| bool | isUnspillableTerminator (const MachineInstr *MI) const |
| Return true if the given instruction is terminator that is unspillable, according to isUnspillableTerminatorImpl. | |
| virtual unsigned | getInstSizeInBytes (const MachineInstr &MI) const |
| Returns the size in bytes of the specified MachineInstr, or ~0U when this function is not implemented by a target. | |
| virtual bool | isAsCheapAsAMove (const MachineInstr &MI) const |
| Return true if the instruction is as cheap as a move instruction. | |
| virtual bool | shouldSink (const MachineInstr &MI) const |
| Return true if the instruction should be sunk by MachineSink. | |
| virtual bool | shouldHoist (const MachineInstr &MI, const MachineLoop *FromLoop) const |
| Return false if the instruction should not be hoisted by MachineLICM. | |
| virtual void | reMaterialize (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, unsigned SubIdx, const MachineInstr &Orig, const TargetRegisterInfo &TRI) const |
| Re-issue the specified 'original' instruction at the specific location targeting a new destination register. | |
| virtual MachineInstr & | duplicate (MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore, const MachineInstr &Orig) const |
Clones instruction or the whole instruction bundle Orig and insert into MBB before InsertBefore. | |
| virtual MachineInstr * | convertToThreeAddress (MachineInstr &MI, LiveVariables *LV, LiveIntervals *LIS) const |
| This method must be implemented by targets that set the M_CONVERTIBLE_TO_3_ADDR flag. | |
| MachineInstr * | commuteInstruction (MachineInstr &MI, bool NewMI=false, unsigned OpIdx1=CommuteAnyOperandIndex, unsigned OpIdx2=CommuteAnyOperandIndex) const |
| This method commutes the operands of the given machine instruction MI. | |
| virtual bool | findCommutedOpIndices (const MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const |
| Returns true iff the routine could find two commutable operands in the given machine instruction. | |
| virtual bool | hasCommutePreference (MachineInstr &MI, bool &Commute) const |
| Returns true if the target has a preference on the operands order of the given machine instruction. | |
| virtual bool | simplifyInstruction (MachineInstr &MI) const |
| If possible, converts the instruction to a simplified/canonical form. | |
| bool | getRegSequenceInputs (const MachineInstr &MI, unsigned DefIdx, SmallVectorImpl< RegSubRegPairAndIdx > &InputRegs) const |
Build the equivalent inputs of a REG_SEQUENCE for the given MI and DefIdx. | |
| bool | getExtractSubregInputs (const MachineInstr &MI, unsigned DefIdx, RegSubRegPairAndIdx &InputReg) const |
Build the equivalent inputs of a EXTRACT_SUBREG for the given MI and DefIdx. | |
| bool | getInsertSubregInputs (const MachineInstr &MI, unsigned DefIdx, RegSubRegPair &BaseReg, RegSubRegPairAndIdx &InsertedReg) const |
Build the equivalent inputs of a INSERT_SUBREG for the given MI and DefIdx. | |
| virtual bool | produceSameValue (const MachineInstr &MI0, const MachineInstr &MI1, const MachineRegisterInfo *MRI=nullptr) const |
| Return true if two machine instructions would produce identical values. | |
| virtual bool | isBranchOffsetInRange (unsigned BranchOpc, int64_t BrOffset) const |
| virtual MachineBasicBlock * | getBranchDestBlock (const MachineInstr &MI) const |
| virtual void | insertIndirectBranch (MachineBasicBlock &MBB, MachineBasicBlock &NewDestBB, MachineBasicBlock &RestoreBB, const DebugLoc &DL, int64_t BrOffset=0, RegScavenger *RS=nullptr) const |
Insert an unconditional indirect branch at the end of MBB to NewDestBB. | |
| virtual bool | analyzeBranch (MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const |
| Analyze the branching code at the end of MBB, returning true if it cannot be understood (e.g. | |
| virtual bool | analyzeBranchPredicate (MachineBasicBlock &MBB, MachineBranchPredicate &MBP, bool AllowModify=false) const |
| Analyze the branching code at the end of MBB and parse it into the MachineBranchPredicate structure if possible. | |
| virtual unsigned | removeBranch (MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const |
| Remove the branching code at the end of the specific MBB. | |
| virtual unsigned | insertBranch (MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const |
| Insert branch code into the end of the specified MachineBasicBlock. | |
| unsigned | insertUnconditionalBranch (MachineBasicBlock &MBB, MachineBasicBlock *DestBB, const DebugLoc &DL, int *BytesAdded=nullptr) const |
| virtual std::unique_ptr< PipelinerLoopInfo > | analyzeLoopForPipelining (MachineBasicBlock *LoopBB) const |
| Analyze loop L, which must be a single-basic-block loop, and if the conditions can be understood enough produce a PipelinerLoopInfo object. | |
| virtual bool | analyzeLoop (MachineLoop &L, MachineInstr *&IndVarInst, MachineInstr *&CmpInst) const |
| Analyze the loop code, return true if it cannot be understood. | |
| virtual unsigned | reduceLoopCount (MachineBasicBlock &MBB, MachineBasicBlock &PreHeader, MachineInstr *IndVar, MachineInstr &Cmp, SmallVectorImpl< MachineOperand > &Cond, SmallVectorImpl< MachineInstr * > &PrevInsts, unsigned Iter, unsigned MaxIter) const |
| Generate code to reduce the loop iteration by one and check if the loop is finished. | |
| virtual void | ReplaceTailWithBranchTo (MachineBasicBlock::iterator Tail, MachineBasicBlock *NewDest) const |
| Delete the instruction OldInst and everything after it, replacing it with an unconditional branch to NewDest. | |
| virtual bool | isLegalToSplitMBBAt (MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) const |
| Return true if it's legal to split the given basic block at the specified instruction (i.e. | |
| virtual bool | isProfitableToIfCvt (MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, BranchProbability Probability) const |
| Return true if it's profitable to predicate instructions with accumulated instruction latency of "NumCycles" of the specified basic block, where the probability of the instructions being executed is given by Probability, and Confidence is a measure of our confidence that it will be properly predicted. | |
| virtual bool | isProfitableToIfCvt (MachineBasicBlock &TMBB, unsigned NumTCycles, unsigned ExtraTCycles, MachineBasicBlock &FMBB, unsigned NumFCycles, unsigned ExtraFCycles, BranchProbability Probability) const |
| Second variant of isProfitableToIfCvt. | |
| virtual bool | isProfitableToDupForIfCvt (MachineBasicBlock &MBB, unsigned NumCycles, BranchProbability Probability) const |
| Return true if it's profitable for if-converter to duplicate instructions of specified accumulated instruction latencies in the specified MBB to enable if-conversion. | |
| virtual unsigned | extraSizeToPredicateInstructions (const MachineFunction &MF, unsigned NumInsts) const |
| Return the increase in code size needed to predicate a contiguous run of NumInsts instructions. | |
| virtual unsigned | predictBranchSizeForIfCvt (MachineInstr &MI) const |
| Return an estimate for the code size reduction (in bytes) which will be caused by removing the given branch instruction during if-conversion. | |
| virtual bool | isProfitableToUnpredicate (MachineBasicBlock &TMBB, MachineBasicBlock &FMBB) const |
| Return true if it's profitable to unpredicate one side of a 'diamond', i.e. | |
| virtual bool | canInsertSelect (const MachineBasicBlock &MBB, ArrayRef< MachineOperand > Cond, Register DstReg, Register TrueReg, Register FalseReg, int &CondCycles, int &TrueCycles, int &FalseCycles) const |
| Return true if it is possible to insert a select instruction that chooses between TrueReg and FalseReg based on the condition code in Cond. | |
| virtual void | insertSelect (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, Register DstReg, ArrayRef< MachineOperand > Cond, Register TrueReg, Register FalseReg) const |
| Insert a select instruction into MBB before I that will copy TrueReg to DstReg when Cond is true, and FalseReg to DstReg when Cond is false. | |
| virtual bool | analyzeSelect (const MachineInstr &MI, SmallVectorImpl< MachineOperand > &Cond, unsigned &TrueOp, unsigned &FalseOp, bool &Optimizable) const |
| Analyze the given select instruction, returning true if it cannot be understood. | |
| virtual MachineInstr * | optimizeSelect (MachineInstr &MI, SmallPtrSetImpl< MachineInstr * > &NewMIs, bool PreferFalse=false) const |
| Given a select instruction that was understood by analyzeSelect and returned Optimizable = true, attempt to optimize MI by merging it with one of its operands. | |
| virtual void | copyPhysReg (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, Register DestReg, Register SrcReg, bool KillSrc, bool RenamableDest=false, bool RenamableSrc=false) const |
| Emit instructions to copy a pair of physical registers. | |
| virtual bool | isPCRelRegisterOperandLegal (const MachineOperand &MO) const |
| Allow targets to tell MachineVerifier whether a specific register MachineOperand can be used as part of PC-relative addressing. | |
| virtual int | getJumpTableIndex (const MachineInstr &MI) const |
Return an index for MachineJumpTableInfo if insn is an indirect jump using a jump table, otherwise -1. | |
| std::optional< DestSourcePair > | isCopyInstr (const MachineInstr &MI) const |
| If the specific machine instruction is a instruction that moves/copies value from one register to another register return destination and source registers as machine operands. | |
| std::optional< DestSourcePair > | isCopyLikeInstr (const MachineInstr &MI) const |
| bool | isFullCopyInstr (const MachineInstr &MI) const |
| virtual std::optional< RegImmPair > | isAddImmediate (const MachineInstr &MI, Register Reg) const |
If the specific machine instruction is an instruction that adds an immediate value and a register, and stores the result in the given register Reg, return a pair of the source register and the offset which has been added. | |
| virtual bool | getConstValDefinedInReg (const MachineInstr &MI, const Register Reg, int64_t &ImmVal) const |
| Returns true if MI is an instruction that defines Reg to have a constant value and the value is recorded in ImmVal. | |
| virtual void | storeRegToStackSlot (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg, MachineInstr::MIFlag Flags=MachineInstr::NoFlags) const |
| Store the specified register of the given register class to the specified stack frame index. | |
| virtual void | loadRegFromStackSlot (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg, MachineInstr::MIFlag Flags=MachineInstr::NoFlags) const |
| Load the specified register of the given register class from the specified stack frame index. | |
| virtual bool | expandPostRAPseudo (MachineInstr &MI) const |
| This function is called for all pseudo instructions that remain after register allocation. | |
| virtual bool | isSubregFoldable () const |
| Check whether the target can fold a load that feeds a subreg operand (or a subreg operand that feeds a store). | |
| virtual std::pair< unsigned, unsigned > | getPatchpointUnfoldableRange (const MachineInstr &MI) const |
| For a patchpoint, stackmap, or statepoint intrinsic, return the range of operands which can't be folded into stack references. | |
| MachineInstr * | foldMemoryOperand (MachineInstr &MI, ArrayRef< unsigned > Ops, int FI, LiveIntervals *LIS=nullptr, VirtRegMap *VRM=nullptr) const |
| Attempt to fold a load or store of the specified stack slot into the specified machine instruction for the specified operand(s). | |
| MachineInstr * | foldMemoryOperand (MachineInstr &MI, ArrayRef< unsigned > Ops, MachineInstr &LoadMI, LiveIntervals *LIS=nullptr) const |
| Same as the previous version except it allows folding of any load and store from / to any address, not just from a specific stack slot. | |
| void | lowerCopy (MachineInstr *MI, const TargetRegisterInfo *TRI) const |
| This function defines the logic to lower COPY instruction to target specific instruction(s). | |
| virtual bool | getMachineCombinerPatterns (MachineInstr &Root, SmallVectorImpl< unsigned > &Patterns, bool DoRegPressureReduce) const |
Return true when there is potentially a faster code sequence for an instruction chain ending in Root. | |
| virtual bool | shouldReduceRegisterPressure (const MachineBasicBlock *MBB, const RegisterClassInfo *RegClassInfo) const |
| Return true if target supports reassociation of instructions in machine combiner pass to reduce register pressure for a given BB. | |
| virtual void | finalizeInsInstrs (MachineInstr &Root, unsigned &Pattern, SmallVectorImpl< MachineInstr * > &InsInstrs) const |
| Fix up the placeholder we may add in genAlternativeCodeSequence(). | |
| virtual bool | isThroughputPattern (unsigned Pattern) const |
| Return true when a code sequence can improve throughput. | |
| virtual CombinerObjective | getCombinerObjective (unsigned Pattern) const |
| Return the objective of a combiner pattern. | |
| bool | isReassociationCandidate (const MachineInstr &Inst, bool &Commuted) const |
| Return true if the input \P Inst is part of a chain of dependent ops that are suitable for reassociation, otherwise return false. | |
| virtual bool | isAssociativeAndCommutative (const MachineInstr &Inst, bool Invert=false) const |
| Return true when \P Inst is both associative and commutative. | |
| bool | getAccumulatorReassociationPatterns (MachineInstr &Root, SmallVectorImpl< unsigned > &Patterns) const |
| Find chains of accumulations that can be rewritten as a tree for increased ILP. | |
| void | getAccumulatorChain (MachineInstr *CurrentInstr, SmallVectorImpl< Register > &Chain) const |
| Find the chain of accumulator instructions in \P MBB and return them in \P Chain. | |
| virtual bool | isAccumulationOpcode (unsigned Opcode) const |
| Return true when \P OpCode is an instruction which performs accumulation into one of its operand registers. | |
| virtual unsigned | getAccumulationStartOpcode (unsigned Opcode) const |
| Returns an opcode which defines the accumulator used by \P Opcode. | |
| virtual unsigned | getReduceOpcodeForAccumulator (unsigned int AccumulatorOpCode) const |
| Returns the opcode that should be use to reduce accumulation registers. | |
| void | reduceAccumulatorTree (SmallVectorImpl< Register > &RegistersToReduce, SmallVectorImpl< MachineInstr * > &InsInstrs, MachineFunction &MF, MachineInstr &Root, MachineRegisterInfo &MRI, DenseMap< Register, unsigned > &InstrIdxForVirtReg, Register ResultReg) const |
| Reduces branches of the accumulator tree into a single register. | |
| virtual std::optional< unsigned > | getInverseOpcode (unsigned Opcode) const |
| Return the inverse operation opcode if it exists for \P Opcode (e.g. | |
| bool | areOpcodesEqualOrInverse (unsigned Opcode1, unsigned Opcode2) const |
| Return true when \P Opcode1 or its inversion is equal to \P Opcode2. | |
| virtual bool | hasReassociableOperands (const MachineInstr &Inst, const MachineBasicBlock *MBB) const |
| Return true when \P Inst has reassociable operands in the same \P MBB. | |
| virtual bool | hasReassociableSibling (const MachineInstr &Inst, bool &Commuted) const |
| Return true when \P Inst has reassociable sibling. | |
| virtual void | genAlternativeCodeSequence (MachineInstr &Root, unsigned Pattern, SmallVectorImpl< MachineInstr * > &InsInstrs, SmallVectorImpl< MachineInstr * > &DelInstrs, DenseMap< Register, unsigned > &InstIdxForVirtReg) const |
| When getMachineCombinerPatterns() finds patterns, this function generates the instructions that could replace the original code sequence. | |
| virtual bool | accumulateInstrSeqToRootLatency (MachineInstr &Root) const |
| When calculate the latency of the root instruction, accumulate the latency of the sequence to the root latency. | |
| virtual void | getReassociateOperandIndices (const MachineInstr &Root, unsigned Pattern, std::array< unsigned, 5 > &OperandIndices) const |
| The returned array encodes the operand index for each parameter because the operands may be commuted; the operand indices for associative operations might also be target-specific. | |
| void | reassociateOps (MachineInstr &Root, MachineInstr &Prev, unsigned Pattern, SmallVectorImpl< MachineInstr * > &InsInstrs, SmallVectorImpl< MachineInstr * > &DelInstrs, ArrayRef< unsigned > OperandIndices, DenseMap< Register, unsigned > &InstrIdxForVirtReg) const |
| Attempt to reassociate \P Root and \P Prev according to \P Pattern to reduce critical path length. | |
| std::pair< unsigned, unsigned > | getReassociationOpcodes (unsigned Pattern, const MachineInstr &Root, const MachineInstr &Prev) const |
| Reassociation of some instructions requires inverse operations (e.g. | |
| virtual int | getExtendResourceLenLimit () const |
| The limit on resource length extension we accept in MachineCombiner Pass. | |
| virtual void | setSpecialOperandAttr (MachineInstr &OldMI1, MachineInstr &OldMI2, MachineInstr &NewMI1, MachineInstr &NewMI2) const |
| This is an architecture-specific helper function of reassociateOps. | |
| virtual bool | useMachineCombiner () const |
| Return true when a target supports MachineCombiner. | |
| virtual MachineTraceStrategy | getMachineCombinerTraceStrategy () const |
| Return a strategy that MachineCombiner must use when creating traces. | |
| virtual bool | canCopyGluedNodeDuringSchedule (SDNode *N) const |
| Return true if the given SDNode can be copied during scheduling even if it has glue. | |
| virtual bool | unfoldMemoryOperand (MachineFunction &MF, MachineInstr &MI, Register Reg, bool UnfoldLoad, bool UnfoldStore, SmallVectorImpl< MachineInstr * > &NewMIs) const |
| unfoldMemoryOperand - Separate a single instruction which folded a load or a store or a load and a store into two or more instruction. | |
| virtual bool | unfoldMemoryOperand (SelectionDAG &DAG, SDNode *N, SmallVectorImpl< SDNode * > &NewNodes) const |
| virtual unsigned | getOpcodeAfterMemoryUnfold (unsigned Opc, bool UnfoldLoad, bool UnfoldStore, unsigned *LoadRegIndex=nullptr) const |
| Returns the opcode of the would be new instruction after load / store are unfolded from an instruction of the specified opcode. | |
| virtual bool | areLoadsFromSameBasePtr (SDNode *Load1, SDNode *Load2, int64_t &Offset1, int64_t &Offset2) const |
| This is used by the pre-regalloc scheduler to determine if two loads are loading from the same base address. | |
| virtual bool | shouldScheduleLoadsNear (SDNode *Load1, SDNode *Load2, int64_t Offset1, int64_t Offset2, unsigned NumLoads) const |
| This is a used by the pre-regalloc scheduler to determine (in conjunction with areLoadsFromSameBasePtr) if two loads should be scheduled together. | |
| bool | getMemOperandWithOffset (const MachineInstr &MI, const MachineOperand *&BaseOp, int64_t &Offset, bool &OffsetIsScalable, const TargetRegisterInfo *TRI) const |
| Get the base operand and byte offset of an instruction that reads/writes memory. | |
| virtual bool | getMemOperandsWithOffsetWidth (const MachineInstr &MI, SmallVectorImpl< const MachineOperand * > &BaseOps, int64_t &Offset, bool &OffsetIsScalable, LocationSize &Width, const TargetRegisterInfo *TRI) const |
| Get zero or more base operands and the byte offset of an instruction that reads/writes memory. | |
| virtual bool | getBaseAndOffsetPosition (const MachineInstr &MI, unsigned &BasePos, unsigned &OffsetPos) const |
| Return true if the instruction contains a base register and offset. | |
| virtual std::optional< ExtAddrMode > | getAddrModeFromMemoryOp (const MachineInstr &MemI, const TargetRegisterInfo *TRI) const |
| Target dependent implementation to get the values constituting the address MachineInstr that is accessing memory. | |
| virtual bool | canFoldIntoAddrMode (const MachineInstr &MemI, Register Reg, const MachineInstr &AddrI, ExtAddrMode &AM) const |
| Check if it's possible and beneficial to fold the addressing computation AddrI into the addressing mode of the load/store instruction MemI. | |
| virtual MachineInstr * | emitLdStWithAddr (MachineInstr &MemI, const ExtAddrMode &AM) const |
| Emit a load/store instruction with the same value register as MemI, but using the address from AM. | |
| virtual bool | preservesZeroValueInReg (const MachineInstr *MI, const Register NullValueReg, const TargetRegisterInfo *TRI) const |
| Returns true if MI's Def is NullValueReg, and the MI does not change the Zero value. | |
| virtual bool | getIncrementValue (const MachineInstr &MI, int &Value) const |
| If the instruction is an increment of a constant value, return the amount. | |
| virtual bool | shouldClusterMemOps (ArrayRef< const MachineOperand * > BaseOps1, int64_t Offset1, bool OffsetIsScalable1, ArrayRef< const MachineOperand * > BaseOps2, int64_t Offset2, bool OffsetIsScalable2, unsigned ClusterSize, unsigned NumBytes) const |
| Returns true if the two given memory operations should be scheduled adjacent. | |
| virtual bool | reverseBranchCondition (SmallVectorImpl< MachineOperand > &Cond) const |
| Reverses the branch condition of the specified condition list, returning false on success and true if it cannot be reversed. | |
| virtual void | insertNoop (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const |
| Insert a noop into the instruction stream at the specified point. | |
| virtual void | insertNoops (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned Quantity) const |
| Insert noops into the instruction stream at the specified point. | |
| virtual MCInst | getNop () const |
| Return the noop instruction to use for a noop. | |
| virtual bool | isPostIncrement (const MachineInstr &MI) const |
| Return true for post-incremented instructions. | |
| virtual bool | isPredicated (const MachineInstr &MI) const |
| Returns true if the instruction is already predicated. | |
| virtual bool | canPredicatePredicatedInstr (const MachineInstr &MI) const |
| Assumes the instruction is already predicated and returns true if the instruction can be predicated again. | |
| virtual std::string | createMIROperandComment (const MachineInstr &MI, const MachineOperand &Op, unsigned OpIdx, const TargetRegisterInfo *TRI) const |
| bool | isUnpredicatedTerminator (const MachineInstr &MI) const |
| Returns true if the instruction is a terminator instruction that has not been predicated. | |
| virtual bool | isUnconditionalTailCall (const MachineInstr &MI) const |
| Returns true if MI is an unconditional tail call. | |
| virtual bool | canMakeTailCallConditional (SmallVectorImpl< MachineOperand > &Cond, const MachineInstr &TailCall) const |
| Returns true if the tail call can be made conditional on BranchCond. | |
| virtual void | replaceBranchWithTailCall (MachineBasicBlock &MBB, SmallVectorImpl< MachineOperand > &Cond, const MachineInstr &TailCall) const |
| Replace the conditional branch in MBB with a conditional tail call. | |
| virtual bool | PredicateInstruction (MachineInstr &MI, ArrayRef< MachineOperand > Pred) const |
| Convert the instruction into a predicated instruction. | |
| virtual bool | SubsumesPredicate (ArrayRef< MachineOperand > Pred1, ArrayRef< MachineOperand > Pred2) const |
| Returns true if the first specified predicate subsumes the second, e.g. | |
| virtual bool | ClobbersPredicate (MachineInstr &MI, std::vector< MachineOperand > &Pred, bool SkipDead) const |
| If the specified instruction defines any predicate or condition code register(s) used for predication, returns true as well as the definition predicate(s) by reference. | |
| virtual bool | isPredicable (const MachineInstr &MI) const |
| Return true if the specified instruction can be predicated. | |
| virtual bool | isSafeToMoveRegClassDefs (const TargetRegisterClass *RC) const |
| Return true if it's safe to move a machine instruction that defines the specified register class. | |
| virtual bool | isSchedulingBoundary (const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const |
| Test if the given instruction should be considered a scheduling boundary. | |
| virtual unsigned | getInlineAsmLength (const char *Str, const MCAsmInfo &MAI, const TargetSubtargetInfo *STI=nullptr) const |
| Measure the specified inline asm to determine an approximation of its length. | |
| virtual ScheduleHazardRecognizer * | CreateTargetHazardRecognizer (const TargetSubtargetInfo *STI, const ScheduleDAG *DAG) const |
| Allocate and return a hazard recognizer to use for this target when scheduling the machine instructions before register allocation. | |
| virtual ScheduleHazardRecognizer * | CreateTargetMIHazardRecognizer (const InstrItineraryData *, const ScheduleDAGMI *DAG) const |
| Allocate and return a hazard recognizer to use for this target when scheduling the machine instructions before register allocation. | |
| virtual ScheduleHazardRecognizer * | CreateTargetPostRAHazardRecognizer (const InstrItineraryData *, const ScheduleDAG *DAG) const |
| Allocate and return a hazard recognizer to use for this target when scheduling the machine instructions after register allocation. | |
| virtual ScheduleHazardRecognizer * | CreateTargetPostRAHazardRecognizer (const MachineFunction &MF) const |
| Allocate and return a hazard recognizer to use for by non-scheduling passes. | |
| bool | usePreRAHazardRecognizer () const |
| Provide a global flag for disabling the PreRA hazard recognizer that targets may choose to honor. | |
| virtual bool | analyzeCompare (const MachineInstr &MI, Register &SrcReg, Register &SrcReg2, int64_t &Mask, int64_t &Value) const |
| For a comparison instruction, return the source registers in SrcReg and SrcReg2 if having two register operands, and the value it compares against in CmpValue. | |
| virtual bool | optimizeCompareInstr (MachineInstr &CmpInstr, Register SrcReg, Register SrcReg2, int64_t Mask, int64_t Value, const MachineRegisterInfo *MRI) const |
| See if the comparison instruction can be converted into something more efficient. | |
| virtual bool | optimizeCondBranch (MachineInstr &MI) const |
| virtual MachineInstr * | optimizeLoadInstr (MachineInstr &MI, const MachineRegisterInfo *MRI, Register &FoldAsLoadDefReg, MachineInstr *&DefMI) const |
| Try to remove the load by folding it to a register operand at the use. | |
| virtual bool | foldImmediate (MachineInstr &UseMI, MachineInstr &DefMI, Register Reg, MachineRegisterInfo *MRI) const |
| 'Reg' is known to be defined by a move immediate instruction, try to fold the immediate into the use instruction. | |
| virtual unsigned | getNumMicroOps (const InstrItineraryData *ItinData, const MachineInstr &MI) const |
| Return the number of u-operations the given machine instruction will be decoded to on the target cpu. | |
| bool | isZeroCost (unsigned Opcode) const |
| Return true for pseudo instructions that don't consume any machine resources in their current form. | |
| virtual std::optional< unsigned > | getOperandLatency (const InstrItineraryData *ItinData, SDNode *DefNode, unsigned DefIdx, SDNode *UseNode, unsigned UseIdx) const |
| virtual std::optional< unsigned > | getOperandLatency (const InstrItineraryData *ItinData, const MachineInstr &DefMI, unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const |
| Compute and return the use operand latency of a given pair of def and use. | |
| virtual unsigned | getInstrLatency (const InstrItineraryData *ItinData, const MachineInstr &MI, unsigned *PredCost=nullptr) const |
| Compute the instruction latency of a given instruction. | |
| virtual unsigned | getPredicationCost (const MachineInstr &MI) const |
| virtual unsigned | getInstrLatency (const InstrItineraryData *ItinData, SDNode *Node) const |
| unsigned | defaultDefLatency (const MCSchedModel &SchedModel, const MachineInstr &DefMI) const |
| Return the default expected latency for a def based on its opcode. | |
| virtual bool | isHighLatencyDef (int opc) const |
| Return true if this opcode has high latency to its result. | |
| virtual bool | hasHighOperandLatency (const TargetSchedModel &SchedModel, const MachineRegisterInfo *MRI, const MachineInstr &DefMI, unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const |
| Compute operand latency between a def of 'Reg' and a use in the current loop. | |
| virtual bool | hasLowDefLatency (const TargetSchedModel &SchedModel, const MachineInstr &DefMI, unsigned DefIdx) const |
| Compute operand latency of a def of 'Reg'. | |
| virtual bool | verifyInstruction (const MachineInstr &MI, StringRef &ErrInfo) const |
| Perform target-specific instruction verification. | |
| virtual std::pair< uint16_t, uint16_t > | getExecutionDomain (const MachineInstr &MI) const |
| Return the current execution domain and bit mask of possible domains for instruction. | |
| virtual void | setExecutionDomain (MachineInstr &MI, unsigned Domain) const |
| Change the opcode of MI to execute in Domain. | |
| virtual unsigned | getPartialRegUpdateClearance (const MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) const |
| Returns the preferred minimum clearance before an instruction with an unwanted partial register update. | |
| virtual unsigned | getUndefRegClearance (const MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) const |
| Return the minimum clearance before an instruction that reads an unused register. | |
| virtual void | breakPartialRegDependency (MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) const |
| Insert a dependency-breaking instruction before MI to eliminate an unwanted dependency on OpNum. | |
| virtual DFAPacketizer * | CreateTargetScheduleState (const TargetSubtargetInfo &) const |
| Create machine specific model for scheduling. | |
| virtual bool | areMemAccessesTriviallyDisjoint (const MachineInstr &MIa, const MachineInstr &MIb) const |
| Sometimes, it is possible for the target to tell, even without aliasing information, that two MIs access different memory addresses. | |
| virtual unsigned | getMachineCSELookAheadLimit () const |
| Return the value to use for the MachineCSE's LookAheadLimit, which is a heuristic used for CSE'ing phys reg defs. | |
| virtual unsigned | getMemOperandAACheckLimit () const |
| Return the maximal number of alias checks on memory operands. | |
| virtual ArrayRef< std::pair< int, const char * > > | getSerializableTargetIndices () const |
| Return an array that contains the ids of the target indices (used for the TargetIndex machine operand) and their names. | |
| virtual std::pair< unsigned, unsigned > | decomposeMachineOperandsTargetFlags (unsigned) const |
| Decompose the machine operand's target flags into two values - the direct target flag value and any of bit flags that are applied. | |
| virtual ArrayRef< std::pair< unsigned, const char * > > | getSerializableDirectMachineOperandTargetFlags () const |
| Return an array that contains the direct target flag values and their names. | |
| virtual ArrayRef< std::pair< unsigned, const char * > > | getSerializableBitmaskMachineOperandTargetFlags () const |
| Return an array that contains the bitmask target flag values and their names. | |
| virtual ArrayRef< std::pair< MachineMemOperand::Flags, const char * > > | getSerializableMachineMemOperandTargetFlags () const |
| Return an array that contains the MMO target flag values and their names. | |
| virtual bool | isTailCall (const MachineInstr &Inst) const |
Determines whether Inst is a tail call instruction. | |
| virtual bool | isBasicBlockPrologue (const MachineInstr &MI, Register Reg=Register()) const |
| True if the instruction is bound to the top of its basic block and no other instructions shall be inserted before it. | |
| virtual unsigned | getLiveRangeSplitOpcode (Register Reg, const MachineFunction &MF) const |
| Allows targets to use appropriate copy instruction while spilitting live range of a register in register allocation. | |
| virtual MachineInstr * | createPHIDestinationCopy (MachineBasicBlock &MBB, MachineBasicBlock::iterator InsPt, const DebugLoc &DL, Register Src, Register Dst) const |
| During PHI eleimination lets target to make necessary checks and insert the copy to the PHI destination register in a target specific manner. | |
| virtual MachineInstr * | createPHISourceCopy (MachineBasicBlock &MBB, MachineBasicBlock::iterator InsPt, const DebugLoc &DL, Register Src, unsigned SrcSubReg, Register Dst) const |
| During PHI eleimination lets target to make necessary checks and insert the copy to the PHI destination register in a target specific manner. | |
| virtual std::optional< std::unique_ptr< outliner::OutlinedFunction > > | getOutliningCandidateInfo (const MachineModuleInfo &MMI, std::vector< outliner::Candidate > &RepeatedSequenceLocs, unsigned MinRepeats) const |
Returns a outliner::OutlinedFunction struct containing target-specific information for a set of outlining candidates. | |
| virtual void | mergeOutliningCandidateAttributes (Function &F, std::vector< outliner::Candidate > &Candidates) const |
| Optional target hook to create the LLVM IR attributes for the outlined function. | |
| outliner::InstrType | getOutliningType (const MachineModuleInfo &MMI, MachineBasicBlock::iterator &MIT, unsigned Flags) const |
Returns how or if MIT should be outlined. | |
| virtual bool | isMBBSafeToOutlineFrom (MachineBasicBlock &MBB, unsigned &Flags) const |
Optional target hook that returns true if MBB is safe to outline from, and returns any target-specific information in Flags. | |
| virtual SmallVector< std::pair< MachineBasicBlock::iterator, MachineBasicBlock::iterator > > | getOutlinableRanges (MachineBasicBlock &MBB, unsigned &Flags) const |
Optional target hook which partitions MBB into outlinable ranges for instruction mapping purposes. | |
| virtual void | buildOutlinedFrame (MachineBasicBlock &MBB, MachineFunction &MF, const outliner::OutlinedFunction &OF) const |
| Insert a custom frame for outlined functions. | |
| virtual MachineBasicBlock::iterator | insertOutlinedCall (Module &M, MachineBasicBlock &MBB, MachineBasicBlock::iterator &It, MachineFunction &MF, outliner::Candidate &C) const |
| Insert a call to an outlined function into the program. | |
| virtual void | buildClearRegister (Register Reg, MachineBasicBlock &MBB, MachineBasicBlock::iterator Iter, DebugLoc &DL, bool AllowSideEffects=true) const |
| Insert an architecture-specific instruction to clear a register. | |
| virtual bool | isFunctionSafeToOutlineFrom (MachineFunction &MF, bool OutlineFromLinkOnceODRs) const |
| Return true if the function can safely be outlined from. | |
| virtual bool | shouldOutlineFromFunctionByDefault (MachineFunction &MF) const |
| Return true if the function should be outlined from by default. | |
| virtual bool | isFunctionSafeToSplit (const MachineFunction &MF) const |
| Return true if the function is a viable candidate for machine function splitting. | |
| virtual bool | isMBBSafeToSplitToCold (const MachineBasicBlock &MBB) const |
| Return true if the MachineBasicBlock can safely be split to the cold section. | |
| virtual std::optional< ParamLoadedValue > | describeLoadedValue (const MachineInstr &MI, Register Reg) const |
Produce the expression describing the MI loading a value into the physical register Reg. | |
| virtual bool | isExtendLikelyToBeFolded (MachineInstr &ExtMI, MachineRegisterInfo &MRI) const |
Given the generic extension instruction ExtMI, returns true if this extension is a likely candidate for being folded into an another instruction. | |
| virtual const MIRFormatter * | getMIRFormatter () const |
| Return MIR formatter to format/parse MIR operands. | |
| virtual unsigned | getTailDuplicateSize (CodeGenOptLevel OptLevel) const |
| Returns the target-specific default value for tail duplication. | |
| virtual unsigned | getTailMergeSize (const MachineFunction &MF) const |
| Returns the target-specific default value for tail merging. | |
| virtual const MachineOperand & | getCalleeOperand (const MachineInstr &MI) const |
Returns the callee operand from the given MI. | |
| virtual InstructionUniformity | getInstructionUniformity (const MachineInstr &MI) const |
| Return the uniformity behavior of the given instruction. | |
| virtual bool | isExplicitTargetIndexDef (const MachineInstr &MI, int &Index, int64_t &Offset) const |
Returns true if the given MI defines a TargetIndex operand that can be tracked by their offset, can have values, and can have debug info associated with it. | |
| unsigned | getCallFrameSizeAt (MachineInstr &MI) const |
| virtual void | getFrameIndexOperands (SmallVectorImpl< MachineOperand > &Ops, int FI) const |
| Fills in the necessary MachineOperands to refer to a frame index. | |
| Public Member Functions inherited from llvm::MCInstrInfo | |
| void | InitMCInstrInfo (const MCInstrDesc *D, const unsigned *NI, const char *ND, const uint8_t *DF, const ComplexDeprecationPredicate *CDI, unsigned NO, const int16_t *RCHWTables=nullptr, int16_t NumRegClassByHwMode=0) |
| Initialize MCInstrInfo, called by TableGen auto-generated routines. | |
| unsigned | getNumOpcodes () const |
| const int16_t * | getRegClassByHwModeTable (unsigned ModeId) const |
| int16_t | getOpRegClassID (const MCOperandInfo &OpInfo, unsigned HwModeId) const |
Return the ID of the register class to use for OpInfo, for the active HwMode HwModeId. | |
| const MCInstrDesc & | get (unsigned Opcode) const |
| Return the machine instruction descriptor that corresponds to the specified instruction opcode. | |
| StringRef | getName (unsigned Opcode) const |
| Returns the name for the instructions with the given opcode. | |
| LLVM_ABI bool | getDeprecatedInfo (MCInst &MI, const MCSubtargetInfo &STI, std::string &Info) const |
Returns true if a certain instruction is deprecated and if so returns the reason in Info. | |
Static Public Member Functions | |
| static bool | isGenericOpcode (unsigned Opc) |
| static bool | isGenericAtomicRMWOpcode (unsigned Opc) |
Static Public Attributes | |
| static const unsigned | CommuteAnyOperandIndex = ~0U |
Protected Member Functions | |
| TargetInstrInfo (unsigned CFSetupOpcode=~0u, unsigned CFDestroyOpcode=~0u, unsigned CatchRetOpcode=~0u, unsigned ReturnOpcode=~0u, const int16_t *const RegClassByHwModeTable=nullptr) | |
| virtual bool | isReallyTriviallyReMaterializable (const MachineInstr &MI) const |
| For instructions with opcodes for which the M_REMATERIALIZABLE flag is set, this hook lets the target specify whether the instruction is actually trivially rematerializable, taking into consideration its operands. | |
| virtual MachineInstr * | commuteInstructionImpl (MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const |
| This method commutes the operands of the given machine instruction MI. | |
| virtual std::optional< DestSourcePair > | isCopyInstrImpl (const MachineInstr &MI) const |
| Target-dependent implementation for IsCopyInstr. | |
| virtual std::optional< DestSourcePair > | isCopyLikeInstrImpl (const MachineInstr &MI) const |
| virtual bool | isUnspillableTerminatorImpl (const MachineInstr *MI) const |
| Return true if the given terminator MI is not expected to spill. | |
| virtual MachineInstr * | foldMemoryOperandImpl (MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex, LiveIntervals *LIS=nullptr, VirtRegMap *VRM=nullptr) const |
| Target-dependent implementation for foldMemoryOperand. | |
| virtual MachineInstr * | foldMemoryOperandImpl (MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI, LiveIntervals *LIS=nullptr) const |
| Target-dependent implementation for foldMemoryOperand. | |
| virtual bool | getRegSequenceLikeInputs (const MachineInstr &MI, unsigned DefIdx, SmallVectorImpl< RegSubRegPairAndIdx > &InputRegs) const |
| Target-dependent implementation of getRegSequenceInputs. | |
| virtual bool | getExtractSubregLikeInputs (const MachineInstr &MI, unsigned DefIdx, RegSubRegPairAndIdx &InputReg) const |
| Target-dependent implementation of getExtractSubregInputs. | |
| virtual bool | getInsertSubregLikeInputs (const MachineInstr &MI, unsigned DefIdx, RegSubRegPair &BaseReg, RegSubRegPairAndIdx &InsertedReg) const |
| Target-dependent implementation of getInsertSubregInputs. | |
| virtual outliner::InstrType | getOutliningTypeImpl (const MachineModuleInfo &MMI, MachineBasicBlock::iterator &MIT, unsigned Flags) const |
| Target-dependent implementation for getOutliningTypeImpl. | |
Static Protected Member Functions | |
| static bool | fixCommutedOpIndices (unsigned &ResultIdx1, unsigned &ResultIdx2, unsigned CommutableOpIdx1, unsigned CommutableOpIdx2) |
| Assigns the (CommutableOpIdx1, CommutableOpIdx2) pair of commutable operand indices to (ResultIdx1, ResultIdx2). | |
Protected Attributes | |
| const int16_t *const | RegClassByHwMode |
| Subtarget specific sub-array of MCInstrInfo's RegClassByHwModeTables (i.e. | |
| Protected Attributes inherited from llvm::MCInstrInfo | |
| const int16_t * | RegClassByHwModeTables |
| int16_t | NumRegClassByHwModes |
Additional Inherited Members | |
| Public Types inherited from llvm::MCInstrInfo | |
| using | ComplexDeprecationPredicate |
Detailed Description
TargetInstrInfo - Interface to description of machine instruction set.
Definition at line 114 of file TargetInstrInfo.h.
Constructor & Destructor Documentation
◆ TargetInstrInfo() [1/2]
|
inlineprotected |
Definition at line 121 of file TargetInstrInfo.h.
References RegClassByHwMode.
Referenced by genAlternativeCodeSequence(), operator=(), reassociateOps(), reduceAccumulatorTree(), and TargetInstrInfo().
◆ TargetInstrInfo() [2/2]
|
delete |
References TargetInstrInfo().
◆ ~TargetInstrInfo()
|
virtualdefault |
Member Function Documentation
◆ accumulateInstrSeqToRootLatency()
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inlinevirtual |
When calculate the latency of the root instruction, accumulate the latency of the sequence to the root latency.
- Parameters
-
Root - Instruction that could be combined with one of its operands
Definition at line 1381 of file TargetInstrInfo.h.
◆ analyzeBranch()
|
inlinevirtual |
Analyze the branching code at the end of MBB, returning true if it cannot be understood (e.g.
it's a switch dispatch or isn't implemented for a target). Upon success, this returns false and returns with the following information in various cases:
- If this block ends with no branches (it just falls through to its succ) just return false, leaving TBB/FBB null.
- If this block ends with only an unconditional branch, it sets TBB to be the destination block.
- If this block ends with a conditional branch and it falls through to a successor block, it sets TBB to be the branch destination block and a list of operands that evaluate the condition. These operands can be passed to other TargetInstrInfo methods to create new branches.
- If this block ends with a conditional branch followed by an unconditional branch, it returns the 'true' destination in TBB, the 'false' destination in FBB, and a list of operands that evaluate the condition. These operands can be passed to other TargetInstrInfo methods to create new branches.
Note that removeBranch and insertBranch must be implemented to support cases where this method returns success.
If AllowModify is true, then this routine is allowed to modify the basic block (e.g. delete instructions after the unconditional branch).
The CFG information in MBB.Predecessors and MBB.Successors must be valid before calling this function.
Definition at line 693 of file TargetInstrInfo.h.
◆ analyzeBranchPredicate()
|
inlinevirtual |
Analyze the branching code at the end of MBB and parse it into the MachineBranchPredicate structure if possible.
Returns false on success and true on failure.
If AllowModify is true, then this routine is allowed to modify the basic block (e.g. delete instructions after the unconditional branch).
Definition at line 735 of file TargetInstrInfo.h.
References MBB.
◆ analyzeCompare()
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inlinevirtual |
For a comparison instruction, return the source registers in SrcReg and SrcReg2 if having two register operands, and the value it compares against in CmpValue.
Return true if the comparison instruction can be analyzed.
Definition at line 1798 of file TargetInstrInfo.h.
References MI.
◆ analyzeLoop()
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inlinevirtual |
Analyze the loop code, return true if it cannot be understood.
Upon success, this function returns false and returns information about the induction variable and compare instruction used at the end.
Definition at line 862 of file TargetInstrInfo.h.
◆ analyzeLoopForPipelining()
|
inlinevirtual |
Analyze loop L, which must be a single-basic-block loop, and if the conditions can be understood enough produce a PipelinerLoopInfo object.
Definition at line 855 of file TargetInstrInfo.h.
◆ analyzeSelect()
|
inlinevirtual |
Analyze the given select instruction, returning true if it cannot be understood.
It is assumed that MI->isSelect() is true.
When successful, return the controlling condition and the operands that determine the true and false result values.
Result = SELECT Cond, TrueOp, FalseOp
Some targets can optimize select instructions, for example by predicating the instruction defining one of the operands. Such targets should set Optimizable.
- Parameters
-
MI Select instruction to analyze. Cond Condition controlling the select. TrueOp Operand number of the value selected when Cond is true. FalseOp Operand number of the value selected when Cond is false. Optimizable Returned as true if MI is optimizable.
- Returns
- False on success.
Definition at line 1025 of file TargetInstrInfo.h.
◆ areLoadsFromSameBasePtr()
|
inlinevirtual |
This is used by the pre-regalloc scheduler to determine if two loads are loading from the same base address.
It should only return true if the base pointers are the same and the only differences between the two addresses are the offset. It also returns the offsets by reference.
Definition at line 1530 of file TargetInstrInfo.h.
◆ areMemAccessesTriviallyDisjoint()
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inlinevirtual |
Sometimes, it is possible for the target to tell, even without aliasing information, that two MIs access different memory addresses.
This function returns true if two MIs access different memory addresses and false otherwise.
Assumes any physical registers used to compute addresses have the same value for both instructions. (This is the most useful assumption for post-RA scheduling.)
See also MachineInstr::mayAlias, which is implemented on top of this function.
Definition at line 2048 of file TargetInstrInfo.h.
References assert(), and llvm::MachineInstr::mayLoadOrStore().
◆ areOpcodesEqualOrInverse()
Return true when \P Opcode1 or its inversion is equal to \P Opcode2.
Definition at line 937 of file TargetInstrInfo.cpp.
References getInverseOpcode().
Referenced by getReassociationOpcodes(), and hasReassociableSibling().
◆ breakPartialRegDependency()
|
inlinevirtual |
Insert a dependency-breaking instruction before MI to eliminate an unwanted dependency on OpNum.
If it wasn't possible to avoid a def in the last N instructions before MI (see getPartialRegUpdateClearance), this hook will be called to break the unwanted dependency.
On x86, an xorps instruction can be used as a dependency breaker:
addps xmm1, xmm0 movaps xmm0, (rax) xorps xmm0, xmm0 cvtsi2ss rbx, xmm0
An <imp-kill> operand should be added to MI if an instruction was inserted. This ties the instructions together in the post-ra scheduler.
Definition at line 2027 of file TargetInstrInfo.h.
◆ buildClearRegister()
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inlinevirtual |
Insert an architecture-specific instruction to clear a register.
If you need to avoid sideeffects (e.g. avoid XOR on x86, which sets EFLAGS), set AllowSideEffects to false.
Definition at line 2252 of file TargetInstrInfo.h.
References DL, llvm_unreachable, MBB, and Reg.
◆ buildOutlinedFrame()
|
inlinevirtual |
Insert a custom frame for outlined functions.
Definition at line 2232 of file TargetInstrInfo.h.
References llvm_unreachable, and MBB.
◆ canCopyGluedNodeDuringSchedule()
|
inlinevirtual |
Return true if the given SDNode can be copied during scheduling even if it has glue.
Definition at line 1426 of file TargetInstrInfo.h.
References N.
◆ canFoldIntoAddrMode()
|
inlinevirtual |
Check if it's possible and beneficial to fold the addressing computation AddrI into the addressing mode of the load/store instruction MemI.
The memory instruction is a user of the virtual register Reg, which in turn is the ultimate destination of zero or more COPY instructions from the output register of AddrI. Return the adddressing mode after folding in AM.
Definition at line 1601 of file TargetInstrInfo.h.
References Reg.
◆ canInsertSelect()
|
inlinevirtual |
Return true if it is possible to insert a select instruction that chooses between TrueReg and FalseReg based on the condition code in Cond.
When successful, also return the latency in cycles from TrueReg, FalseReg, and Cond to the destination register. In most cases, a select instruction will be 1 cycle, so CondCycles = TrueCycles = FalseCycles = 1
Some x86 implementations have 2-cycle cmov instructions.
- Parameters
-
MBB Block where select instruction would be inserted. Cond Condition returned by analyzeBranch. DstReg Virtual dest register that the result should write to. TrueReg Virtual register to select when Cond is true. FalseReg Virtual register to select when Cond is false. CondCycles Latency from Cond+Branch to select output. TrueCycles Latency from TrueReg to select output. FalseCycles Latency from FalseReg to select output.
Definition at line 977 of file TargetInstrInfo.h.
◆ canMakeTailCallConditional()
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inlinevirtual |
Returns true if the tail call can be made conditional on BranchCond.
Definition at line 1703 of file TargetInstrInfo.h.
References Cond.
◆ canPredicatePredicatedInstr()
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inlinevirtual |
Assumes the instruction is already predicated and returns true if the instruction can be predicated again.
Definition at line 1683 of file TargetInstrInfo.h.
References assert(), isPredicated(), and MI.
◆ ClobbersPredicate()
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inlinevirtual |
If the specified instruction defines any predicate or condition code register(s) used for predication, returns true as well as the definition predicate(s) by reference.
SkipDead should be set to false at any point that dead predicate instructions should be considered as being defined. A dead predicate instruction is one that is guaranteed to be removed after a call to PredicateInstruction.
Definition at line 1734 of file TargetInstrInfo.h.
References MI.
◆ commuteInstruction()
| MachineInstr * TargetInstrInfo::commuteInstruction | ( | MachineInstr & | MI, |
| bool | NewMI = false, | ||
| unsigned | OpIdx1 = CommuteAnyOperandIndex, | ||
| unsigned | OpIdx2 = CommuteAnyOperandIndex ) const |
This method commutes the operands of the given machine instruction MI.
The operands to be commuted are specified by their indices OpIdx1 and OpIdx2. OpIdx1 and OpIdx2 arguments may be set to a special value 'CommuteAnyOperandIndex', which means that the method is free to choose any arbitrarily chosen commutable operand. If both arguments are set to 'CommuteAnyOperandIndex' then the method looks for 2 different commutable operands; then commutes them if such operands could be found.
If NewMI is false, MI is modified in place and returned; otherwise, a new machine instruction is created and returned.
Do not call this method for a non-commutable instruction or for non-commuable operands. Even though the instruction is commutable, the method may still fail to commute the operands, null pointer is returned in such cases.
Definition at line 285 of file TargetInstrInfo.cpp.
References assert(), CommuteAnyOperandIndex, commuteInstructionImpl(), findCommutedOpIndices(), and MI.
◆ commuteInstructionImpl()
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protectedvirtual |
This method commutes the operands of the given machine instruction MI.
The operands to be commuted are specified by their indices OpIdx1 and OpIdx2.
If a target has any instructions that are commutable but require converting to different instructions or making non-trivial changes to commute them, this method can be overloaded to do that. The default implementation simply swaps the commutable operands.
If NewMI is false, MI is modified in place and returned; otherwise, a new machine instruction is created and returned.
Do not call this method for a non-commutable instruction. Even though the instruction is commutable, the method may still fail to commute the operands, null pointer is returned in such cases.
Definition at line 184 of file TargetInstrInfo.cpp.
References assert(), llvm::enumerate(), findCommutedOpIndices(), llvm::MachineInstr::getOperand(), llvm::Register::isPhysical(), llvm::Register::isVirtual(), MI, llvm::SmallVectorTemplateBase< T, bool >::push_back(), Register, llvm::MachineOperand::setIsInternalRead(), llvm::MachineOperand::setIsKill(), llvm::MachineOperand::setIsRenamable(), llvm::MachineOperand::setIsUndef(), llvm::MachineOperand::setReg(), llvm::MachineOperand::setSubReg(), llvm::MCOI::TIED_TO, and TRI.
Referenced by commuteInstruction(), llvm::ARMBaseInstrInfo::commuteInstructionImpl(), llvm::PPCInstrInfo::commuteInstructionImpl(), llvm::RISCVInstrInfo::commuteInstructionImpl(), llvm::SIInstrInfo::commuteInstructionImpl(), llvm::SystemZInstrInfo::commuteInstructionImpl(), llvm::WebAssemblyInstrInfo::commuteInstructionImpl(), and llvm::X86InstrInfo::commuteInstructionImpl().
◆ convertToThreeAddress()
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inlinevirtual |
This method must be implemented by targets that set the M_CONVERTIBLE_TO_3_ADDR flag.
When this flag is set, the target may be able to convert a two-address instruction into one or more true three-address instructions on demand. This allows the X86 target (for example) to convert ADD and SHL instructions into LEA instructions if they would require register copies due to two-addressness.
This method returns a null pointer if the transformation cannot be performed, otherwise it returns the last new instruction.
If LIS is not nullptr, the LiveIntervals info should be updated for replacing MI with new instructions, even though this function does not remove MI.
Definition at line 473 of file TargetInstrInfo.h.
References MI.
◆ copyPhysReg()
|
inlinevirtual |
Emit instructions to copy a pair of physical registers.
This function should support copies within any legal register class as well as any cross-class copies created during instruction selection.
The source and destination registers may overlap, which may require a careful implementation when multiple copy instructions are required for large registers. See for example the ARM target.
If RenamableDest is true, the copy instruction's destination operand is marked renamable. If RenamableSrc is true, the copy instruction's source operand is marked renamable.
Definition at line 1068 of file TargetInstrInfo.h.
References DL, llvm_unreachable, MBB, and MI.
Referenced by lowerCopy().
◆ createMIROperandComment()
|
virtual |
Definition at line 2052 of file TargetInstrInfo.cpp.
References assert(), F, llvm::First, llvm::InlineAsm::getExtraInfoNames(), llvm::InlineAsm::getMemConstraintName(), MI, llvm::InlineAsm::MIOp_ExtraInfo, OpIdx, and TRI.
Referenced by llvm::ARMBaseInstrInfo::createMIROperandComment(), and llvm::RISCVInstrInfo::createMIROperandComment().
◆ createPHIDestinationCopy()
|
inlinevirtual |
During PHI eleimination lets target to make necessary checks and insert the copy to the PHI destination register in a target specific manner.
Definition at line 2153 of file TargetInstrInfo.h.
References llvm::BuildMI(), DL, llvm::MCInstrInfo::get(), and MBB.
Referenced by llvm::SIInstrInfo::createPHIDestinationCopy().
◆ createPHISourceCopy()
|
inlinevirtual |
During PHI eleimination lets target to make necessary checks and insert the copy to the PHI destination register in a target specific manner.
Definition at line 2163 of file TargetInstrInfo.h.
References llvm::BuildMI(), DL, llvm::MCInstrInfo::get(), and MBB.
Referenced by llvm::SIInstrInfo::createPHISourceCopy().
◆ CreateTargetHazardRecognizer()
|
virtual |
Allocate and return a hazard recognizer to use for this target when scheduling the machine instructions before register allocation.
Definition at line 1724 of file TargetInstrInfo.cpp.
Referenced by llvm::ARMBaseInstrInfo::CreateTargetHazardRecognizer(), and llvm::PPCInstrInfo::CreateTargetHazardRecognizer().
◆ CreateTargetMIHazardRecognizer()
|
virtual |
Allocate and return a hazard recognizer to use for this target when scheduling the machine instructions before register allocation.
Definition at line 1732 of file TargetInstrInfo.cpp.
References II.
Referenced by llvm::ARMBaseInstrInfo::CreateTargetMIHazardRecognizer(), and llvm::SIInstrInfo::CreateTargetMIHazardRecognizer().
◆ CreateTargetPostRAHazardRecognizer() [1/2]
|
virtual |
Allocate and return a hazard recognizer to use for this target when scheduling the machine instructions after register allocation.
Definition at line 1738 of file TargetInstrInfo.cpp.
References II.
Referenced by llvm::ARMBaseInstrInfo::CreateTargetPostRAHazardRecognizer(), and llvm::HexagonInstrInfo::CreateTargetPostRAHazardRecognizer().
◆ CreateTargetPostRAHazardRecognizer() [2/2]
|
inlinevirtual |
Allocate and return a hazard recognizer to use for by non-scheduling passes.
Definition at line 1786 of file TargetInstrInfo.h.
◆ CreateTargetScheduleState()
|
inlinevirtual |
Create machine specific model for scheduling.
Definition at line 2032 of file TargetInstrInfo.h.
Referenced by llvm::VLIWResourceModel::createPacketizer().
◆ decomposeMachineOperandsTargetFlags()
|
inlinevirtual |
Decompose the machine operand's target flags into two values - the direct target flag value and any of bit flags that are applied.
Definition at line 2093 of file TargetInstrInfo.h.
◆ defaultDefLatency()
| unsigned TargetInstrInfo::defaultDefLatency | ( | const MCSchedModel & | SchedModel, |
| const MachineInstr & | DefMI ) const |
Return the default expected latency for a def based on its opcode.
Return the default expected latency for a def based on it's opcode.
Definition at line 1810 of file TargetInstrInfo.cpp.
References DefMI, llvm::MCSchedModel::HighLatency, isHighLatencyDef(), and llvm::MCSchedModel::LoadLatency.
◆ describeLoadedValue()
|
virtual |
Produce the expression describing the MI loading a value into the physical register Reg.
This hook should only be used with MIs belonging to VReg-less functions.
Definition at line 1869 of file TargetInstrInfo.cpp.
References AbstractManglingParser< Derived, Alloc >::Ops, llvm::DIExpression::appendOffset(), llvm::DIExpression::ApplyOffset, assert(), llvm::MachineOperand::CreateReg(), llvm::MDNode::get(), llvm::Function::getContext(), llvm::MachineFunction::getFrameInfo(), llvm::MachineFunction::getFunction(), llvm::TargetSubtargetInfo::getInstrInfo(), llvm::MachineFunction::getProperties(), llvm::MachineMemOperand::getPseudoValue(), llvm::TargetSubtargetInfo::getRegisterInfo(), llvm::MachineMemOperand::getSize(), llvm::MachineFunction::getSubtarget(), llvm::LocationSize::getValue(), llvm::LocationSize::hasValue(), isAddImmediate(), isCopyInstr(), llvm::PseudoSourceValue::mayAlias(), MI, llvm::Offset, llvm::DIExpression::prepend(), llvm::DIExpression::prependOpcodes(), TII, and TRI.
Referenced by llvm::ARMBaseInstrInfo::describeLoadedValue(), llvm::MipsInstrInfo::describeLoadedValue(), and llvm::X86InstrInfo::describeLoadedValue().
◆ duplicate()
|
virtual |
Clones instruction or the whole instruction bundle Orig and insert into MBB before InsertBefore.
The target may update operands that are required to be unique.
Orig must not return true for MachineInstr::isNotDuplicable().
Definition at line 471 of file TargetInstrInfo.cpp.
References assert(), llvm::MachineFunction::getTarget(), llvm::TargetMachine::getTargetTriple(), llvm::MachineInstr::isCFIInstruction(), llvm::MachineInstr::isNotDuplicable(), llvm::Triple::isOSDarwin(), and MBB.
Referenced by llvm::ARMBaseInstrInfo::duplicate().
◆ emitLdStWithAddr()
|
inlinevirtual |
Emit a load/store instruction with the same value register as MemI, but using the address from AM.
The addressing mode must have been obtained from canFoldIntoAddr for the same memory instruction.
Definition at line 1610 of file TargetInstrInfo.h.
References llvm_unreachable.
◆ expandPostRAPseudo()
|
inlinevirtual |
This function is called for all pseudo instructions that remain after register allocation.
Many pseudo instructions are created to help register allocation. This is the place to convert them into real instructions. The target can edit MI in place, or it can insert new instructions and erase MI. The function should return true if anything was changed.
Definition at line 1214 of file TargetInstrInfo.h.
References MI.
Referenced by llvm::SIInstrInfo::expandPostRAPseudo().
◆ extraSizeToPredicateInstructions()
|
inlinevirtual |
Return the increase in code size needed to predicate a contiguous run of NumInsts instructions.
Definition at line 932 of file TargetInstrInfo.h.
◆ finalizeInsInstrs()
|
inlinevirtual |
Fix up the placeholder we may add in genAlternativeCodeSequence().
Definition at line 1284 of file TargetInstrInfo.h.
◆ findCommutedOpIndices()
|
virtual |
Returns true iff the routine could find two commutable operands in the given machine instruction.
The 'SrcOpIdx1' and 'SrcOpIdx2' are INPUT and OUTPUT arguments. If any of the INPUT values is set to the special value 'CommuteAnyOperandIndex' then the method arbitrarily picks a commutable operand, then returns its index in the corresponding argument. If both of INPUT values are set to 'CommuteAnyOperandIndex' then method looks for 2 commutable operands. If INPUT values refer to some operands of MI, then the method simply returns true if the corresponding operands are commutable and returns false otherwise.
For example, calling this method this way: unsigned Op1 = 1, Op2 = CommuteAnyOperandIndex; findCommutedOpIndices(MI, Op1, Op2); can be interpreted as a query asking to find an operand that would be commutable with the operand#1.
Definition at line 331 of file TargetInstrInfo.cpp.
References assert(), fixCommutedOpIndices(), and MI.
Referenced by commuteInstruction(), commuteInstructionImpl(), llvm::MipsInstrInfo::findCommutedOpIndices(), llvm::PPCInstrInfo::findCommutedOpIndices(), llvm::RISCVInstrInfo::findCommutedOpIndices(), and llvm::X86InstrInfo::findCommutedOpIndices().
◆ fixCommutedOpIndices()
|
staticprotected |
Assigns the (CommutableOpIdx1, CommutableOpIdx2) pair of commutable operand indices to (ResultIdx1, ResultIdx2).
One or both input values of the pair: (ResultIdx1, ResultIdx2) may be predefined to some indices or be undefined (designated by the special value 'CommuteAnyOperandIndex'). The predefined result indices cannot be re-defined. The function returns true iff after the result pair redefinition the fixed result pair is equal to or equivalent to the source pair of indices: (CommutableOpIdx1, CommutableOpIdx2). It is assumed here that the pairs (x,y) and (y,x) are equivalent.
Definition at line 300 of file TargetInstrInfo.cpp.
References CommuteAnyOperandIndex.
Referenced by findCommutedOpIndices().
◆ foldImmediate()
|
inlinevirtual |
'Reg' is known to be defined by a move immediate instruction, try to fold the immediate into the use instruction.
If MRI->hasOneNonDBGUse(Reg) is true, and this function returns true, then the caller may assume that DefMI has been erased from its parent block. The caller may assume that it will not be erased by this function otherwise.
Definition at line 1833 of file TargetInstrInfo.h.
◆ foldMemoryOperand() [1/2]
| MachineInstr * TargetInstrInfo::foldMemoryOperand | ( | MachineInstr & | MI, |
| ArrayRef< unsigned > | Ops, | ||
| int | FI, | ||
| LiveIntervals * | LIS = nullptr, | ||
| VirtRegMap * | VRM = nullptr ) const |
Attempt to fold a load or store of the specified stack slot into the specified machine instruction for the specified operand(s).
If this is possible, a new instruction is returned with the specified operand folded, otherwise NULL is returned. The new instruction is inserted before MI, and the client is responsible for removing the old instruction. If VRM is passed, the assigned physregs can be inspected by target to decide on using an opcode (note that those assignments can still change).
Definition at line 711 of file TargetInstrInfo.cpp.
References AbstractManglingParser< Derived, Alloc >::Ops, llvm::MachineInstrBuilder::add(), llvm::MachineInstr::addMemOperand(), assert(), llvm::BuildMI(), canFoldCopy(), llvm::MachineInstr::cloneInstrSymbols(), foldInlineAsmMemOperand(), foldMemoryOperandImpl(), foldPatchpoint(), llvm::MCInstrInfo::get(), llvm::MachinePointerInfo::getFixedStack(), llvm::MachineFunction::getFrameInfo(), llvm::MachineFunction::getMachineMemOperand(), llvm::MachineFrameInfo::getObjectAlign(), llvm::MachineFrameInfo::getObjectOffset(), llvm::MachineFrameInfo::getObjectSize(), llvm::MachineOperand::getReg(), llvm::TargetSubtargetInfo::getRegisterInfo(), llvm::MachineFunction::getSubtarget(), isCopyInstr(), llvm::MachineOperand::isKill(), llvm::MachineOperand::isUndef(), loadRegFromStackSlot(), llvm::MachineInstr::mayLoad(), llvm::MachineInstr::mayStore(), MBB, MI, llvm::MachineMemOperand::MOLoad, llvm::MachineMemOperand::MONone, llvm::MachineMemOperand::MOStore, OpIdx, llvm::MachineInstr::setMemRefs(), storeRegToStackSlot(), SubReg, and TRI.
Referenced by optimizeLoadInstr().
◆ foldMemoryOperand() [2/2]
| MachineInstr * TargetInstrInfo::foldMemoryOperand | ( | MachineInstr & | MI, |
| ArrayRef< unsigned > | Ops, | ||
| MachineInstr & | LoadMI, | ||
| LiveIntervals * | LIS = nullptr ) const |
Same as the previous version except it allows folding of any load and store from / to any address, not just from a specific stack slot.
Definition at line 812 of file TargetInstrInfo.cpp.
References AbstractManglingParser< Derived, Alloc >::Ops, llvm::MachineInstr::addMemOperand(), assert(), llvm::MachineInstr::canFoldAsLoad(), foldInlineAsmMemOperand(), foldMemoryOperandImpl(), foldPatchpoint(), I, isLoadFromStackSlot(), MBB, llvm::MachineInstr::memoperands(), llvm::MachineInstr::memoperands_begin(), llvm::MachineInstr::memoperands_end(), MI, OpIdx, and llvm::MachineInstr::setMemRefs().
◆ foldMemoryOperandImpl() [1/2]
|
inlineprotectedvirtual |
Target-dependent implementation for foldMemoryOperand.
Target-independent code in foldMemoryOperand will take care of adding a MachineMemOperand to the newly created instruction. The instruction and any auxiliary instructions necessary will be inserted at InsertPt.
Definition at line 1435 of file TargetInstrInfo.h.
References AbstractManglingParser< Derived, Alloc >::Ops, and MI.
Referenced by foldMemoryOperand(), and foldMemoryOperand().
◆ foldMemoryOperandImpl() [2/2]
|
inlineprotectedvirtual |
Target-dependent implementation for foldMemoryOperand.
Target-independent code in foldMemoryOperand will take care of adding a MachineMemOperand to the newly created instruction. The instruction and any auxiliary instructions necessary will be inserted at InsertPt.
Definition at line 1448 of file TargetInstrInfo.h.
References AbstractManglingParser< Derived, Alloc >::Ops, and MI.
◆ genAlternativeCodeSequence()
|
virtual |
When getMachineCombinerPatterns() finds patterns, this function generates the instructions that could replace the original code sequence.
The client has to decide whether the actual replacement is beneficial or not.
- Parameters
-
Root - Instruction that could be combined with one of its operands Pattern - Combination pattern for Root InsInstrs - Vector of new instructions that implement P DelInstrs - Old instructions, including Root, that could be replaced by InsInstr InstIdxForVirtReg - map of virtual register to instruction in InsInstr that defines it
Definition at line 1489 of file TargetInstrInfo.cpp.
References llvm::ACC_CHAIN, llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), llvm::Depth, llvm::enumerate(), getAccumulationStartOpcode(), getAccumulatorChain(), llvm::TargetSubtargetInfo::getInstrInfo(), llvm::getKillRegState(), llvm::MachineInstr::getMF(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), getReassociateOperandIndices(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), llvm::MachineFunction::getSubtarget(), llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::insert(), llvm::Log2_32(), MaxAccumulatorWidth, MBB, MRI, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::REASSOC_AX_BY, llvm::REASSOC_AX_YB, llvm::REASSOC_XA_BY, llvm::REASSOC_XA_YB, reassociateOps(), reduceAccumulatorTree(), llvm::reverse(), llvm::MachineInstr::setFlags(), llvm::SmallVectorTemplateCommon< T, typename >::size(), TargetInstrInfo(), and TII.
Referenced by llvm::PPCInstrInfo::genAlternativeCodeSequence(), llvm::RISCVInstrInfo::genAlternativeCodeSequence(), and llvm::X86InstrInfo::genAlternativeCodeSequence().
◆ getAccumulationStartOpcode()
|
inlinevirtual |
Returns an opcode which defines the accumulator used by \P Opcode.
Definition at line 1325 of file TargetInstrInfo.h.
References llvm_unreachable.
Referenced by genAlternativeCodeSequence(), and getAccumulatorChain().
◆ getAccumulatorChain()
| void TargetInstrInfo::getAccumulatorChain | ( | MachineInstr * | CurrentInstr, |
| SmallVectorImpl< Register > & | Chain ) const |
Find the chain of accumulator instructions in \P MBB and return them in \P Chain.
Definition at line 1014 of file TargetInstrInfo.cpp.
References canCombine(), getAccumulationStartOpcode(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), MBB, MRI, and llvm::SmallVectorTemplateBase< T, bool >::push_back().
Referenced by genAlternativeCodeSequence(), and getAccumulatorReassociationPatterns().
◆ getAccumulatorReassociationPatterns()
| bool TargetInstrInfo::getAccumulatorReassociationPatterns | ( | MachineInstr & | Root, |
| SmallVectorImpl< unsigned > & | Patterns ) const |
Find chains of accumulations that can be rewritten as a tree for increased ILP.
Definition at line 1045 of file TargetInstrInfo.cpp.
References llvm::ACC_CHAIN, llvm::SmallSet< T, N, C >::contains(), EnableAccReassociation, llvm::from_range, getAccumulatorChain(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), I, isAccumulationOpcode(), MBB, MinAccumulatorDepth, MRI, Opc, llvm::SmallVectorTemplateBase< T, bool >::push_back(), and llvm::SmallVectorTemplateCommon< T, typename >::size().
Referenced by getMachineCombinerPatterns().
◆ getAddrModeFromMemoryOp()
|
inlinevirtual |
Target dependent implementation to get the values constituting the address MachineInstr that is accessing memory.
These values are returned as a struct ExtAddrMode which contains all relevant information to make up the address.
Definition at line 1590 of file TargetInstrInfo.h.
References TRI.
◆ getBaseAndOffsetPosition()
|
inlinevirtual |
Return true if the instruction contains a base register and offset.
If true, the function also sets the operand position in the instruction for the base register and offset.
Definition at line 1579 of file TargetInstrInfo.h.
References MI.
◆ getBranchDestBlock()
|
inlinevirtual |
- Returns
- The block that branch instruction
MIjumps to.
Definition at line 650 of file TargetInstrInfo.h.
References llvm_unreachable, and MI.
◆ getCalleeOperand()
|
inlinevirtual |
Returns the callee operand from the given MI.
Definition at line 2326 of file TargetInstrInfo.h.
References MI.
◆ getCallFrameDestroyOpcode()
|
inline |
Definition at line 244 of file TargetInstrInfo.h.
Referenced by getCallFrameSizeAt(), getSPAdjust(), and isFrameInstr().
◆ getCallFrameSetupOpcode()
|
inline |
These methods return the opcode of the frame setup/destroy instructions if they exist (-1 otherwise).
Some targets use pseudo instructions in order to abstract away the difference between operating with a frame pointer and operating without, through the use of these two instructions. A FrameSetup MI in MF implies MFI::AdjustsStack.
Definition at line 243 of file TargetInstrInfo.h.
Referenced by getCallFrameSizeAt(), getSPAdjust(), isFrameInstr(), and isFrameSetup().
◆ getCallFrameSizeAt()
| unsigned TargetInstrInfo::getCallFrameSizeAt | ( | MachineInstr & | MI | ) | const |
Definition at line 1946 of file TargetInstrInfo.cpp.
References getCallFrameDestroyOpcode(), getCallFrameSetupOpcode(), getFrameTotalSize(), llvm::make_range(), MBB, MI, and llvm::reverse().
◆ getCatchReturnOpcode()
|
inline |
Definition at line 283 of file TargetInstrInfo.h.
◆ getCombinerObjective()
|
virtual |
Return the objective of a combiner pattern.
- Parameters
-
Pattern - combiner pattern
Definition at line 1184 of file TargetInstrInfo.cpp.
References llvm::ACC_CHAIN, llvm::Default, and llvm::MustReduceDepth.
Referenced by llvm::AArch64InstrInfo::getCombinerObjective(), llvm::PPCInstrInfo::getCombinerObjective(), and llvm::RISCVInstrInfo::getCombinerObjective().
◆ getConstValDefinedInReg()
|
inlinevirtual |
Returns true if MI is an instruction that defines Reg to have a constant value and the value is recorded in ImmVal.
The ImmVal is a result that should be interpreted as modulo size of Reg.
Definition at line 1163 of file TargetInstrInfo.h.
◆ getExecutionDomain()
|
inlinevirtual |
Return the current execution domain and bit mask of possible domains for instruction.
Some micro-architectures have multiple execution domains, and multiple opcodes that perform the same operation in different domains. For example, the x86 architecture provides the por, orps, and orpd instructions that all do the same thing. There is a latency penalty if a register is written in one domain and read in another.
This function returns a pair (domain, mask) containing the execution domain of MI, and a bit mask of possible domains. The setExecutionDomain function can be used to change the opcode to one of the domains in the bit mask. Instructions whose execution domain can't be changed should return a 0 mask.
The execution domain numbers don't have any special meaning except domain 0 is used for instructions that are not associated with any interesting execution domain.
Definition at line 1934 of file TargetInstrInfo.h.
References MI.
◆ getExtendResourceLenLimit()
|
inlinevirtual |
The limit on resource length extension we accept in MachineCombiner Pass.
Definition at line 1410 of file TargetInstrInfo.h.
◆ getExtractSubregInputs()
| bool TargetInstrInfo::getExtractSubregInputs | ( | const MachineInstr & | MI, |
| unsigned | DefIdx, | ||
| RegSubRegPairAndIdx & | InputReg ) const |
Build the equivalent inputs of a EXTRACT_SUBREG for the given MI and DefIdx.
[out] InputReg of the equivalent EXTRACT_SUBREG. E.g., EXTRACT_SUBREG %1:sub1, sub0, sub1 would produce:
- %1:sub1, sub0
- Returns
- true if it is possible to build such an input sequence with the pair
MI,DefIdxand the operand has no undef flag set. False otherwise.
- Precondition
- MI.isExtractSubreg() or MI.isExtractSubregLike().
- Note
- The generic implementation does not provide any support for MI.isExtractSubregLike(). In other words, one has to override getExtractSubregLikeInputs for target specific instructions.
Definition at line 1998 of file TargetInstrInfo.cpp.
References assert(), getExtractSubregLikeInputs(), llvm::MachineOperand::getImm(), llvm::MachineOperand::getReg(), llvm::MachineOperand::getSubReg(), llvm::MachineOperand::isImm(), llvm::MachineOperand::isUndef(), MI, llvm::TargetInstrInfo::RegSubRegPair::Reg, llvm::TargetInstrInfo::RegSubRegPairAndIdx::SubIdx, and llvm::TargetInstrInfo::RegSubRegPair::SubReg.
◆ getExtractSubregLikeInputs()
|
inlineprotectedvirtual |
Target-dependent implementation of getExtractSubregInputs.
- Returns
- true if it is possible to build the equivalent EXTRACT_SUBREG inputs with the pair
MI,DefIdx. False otherwise.
- Precondition
- MI.isExtractSubregLike().
Definition at line 1477 of file TargetInstrInfo.h.
References MI.
Referenced by getExtractSubregInputs().
◆ getFrameIndexOperands()
|
inlinevirtual |
Fills in the necessary MachineOperands to refer to a frame index.
The best way to understand this is to print asm(""::"m"(x)); after finalize-isel. Example: INLINEASM ... 262190 /* mem:m */, stack.0.x.addr, 1, $noreg, 0, $noreg we would add placeholders for: ^ ^ ^ ^
Definition at line 2353 of file TargetInstrInfo.h.
References AbstractManglingParser< Derived, Alloc >::Ops, and llvm_unreachable.
◆ getFrameSize()
|
inline |
Returns size of the frame associated with the given frame instruction.
For frame setup instruction this is frame that is set up space set up after the instruction. For frame destroy instruction this is the frame freed by the caller. Note, in some cases a call frame (or a part of it) may be prepared prior to the frame setup instruction. It occurs in the calls that involve inalloca arguments. This function reports only the size of the frame part that is set up between the frame setup and destroy pseudo instructions.
Definition at line 265 of file TargetInstrInfo.h.
References assert(), I, and isFrameInstr().
Referenced by getFrameTotalSize(), and getSPAdjust().
◆ getFrameTotalSize()
|
inline |
Returns the total frame size, which is made up of the space set up inside the pair of frame start-stop instructions and the space that is set up prior to the pair.
Definition at line 274 of file TargetInstrInfo.h.
References assert(), getFrameSize(), I, and isFrameSetup().
Referenced by getCallFrameSizeAt().
◆ getIncrementValue()
|
inlinevirtual |
If the instruction is an increment of a constant value, return the amount.
Definition at line 1627 of file TargetInstrInfo.h.
References MI.
◆ getInlineAsmLength()
|
virtual |
Measure the specified inline asm to determine an approximation of its length.
Comments (which run till the next SeparatorString or newline) do not count as an instruction. Any other non-whitespace text is considered an instruction, with multiple instructions separated by SeparatorString or newlines. Variable-length instructions are not handled here; this function may be overloaded in the target code to do that. We implement a special case of the .space directive which takes only a single integer argument in base 10 that is the size in bytes. This is a restricted form of the GAS directive in that we only interpret simple–i.e. not a logical or arithmetic expression–size values without the optional fill value. This is primarily used for creating arbitrary sized inline asm blocks for testing purposes.
Definition at line 117 of file TargetInstrInfo.cpp.
References llvm::MCAsmInfo::getMaxInstLength(), llvm::MCAsmInfo::getSeparatorString(), isAsmComment(), llvm::isSpace(), and llvm::Length.
◆ getInsertSubregInputs()
| bool TargetInstrInfo::getInsertSubregInputs | ( | const MachineInstr & | MI, |
| unsigned | DefIdx, | ||
| RegSubRegPair & | BaseReg, | ||
| RegSubRegPairAndIdx & | InsertedReg ) const |
Build the equivalent inputs of a INSERT_SUBREG for the given MI and DefIdx.
[out] BaseReg and [out] InsertedReg contain the equivalent inputs of INSERT_SUBREG. E.g., INSERT_SUBREG %0:sub0, %1:sub1, sub3 would produce:
- BaseReg: %0:sub0
- InsertedReg: %1:sub1, sub3
- Returns
- true if it is possible to build such an input sequence with the pair
MI,DefIdxand the operand has no undef flag set. False otherwise.
- Precondition
- MI.isInsertSubreg() or MI.isInsertSubregLike().
- Note
- The generic implementation does not provide any support for MI.isInsertSubregLike(). In other words, one has to override getInsertSubregLikeInputs for target specific instructions.
Definition at line 2023 of file TargetInstrInfo.cpp.
References assert(), llvm::MachineOperand::getImm(), getInsertSubregLikeInputs(), llvm::MachineOperand::getReg(), llvm::MachineOperand::getSubReg(), llvm::MachineOperand::isImm(), llvm::MachineOperand::isUndef(), MI, llvm::TargetInstrInfo::RegSubRegPair::Reg, llvm::TargetInstrInfo::RegSubRegPairAndIdx::SubIdx, and llvm::TargetInstrInfo::RegSubRegPair::SubReg.
◆ getInsertSubregLikeInputs()
|
inlineprotectedvirtual |
Target-dependent implementation of getInsertSubregInputs.
- Returns
- true if it is possible to build the equivalent INSERT_SUBREG inputs with the pair
MI,DefIdx. False otherwise.
- Precondition
- MI.isInsertSubregLike().
Definition at line 1492 of file TargetInstrInfo.h.
References MI.
Referenced by getInsertSubregInputs().
◆ getInstrLatency() [1/2]
|
virtual |
Compute the instruction latency of a given instruction.
If the instruction has higher cost when predicated, it's returned via PredCost.
Definition at line 1825 of file TargetInstrInfo.cpp.
References llvm::InstrItineraryData::getStageLatency(), and MI.
◆ getInstrLatency() [2/2]
|
virtual |
Definition at line 1779 of file TargetInstrInfo.cpp.
References llvm::MCInstrInfo::get(), llvm::MCInstrDesc::getSchedClass(), llvm::InstrItineraryData::getStageLatency(), llvm::InstrItineraryData::isEmpty(), and N.
◆ getInstructionUniformity()
|
inlinevirtual |
Return the uniformity behavior of the given instruction.
Definition at line 2332 of file TargetInstrInfo.h.
References llvm::Default, and MI.
◆ getInstSizeInBytes()
|
inlinevirtual |
Returns the size in bytes of the specified MachineInstr, or ~0U when this function is not implemented by a target.
Definition at line 411 of file TargetInstrInfo.h.
References MI.
◆ getInverseOpcode()
|
inlinevirtual |
Return the inverse operation opcode if it exists for \P Opcode (e.g.
add for sub and vice versa).
Definition at line 1347 of file TargetInstrInfo.h.
Referenced by areOpcodesEqualOrInverse(), and getReassociationOpcodes().
◆ getJumpTableIndex()
|
inlinevirtual |
Return an index for MachineJumpTableInfo if insn is an indirect jump using a jump table, otherwise -1.
Definition at line 1091 of file TargetInstrInfo.h.
References MI.
◆ getLiveRangeSplitOpcode()
|
inlinevirtual |
Allows targets to use appropriate copy instruction while spilitting live range of a register in register allocation.
Definition at line 2145 of file TargetInstrInfo.h.
References Reg.
◆ getMachineCombinerPatterns()
|
virtual |
Return true when there is potentially a faster code sequence for an instruction chain ending in Root.
All potential patterns are returned in the Pattern vector. Pattern should be sorted in priority order since the pattern evaluator stops checking as soon as it finds a faster sequence.
- Parameters
-
Root - Instruction that could be combined with one of its operands Patterns - Vector of possible combination patterns
Definition at line 1154 of file TargetInstrInfo.cpp.
References getAccumulatorReassociationPatterns(), isReassociationCandidate(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::REASSOC_AX_BY, llvm::REASSOC_AX_YB, llvm::REASSOC_XA_BY, and llvm::REASSOC_XA_YB.
Referenced by llvm::PPCInstrInfo::getMachineCombinerPatterns(), llvm::RISCVInstrInfo::getMachineCombinerPatterns(), and llvm::X86InstrInfo::getMachineCombinerPatterns().
◆ getMachineCombinerTraceStrategy()
|
virtual |
Return a strategy that MachineCombiner must use when creating traces.
Definition at line 1589 of file TargetInstrInfo.cpp.
References llvm::TS_MinInstrCount.
◆ getMachineCSELookAheadLimit()
|
inlinevirtual |
Return the value to use for the MachineCSE's LookAheadLimit, which is a heuristic used for CSE'ing phys reg defs.
Definition at line 2059 of file TargetInstrInfo.h.
◆ getMemOperandAACheckLimit()
|
inlinevirtual |
Return the maximal number of alias checks on memory operands.
For instructions with more than one memory operands, the alias check on a single MachineInstr pair has quadratic overhead and results in unacceptable performance in the worst case. The limit here is to clamp that maximal checks performed. Usually, that's the product of memory operand numbers from that pair of MachineInstr to be checked. For instance, with two MachineInstrs with 4 and 5 memory operands correspondingly, a total of 20 checks are required. With this limit set to 16, their alias check is skipped. We choose to limit the product instead of the individual instruction as targets may have special MachineInstrs with a considerably high number of memory operands, such as ldm in ARM. Setting this limit per MachineInstr would result in either too high overhead or too rigid restriction.
Definition at line 2078 of file TargetInstrInfo.h.
◆ getMemOperandsWithOffsetWidth()
|
inlinevirtual |
Get zero or more base operands and the byte offset of an instruction that reads/writes memory.
Note that there may be zero base operands if the instruction accesses a constant address. It returns false if MI does not read/write memory. It returns false if base operands and offset could not be determined. It is not guaranteed to always recognize base operands and offsets in all cases. FIXME: Move Offset and OffsetIsScalable to some ElementCount-style abstraction that supports negative offsets.
Definition at line 1569 of file TargetInstrInfo.h.
References MI, llvm::Offset, and TRI.
Referenced by getMemOperandWithOffset().
◆ getMemOperandWithOffset()
| bool TargetInstrInfo::getMemOperandWithOffset | ( | const MachineInstr & | MI, |
| const MachineOperand *& | BaseOp, | ||
| int64_t & | Offset, | ||
| bool & | OffsetIsScalable, | ||
| const TargetRegisterInfo * | TRI ) const |
Get the base operand and byte offset of an instruction that reads/writes memory.
This is a convenience function for callers that are only prepared to handle a single base operand. FIXME: Move Offset and OffsetIsScalable to some ElementCount-style abstraction that supports negative offsets.
Definition at line 1745 of file TargetInstrInfo.cpp.
References llvm::SmallVectorTemplateCommon< T, typename >::front(), getMemOperandsWithOffsetWidth(), MI, llvm::Offset, llvm::LocationSize::precise(), llvm::SmallVectorTemplateCommon< T, typename >::size(), and TRI.
◆ getMIRFormatter()
|
inlinevirtual |
Return MIR formatter to format/parse MIR operands.
Target can override this virtual function and return target specific MIR formatter.
Definition at line 2306 of file TargetInstrInfo.h.
◆ getNop()
|
virtual |
Return the noop instruction to use for a noop.
Definition at line 519 of file TargetInstrInfo.cpp.
References llvm_unreachable.
◆ getNumMicroOps()
|
virtual |
Return the number of u-operations the given machine instruction will be decoded to on the target cpu.
The itinerary's IssueWidth is the number of microops that can be dispatched each cycle. An instruction with zero microops takes no dispatch resources.
Definition at line 1794 of file TargetInstrInfo.cpp.
References llvm::InstrItineraryData::isEmpty(), llvm::InstrItineraryData::Itineraries, MI, and llvm::InstrItinerary::NumMicroOps.
◆ getOpcodeAfterMemoryUnfold()
|
inlinevirtual |
Returns the opcode of the would be new instruction after load / store are unfolded from an instruction of the specified opcode.
It returns zero if the specified unfolding is not possible. If LoadRegIndex is non-null, it is filled in with the operand index of the operand which will hold the register holding the loaded value.
Definition at line 1521 of file TargetInstrInfo.h.
References Opc.
◆ getOperandLatency() [1/2]
|
virtual |
Compute and return the use operand latency of a given pair of def and use.
Both DefMI and UseMI must be valid.
In most cases, the static scheduling itinerary was enough to determine the operand latency. But it may not be possible for instructions with variable number of defs / uses.
This is a raw interface to the itinerary that may be directly overridden by a target. Use computeOperandLatency to get the best estimate of latency.
By default, call directly to the itinerary. This may be overriden by the target.
Definition at line 1963 of file TargetInstrInfo.cpp.
References DefMI, llvm::InstrItineraryData::getOperandLatency(), and UseMI.
◆ getOperandLatency() [2/2]
|
virtual |
Definition at line 1763 of file TargetInstrInfo.cpp.
References llvm::MCInstrInfo::get(), llvm::SDNode::getMachineOpcode(), llvm::InstrItineraryData::getOperandCycle(), llvm::InstrItineraryData::getOperandLatency(), llvm::MCInstrDesc::getSchedClass(), llvm::InstrItineraryData::isEmpty(), and llvm::SDNode::isMachineOpcode().
Referenced by llvm::HexagonInstrInfo::getOperandLatency().
◆ getOpRegClassID()
|
inline |
- Returns
- the subtarget appropriate RegClassID for
OpInfo
Note this shadows a version of getOpRegClassID in MCInstrInfo which takes an additional argument for the subtarget's HwMode, since TargetInstrInfo is owned by a subtarget in CodeGen but MCInstrInfo is a TargetMachine constant.
Definition at line 149 of file TargetInstrInfo.h.
References RegClassByHwMode.
Referenced by getRegClass().
◆ getOutlinableRanges()
|
inlinevirtual |
Optional target hook which partitions MBB into outlinable ranges for instruction mapping purposes.
Each range is defined by two iterators: [start, end).
Ranges are expected to be ordered top-down. That is, ranges closer to the top of the block should come before ranges closer to the end of the block.
Ranges cannot overlap.
If an entire block is mappable, then its range is [MBB.begin(), MBB.end())
All instructions not present in an outlinable range are considered illegal.
Definition at line 2227 of file TargetInstrInfo.h.
References MBB.
◆ getOutliningCandidateInfo()
|
inlinevirtual |
Returns a outliner::OutlinedFunction struct containing target-specific information for a set of outlining candidates.
Returns std::nullopt if the candidates are not suitable for outlining. MinRepeats is the minimum number of times the instruction sequence must be repeated.
Definition at line 2177 of file TargetInstrInfo.h.
References llvm_unreachable.
◆ getOutliningType()
| outliner::InstrType TargetInstrInfo::getOutliningType | ( | const MachineModuleInfo & | MMI, |
| MachineBasicBlock::iterator & | MIT, | ||
| unsigned | Flags ) const |
Returns how or if MIT should be outlined.
Flags is the target-specific information returned by isMBBSafeToOutlineFrom.
Definition at line 2133 of file TargetInstrInfo.cpp.
References assert(), getOutliningTypeImpl(), llvm::outliner::Illegal, llvm::outliner::Invisible, isPredicated(), and MI.
◆ getOutliningTypeImpl()
|
inlineprotectedvirtual |
Target-dependent implementation for getOutliningTypeImpl.
Definition at line 2194 of file TargetInstrInfo.h.
References llvm_unreachable.
Referenced by getOutliningType().
◆ getPartialRegUpdateClearance()
|
inlinevirtual |
Returns the preferred minimum clearance before an instruction with an unwanted partial register update.
Some instructions only write part of a register, and implicitly need to read the other parts of the register. This may cause unwanted stalls preventing otherwise unrelated instructions from executing in parallel in an out-of-order CPU.
For example, the x86 instruction cvtsi2ss writes its result to bits [31:0] of the destination xmm register. Bits [127:32] are unaffected, so the instruction needs to wait for the old value of the register to become available:
addps xmm1, xmm0 movaps xmm0, (rax) cvtsi2ss rbx, xmm0
In the code above, the cvtsi2ss instruction needs to wait for the addps instruction before it can issue, even though the high bits of xmm0 probably aren't needed.
This hook returns the preferred clearance before MI, measured in instructions. Other defs of MI's operand OpNum are avoided in the last N instructions before MI. It should only return a positive value for unwanted dependencies. If the old bits of the defined register have useful values, or if MI is determined to otherwise read the dependency, the hook should return 0.
The unwanted dependency may be handled by:
- Allocating the same register for an MI def and use. That makes the unwanted dependency identical to a required dependency.
- Allocating a register for the def that has no defs in the previous N instructions.
- Calling breakPartialRegDependency() with the same arguments. This allows the target to insert a dependency breaking instruction.
Definition at line 1984 of file TargetInstrInfo.h.
◆ getPatchpointUnfoldableRange()
|
virtual |
For a patchpoint, stackmap, or statepoint intrinsic, return the range of operands which can't be folded into stack references.
Operands outside of the range are most likely foldable but it is not guaranteed. These instructions are unique in that stack references for some operands have the same execution cost (e.g. none) as the unfolded register forms. The ranged return is guaranteed to include all operands which can't be folded at zero cost.
Definition at line 563 of file TargetInstrInfo.cpp.
References llvm_unreachable, and MI.
◆ getPredicationCost()
|
virtual |
Definition at line 1821 of file TargetInstrInfo.cpp.
◆ getReassociateOperandIndices()
|
virtual |
The returned array encodes the operand index for each parameter because the operands may be commuted; the operand indices for associative operations might also be target-specific.
Each element specifies the index of {Prev, A, B, X, Y}.
Definition at line 1298 of file TargetInstrInfo.cpp.
References llvm_unreachable, llvm::REASSOC_AX_BY, llvm::REASSOC_AX_YB, llvm::REASSOC_XA_BY, and llvm::REASSOC_XA_YB.
Referenced by genAlternativeCodeSequence(), and llvm::RISCVInstrInfo::getReassociateOperandIndices().
◆ getReassociationOpcodes()
| std::pair< unsigned, unsigned > TargetInstrInfo::getReassociationOpcodes | ( | unsigned | Pattern, |
| const MachineInstr & | Root, | ||
| const MachineInstr & | Prev ) const |
Reassociation of some instructions requires inverse operations (e.g.
(X + A) - Y => (X - Y) + A). This method returns a pair of new opcodes (new root opcode, new prev opcode) that must be used to reassociate \P Root and \P Prev accoring to \P Pattern.
Definition at line 1194 of file TargetInstrInfo.cpp.
References areOpcodesEqualOrInverse(), assert(), getInverseOpcode(), llvm::MachineInstr::getOpcode(), isAssociativeAndCommutative(), llvm_unreachable, llvm::REASSOC_AX_BY, llvm::REASSOC_AX_YB, llvm::REASSOC_XA_BY, llvm::REASSOC_XA_YB, and std::swap().
Referenced by reassociateOps().
◆ getReduceOpcodeForAccumulator()
|
inlinevirtual |
Returns the opcode that should be use to reduce accumulation registers.
Definition at line 1332 of file TargetInstrInfo.h.
References llvm_unreachable.
Referenced by reduceAccumulatorTree().
◆ getRegClass()
|
virtual |
Given a machine instruction descriptor, returns the register class constraint for OpNum, or NULL.
Definition at line 62 of file TargetInstrInfo.cpp.
References getOpRegClassID(), and TRI.
Referenced by llvm::X86InstrInfo::getRegClass().
◆ getRegSequenceInputs()
| bool TargetInstrInfo::getRegSequenceInputs | ( | const MachineInstr & | MI, |
| unsigned | DefIdx, | ||
| SmallVectorImpl< RegSubRegPairAndIdx > & | InputRegs ) const |
Build the equivalent inputs of a REG_SEQUENCE for the given MI and DefIdx.
[out] InputRegs of the equivalent REG_SEQUENCE. Each element of the list is modeled as <Reg:SubReg, SubIdx>. Operands with the undef flag are not added to this list. E.g., REG_SEQUENCE %1:sub1, sub0, %2, sub1 would produce two elements:
- %1:sub1, sub0
- %2<:0>, sub1
- Returns
- true if it is possible to build such an input sequence with the pair
MI,DefIdx. False otherwise.
- Precondition
- MI.isRegSequence() or MI.isRegSequenceLike().
- Note
- The generic implementation does not provide any support for MI.isRegSequenceLike(). In other words, one has to override getRegSequenceLikeInputs for target specific instructions.
Definition at line 1971 of file TargetInstrInfo.cpp.
References assert(), llvm::MachineOperand::getImm(), llvm::MachineOperand::getReg(), getRegSequenceLikeInputs(), llvm::MachineOperand::getSubReg(), llvm::MachineOperand::isImm(), llvm::MachineOperand::isUndef(), MI, OpIdx, and llvm::SmallVectorTemplateBase< T, bool >::push_back().
◆ getRegSequenceLikeInputs()
|
inlineprotectedvirtual |
Target-dependent implementation of getRegSequenceInputs.
- Returns
- true if it is possible to build the equivalent REG_SEQUENCE inputs with the pair
MI,DefIdx. False otherwise.
- Precondition
- MI.isRegSequenceLike().
Definition at line 1463 of file TargetInstrInfo.h.
References MI.
Referenced by getRegSequenceInputs().
◆ getReturnOpcode()
|
inline |
Definition at line 284 of file TargetInstrInfo.h.
◆ getSerializableBitmaskMachineOperandTargetFlags()
|
inlinevirtual |
Return an array that contains the bitmask target flag values and their names.
MIR Serialization is able to serialize only the target flags that are defined by this method.
Definition at line 2113 of file TargetInstrInfo.h.
◆ getSerializableDirectMachineOperandTargetFlags()
|
inlinevirtual |
Return an array that contains the direct target flag values and their names.
MIR Serialization is able to serialize only the target flags that are defined by this method.
Definition at line 2103 of file TargetInstrInfo.h.
◆ getSerializableMachineMemOperandTargetFlags()
|
inlinevirtual |
Return an array that contains the MMO target flag values and their names.
MIR Serialization is able to serialize only the MMO target flags that are defined by this method.
Definition at line 2123 of file TargetInstrInfo.h.
◆ getSerializableTargetIndices()
|
inlinevirtual |
Return an array that contains the ids of the target indices (used for the TargetIndex machine operand) and their names.
MIR Serialization is able to serialize only the target indices that are defined by this method.
Definition at line 2086 of file TargetInstrInfo.h.
◆ getSPAdjust()
|
virtual |
Returns the actual stack pointer adjustment made by an instruction as part of a call sequence.
By default, only call frame setup/destroy instructions adjust the stack, but targets may want to override this to enable more fine-grained adjustment, or adjust by a different value.
Definition at line 1672 of file TargetInstrInfo.cpp.
References llvm::TargetFrameLowering::alignSPAdjust(), getCallFrameDestroyOpcode(), getCallFrameSetupOpcode(), llvm::TargetSubtargetInfo::getFrameLowering(), getFrameSize(), llvm::TargetFrameLowering::getStackGrowthDirection(), llvm::MachineFunction::getSubtarget(), isFrameInstr(), MI, and llvm::TargetFrameLowering::StackGrowsDown.
◆ getStackSlotRange()
|
virtual |
Compute the size in bytes and offset within a stack slot of a spilled register or subregister.
- Parameters
-
[out] Size in bytes of the spilled value. [out] Offset in bytes within the stack slot.
- Returns
- true if both Size and Offset are successfully computed.
Not all subregisters have computable spill slots. For example, subregisters registers may not be byte-sized, and a pair of discontiguous subregisters has no single offset.
Targets with nontrivial bigendian implementations may need to override this, particularly to support spilled vector registers.
Definition at line 424 of file TargetInstrInfo.cpp.
References assert(), llvm::MachineFunction::getDataLayout(), llvm::TargetSubtargetInfo::getRegisterInfo(), llvm::MachineFunction::getSubtarget(), llvm::DataLayout::isLittleEndian(), llvm::Offset, Size, and TRI.
◆ getTailDuplicateSize()
|
inlinevirtual |
Returns the target-specific default value for tail duplication.
This value will be used if the tail-dup-placement-threshold argument is not provided.
Definition at line 2315 of file TargetInstrInfo.h.
References llvm::Aggressive.
◆ getTailMergeSize()
|
inlinevirtual |
Returns the target-specific default value for tail merging.
This value will be used if the tail-merge-size argument is not provided.
Definition at line 2321 of file TargetInstrInfo.h.
◆ getUndefRegClearance()
|
inlinevirtual |
Return the minimum clearance before an instruction that reads an unused register.
For example, AVX instructions may copy part of a register operand into the unused high bits of the destination register.
vcvtsi2sdq rax, undef xmm0, xmm14
In the code above, vcvtsi2sdq copies xmm0[127:64] into xmm14 creating a false dependence on any previous write to xmm0.
This hook works similarly to getPartialRegUpdateClearance, except that it does not take an operand index. Instead sets OpNum to the index of the unused register.
Definition at line 2004 of file TargetInstrInfo.h.
◆ hasCommutePreference()
|
inlinevirtual |
Returns true if the target has a preference on the operands order of the given machine instruction.
And specify if Commute is required to get the desired operands order.
Definition at line 530 of file TargetInstrInfo.h.
References MI.
◆ hasHighOperandLatency()
|
inlinevirtual |
Compute operand latency between a def of 'Reg' and a use in the current loop.
Return true if the target considered it 'high'. This is used by optimization passes such as machine LICM to determine whether it makes sense to hoist an instruction out even in a high register pressure situation.
Definition at line 1894 of file TargetInstrInfo.h.
◆ hasLoadFromStackSlot()
|
virtual |
If the specified machine instruction has a load from a stack slot, return true along with the FrameIndices of the loaded stack slot and the machine mem operands containing the reference.
If not, return false. Unlike isLoadFromStackSlot, this returns true for any instructions that loads from the stack. This is just a hint, as some cases may be missed.
Definition at line 396 of file TargetInstrInfo.cpp.
References Accesses, llvm::isa_and_nonnull(), and MI.
Referenced by llvm::HexagonInstrInfo::hasLoadFromStackSlot().
◆ hasLowDefLatency()
|
virtual |
Compute operand latency of a def of 'Reg'.
Return true if the target considered it 'low'.
Definition at line 1836 of file TargetInstrInfo.cpp.
References DefMI, llvm::TargetSchedModel::getInstrItineraries(), llvm::InstrItineraryData::getOperandCycle(), and llvm::InstrItineraryData::isEmpty().
◆ hasReassociableOperands()
|
virtual |
Return true when \P Inst has reassociable operands in the same \P MBB.
Definition at line 918 of file TargetInstrInfo.cpp.
References llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::MachineOperand::isReg(), llvm::Register::isVirtual(), MBB, and MRI.
Referenced by llvm::RISCVInstrInfo::hasReassociableOperands(), llvm::X86InstrInfo::hasReassociableOperands(), hasReassociableSibling(), and isReassociationCandidate().
◆ hasReassociableSibling()
|
virtual |
Return true when \P Inst has reassociable sibling.
Definition at line 942 of file TargetInstrInfo.cpp.
References areOpcodesEqualOrInverse(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), hasReassociableOperands(), isAssociativeAndCommutative(), MBB, MRI, and std::swap().
Referenced by llvm::RISCVInstrInfo::hasReassociableSibling(), and isReassociationCandidate().
◆ hasStoreToStackSlot()
|
virtual |
If the specified machine instruction has a store to a stack slot, return true along with the FrameIndices of the loaded stack slot and the machine mem operands containing the reference.
If not, return false. Unlike isStoreToStackSlot, this returns true for any instructions that stores to the stack. This is just a hint, as some cases may be missed.
Definition at line 410 of file TargetInstrInfo.cpp.
References Accesses, llvm::isa_and_nonnull(), and MI.
Referenced by llvm::HexagonInstrInfo::hasStoreToStackSlot().
◆ insertBranch()
|
inlinevirtual |
Insert branch code into the end of the specified MachineBasicBlock.
The operands to this method are the same as those returned by analyzeBranch. This is only invoked in cases where analyzeBranch returns success. It returns the number of instructions inserted. If BytesAdded is non-null, report the change in code size from the added instructions.
It is also invoked by tail merging to add unconditional branches in cases where analyzeBranch doesn't apply because there was no original branch to analyze. At least this much must be implemented, else tail merging needs to be disabled.
The CFG information in MBB.Predecessors and MBB.Successors must be valid before calling this function.
Definition at line 764 of file TargetInstrInfo.h.
References Cond, DL, llvm_unreachable, MBB, and TBB.
Referenced by insertUnconditionalBranch(), and ReplaceTailWithBranchTo().
◆ insertIndirectBranch()
|
inlinevirtual |
Insert an unconditional indirect branch at the end of MBB to NewDestBB.
Optionally, insert the clobbered register restoring in RestoreBB. BrOffset indicates the offset of NewDestBB relative to the offset of the position to insert the new branch.
Definition at line 658 of file TargetInstrInfo.h.
References DL, llvm_unreachable, and MBB.
◆ insertNoop()
|
virtual |
Insert a noop into the instruction stream at the specified point.
insertNoop - Insert a noop into the instruction stream at the specified point.
Definition at line 84 of file TargetInstrInfo.cpp.
References llvm_unreachable, MBB, and MI.
Referenced by llvm::avoidZeroOffsetLandingPad(), and insertNoops().
◆ insertNoops()
|
virtual |
Insert noops into the instruction stream at the specified point.
insertNoops - Insert noops into the instruction stream at the specified point.
Definition at line 91 of file TargetInstrInfo.cpp.
References insertNoop(), MBB, and MI.
◆ insertOutlinedCall()
|
inlinevirtual |
Insert a call to an outlined function into the program.
Returns an iterator to the spot where we inserted the call. This must be implemented by the target.
Definition at line 2242 of file TargetInstrInfo.h.
References llvm::CallingConv::C, llvm_unreachable, and MBB.
◆ insertSelect()
|
inlinevirtual |
Insert a select instruction into MBB before I that will copy TrueReg to DstReg when Cond is true, and FalseReg to DstReg when Cond is false.
This function can only be called after canInsertSelect() returned true. The condition in Cond comes from analyzeBranch, and it can be assumed that the same flags or registers required by Cond are available at the insertion point.
- Parameters
-
MBB Block where select instruction should be inserted. I Insertion point. DL Source location for debugging. DstReg Virtual register to be defined by select instruction. Cond Condition as computed by analyzeBranch. TrueReg Virtual register to copy when Cond is true. FalseReg Virtual register to copy when Cons is false.
Definition at line 1000 of file TargetInstrInfo.h.
References Cond, DL, I, llvm_unreachable, and MBB.
◆ insertUnconditionalBranch()
|
inline |
Definition at line 772 of file TargetInstrInfo.h.
References DL, insertBranch(), and MBB.
◆ isAccumulationOpcode()
Return true when \P OpCode is an instruction which performs accumulation into one of its operand registers.
Definition at line 1322 of file TargetInstrInfo.h.
Referenced by getAccumulatorReassociationPatterns().
◆ isAddImmediate()
|
inlinevirtual |
If the specific machine instruction is an instruction that adds an immediate value and a register, and stores the result in the given register Reg, return a pair of the source register and the offset which has been added.
Definition at line 1155 of file TargetInstrInfo.h.
Referenced by describeLoadedValue().
◆ isAsCheapAsAMove()
|
inlinevirtual |
Return true if the instruction is as cheap as a move instruction.
Targets for different archs need to override this, and different micro-architectures can also be finely tuned inside.
Definition at line 419 of file TargetInstrInfo.h.
References MI.
◆ isAssociativeAndCommutative()
|
inlinevirtual |
Return true when \P Inst is both associative and commutative.
If \P Invert is true, then the inverse of \P Inst operation must be tested.
Definition at line 1305 of file TargetInstrInfo.h.
Referenced by getReassociationOpcodes(), hasReassociableSibling(), and isReassociationCandidate().
◆ isBasicBlockPrologue()
|
inlinevirtual |
True if the instruction is bound to the top of its basic block and no other instructions shall be inserted before it.
This can be implemented to prevent register allocator to insert spills for Reg before such instructions.
Definition at line 2138 of file TargetInstrInfo.h.
◆ isBranchOffsetInRange()
|
inlinevirtual |
- Returns
- true if a branch from an instruction with opcode
BranchOpcbytes is capable of jumping to a positionBrOffsetbytes away.
Definition at line 644 of file TargetInstrInfo.h.
References llvm_unreachable.
◆ isCoalescableExtInstr()
|
inlinevirtual |
Return true if the instruction is a "coalescable" extension instruction.
That is, it's like a copy where it's legal for the source to overlap the destination. e.g. X86::MOVSX64rr32. If this returns true, then it's expected the pre-extension value is available as a subreg of the result register. This also returns the sub-register index in SubIdx.
Definition at line 297 of file TargetInstrInfo.h.
References MI.
◆ isCopyInstr()
|
inline |
If the specific machine instruction is a instruction that moves/copies value from one register to another register return destination and source registers as machine operands.
For COPY-instruction the method naturally returns destination and source registers as machine operands, for all other instructions the method calls target-dependent implementation.
Definition at line 1126 of file TargetInstrInfo.h.
References isCopyInstrImpl(), and MI.
Referenced by describeLoadedValue(), foldMemoryOperand(), isCopyLikeInstr(), and isFullCopyInstr().
◆ isCopyInstrImpl()
|
inlineprotectedvirtual |
Target-dependent implementation for IsCopyInstr.
If the specific machine instruction is a instruction that moves/copies value from one register to another register return destination and source registers as machine operands.
Definition at line 1099 of file TargetInstrInfo.h.
References MI.
Referenced by isCopyInstr().
◆ isCopyLikeInstr()
|
inline |
Definition at line 1135 of file TargetInstrInfo.h.
References isCopyInstr(), isCopyLikeInstrImpl(), and MI.
◆ isCopyLikeInstrImpl()
|
inlineprotectedvirtual |
◆ isExplicitTargetIndexDef()
|
inlinevirtual |
Returns true if the given MI defines a TargetIndex operand that can be tracked by their offset, can have values, and can have debug info associated with it.
If so, sets Index and Offset of the target index operand.
Definition at line 2340 of file TargetInstrInfo.h.
References MI, and llvm::Offset.
◆ isExtendLikelyToBeFolded()
|
inlinevirtual |
Given the generic extension instruction ExtMI, returns true if this extension is a likely candidate for being folded into an another instruction.
Definition at line 2299 of file TargetInstrInfo.h.
References MRI.
◆ isFrameInstr()
|
inline |
Returns true if the argument is a frame pseudo instruction.
Definition at line 247 of file TargetInstrInfo.h.
References getCallFrameDestroyOpcode(), getCallFrameSetupOpcode(), and I.
Referenced by getFrameSize(), and getSPAdjust().
◆ isFrameSetup()
|
inline |
Returns true if the argument is a frame setup pseudo instruction.
Definition at line 253 of file TargetInstrInfo.h.
References getCallFrameSetupOpcode(), and I.
Referenced by getFrameTotalSize().
◆ isFullCopyInstr()
|
inline |
Definition at line 1141 of file TargetInstrInfo.h.
References llvm::MachineOperand::getSubReg(), isCopyInstr(), and MI.
◆ isFunctionSafeToOutlineFrom()
|
inlinevirtual |
Return true if the function can safely be outlined from.
A function MF is considered safe for outlining if an outlined function produced from instructions in F will produce a program which produces the same output for any set of given inputs.
Definition at line 2268 of file TargetInstrInfo.h.
References llvm_unreachable.
◆ isFunctionSafeToSplit()
|
virtual |
Return true if the function is a viable candidate for machine function splitting.
The criteria for if a function can be split may vary by target.
Definition at line 1849 of file TargetInstrInfo.cpp.
References llvm::MachineFunction::getFunction(), llvm::GlobalObject::getSectionPrefix(), and llvm::GlobalObject::hasSection().
◆ isGenericAtomicRMWOpcode()
Definition at line 138 of file TargetInstrInfo.h.
References Opc.
◆ isGenericOpcode()
Definition at line 134 of file TargetInstrInfo.h.
References Opc.
◆ isGlobalMemoryObject()
|
virtual |
Returns true if MI is an instruction we are unable to reason about (like a call or something with unmodeled side effects).
Definition at line 2239 of file TargetInstrInfo.cpp.
References MI.
Referenced by llvm::SIInstrInfo::isGlobalMemoryObject().
◆ isHighLatencyDef()
|
inlinevirtual |
Return true if this opcode has high latency to its result.
Definition at line 1887 of file TargetInstrInfo.h.
Referenced by defaultDefLatency().
◆ isIgnorableUse()
|
inlinevirtual |
Given MO is a PhysReg use return if it can be ignored for the purpose of instruction rematerialization or sinking.
Definition at line 179 of file TargetInstrInfo.h.
◆ isLegalToSplitMBBAt()
|
inlinevirtual |
Return true if it's legal to split the given basic block at the specified instruction (i.e.
instruction would be the start of a new basic block).
Definition at line 888 of file TargetInstrInfo.h.
◆ isLoadFromStackSlot() [1/2]
|
inlinevirtual |
If the specified machine instruction is a direct load from a stack slot, return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot.
If not, return 0. This predicate must return 0 if the instruction has any side effects other than loading from the stack slot.
Definition at line 307 of file TargetInstrInfo.h.
References MI.
Referenced by foldMemoryOperand(), isLoadFromStackSlot(), and isReallyTriviallyReMaterializable().
◆ isLoadFromStackSlot() [2/2]
|
inlinevirtual |
Optional extension of isLoadFromStackSlot that returns the number of bytes loaded from the stack.
This must be implemented if a backend supports partial stack slot spills/loads to further disambiguate what the load does.
Definition at line 316 of file TargetInstrInfo.h.
References llvm::TypeSize::getZero(), isLoadFromStackSlot(), and MI.
◆ isLoadFromStackSlotPostFE()
|
inlinevirtual |
Check for post-frame ptr elimination stack locations as well.
This uses a heuristic so it isn't reliable for correctness.
Definition at line 325 of file TargetInstrInfo.h.
References MI.
◆ isMBBSafeToOutlineFrom()
|
virtual |
Optional target hook that returns true if MBB is safe to outline from, and returns any target-specific information in Flags.
Definition at line 2211 of file TargetInstrInfo.cpp.
References llvm::First, llvm::Last, and MBB.
Referenced by llvm::RISCVInstrInfo::isMBBSafeToOutlineFrom().
◆ isMBBSafeToSplitToCold()
|
inlinevirtual |
Return true if the MachineBasicBlock can safely be split to the cold section.
On AArch64, certain instructions may cause a block to be unsafe to split to the cold section.
Definition at line 2286 of file TargetInstrInfo.h.
References MBB.
◆ isPCRelRegisterOperandLegal()
|
inlinevirtual |
Allow targets to tell MachineVerifier whether a specific register MachineOperand can be used as part of PC-relative addressing.
PC-relative addressing modes in many CISC architectures contain (non-PC) registers as offsets or scaling values, which inherently tags the corresponding MachineOperand with OPERAND_PCREL.
- Parameters
-
MO The MachineOperand in question. MO.isReg() should always be true.
- Returns
- Whether this operand is allowed to be used PC-relatively.
Definition at line 1085 of file TargetInstrInfo.h.
◆ isPostIncrement()
|
inlinevirtual |
Return true for post-incremented instructions.
Definition at line 1676 of file TargetInstrInfo.h.
References MI.
◆ isPredicable()
|
inlinevirtual |
Return true if the specified instruction can be predicated.
By default, this returns true for every instruction with a PredicateOperand.
Definition at line 1743 of file TargetInstrInfo.h.
References MI.
Referenced by llvm::R600InstrInfo::isPredicable().
◆ isPredicated()
|
inlinevirtual |
Returns true if the instruction is already predicated.
Definition at line 1679 of file TargetInstrInfo.h.
References MI.
Referenced by canPredicatePredicatedInstr(), getOutliningType(), and isUnpredicatedTerminator().
◆ isProfitableToDupForIfCvt()
|
inlinevirtual |
Return true if it's profitable for if-converter to duplicate instructions of specified accumulated instruction latencies in the specified MBB to enable if-conversion.
The probability of the instructions being executed is given by Probability, and Confidence is a measure of our confidence that it will be properly predicted.
Definition at line 924 of file TargetInstrInfo.h.
References MBB.
◆ isProfitableToIfCvt() [1/2]
|
inlinevirtual |
Return true if it's profitable to predicate instructions with accumulated instruction latency of "NumCycles" of the specified basic block, where the probability of the instructions being executed is given by Probability, and Confidence is a measure of our confidence that it will be properly predicted.
Definition at line 898 of file TargetInstrInfo.h.
References MBB.
◆ isProfitableToIfCvt() [2/2]
|
inlinevirtual |
Second variant of isProfitableToIfCvt.
This one checks for the case where two basic blocks from true and false path of a if-then-else (diamond) are predicated on mutually exclusive predicates, where the probability of the true path being taken is given by Probability, and Confidence is a measure of our confidence that it will be properly predicted.
Definition at line 910 of file TargetInstrInfo.h.
◆ isProfitableToUnpredicate()
|
inlinevirtual |
Return true if it's profitable to unpredicate one side of a 'diamond', i.e.
two sides of if-else predicated on mutually exclusive predicates. e.g. subeq r0, r1, #1 addne r0, r1, #1 => sub r0, r1, #1 addne r0, r1, #1
This may be profitable is conditional instructions are always executed.
Definition at line 954 of file TargetInstrInfo.h.
◆ isReallyTriviallyReMaterializable()
|
protectedvirtual |
For instructions with opcodes for which the M_REMATERIALIZABLE flag is set, this hook lets the target specify whether the instruction is actually trivially rematerializable, taking into consideration its operands.
This predicate must return false if the instruction has any side effects other than producing a value, or if it requres any address registers that are not always available.
Definition at line 1593 of file TargetInstrInfo.cpp.
References llvm::MachineFunction::getFrameInfo(), llvm::MachineFunction::getRegInfo(), llvm::MachineFrameInfo::isImmutableObjectIndex(), isLoadFromStackSlot(), llvm::Register::isVirtual(), MI, and MRI.
Referenced by llvm::PPCInstrInfo::isReallyTriviallyReMaterializable(), llvm::RISCVInstrInfo::isReallyTriviallyReMaterializable(), llvm::SIInstrInfo::isReallyTriviallyReMaterializable(), llvm::WebAssemblyInstrInfo::isReallyTriviallyReMaterializable(), llvm::X86InstrInfo::isReallyTriviallyReMaterializable(), and isTriviallyReMaterializable().
◆ isReassociationCandidate()
| bool TargetInstrInfo::isReassociationCandidate | ( | const MachineInstr & | Inst, |
| bool & | Commuted ) const |
Return true if the input \P Inst is part of a chain of dependent ops that are suitable for reassociation, otherwise return false.
If the instruction's operands must be commuted to have a previous instruction of the same type define the first source operand, \P Commuted will be set to true.
Definition at line 977 of file TargetInstrInfo.cpp.
References llvm::MachineInstr::getParent(), hasReassociableOperands(), hasReassociableSibling(), and isAssociativeAndCommutative().
Referenced by getMachineCombinerPatterns().
◆ isSafeToMoveRegClassDefs()
|
inlinevirtual |
Return true if it's safe to move a machine instruction that defines the specified register class.
Definition at line 1749 of file TargetInstrInfo.h.
◆ isSafeToSink()
|
inlinevirtual |
Definition at line 183 of file TargetInstrInfo.h.
References MI.
◆ isSchedulingBoundary()
|
virtual |
Test if the given instruction should be considered a scheduling boundary.
isSchedulingBoundary - Test if the given instruction should be considered a scheduling boundary.
This primarily includes labels and terminators.
Definition at line 1696 of file TargetInstrInfo.cpp.
References llvm::TargetSubtargetInfo::getRegisterInfo(), llvm::TargetLoweringBase::getStackPointerRegisterToSaveRestore(), llvm::MachineFunction::getSubtarget(), llvm::TargetSubtargetInfo::getTargetLowering(), MBB, MI, and TRI.
Referenced by llvm::AArch64InstrInfo::isSchedulingBoundary(), llvm::LoongArchInstrInfo::isSchedulingBoundary(), llvm::PPCInstrInfo::isSchedulingBoundary(), and llvm::X86InstrInfo::isSchedulingBoundary().
◆ isStackSlotCopy()
|
inlinevirtual |
Return true if the specified machine instruction is a copy of one stack slot to another and has no other effect.
Provide the identity of the two frame indices.
Definition at line 381 of file TargetInstrInfo.h.
References MI.
◆ isStoreToStackSlot() [1/2]
|
inlinevirtual |
If the specified machine instruction is a direct store to a stack slot, return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot.
If not, return 0. This predicate must return 0 if the instruction has any side effects other than storing to the stack slot.
Definition at line 345 of file TargetInstrInfo.h.
References MI.
Referenced by isStoreToStackSlot().
◆ isStoreToStackSlot() [2/2]
|
inlinevirtual |
Optional extension of isStoreToStackSlot that returns the number of bytes stored to the stack.
This must be implemented if a backend supports partial stack slot spills/loads to further disambiguate what the store does.
Definition at line 354 of file TargetInstrInfo.h.
References llvm::TypeSize::getZero(), isStoreToStackSlot(), and MI.
◆ isStoreToStackSlotPostFE()
|
inlinevirtual |
Check for post-frame ptr elimination stack locations as well.
This uses a heuristic, so it isn't reliable for correctness.
Definition at line 363 of file TargetInstrInfo.h.
References MI.
◆ isSubregFoldable()
|
inlinevirtual |
Check whether the target can fold a load that feeds a subreg operand (or a subreg operand that feeds a store).
For example, X86 may want to return true if it can fold movl (esp), eax subb, al, ... Into: subb (esp), ...
Ideally, we'd like the target implementation of foldMemoryOperand() to reject subregs - but since this behavior used to be enforced in the target-independent code, moving this responsibility to the targets has the potential of causing nasty silent breakage in out-of-tree targets.
Definition at line 1228 of file TargetInstrInfo.h.
◆ isTailCall()
|
inlinevirtual |
Determines whether Inst is a tail call instruction.
Override this method on targets that do not properly set MCID::Return and MCID::Call on tail call instructions."
Definition at line 2130 of file TargetInstrInfo.h.
References llvm::MachineInstr::isCall(), and llvm::MachineInstr::isReturn().
◆ isThroughputPattern()
Return true when a code sequence can improve throughput.
Return true when a code sequence can improve loop throughput.
It should be called only for instructions in loops.
- Parameters
-
Pattern - combiner pattern
Definition at line 1179 of file TargetInstrInfo.cpp.
◆ isTriviallyReMaterializable()
|
inline |
Return true if the instruction is trivially rematerializable, meaning it has no side effects and requires no operands that aren't always available.
This means the only allowed uses are constants and unallocatable physical registers so that the instructions result is independent of the place in the function.
Definition at line 170 of file TargetInstrInfo.h.
References isReallyTriviallyReMaterializable(), and MI.
Referenced by llvm::calculateRegAllocScore().
◆ isUnconditionalTailCall()
|
inlinevirtual |
Returns true if MI is an unconditional tail call.
Definition at line 1698 of file TargetInstrInfo.h.
References MI.
◆ isUnpredicatedTerminator()
| bool TargetInstrInfo::isUnpredicatedTerminator | ( | const MachineInstr & | MI | ) | const |
Returns true if the instruction is a terminator instruction that has not been predicated.
Definition at line 355 of file TargetInstrInfo.cpp.
References isPredicated(), and MI.
◆ isUnspillableTerminator()
|
inline |
Return true if the given instruction is terminator that is unspillable, according to isUnspillableTerminatorImpl.
Definition at line 405 of file TargetInstrInfo.h.
References isUnspillableTerminatorImpl(), and MI.
◆ isUnspillableTerminatorImpl()
|
inlineprotectedvirtual |
Return true if the given terminator MI is not expected to spill.
This sets the live interval as not spillable and adjusts phi node lowering to not introduce copies after the terminator. Use with care, these are currently used for hardware loop intrinsics in very controlled situations, created prior to registry allocation in loops that only have single phi users for the terminators value. They may run out of registers if not used carefully.
Definition at line 1115 of file TargetInstrInfo.h.
References MI.
Referenced by isUnspillableTerminator().
◆ isZeroCost()
Return true for pseudo instructions that don't consume any machine resources in their current form.
These are common cases that the scheduler should consider free, rather than conservatively handling them as instructions with no itinerary.
Definition at line 1849 of file TargetInstrInfo.h.
◆ loadRegFromStackSlot()
|
inlinevirtual |
Load the specified register of the given register class from the specified stack frame index.
The load instruction is to be added to the given machine basic block before the specified machine instruction. If DestReg is being directly reloaded as part of assigning a virtual register, VReg is the register being assigned. This additional register argument is needed for certain targets when invoked from RegAllocFast to map the loaded physical register to its virtual register. A null register can be passed elsewhere. The Flags is used to set appropriate machine flags on the spill instruction e.g. FrameDestroy flag on a callee saved register reload instruction, part of epilogue, during the frame lowering.
Definition at line 1199 of file TargetInstrInfo.h.
References llvm_unreachable, MBB, MI, llvm::MachineInstr::NoFlags, and TRI.
Referenced by foldMemoryOperand().
◆ lowerCopy()
| void TargetInstrInfo::lowerCopy | ( | MachineInstr * | MI, |
| const TargetRegisterInfo * | TRI ) const |
This function defines the logic to lower COPY instruction to target specific instruction(s).
Definition at line 883 of file TargetInstrInfo.cpp.
References copyPhysReg(), llvm::MCInstrInfo::get(), llvm::MachineOperand::getReg(), llvm::MachineOperand::isKill(), llvm::Register::isPhysical(), llvm::MachineOperand::isRenamable(), llvm::MachineOperand::isUndef(), MI, transferImplicitOperands(), and TRI.
◆ mergeOutliningCandidateAttributes()
|
virtual |
Optional target hook to create the LLVM IR attributes for the outlined function.
If overridden, the overriding function must call the default implementation.
Definition at line 2112 of file TargetInstrInfo.cpp.
References llvm::all_of(), llvm::CallingConv::C, F, llvm::Function::getFnAttribute(), llvm::MachineFunction::getFunction(), llvm::outliner::Candidate::getMF(), and llvm::Function::hasFnAttribute().
◆ operator=()
|
delete |
References TargetInstrInfo().
◆ optimizeCompareInstr()
|
inlinevirtual |
See if the comparison instruction can be converted into something more efficient.
E.g., on ARM most instructions can set the flags register, obviating the need for a separate CMP.
Definition at line 1807 of file TargetInstrInfo.h.
References MRI.
◆ optimizeCondBranch()
|
inlinevirtual |
Definition at line 1813 of file TargetInstrInfo.h.
References MI.
◆ optimizeLoadInstr()
|
virtual |
Try to remove the load by folding it to a register operand at the use.
We fold the load instructions if and only if the def and use are in the same BB. We only look at one load and see whether it can be folded into MI. FoldAsLoadDefReg is the virtual register defined by the load we are trying to fold. DefMI returns the machine instruction that defines FoldAsLoadDefReg, and the function returns the machine instruction generated due to folding.
We fold the load instructions if load defines a virtual register, the virtual register is used once in the same BB, and the instructions in-between do not load or store, and have no side effects.
Definition at line 525 of file TargetInstrInfo.cpp.
References assert(), DefMI, llvm::SmallVectorTemplateCommon< T, typename >::empty(), foldMemoryOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::getSubReg(), llvm::MachineOperand::isDef(), llvm::MachineOperand::isReg(), MI, MRI, and llvm::SmallVectorTemplateBase< T, bool >::push_back().
◆ optimizeSelect()
|
inlinevirtual |
Given a select instruction that was understood by analyzeSelect and returned Optimizable = true, attempt to optimize MI by merging it with one of its operands.
Returns NULL on failure.
When successful, returns the new select instruction. The client is responsible for deleting MI.
If both sides of the select can be optimized, PreferFalse is used to pick a side.
- Parameters
-
MI Optimizable select instruction. NewMIs Set that record all MIs in the basic block up to MI. Has to be updated with any newly created MI or deleted ones.PreferFalse Try to optimize FalseOp instead of TrueOp.
- Returns
- Optimized instruction or NULL.
Definition at line 1048 of file TargetInstrInfo.h.
References llvm_unreachable, and MI.
◆ PredicateInstruction()
|
virtual |
Convert the instruction into a predicated instruction.
It returns true if the operation was successful.
Definition at line 366 of file TargetInstrInfo.cpp.
References assert(), llvm::getImm(), getReg(), llvm::MachineOperand::isImm(), llvm::MachineOperand::isMBB(), llvm::MachineOperand::isReg(), MI, llvm::MachineOperand::setImm(), llvm::MachineOperand::setMBB(), and llvm::MachineOperand::setReg().
◆ predictBranchSizeForIfCvt()
|
inlinevirtual |
Return an estimate for the code size reduction (in bytes) which will be caused by removing the given branch instruction during if-conversion.
Definition at line 939 of file TargetInstrInfo.h.
References getInstSizeInBytes(), and MI.
◆ preservesZeroValueInReg()
|
inlinevirtual |
Returns true if MI's Def is NullValueReg, and the MI does not change the Zero value.
i.e. cases such as rax = shr rax, X where NullValueReg = rax. Note that if the NullValueReg is non-zero, this function can return true even if becomes zero. Specifically cases such as NullValueReg = shl NullValueReg, 63.
Definition at line 1620 of file TargetInstrInfo.h.
◆ produceSameValue()
|
virtual |
Return true if two machine instructions would produce identical values.
By default, this is only true when the two instructions are deemed identical except for defs. If this function is called when the IR is still in SSA form, the caller can pass the MachineRegisterInfo for aggressive checks.
Definition at line 464 of file TargetInstrInfo.cpp.
References llvm::MachineInstr::IgnoreVRegDefs, llvm::MachineInstr::isIdenticalTo(), and MRI.
◆ reassociateOps()
| void TargetInstrInfo::reassociateOps | ( | MachineInstr & | Root, |
| MachineInstr & | Prev, | ||
| unsigned | Pattern, | ||
| SmallVectorImpl< MachineInstr * > & | InsInstrs, | ||
| SmallVectorImpl< MachineInstr * > & | DelInstrs, | ||
| ArrayRef< unsigned > | OperandIndices, | ||
| DenseMap< Register, unsigned > & | InstrIdxForVirtReg ) const |
Attempt to reassociate \P Root and \P Prev according to \P Pattern to reduce critical path length.
Attempt the reassociation transformation to reduce critical path length.
See the above comments before getMachineCombinerPatterns().
Definition at line 1321 of file TargetInstrInfo.cpp.
References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addReg(), llvm::MachineInstr::clearFlag(), llvm::MachineInstrBuilder::copyImplicitOps(), llvm::MachineInstrBuilder::copyMIMetadata(), llvm::RegState::Define, llvm::MachineInstr::Disjoint, llvm::MachineInstr::explicit_operands(), llvm::MachineInstr::getFlags(), llvm::MachineInstrBuilder::getInstr(), llvm::TargetSubtargetInfo::getInstrInfo(), llvm::getKillRegState(), llvm::MachineInstr::getMF(), llvm::MachineInstr::getOperand(), getReassociationOpcodes(), llvm::MachineOperand::getReg(), llvm::MachineInstr::getRegClassConstraint(), llvm::MachineFunction::getRegInfo(), llvm::TargetSubtargetInfo::getRegisterInfo(), llvm::MachineFunction::getSubtarget(), llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::insert(), llvm::MachineInstr::IsExact, llvm::MachineOperand::isKill(), llvm::Register::isVirtual(), llvm_unreachable, MRI, mustSwapOperands(), llvm::MachineInstr::NoSWrap, llvm::MachineInstr::NoUWrap, llvm::MachineInstr::peekDebugInstrNum(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::REASSOC_AX_BY, llvm::REASSOC_AX_YB, llvm::REASSOC_XA_BY, llvm::REASSOC_XA_YB, llvm::MachineInstr::setDebugInstrNum(), llvm::MachineInstr::setFlags(), setSpecialOperandAttr(), std::swap(), TargetInstrInfo(), TII, and TRI.
Referenced by genAlternativeCodeSequence().
◆ reduceAccumulatorTree()
| void TargetInstrInfo::reduceAccumulatorTree | ( | SmallVectorImpl< Register > & | RegistersToReduce, |
| SmallVectorImpl< MachineInstr * > & | InsInstrs, | ||
| MachineFunction & | MF, | ||
| MachineInstr & | Root, | ||
| MachineRegisterInfo & | MRI, | ||
| DenseMap< Register, unsigned > & | InstrIdxForVirtReg, | ||
| Register | ResultReg ) const |
Reduces branches of the accumulator tree into a single register.
Definition at line 1086 of file TargetInstrInfo.cpp.
References llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::MachineInstr::getFlags(), llvm::TargetSubtargetInfo::getInstrInfo(), llvm::getKillRegState(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), getReduceOpcodeForAccumulator(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getSubtarget(), llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::insert(), MRI, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::MachineInstr::setFlags(), llvm::SmallVectorTemplateCommon< T, typename >::size(), TargetInstrInfo(), and TII.
Referenced by genAlternativeCodeSequence().
◆ reduceLoopCount()
|
inlinevirtual |
Generate code to reduce the loop iteration by one and check if the loop is finished.
Return the value/register of the new loop count. We need this function when peeling off one or more iterations of a loop. This function assumes the nth iteration is peeled first.
Definition at line 871 of file TargetInstrInfo.h.
References Cond, llvm_unreachable, and MBB.
◆ reMaterialize()
|
virtual |
Re-issue the specified 'original' instruction at the specific location targeting a new destination register.
The register in Orig->getOperand(0).getReg() will be substituted by DestReg:SubIdx. Any existing subreg index is preserved or composed with SubIdx.
Definition at line 454 of file TargetInstrInfo.cpp.
References I, MBB, MI, and TRI.
Referenced by llvm::SIInstrInfo::reMaterialize().
◆ removeBranch()
|
inlinevirtual |
Remove the branching code at the end of the specific MBB.
This is only invoked in cases where analyzeBranch returns success. It returns the number of instructions that were removed. If BytesRemoved is non-null, report the change in code size from the removed instructions.
Definition at line 746 of file TargetInstrInfo.h.
References llvm_unreachable, and MBB.
◆ replaceBranchWithTailCall()
|
inlinevirtual |
Replace the conditional branch in MBB with a conditional tail call.
Definition at line 1709 of file TargetInstrInfo.h.
References Cond, llvm_unreachable, and MBB.
◆ ReplaceTailWithBranchTo()
|
virtual |
Delete the instruction OldInst and everything after it, replacing it with an unconditional branch to NewDest.
ReplaceTailWithBranchTo - Delete the instruction OldInst and everything after it, replacing it with an unconditional branch to NewDest.
This is used by the tail merging pass.
Definition at line 158 of file TargetInstrInfo.cpp.
References DL, insertBranch(), MBB, MI, and llvm::CallingConv::Tail.
Referenced by llvm::Thumb2InstrInfo::ReplaceTailWithBranchTo().
◆ reverseBranchCondition()
|
inlinevirtual |
Reverses the branch condition of the specified condition list, returning false on success and true if it cannot be reversed.
Definition at line 1659 of file TargetInstrInfo.h.
References Cond.
◆ setExecutionDomain()
|
inlinevirtual |
Change the opcode of MI to execute in Domain.
The bit (1 << Domain) must be set in the mask returned from getExecutionDomain(MI).
Definition at line 1942 of file TargetInstrInfo.h.
References MI.
◆ setSpecialOperandAttr()
|
inlinevirtual |
This is an architecture-specific helper function of reassociateOps.
Set special operand attributes for new instructions after reassociation.
Definition at line 1414 of file TargetInstrInfo.h.
Referenced by reassociateOps().
◆ shouldBreakCriticalEdgeToSink()
|
inlinevirtual |
For a "cheap" instruction which doesn't enable additional sinking, should MachineSink break a critical edge to sink it anyways?
Definition at line 190 of file TargetInstrInfo.h.
References MI.
◆ shouldClusterMemOps()
|
inlinevirtual |
Returns true if the two given memory operations should be scheduled adjacent.
Note that you have to add: DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI)); or DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI)); to TargetMachine::createMachineScheduler() to have an effect.
BaseOps1 and BaseOps2 are memory operands of two memory operations. Offset1 and Offset2 are the byte offsets for the memory operations. OffsetIsScalable1 and OffsetIsScalable2 indicate if the offset is scaled by a runtime quantity. ClusterSize is the number of operations in the resulting load/store cluster if this hook returns true. NumBytes is the number of bytes that will be loaded from all the clustered loads if this hook returns true.
Definition at line 1647 of file TargetInstrInfo.h.
References llvm_unreachable.
◆ shouldHoist()
|
inlinevirtual |
Return false if the instruction should not be hoisted by MachineLICM.
MachineLICM determines on its own whether the instruction is safe to hoist; this gives the target a hook to extend this assessment and prevent an instruction being hoisted from a given loop for target specific reasons.
Definition at line 436 of file TargetInstrInfo.h.
References MI.
◆ shouldOutlineFromFunctionByDefault()
|
inlinevirtual |
Return true if the function should be outlined from by default.
Definition at line 2275 of file TargetInstrInfo.h.
◆ shouldReduceRegisterPressure()
|
inlinevirtual |
Return true if target supports reassociation of instructions in machine combiner pass to reduce register pressure for a given BB.
Definition at line 1277 of file TargetInstrInfo.h.
References MBB.
◆ shouldScheduleLoadsNear()
|
inlinevirtual |
This is a used by the pre-regalloc scheduler to determine (in conjunction with areLoadsFromSameBasePtr) if two loads should be scheduled together.
On some targets if two loads are loading from addresses in the same cache line, it's better if they are scheduled together. This function takes two integers that represent the load offsets from the common base address. It returns true if it decides it's desirable to schedule the two loads together. "NumLoads" is the number of loads that have already been scheduled after Load1.
Definition at line 1544 of file TargetInstrInfo.h.
◆ shouldSink()
|
inlinevirtual |
Return true if the instruction should be sunk by MachineSink.
MachineSink determines on its own whether the instruction is safe to sink; this gives the target a hook to override the default behavior with regards to which instructions should be sunk.
Definition at line 428 of file TargetInstrInfo.h.
References MI.
◆ simplifyInstruction()
|
inlinevirtual |
If possible, converts the instruction to a simplified/canonical form.
Returns true if the instruction was modified.
This function is only called after register allocation. The MI will be modified in place. This is called by passes such as MachineCopyPropagation, where their mutation of the MI operands may expose opportunities to convert the instruction to a simpler form (e.g. a load of 0).
Definition at line 542 of file TargetInstrInfo.h.
References MI.
◆ storeRegToStackSlot()
|
inlinevirtual |
Store the specified register of the given register class to the specified stack frame index.
The store instruction is to be added to the given machine basic block before the specified machine instruction. If isKill is true, the register operand is the last use and must be marked kill. If SrcReg is being directly spilled as part of assigning a virtual register, VReg is the register being assigned. This additional register argument is needed for certain targets when invoked from RegAllocFast to map the spilled physical register to its virtual register. A null register can be passed elsewhere. The Flags is used to set appropriate machine flags on the spill instruction e.g. FrameSetup flag on a callee saved register spill instruction, part of prologue, during the frame lowering.
Definition at line 1180 of file TargetInstrInfo.h.
References llvm_unreachable, MBB, MI, llvm::MachineInstr::NoFlags, and TRI.
Referenced by foldMemoryOperand().
◆ SubsumesPredicate()
|
inlinevirtual |
Returns true if the first specified predicate subsumes the second, e.g.
GE subsumes GT.
Definition at line 1722 of file TargetInstrInfo.h.
◆ unfoldMemoryOperand() [1/2]
|
inlinevirtual |
unfoldMemoryOperand - Separate a single instruction which folded a load or a store or a load and a store into two or more instruction.
If this is possible, returns true as well as the new instructions by reference.
Definition at line 1503 of file TargetInstrInfo.h.
◆ unfoldMemoryOperand() [2/2]
|
inlinevirtual |
Definition at line 1509 of file TargetInstrInfo.h.
References N.
◆ useMachineCombiner()
|
inlinevirtual |
Return true when a target supports MachineCombiner.
Definition at line 1419 of file TargetInstrInfo.h.
◆ usePreRAHazardRecognizer()
| bool TargetInstrInfo::usePreRAHazardRecognizer | ( | ) | const |
Provide a global flag for disabling the PreRA hazard recognizer that targets may choose to honor.
Definition at line 1719 of file TargetInstrInfo.cpp.
References DisableHazardRecognizer.
◆ verifyInstruction()
|
inlinevirtual |
Perform target-specific instruction verification.
Definition at line 1909 of file TargetInstrInfo.h.
References MI.
Member Data Documentation
◆ CommuteAnyOperandIndex
Definition at line 483 of file TargetInstrInfo.h.
Referenced by commuteInstruction(), and fixCommutedOpIndices().
◆ RegClassByHwMode
Subtarget specific sub-array of MCInstrInfo's RegClassByHwModeTables (i.e.
the table for the active HwMode). This should be indexed by MCOperandInfo's RegClass field for LookupRegClassByHwMode operands.
Definition at line 119 of file TargetInstrInfo.h.
Referenced by getOpRegClassID(), and TargetInstrInfo().
The documentation for this class was generated from the following files:
- include/llvm/CodeGen/TargetInstrInfo.h
- lib/CodeGen/TargetInstrInfo.cpp
Generated on for LLVM by
1.14.0