25#define GET_INSTRINFO_CTOR_DTOR
26#include "R600GenDFAPacketizer.inc"
28#define GET_INSTRINFO_CTOR_DTOR
29#define GET_INSTRMAP_INFO
30#define GET_INSTRINFO_NAMED_OPS
31#include "R600GenInstrInfo.inc"
44 unsigned VectorComponents = 0;
45 if ((R600::R600_Reg128RegClass.
contains(DestReg) ||
46 R600::R600_Reg128VerticalRegClass.
contains(DestReg)) &&
47 (R600::R600_Reg128RegClass.
contains(SrcReg) ||
48 R600::R600_Reg128VerticalRegClass.
contains(SrcReg))) {
50 }
else if((R600::R600_Reg64RegClass.
contains(DestReg) ||
51 R600::R600_Reg64VerticalRegClass.
contains(DestReg)) &&
52 (R600::R600_Reg64RegClass.
contains(SrcReg) ||
53 R600::R600_Reg64VerticalRegClass.
contains(SrcReg))) {
57 if (VectorComponents > 0) {
58 for (
unsigned I = 0;
I < VectorComponents;
I++) {
61 RI.getSubReg(DestReg, SubRegIndex),
62 RI.getSubReg(SrcReg, SubRegIndex))
78 E =
MBBI->operands_end();
I != E; ++
I) {
79 if (
I->isReg() && !
I->getReg().isVirtual() &&
I->isUse() &&
91 case R600::MOV_IMM_F32:
92 case R600::MOV_IMM_I32:
103 default:
return false;
104 case R600::CUBE_r600_pseudo:
105 case R600::CUBE_r600_real:
106 case R600::CUBE_eg_pseudo:
107 case R600::CUBE_eg_real:
113 unsigned TargetFlags =
get(Opcode).TSFlags;
119 unsigned TargetFlags =
get(Opcode).TSFlags;
127 unsigned TargetFlags =
get(Opcode).TSFlags;
143 switch (
MI.getOpcode()) {
145 case R600::INTERP_PAIR_XY:
146 case R600::INTERP_PAIR_ZW:
147 case R600::INTERP_VEC_LOAD:
159 return (
get(Opcode).getSchedClass() == R600::Sched::TransALU);
167 return (
get(Opcode).getSchedClass() == R600::Sched::VecALU);
202 case R600::GROUP_BARRIER:
210 return MI.findRegisterUseOperandIdx(R600::AR_X, &RI,
false) != -1;
214 return MI.findRegisterDefOperandIdx(R600::AR_X, &RI,
false,
false) != -1;
222 E =
MI.operands_end();
224 if (!
I->isReg() || !
I->isUse() ||
I->getReg().isVirtual())
227 if (R600::R600_LDS_SRC_REGRegClass.
contains(
I->getReg()))
234 static const unsigned SrcSelTable[][2] = {
235 {R600::OpName::src0, R600::OpName::src0_sel},
236 {R600::OpName::src1, R600::OpName::src1_sel},
237 {R600::OpName::src2, R600::OpName::src2_sel},
238 {R600::OpName::src0_X, R600::OpName::src0_sel_X},
239 {R600::OpName::src0_Y, R600::OpName::src0_sel_Y},
240 {R600::OpName::src0_Z, R600::OpName::src0_sel_Z},
241 {R600::OpName::src0_W, R600::OpName::src0_sel_W},
242 {R600::OpName::src1_X, R600::OpName::src1_sel_X},
243 {R600::OpName::src1_Y, R600::OpName::src1_sel_Y},
244 {R600::OpName::src1_Z, R600::OpName::src1_sel_Z},
245 {R600::OpName::src1_W, R600::OpName::src1_sel_W}
248 for (
const auto &Row : SrcSelTable) {
260 if (
MI.getOpcode() == R600::DOT_4) {
261 static const unsigned OpTable[8][2] = {
262 {R600::OpName::src0_X, R600::OpName::src0_sel_X},
263 {R600::OpName::src0_Y, R600::OpName::src0_sel_Y},
264 {R600::OpName::src0_Z, R600::OpName::src0_sel_Z},
265 {R600::OpName::src0_W, R600::OpName::src0_sel_W},
266 {R600::OpName::src1_X, R600::OpName::src1_sel_X},
267 {R600::OpName::src1_Y, R600::OpName::src1_sel_Y},
268 {R600::OpName::src1_Z, R600::OpName::src1_sel_Z},
269 {R600::OpName::src1_W, R600::OpName::src1_sel_W},
272 for (
const auto &
Op : OpTable) {
275 if (Reg == R600::ALU_CONST) {
278 Result.push_back(std::pair(&MO, Sel.
getImm()));
285 static const unsigned OpTable[3][2] = {
286 {R600::OpName::src0, R600::OpName::src0_sel},
287 {R600::OpName::src1, R600::OpName::src1_sel},
288 {R600::OpName::src2, R600::OpName::src2_sel},
291 for (
const auto &
Op : OpTable) {
297 if (Reg == R600::ALU_CONST) {
299 Result.push_back(std::pair(&MO, Sel.
getImm()));
302 if (Reg == R600::ALU_LITERAL_X) {
305 if (Operand.
isImm()) {
306 Result.push_back(std::pair(&MO, Operand.
getImm()));
311 Result.push_back(std::pair(&MO, 0));
316std::vector<std::pair<int, unsigned>>
319 unsigned &ConstCount)
const {
321 const std::pair<int, unsigned> DummyPair(-1, 0);
322 std::vector<std::pair<int, unsigned>> Result;
327 int Index = RI.getEncodingValue(Reg) & 0xff;
328 if (Reg == R600::OQAP) {
329 Result.emplace_back(
Index, 0U);
333 Result.emplace_back(255, 0U);
338 Result.push_back(DummyPair);
345 Result.push_back(DummyPair);
349static std::vector<std::pair<int, unsigned>>
350Swizzle(std::vector<std::pair<int, unsigned>> Src,
352 if (Src[0] == Src[1])
379 assert(
Op < 3 &&
"Out of range swizzle index");
382 unsigned Cycles[3] = { 2, 1, 0};
386 unsigned Cycles[3] = { 1, 2, 2};
390 unsigned Cycles[3] = { 2, 1, 2};
394 unsigned Cycles[3] = { 2, 2, 1};
406 const std::vector<std::vector<std::pair<int, unsigned>>> &IGSrcs,
407 const std::vector<R600InstrInfo::BankSwizzle> &Swz,
408 const std::vector<std::pair<int, unsigned>> &TransSrcs,
412 for (
unsigned i = 0, e = IGSrcs.size(); i < e; i++) {
413 const std::vector<std::pair<int, unsigned>> &Srcs =
415 for (
unsigned j = 0; j < 3; j++) {
416 const std::pair<int, unsigned> &Src = Srcs[j];
417 if (Src.first < 0 || Src.first == 255)
419 if (Src.first ==
GET_REG_INDEX(RI.getEncodingValue(R600::OQAP))) {
429 if (
Vector[Src.second][j] < 0)
430 Vector[Src.second][j] = Src.first;
431 if (
Vector[Src.second][j] != Src.first)
436 for (
unsigned i = 0, e = TransSrcs.size(); i < e; ++i) {
437 const std::pair<int, unsigned> &Src = TransSrcs[i];
441 if (Src.first == 255)
446 return IGSrcs.size() - 1;
448 return IGSrcs.size();
456 std::vector<R600InstrInfo::BankSwizzle> &SwzCandidate,
462 for (
unsigned i = ResetIdx + 1, e = SwzCandidate.size(); i < e; i++) {
467 int NextSwizzle = SwzCandidate[ResetIdx] + 1;
475 const std::vector<std::vector<std::pair<int, unsigned>>> &IGSrcs,
476 std::vector<R600InstrInfo::BankSwizzle> &SwzCandidate,
477 const std::vector<std::pair<int, unsigned>> &TransSrcs,
479 unsigned ValidUpTo = 0;
481 ValidUpTo =
isLegalUpTo(IGSrcs, SwzCandidate, TransSrcs, TransSwz);
482 if (ValidUpTo == IGSrcs.size())
492 const std::vector<std::pair<int, unsigned>> &TransOps,
493 unsigned ConstCount) {
497 for (
unsigned i = 0, e = TransOps.size(); i < e; ++i) {
498 const std::pair<int, unsigned> &Src = TransOps[i];
502 if (ConstCount > 0 &&
Cycle == 0)
504 if (ConstCount > 1 &&
Cycle == 1)
513 std::vector<BankSwizzle> &ValidSwizzle,
518 std::vector<std::vector<std::pair<int, unsigned>>> IGSrcs;
519 ValidSwizzle.clear();
523 IGSrcs.push_back(ExtractSrcs(*
MI, PV, ConstCount));
525 ValidSwizzle.push_back(
528 std::vector<std::pair<int, unsigned>> TransOps;
532 TransOps = std::move(IGSrcs.back());
534 ValidSwizzle.pop_back();
548 ValidSwizzle.push_back(TransBS);
559 assert (Consts.size() <= 12 &&
"Too many operands in instructions group");
560 unsigned Pair1 = 0, Pair2 = 0;
561 for (
unsigned Const : Consts) {
562 unsigned ReadConstHalf = Const & 2;
563 unsigned ReadConstIndex = Const & (~3);
564 unsigned ReadHalfConst = ReadConstIndex | ReadConstHalf;
566 Pair1 = ReadHalfConst;
569 if (Pair1 == ReadHalfConst)
572 Pair2 = ReadHalfConst;
575 if (Pair2 != ReadHalfConst)
584 std::vector<unsigned> Consts;
591 if (Src.first->getReg() == R600::ALU_LITERAL_X)
592 Literals.
insert(Src.second);
593 if (Literals.
size() > 4)
595 if (Src.first->getReg() == R600::ALU_CONST)
596 Consts.push_back(Src.second);
597 if (R600::R600_KC0RegClass.
contains(Src.first->getReg()) ||
598 R600::R600_KC1RegClass.contains(Src.first->getReg())) {
599 unsigned Index = RI.getEncodingValue(Src.first->getReg()) & 0xff;
601 Consts.push_back((
Index << 2) | Chan);
611 return static_cast<const R600Subtarget &
>(STI).createDFAPacketizer(
II);
639 return Opcode == R600::JUMP || Opcode == R600::JUMP_COND;
643 return Opcode == R600::BRANCH || Opcode == R600::BRANCH_COND_i32 ||
644 Opcode == R600::BRANCH_COND_f32;
651 bool AllowModify)
const {
668 while (
I !=
MBB.
begin() && std::prev(
I)->getOpcode() == R600::JUMP) {
671 I->removeFromParent();
679 if (LastOpc == R600::JUMP) {
683 if (LastOpc == R600::JUMP_COND) {
689 Cond.push_back(predSet->getOperand(1));
690 Cond.push_back(predSet->getOperand(2));
699 unsigned SecondLastOpc = SecondLastInst.
getOpcode();
702 if (SecondLastOpc == R600::JUMP_COND && LastOpc == R600::JUMP) {
709 Cond.push_back(predSet->getOperand(1));
710 Cond.push_back(predSet->getOperand(2));
723 if (It->getOpcode() == R600::CF_ALU ||
724 It->getOpcode() == R600::CF_ALU_PUSH_BEFORE)
735 int *BytesAdded)
const {
736 assert(
TBB &&
"insertBranch must not be told to insert a fallthrough");
737 assert(!BytesAdded &&
"code size not handled");
745 assert(PredSet &&
"No previous predicate !");
755 assert (CfAlu->getOpcode() == R600::CF_ALU);
756 CfAlu->setDesc(
get(R600::CF_ALU_PUSH_BEFORE));
760 assert(PredSet &&
"No previous predicate !");
770 assert(CfAlu->getOpcode() == R600::CF_ALU);
771 CfAlu->setDesc(
get(R600::CF_ALU_PUSH_BEFORE));
776 int *BytesRemoved)
const {
777 assert(!BytesRemoved &&
"code size not handled");
788 switch (
I->getOpcode()) {
791 case R600::JUMP_COND: {
794 I->eraseFromParent();
798 assert (CfAlu->getOpcode() == R600::CF_ALU_PUSH_BEFORE);
799 CfAlu->setDesc(
get(R600::CF_ALU));
803 I->eraseFromParent();
812 switch (
I->getOpcode()) {
816 case R600::JUMP_COND: {
819 I->eraseFromParent();
823 assert (CfAlu->getOpcode() == R600::CF_ALU_PUSH_BEFORE);
824 CfAlu->setDesc(
get(R600::CF_ALU));
828 I->eraseFromParent();
835 int idx =
MI.findFirstPredOperandIdx();
841 default:
return false;
842 case R600::PRED_SEL_ONE:
843 case R600::PRED_SEL_ZERO:
844 case R600::PREDICATE_BIT:
855 if (
MI.getOpcode() == R600::KILLGT)
857 if (
MI.getOpcode() == R600::CF_ALU) {
863 return MI.getOperand(3).getImm() == 0 &&
MI.getOperand(4).getImm() == 0;
873 unsigned ExtraPredCycles,
881 unsigned ExtraTCycles,
884 unsigned ExtraFCycles,
907 case R600::PRED_SETE_INT:
908 MO.
setImm(R600::PRED_SETNE_INT);
910 case R600::PRED_SETNE_INT:
911 MO.
setImm(R600::PRED_SETE_INT);
913 case R600::PRED_SETE:
914 MO.
setImm(R600::PRED_SETNE);
916 case R600::PRED_SETNE:
917 MO.
setImm(R600::PRED_SETE);
925 case R600::PRED_SEL_ZERO:
926 MO2.
setReg(R600::PRED_SEL_ONE);
928 case R600::PRED_SEL_ONE:
929 MO2.
setReg(R600::PRED_SEL_ZERO);
938 std::vector<MachineOperand> &Pred,
939 bool SkipDead)
const {
945 int PIdx =
MI.findFirstPredOperandIdx();
947 if (
MI.getOpcode() == R600::CF_ALU) {
948 MI.getOperand(8).setImm(0);
952 if (
MI.getOpcode() == R600::DOT_4) {
954 .setReg(Pred[2].
getReg());
956 .setReg(Pred[2].
getReg());
958 .setReg(Pred[2].
getReg());
960 .setReg(Pred[2].
getReg());
983 unsigned *PredCost)
const {
990 unsigned Channel)
const {
996 switch (
MI.getOpcode()) {
1000 R600::getNamedOperandIdx(
MI.getOpcode(), R600::OpName::addr);
1003 int RegOpIdx = OffsetOpIdx + 1;
1005 R600::getNamedOperandIdx(
MI.getOpcode(), R600::OpName::chan);
1008 R600::getNamedOperandIdx(
MI.getOpcode(), R600::OpName::dst);
1009 unsigned RegIndex =
MI.getOperand(RegOpIdx).getImm();
1010 unsigned Channel =
MI.getOperand(ChanOpIdx).getImm();
1012 Register OffsetReg =
MI.getOperand(OffsetOpIdx).getReg();
1013 if (OffsetReg == R600::INDIRECT_BASE_ADDR) {
1017 buildIndirectRead(
MBB,
MI,
MI.getOperand(DstOpIdx).getReg(),
Address,
1022 R600::getNamedOperandIdx(
MI.getOpcode(), R600::OpName::val);
1023 unsigned RegIndex =
MI.getOperand(RegOpIdx).getImm();
1024 unsigned Channel =
MI.getOperand(ChanOpIdx).getImm();
1026 Register OffsetReg =
MI.getOperand(OffsetOpIdx).getReg();
1027 if (OffsetReg == R600::INDIRECT_BASE_ADDR) {
1029 MI.getOperand(ValOpIdx).getReg());
1031 buildIndirectWrite(
MBB,
MI,
MI.getOperand(ValOpIdx).getReg(),
1042 case R600::R600_EXTRACT_ELT_V2:
1043 case R600::R600_EXTRACT_ELT_V4:
1044 buildIndirectRead(
MI.getParent(),
MI,
MI.getOperand(0).getReg(),
1046 MI.getOperand(2).getReg(),
1049 case R600::R600_INSERT_ELT_V2:
1050 case R600::R600_INSERT_ELT_V4:
1051 buildIndirectWrite(
MI.getParent(),
MI,
MI.getOperand(2).getReg(),
1053 MI.getOperand(3).getReg(),
1057 MI.eraseFromParent();
1067 unsigned StackWidth = TFL->getStackWidth(MF);
1074 for (
unsigned Chan = 0; Chan < StackWidth; ++Chan) {
1075 unsigned Reg = R600::R600_TReg32RegClass.getRegister((4 *
Index) + Chan);
1082 return &R600::R600_TReg32_XRegClass;
1087 unsigned ValueReg,
unsigned Address,
1088 unsigned OffsetReg)
const {
1089 return buildIndirectWrite(
MBB,
I, ValueReg,
Address, OffsetReg, 0);
1094 unsigned ValueReg,
unsigned Address,
1096 unsigned AddrChan)
const {
1100 case 0: AddrReg = R600::R600_AddrRegClass.getRegister(
Address);
break;
1101 case 1: AddrReg = R600::R600_Addr_YRegClass.getRegister(
Address);
break;
1102 case 2: AddrReg = R600::R600_Addr_ZRegClass.getRegister(
Address);
break;
1103 case 3: AddrReg = R600::R600_Addr_WRegClass.getRegister(
Address);
break;
1106 R600::AR_X, OffsetReg);
1119 unsigned ValueReg,
unsigned Address,
1120 unsigned OffsetReg)
const {
1121 return buildIndirectRead(
MBB,
I, ValueReg,
Address, OffsetReg, 0);
1126 unsigned ValueReg,
unsigned Address,
1128 unsigned AddrChan)
const {
1132 case 0: AddrReg = R600::R600_AddrRegClass.getRegister(
Address);
break;
1133 case 1: AddrReg = R600::R600_Addr_YRegClass.getRegister(
Address);
break;
1134 case 2: AddrReg = R600::R600_Addr_ZRegClass.getRegister(
Address);
break;
1135 case 3: AddrReg = R600::R600_Addr_WRegClass.getRegister(
Address);
break;
1160 if (
MRI.livein_empty()) {
1165 for (std::pair<unsigned, unsigned> LI :
MRI.liveins()) {
1167 if (Reg.isVirtual() || !IndirectRC->
contains(Reg))
1172 for (RegIndex = 0, RegEnd = IndirectRC->
getNumRegs(); RegIndex != RegEnd;
1174 if (IndirectRC->
getRegister(RegIndex) == (
unsigned)Reg)
1200 Offset = TFL->getFrameIndexReference(MF, -1, IgnoredFrameReg).getFixed();
1214 unsigned Src1Reg)
const {
1243 .
addReg(R600::PRED_SEL_OFF)
1250#define OPERAND_CASE(Label) \
1252 static const unsigned Ops[] = \
1291 assert (
MI->getOpcode() == R600::DOT_4 &&
"Not Implemented");
1294 Opcode = R600::DOT4_r600;
1296 Opcode = R600::DOT4_eg;
1304 static const unsigned Operands[14] = {
1305 R600::OpName::update_exec_mask,
1306 R600::OpName::update_pred,
1307 R600::OpName::write,
1309 R600::OpName::dst_rel,
1310 R600::OpName::clamp,
1311 R600::OpName::src0_neg,
1312 R600::OpName::src0_rel,
1313 R600::OpName::src0_abs,
1314 R600::OpName::src0_sel,
1315 R600::OpName::src1_neg,
1316 R600::OpName::src1_rel,
1317 R600::OpName::src1_abs,
1318 R600::OpName::src1_sel,
1326 for (
unsigned Operand :
Operands) {
1341 R600::ALU_LITERAL_X);
1348 unsigned DstReg,
unsigned SrcReg)
const {
1357 return R600::getNamedOperandIdx(Opcode,
Op);
1361 int64_t Imm)
const {
1363 assert(
Idx != -1 &&
"Operand not supported for this instruction.");
1365 MI.getOperand(
Idx).setImm(Imm);
1373 unsigned Flag)
const {
1374 unsigned TargetFlags =
get(
MI.getOpcode()).TSFlags;
1408 assert(!IsOP3 &&
"Cannot set absolute value modifier for OP3 "
1425 assert(FlagIndex != -1 &&
"Flag not supported for this instruction");
1429 "Instruction flags not supported for this instruction");
1438 unsigned Flag)
const {
1439 unsigned TargetFlags =
get(
MI.getOpcode()).TSFlags;
1459 unsigned Flag)
const {
1460 unsigned TargetFlags =
get(
MI.getOpcode()).TSFlags;
1466 unsigned InstFlags = FlagOp.
getImm();
1468 FlagOp.
setImm(InstFlags);
unsigned const MachineRegisterInfo * MRI
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
MachineBasicBlock MachineBasicBlock::iterator MBBI
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
mir Rename Register Operands
unsigned const TargetRegisterInfo * TRI
static unsigned getReg(const MCDisassembler *D, unsigned RC, unsigned RegNo)
uint64_t IntrinsicInst * II
#define GET_REG_INDEX(reg)
#define HAS_NATIVE_OPERANDS(Flags)
#define GET_FLAG_OPERAND_IDX(Flags)
Helper for getting the operand index for the instruction flags operand.
static MachineInstr * findFirstPredicateSetterFrom(MachineBasicBlock &MBB, MachineBasicBlock::iterator I)
static bool isBranch(unsigned Opcode)
static MachineBasicBlock::iterator FindLastAluClause(MachineBasicBlock &MBB)
#define OPERAND_CASE(Label)
static std::vector< std::pair< int, unsigned > > Swizzle(std::vector< std::pair< int, unsigned > > Src, R600InstrInfo::BankSwizzle Swz)
static unsigned getTransSwizzle(R600InstrInfo::BankSwizzle Swz, unsigned Op)
static bool isConstCompatible(R600InstrInfo::BankSwizzle TransSwz, const std::vector< std::pair< int, unsigned > > &TransOps, unsigned ConstCount)
Instructions in Trans slot can't read gpr at cycle 0 if they also read a const, and can't read a gpr ...
static bool isPredicateSetter(unsigned Opcode)
static bool NextPossibleSolution(std::vector< R600InstrInfo::BankSwizzle > &SwzCandidate, unsigned Idx)
Given a swizzle sequence SwzCandidate and an index Idx, returns the next (in lexicographic term) swiz...
static unsigned getSlotedOps(unsigned Op, unsigned Slot)
static bool isJump(unsigned Opcode)
Interface definition for R600InstrInfo.
Provides R600 specific target descriptions.
AMDGPU R600 specific subclass of TargetSubtarget.
const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB
const SmallVectorImpl< MachineOperand > & Cond
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file defines the SmallSet class.
static std::optional< unsigned > getOpcode(ArrayRef< VPValue * > Values)
Returns the opcode of Values or ~0 if they do not all agree.
static bool contains(SmallPtrSetImpl< ConstantExpr * > &Cache, ConstantExpr *Expr, Constant *C)
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
This class represents an Operation in the Expression.
bool contains(const_arg_type_t< KeyT > Val) const
Return true if the specified key is in the map, false otherwise.
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
A possibly irreducible generalization of a Loop.
Itinerary data supplied by a subtarget to be used by a target.
Wrapper class representing physical registers. Should be passed by value.
DebugLoc findDebugLoc(instr_iterator MBBI)
Find the next valid DebugLoc starting at MBBI, skipping any debug instructions.
iterator getLastNonDebugInstr(bool SkipPseudoOp=true)
Returns an iterator to the last non-debug instruction in the basic block, or end().
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
reverse_iterator rbegin()
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
unsigned getNumObjects() const
Return the number of objects.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Function & getFunction()
Return the LLVM function that this machine code represents.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
reverse_iterator getReverse() const
Get a reverse iterator to the same node.
Representation of each machine instruction.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
const MachineOperand & getOperand(unsigned i) const
MachineOperand class - Representation of each machine instruction operand.
void setImm(int64_t immVal)
MachineBasicBlock * getMBB() const
void setReg(Register Reg)
Change the register this operand corresponds to.
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
void setIsKill(bool Val=true)
bool isGlobal() const
isGlobal - Tests if this is a MO_GlobalAddress operand.
Register getReg() const
getReg - Returns the register number.
static MachineOperand CreateReg(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
bool usesVertexCache(unsigned Opcode) const
MachineInstrBuilder buildDefaultInstruction(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned Opcode, unsigned DstReg, unsigned Src0Reg, unsigned Src1Reg=0) const
buildDefaultInstruction - This function returns a MachineInstr with all the instruction modifiers ini...
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override
bool usesAddressRegister(MachineInstr &MI) const
unsigned calculateIndirectAddress(unsigned RegIndex, unsigned Channel) const
Calculate the "Indirect Address" for the given RegIndex and Channel.
bool hasInstrModifiers(unsigned Opcode) const
R600InstrInfo(const R600Subtarget &)
bool isMov(unsigned Opcode) const
bool isRegisterLoad(const MachineInstr &MI) const
int getIndirectIndexBegin(const MachineFunction &MF) const
bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, BranchProbability Probability) const override
bool usesTextureCache(unsigned Opcode) const
unsigned isLegalUpTo(const std::vector< std::vector< std::pair< int, unsigned > > > &IGSrcs, const std::vector< R600InstrInfo::BankSwizzle > &Swz, const std::vector< std::pair< int, unsigned > > &TransSrcs, R600InstrInfo::BankSwizzle TransSwz) const
returns how many MIs (whose inputs are represented by IGSrcs) can be packed in the same Instruction G...
unsigned int getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr &MI, unsigned *PredCost=nullptr) const override
const TargetRegisterClass * getIndirectAddrRegClass() const
MachineInstr * buildMovImm(MachineBasicBlock &BB, MachineBasicBlock::iterator I, unsigned DstReg, uint64_t Imm) const
bool definesAddressRegister(MachineInstr &MI) const
unsigned getMaxAlusPerClause() const
bool PredicateInstruction(MachineInstr &MI, ArrayRef< MachineOperand > Pred) const override
bool isLegalToSplitMBBAt(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) const override
bool canBeConsideredALU(const MachineInstr &MI) const
bool isProfitableToUnpredicate(MachineBasicBlock &TMBB, MachineBasicBlock &FMBB) const override
bool fitsConstReadLimitations(const std::vector< MachineInstr * > &) const
An instruction group can only access 2 channel pair (either [XY] or [ZW]) from KCache bank on R700+.
void addFlag(MachineInstr &MI, unsigned Operand, unsigned Flag) const
Add one of the MO_FLAG* flags to the specified Operand.
bool isVector(const MachineInstr &MI) const
Vector instructions are instructions that must fill all instruction slots within an instruction group...
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
bool mustBeLastInClause(unsigned Opcode) const
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
int getIndirectIndexEnd(const MachineFunction &MF) const
bool isTransOnly(unsigned Opcode) const
DFAPacketizer * CreateTargetScheduleState(const TargetSubtargetInfo &) const override
bool isReductionOp(unsigned opcode) const
bool isRegisterStore(const MachineInstr &MI) const
bool isCubeOp(unsigned opcode) const
bool isLDSInstr(unsigned Opcode) const
void reserveIndirectRegisters(BitVector &Reserved, const MachineFunction &MF, const R600RegisterInfo &TRI) const
Reserve the registers that may be accessed using indirect addressing.
bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, BranchProbability Probability) const override
bool isPredicable(const MachineInstr &MI) const override
bool isPredicated(const MachineInstr &MI) const override
bool expandPostRAPseudo(MachineInstr &MI) const override
bool isLDSRetInstr(unsigned Opcode) const
int getSelIdx(unsigned Opcode, unsigned SrcIdx) const
MachineOperand & getFlagOp(MachineInstr &MI, unsigned SrcIdx=0, unsigned Flag=0) const
unsigned int getPredicationCost(const MachineInstr &) const override
MachineInstr * buildSlotOfVectorInstruction(MachineBasicBlock &MBB, MachineInstr *MI, unsigned Slot, unsigned DstReg) const
bool readsLDSSrcReg(const MachineInstr &MI) const
bool FindSwizzleForVectorSlot(const std::vector< std::vector< std::pair< int, unsigned > > > &IGSrcs, std::vector< R600InstrInfo::BankSwizzle > &SwzCandidate, const std::vector< std::pair< int, unsigned > > &TransSrcs, R600InstrInfo::BankSwizzle TransSwz) const
Enumerate all possible Swizzle sequence to find one that can meet all read port requirements.
bool fitsReadPortLimitations(const std::vector< MachineInstr * > &MIs, const DenseMap< unsigned, unsigned > &PV, std::vector< BankSwizzle > &BS, bool isLastAluTrans) const
Given the order VEC_012 < VEC_021 < VEC_120 < VEC_102 < VEC_201 < VEC_210 returns true and the first ...
bool ClobbersPredicate(MachineInstr &MI, std::vector< MachineOperand > &Pred, bool SkipDead) const override
bool isALUInstr(unsigned Opcode) const
bool isVectorOnly(unsigned Opcode) const
bool isExport(unsigned Opcode) const
int getOperandIdx(const MachineInstr &MI, unsigned Op) const
Get the index of Op in the MachineInstr.
SmallVector< std::pair< MachineOperand *, int64_t >, 3 > getSrcs(MachineInstr &MI) const
void setImmOperand(MachineInstr &MI, unsigned Op, int64_t Imm) const
Helper function for setting instruction flag values.
MachineInstr * buildMovInstr(MachineBasicBlock *MBB, MachineBasicBlock::iterator I, unsigned DstReg, unsigned SrcReg) const
void clearFlag(MachineInstr &MI, unsigned Operand, unsigned Flag) const
Clear the specified flag on the instruction.
bool hasVertexCache() const
bool hasCaymanISA() const
Generation getGeneration() const
Wrapper class representing virtual and physical registers.
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
std::pair< const_iterator, bool > insert(const T &V)
insert - Insert an element into the set if it isn't already there.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
virtual bool isPredicable(const MachineInstr &MI) const
Return true if the specified instruction can be predicated.
unsigned getNumRegs() const
Return the number of registers in this class.
bool contains(Register Reg) const
Return true if the specified register is included in this register class.
MCRegister getRegister(unsigned i) const
Return the specified register in the class.
TargetSubtargetInfo - Generic base class for all target subtargets.
virtual const InstrItineraryData * getInstrItineraryData() const
getInstrItineraryData - Returns instruction itinerary data for the target or specific subtarget.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
bool isCompute(CallingConv::ID cc)
@ Implicit
Not emitted register (e.g. carry, or temporary result).
@ Define
Register definition.
@ Kill
The last use of a register.
This is an optimization pass for GlobalISel generic memory operations.
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
decltype(auto) get(const PointerIntPair< PointerTy, IntBits, IntType, PtrTraits, Info > &Pair)
DWARFExpression::Operation Op
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
unsigned getHWRegIndex(unsigned Reg) const
unsigned getHWRegChan(unsigned reg) const
get the HW encoding for a register's channel.
static unsigned getSubRegFromChannel(unsigned Channel)
bool isPhysRegLiveAcrossClauses(Register Reg) const