LLVM 20.0.0git
MipsDisassembler.cpp
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1//===- MipsDisassembler.cpp - Disassembler for Mips -----------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file is part of the Mips Disassembler.
10//
11//===----------------------------------------------------------------------===//
12
13#include "MCTargetDesc/MipsMCTargetDesc.h"
14#include "TargetInfo/MipsTargetInfo.h"
15#include "llvm/ADT/ArrayRef.h"
16#include "llvm/MC/MCContext.h"
17#include "llvm/MC/MCDecoderOps.h"
18#include "llvm/MC/MCDisassembler/MCDisassembler.h"
19#include "llvm/MC/MCInst.h"
20#include "llvm/MC/MCRegisterInfo.h"
21#include "llvm/MC/MCSubtargetInfo.h"
22#include "llvm/MC/TargetRegistry.h"
23#include "llvm/Support/Compiler.h"
24#include "llvm/Support/Debug.h"
25#include "llvm/Support/ErrorHandling.h"
26#include "llvm/Support/MathExtras.h"
27#include "llvm/Support/raw_ostream.h"
28#include <cassert>
29#include <cstdint>
30
31using namespace llvm;
32
33#define DEBUG_TYPE "mips-disassembler"
34
35using DecodeStatus = MCDisassembler::DecodeStatus;
36
37namespace {
38
39class MipsDisassembler : public MCDisassembler {
40 bool IsMicroMips;
41 bool IsBigEndian;
42
43public:
44 MipsDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, bool IsBigEndian)
45 : MCDisassembler(STI, Ctx),
46 IsMicroMips(STI.hasFeature(Mips::FeatureMicroMips)),
47 IsBigEndian(IsBigEndian) {}
48
49 bool hasMips2() const { return STI.hasFeature(Mips::FeatureMips2); }
50 bool hasMips3() const { return STI.hasFeature(Mips::FeatureMips3); }
51 bool hasMips32() const { return STI.hasFeature(Mips::FeatureMips32); }
52
53 bool hasMips32r6() const {
54 return STI.hasFeature(Mips::FeatureMips32r6);
55 }
56
57 bool isFP64() const { return STI.hasFeature(Mips::FeatureFP64Bit); }
58
59 bool isGP64() const { return STI.hasFeature(Mips::FeatureGP64Bit); }
60
61 bool isPTR64() const { return STI.hasFeature(Mips::FeaturePTR64Bit); }
62
63 bool hasCnMips() const { return STI.hasFeature(Mips::FeatureCnMips); }
64
65 bool hasCnMipsP() const { return STI.hasFeature(Mips::FeatureCnMipsP); }
66
67 bool hasCOP3() const {
68 // Only present in MIPS-I and MIPS-II
69 return !hasMips32() && !hasMips3();
70 }
71
72 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
73 ArrayRef<uint8_t> Bytes, uint64_t Address,
74 raw_ostream &CStream) const override;
75};
76
77} // end anonymous namespace
78
79// Forward declare these because the autogenerated code will reference them.
80// Definitions are further down.
81static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo,
82 uint64_t Address,
83 const MCDisassembler *Decoder);
84
85static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst, unsigned RegNo,
86 uint64_t Address,
87 const MCDisassembler *Decoder);
88
89static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst, unsigned RegNo,
90 uint64_t Address,
91 const MCDisassembler *Decoder);
92
93static DecodeStatus
94DecodeGPRMM16ZeroRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
95 const MCDisassembler *Decoder);
96
97static DecodeStatus
98DecodeGPRMM16MovePRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
99 const MCDisassembler *Decoder);
100
101static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo,
102 uint64_t Address,
103 const MCDisassembler *Decoder);
104
105static DecodeStatus DecodePtrRegisterClass(MCInst &Inst, unsigned Insn,
106 uint64_t Address,
107 const MCDisassembler *Decoder);
108
109static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst, unsigned RegNo,
110 uint64_t Address,
111 const MCDisassembler *Decoder);
112
113static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst, unsigned RegNo,
114 uint64_t Address,
115 const MCDisassembler *Decoder);
116
117static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst, unsigned RegNo,
118 uint64_t Address,
119 const MCDisassembler *Decoder);
120
121static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst, unsigned RegNo,
122 uint64_t Address,
123 const MCDisassembler *Decoder);
124
125static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst, unsigned RegNo,
126 uint64_t Address,
127 const MCDisassembler *Decoder);
128
129static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo,
130 uint64_t Address,
131 const MCDisassembler *Decoder);
132
133static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst, unsigned Insn,
134 uint64_t Address,
135 const MCDisassembler *Decoder);
136
137static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst, unsigned RegNo,
138 uint64_t Address,
139 const MCDisassembler *Decoder);
140
141static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst, unsigned RegNo,
142 uint64_t Address,
143 const MCDisassembler *Decoder);
144
145static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst, unsigned RegNo,
146 uint64_t Address,
147 const MCDisassembler *Decoder);
148
149static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst, unsigned RegNo,
150 uint64_t Address,
151 const MCDisassembler *Decoder);
152
153static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst, unsigned RegNo,
154 uint64_t Address,
155 const MCDisassembler *Decoder);
156
157static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst, unsigned RegNo,
158 uint64_t Address,
159 const MCDisassembler *Decoder);
160
161static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst, unsigned RegNo,
162 uint64_t Address,
163 const MCDisassembler *Decoder);
164
165static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst, unsigned RegNo,
166 uint64_t Address,
167 const MCDisassembler *Decoder);
168
169static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst, unsigned RegNo,
170 uint64_t Address,
171 const MCDisassembler *Decoder);
172
173static DecodeStatus DecodeCOP0RegisterClass(MCInst &Inst, unsigned RegNo,
174 uint64_t Address,
175 const MCDisassembler *Decoder);
176
177static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst, unsigned RegNo,
178 uint64_t Address,
179 const MCDisassembler *Decoder);
180
181static DecodeStatus DecodeBranchTarget(MCInst &Inst, unsigned Offset,
182 uint64_t Address,
183 const MCDisassembler *Decoder);
184
185static DecodeStatus DecodeBranchTarget1SImm16(MCInst &Inst, unsigned Offset,
186 uint64_t Address,
187 const MCDisassembler *Decoder);
188
189static DecodeStatus DecodeJumpTarget(MCInst &Inst, unsigned Insn,
190 uint64_t Address,
191 const MCDisassembler *Decoder);
192
193static DecodeStatus DecodeBranchTarget21(MCInst &Inst, unsigned Offset,
194 uint64_t Address,
195 const MCDisassembler *Decoder);
196
197static DecodeStatus DecodeBranchTarget21MM(MCInst &Inst, unsigned Offset,
198 uint64_t Address,
199 const MCDisassembler *Decoder);
200
201static DecodeStatus DecodeBranchTarget26(MCInst &Inst, unsigned Offset,
202 uint64_t Address,
203 const MCDisassembler *Decoder);
204
205// DecodeBranchTarget7MM - Decode microMIPS branch offset, which is
206// shifted left by 1 bit.
207static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst, unsigned Offset,
208 uint64_t Address,
209 const MCDisassembler *Decoder);
210
211// DecodeBranchTarget10MM - Decode microMIPS branch offset, which is
212// shifted left by 1 bit.
213static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst, unsigned Offset,
214 uint64_t Address,
215 const MCDisassembler *Decoder);
216
217// DecodeBranchTargetMM - Decode microMIPS branch offset, which is
218// shifted left by 1 bit.
219static DecodeStatus DecodeBranchTargetMM(MCInst &Inst, unsigned Offset,
220 uint64_t Address,
221 const MCDisassembler *Decoder);
222
223// DecodeBranchTarget26MM - Decode microMIPS branch offset, which is
224// shifted left by 1 bit.
225static DecodeStatus DecodeBranchTarget26MM(MCInst &Inst, unsigned Offset,
226 uint64_t Address,
227 const MCDisassembler *Decoder);
228
229// DecodeJumpTargetMM - Decode microMIPS jump target, which is
230// shifted left by 1 bit.
231static DecodeStatus DecodeJumpTargetMM(MCInst &Inst, unsigned Insn,
232 uint64_t Address,
233 const MCDisassembler *Decoder);
234
235// DecodeJumpTargetXMM - Decode microMIPS jump and link exchange target,
236// which is shifted left by 2 bit.
237static DecodeStatus DecodeJumpTargetXMM(MCInst &Inst, unsigned Insn,
238 uint64_t Address,
239 const MCDisassembler *Decoder);
240
241static DecodeStatus DecodeMem(MCInst &Inst, unsigned Insn, uint64_t Address,
242 const MCDisassembler *Decoder);
243
244static DecodeStatus DecodeMemEVA(MCInst &Inst, unsigned Insn, uint64_t Address,
245 const MCDisassembler *Decoder);
246
247static DecodeStatus DecodeLoadByte15(MCInst &Inst, unsigned Insn,
248 uint64_t Address,
249 const MCDisassembler *Decoder);
250
251static DecodeStatus DecodeCacheOp(MCInst &Inst, unsigned Insn, uint64_t Address,
252 const MCDisassembler *Decoder);
253
254static DecodeStatus DecodeCacheeOp_CacheOpR6(MCInst &Inst, unsigned Insn,
255 uint64_t Address,
256 const MCDisassembler *Decoder);
257
258static DecodeStatus DecodeCacheOpMM(MCInst &Inst, unsigned Insn,
259 uint64_t Address,
260 const MCDisassembler *Decoder);
261
262static DecodeStatus DecodePrefeOpMM(MCInst &Inst, unsigned Insn,
263 uint64_t Address,
264 const MCDisassembler *Decoder);
265
266static DecodeStatus DecodeSyncI(MCInst &Inst, unsigned Insn, uint64_t Address,
267 const MCDisassembler *Decoder);
268
269static DecodeStatus DecodeSyncI_MM(MCInst &Inst, unsigned Insn,
270 uint64_t Address,
271 const MCDisassembler *Decoder);
272
273static DecodeStatus DecodeSynciR6(MCInst &Inst, unsigned Insn, uint64_t Address,
274 const MCDisassembler *Decoder);
275
276static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
277 uint64_t Address,
278 const MCDisassembler *Decoder);
279
280static DecodeStatus DecodeMemMMImm4(MCInst &Inst, unsigned Insn,
281 uint64_t Address,
282 const MCDisassembler *Decoder);
283
284static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst, unsigned Insn,
285 uint64_t Address,
286 const MCDisassembler *Decoder);
287
288static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst, unsigned Insn,
289 uint64_t Address,
290 const MCDisassembler *Decoder);
291
292static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst, unsigned Insn,
293 uint64_t Address,
294 const MCDisassembler *Decoder);
295
296static DecodeStatus DecodeMemMMImm9(MCInst &Inst, unsigned Insn,
297 uint64_t Address,
298 const MCDisassembler *Decoder);
299
300static DecodeStatus DecodeMemMMImm12(MCInst &Inst, unsigned Insn,
301 uint64_t Address,
302 const MCDisassembler *Decoder);
303
304static DecodeStatus DecodeMemMMImm16(MCInst &Inst, unsigned Insn,
305 uint64_t Address,
306 const MCDisassembler *Decoder);
307
308static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn, uint64_t Address,
309 const MCDisassembler *Decoder);
310
311static DecodeStatus DecodeFMemMMR2(MCInst &Inst, unsigned Insn,
312 uint64_t Address,
313 const MCDisassembler *Decoder);
314
315static DecodeStatus DecodeFMem2(MCInst &Inst, unsigned Insn, uint64_t Address,
316 const MCDisassembler *Decoder);
317
318static DecodeStatus DecodeFMem3(MCInst &Inst, unsigned Insn, uint64_t Address,
319 const MCDisassembler *Decoder);
320
321static DecodeStatus DecodeFMemCop2R6(MCInst &Inst, unsigned Insn,
322 uint64_t Address,
323 const MCDisassembler *Decoder);
324
325static DecodeStatus DecodeFMemCop2MMR6(MCInst &Inst, unsigned Insn,
326 uint64_t Address,
327 const MCDisassembler *Decoder);
328
329static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst, unsigned Insn,
330 uint64_t Address,
331 const MCDisassembler *Decoder);
332
333static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst, unsigned Value,
334 uint64_t Address,
335 const MCDisassembler *Decoder);
336
337static DecodeStatus DecodeLi16Imm(MCInst &Inst, unsigned Value,
338 uint64_t Address,
339 const MCDisassembler *Decoder);
340
341static DecodeStatus DecodePOOL16BEncodedField(MCInst &Inst, unsigned Value,
342 uint64_t Address,
343 const MCDisassembler *Decoder);
344
345template <unsigned Bits, int Offset, int Scale>
346static DecodeStatus DecodeUImmWithOffsetAndScale(MCInst &Inst, unsigned Value,
347 uint64_t Address,
348 const MCDisassembler *Decoder);
349
350template <unsigned Bits, int Offset>
351static DecodeStatus DecodeUImmWithOffset(MCInst &Inst, unsigned Value,
352 uint64_t Address,
353 const MCDisassembler *Decoder) {
354 return DecodeUImmWithOffsetAndScale<Bits, Offset, 1>(Inst, Value, Address,
355 Decoder);
356}
357
358template <unsigned Bits, int Offset = 0, int ScaleBy = 1>
359static DecodeStatus DecodeSImmWithOffsetAndScale(MCInst &Inst, unsigned Value,
360 uint64_t Address,
361 const MCDisassembler *Decoder);
362
363static DecodeStatus DecodeInsSize(MCInst &Inst, unsigned Insn, uint64_t Address,
364 const MCDisassembler *Decoder);
365
366static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn,
367 uint64_t Address,
368 const MCDisassembler *Decoder);
369
370static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn,
371 uint64_t Address,
372 const MCDisassembler *Decoder);
373
374static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn, uint64_t Address,
375 const MCDisassembler *Decoder);
376
377static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn,
378 uint64_t Address,
379 const MCDisassembler *Decoder);
380
381static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn,
382 uint64_t Address,
383 const MCDisassembler *Decoder);
384
385/// INSVE_[BHWD] have an implicit operand that the generated decoder doesn't
386/// handle.
387template <typename InsnType>
388static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
389 const MCDisassembler *Decoder);
390
391template <typename InsnType>
392static DecodeStatus DecodeDAHIDATIMMR6(MCInst &MI, InsnType insn,
393 uint64_t Address,
394 const MCDisassembler *Decoder);
395
396template <typename InsnType>
397static DecodeStatus DecodeDAHIDATI(MCInst &MI, InsnType insn, uint64_t Address,
398 const MCDisassembler *Decoder);
399
400template <typename InsnType>
401static DecodeStatus DecodeAddiGroupBranch(MCInst &MI, InsnType insn,
402 uint64_t Address,
403 const MCDisassembler *Decoder);
404
405template <typename InsnType>
406static DecodeStatus DecodePOP35GroupBranchMMR6(MCInst &MI, InsnType insn,
407 uint64_t Address,
408 const MCDisassembler *Decoder);
409
410template <typename InsnType>
411static DecodeStatus DecodeDaddiGroupBranch(MCInst &MI, InsnType insn,
412 uint64_t Address,
413 const MCDisassembler *Decoder);
414
415template <typename InsnType>
416static DecodeStatus DecodePOP37GroupBranchMMR6(MCInst &MI, InsnType insn,
417 uint64_t Address,
418 const MCDisassembler *Decoder);
419
420template <typename InsnType>
421static DecodeStatus DecodePOP65GroupBranchMMR6(MCInst &MI, InsnType insn,
422 uint64_t Address,
423 const MCDisassembler *Decoder);
424
425template <typename InsnType>
426static DecodeStatus DecodePOP75GroupBranchMMR6(MCInst &MI, InsnType insn,
427 uint64_t Address,
428 const MCDisassembler *Decoder);
429
430template <typename InsnType>
431static DecodeStatus DecodeBlezlGroupBranch(MCInst &MI, InsnType insn,
432 uint64_t Address,
433 const MCDisassembler *Decoder);
434
435template <typename InsnType>
436static DecodeStatus DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn,
437 uint64_t Address,
438 const MCDisassembler *Decoder);
439
440template <typename InsnType>
441static DecodeStatus DecodeBgtzGroupBranch(MCInst &MI, InsnType insn,
442 uint64_t Address,
443 const MCDisassembler *Decoder);
444
445template <typename InsnType>
446static DecodeStatus DecodeBlezGroupBranch(MCInst &MI, InsnType insn,
447 uint64_t Address,
448 const MCDisassembler *Decoder);
449
450template <typename InsnType>
451static DecodeStatus DecodeBgtzGroupBranchMMR6(MCInst &MI, InsnType insn,
452 uint64_t Address,
453 const MCDisassembler *Decoder);
454
455template <typename InsnType>
456static DecodeStatus DecodeBlezGroupBranchMMR6(MCInst &MI, InsnType insn,
457 uint64_t Address,
458 const MCDisassembler *Decoder);
459
460template <typename InsnType>
461static DecodeStatus DecodeDINS(MCInst &MI, InsnType Insn, uint64_t Address,
462 const MCDisassembler *Decoder);
463
464template <typename InsnType>
465static DecodeStatus DecodeDEXT(MCInst &MI, InsnType Insn, uint64_t Address,
466 const MCDisassembler *Decoder);
467
468template <typename InsnType>
469static DecodeStatus DecodeCRC(MCInst &MI, InsnType Insn, uint64_t Address,
470 const MCDisassembler *Decoder);
471
472static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Insn,
473 uint64_t Address,
474 const MCDisassembler *Decoder);
475
476static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn,
477 uint64_t Address,
478 const MCDisassembler *Decoder);
479
480static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned RegPair,
481 uint64_t Address,
482 const MCDisassembler *Decoder);
483
484static DecodeStatus DecodeMovePOperands(MCInst &Inst, unsigned Insn,
485 uint64_t Address,
486 const MCDisassembler *Decoder);
487
488static DecodeStatus DecodeFIXMEInstruction(MCInst &Inst, unsigned Insn,
489 uint64_t Address,
490 const MCDisassembler *Decoder);
491
492static MCDisassembler *createMipsDisassembler(
493 const Target &T,
494 const MCSubtargetInfo &STI,
495 MCContext &Ctx) {
496 return new MipsDisassembler(STI, Ctx, true);
497}
498
499static MCDisassembler *createMipselDisassembler(
500 const Target &T,
501 const MCSubtargetInfo &STI,
502 MCContext &Ctx) {
503 return new MipsDisassembler(STI, Ctx, false);
504}
505
506extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeMipsDisassembler() {
507 // Register the disassembler.
508 TargetRegistry::RegisterMCDisassembler(getTheMipsTarget(),
509 createMipsDisassembler);
510 TargetRegistry::RegisterMCDisassembler(getTheMipselTarget(),
511 createMipselDisassembler);
512 TargetRegistry::RegisterMCDisassembler(getTheMips64Target(),
513 createMipsDisassembler);
514 TargetRegistry::RegisterMCDisassembler(getTheMips64elTarget(),
515 createMipselDisassembler);
516}
517
518#include "MipsGenDisassemblerTables.inc"
519
520static unsigned getReg(const MCDisassembler *D, unsigned RC, unsigned RegNo) {
521 const MCRegisterInfo *RegInfo = D->getContext().getRegisterInfo();
522 return *(RegInfo->getRegClass(RC).begin() + RegNo);
523}
524
525template <typename InsnType>
526static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
527 const MCDisassembler *Decoder) {
528 using DecodeFN =
529 DecodeStatus (*)(MCInst &, unsigned, uint64_t, const MCDisassembler *);
530
531 // The size of the n field depends on the element size
532 // The register class also depends on this.
533 InsnType tmp = fieldFromInstruction(insn, 17, 5);
534 unsigned NSize = 0;
535 DecodeFN RegDecoder = nullptr;
536 if ((tmp & 0x18) == 0x00) { // INSVE_B
537 NSize = 4;
538 RegDecoder = DecodeMSA128BRegisterClass;
539 } else if ((tmp & 0x1c) == 0x10) { // INSVE_H
540 NSize = 3;
541 RegDecoder = DecodeMSA128HRegisterClass;
542 } else if ((tmp & 0x1e) == 0x18) { // INSVE_W
543 NSize = 2;
544 RegDecoder = DecodeMSA128WRegisterClass;
545 } else if ((tmp & 0x1f) == 0x1c) { // INSVE_D
546 NSize = 1;
547 RegDecoder = DecodeMSA128DRegisterClass;
548 } else
549 llvm_unreachable("Invalid encoding");
550
551 assert(NSize != 0 && RegDecoder != nullptr);
552
553 // $wd
554 tmp = fieldFromInstruction(insn, 6, 5);
555 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
556 return MCDisassembler::Fail;
557 // $wd_in
558 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
559 return MCDisassembler::Fail;
560 // $n
561 tmp = fieldFromInstruction(insn, 16, NSize);
562 MI.addOperand(MCOperand::createImm(tmp));
563 // $ws
564 tmp = fieldFromInstruction(insn, 11, 5);
565 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
566 return MCDisassembler::Fail;
567 // $n2
568 MI.addOperand(MCOperand::createImm(0));
569
570 return MCDisassembler::Success;
571}
572
573template <typename InsnType>
574static DecodeStatus DecodeDAHIDATIMMR6(MCInst &MI, InsnType insn,
575 uint64_t Address,
576 const MCDisassembler *Decoder) {
577 InsnType Rs = fieldFromInstruction(insn, 16, 5);
578 InsnType Imm = fieldFromInstruction(insn, 0, 16);
579 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID,
580 Rs)));
581 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID,
582 Rs)));
583 MI.addOperand(MCOperand::createImm(Imm));
584
585 return MCDisassembler::Success;
586}
587
588template <typename InsnType>
589static DecodeStatus DecodeDAHIDATI(MCInst &MI, InsnType insn, uint64_t Address,
590 const MCDisassembler *Decoder) {
591 InsnType Rs = fieldFromInstruction(insn, 21, 5);
592 InsnType Imm = fieldFromInstruction(insn, 0, 16);
593 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID,
594 Rs)));
595 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID,
596 Rs)));
597 MI.addOperand(MCOperand::createImm(Imm));
598
599 return MCDisassembler::Success;
600}
601
602template <typename InsnType>
603static DecodeStatus DecodeAddiGroupBranch(MCInst &MI, InsnType insn,
604 uint64_t Address,
605 const MCDisassembler *Decoder) {
606 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
607 // (otherwise we would have matched the ADDI instruction from the earlier
608 // ISA's instead).
609 //
610 // We have:
611 // 0b001000 sssss ttttt iiiiiiiiiiiiiiii
612 // BOVC if rs >= rt
613 // BEQZALC if rs == 0 && rt != 0
614 // BEQC if rs < rt && rs != 0
615
616 InsnType Rs = fieldFromInstruction(insn, 21, 5);
617 InsnType Rt = fieldFromInstruction(insn, 16, 5);
618 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
619 bool HasRs = false;
620
621 if (Rs >= Rt) {
622 MI.setOpcode(Mips::BOVC);
623 HasRs = true;
624 } else if (Rs != 0 && Rs < Rt) {
625 MI.setOpcode(Mips::BEQC);
626 HasRs = true;
627 } else
628 MI.setOpcode(Mips::BEQZALC);
629
630 if (HasRs)
631 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
632 Rs)));
633
634 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
635 Rt)));
636 MI.addOperand(MCOperand::createImm(Imm));
637
638 return MCDisassembler::Success;
639}
640
641template <typename InsnType>
642static DecodeStatus DecodePOP35GroupBranchMMR6(MCInst &MI, InsnType insn,
643 uint64_t Address,
644 const MCDisassembler *Decoder) {
645 InsnType Rt = fieldFromInstruction(insn, 21, 5);
646 InsnType Rs = fieldFromInstruction(insn, 16, 5);
647 int64_t Imm = 0;
648
649 if (Rs >= Rt) {
650 MI.setOpcode(Mips::BOVC_MMR6);
651 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
652 Rt)));
653 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
654 Rs)));
655 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
656 } else if (Rs != 0 && Rs < Rt) {
657 MI.setOpcode(Mips::BEQC_MMR6);
658 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
659 Rs)));
660 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
661 Rt)));
662 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
663 } else {
664 MI.setOpcode(Mips::BEQZALC_MMR6);
665 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
666 Rt)));
667 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
668 }
669
670 MI.addOperand(MCOperand::createImm(Imm));
671
672 return MCDisassembler::Success;
673}
674
675template <typename InsnType>
676static DecodeStatus DecodeDaddiGroupBranch(MCInst &MI, InsnType insn,
677 uint64_t Address,
678 const MCDisassembler *Decoder) {
679 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
680 // (otherwise we would have matched the ADDI instruction from the earlier
681 // ISA's instead).
682 //
683 // We have:
684 // 0b011000 sssss ttttt iiiiiiiiiiiiiiii
685 // BNVC if rs >= rt
686 // BNEZALC if rs == 0 && rt != 0
687 // BNEC if rs < rt && rs != 0
688
689 InsnType Rs = fieldFromInstruction(insn, 21, 5);
690 InsnType Rt = fieldFromInstruction(insn, 16, 5);
691 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
692 bool HasRs = false;
693
694 if (Rs >= Rt) {
695 MI.setOpcode(Mips::BNVC);
696 HasRs = true;
697 } else if (Rs != 0 && Rs < Rt) {
698 MI.setOpcode(Mips::BNEC);
699 HasRs = true;
700 } else
701 MI.setOpcode(Mips::BNEZALC);
702
703 if (HasRs)
704 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
705 Rs)));
706
707 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
708 Rt)));
709 MI.addOperand(MCOperand::createImm(Imm));
710
711 return MCDisassembler::Success;
712}
713
714template <typename InsnType>
715static DecodeStatus DecodePOP37GroupBranchMMR6(MCInst &MI, InsnType insn,
716 uint64_t Address,
717 const MCDisassembler *Decoder) {
718 InsnType Rt = fieldFromInstruction(insn, 21, 5);
719 InsnType Rs = fieldFromInstruction(insn, 16, 5);
720 int64_t Imm = 0;
721
722 if (Rs >= Rt) {
723 MI.setOpcode(Mips::BNVC_MMR6);
724 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
725 Rt)));
726 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
727 Rs)));
728 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
729 } else if (Rs != 0 && Rs < Rt) {
730 MI.setOpcode(Mips::BNEC_MMR6);
731 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
732 Rs)));
733 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
734 Rt)));
735 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
736 } else {
737 MI.setOpcode(Mips::BNEZALC_MMR6);
738 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
739 Rt)));
740 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
741 }
742
743 MI.addOperand(MCOperand::createImm(Imm));
744
745 return MCDisassembler::Success;
746}
747
748template <typename InsnType>
749static DecodeStatus DecodePOP65GroupBranchMMR6(MCInst &MI, InsnType insn,
750 uint64_t Address,
751 const MCDisassembler *Decoder) {
752 // We have:
753 // 0b110101 ttttt sssss iiiiiiiiiiiiiiii
754 // Invalid if rt == 0
755 // BGTZC_MMR6 if rs == 0 && rt != 0
756 // BLTZC_MMR6 if rs == rt && rt != 0
757 // BLTC_MMR6 if rs != rt && rs != 0 && rt != 0
758
759 InsnType Rt = fieldFromInstruction(insn, 21, 5);
760 InsnType Rs = fieldFromInstruction(insn, 16, 5);
761 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
762 bool HasRs = false;
763
764 if (Rt == 0)
765 return MCDisassembler::Fail;
766 else if (Rs == 0)
767 MI.setOpcode(Mips::BGTZC_MMR6);
768 else if (Rs == Rt)
769 MI.setOpcode(Mips::BLTZC_MMR6);
770 else {
771 MI.setOpcode(Mips::BLTC_MMR6);
772 HasRs = true;
773 }
774
775 if (HasRs)
776 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
777 Rs)));
778
779 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
780 Rt)));
781
782 MI.addOperand(MCOperand::createImm(Imm));
783
784 return MCDisassembler::Success;
785}
786
787template <typename InsnType>
788static DecodeStatus DecodePOP75GroupBranchMMR6(MCInst &MI, InsnType insn,
789 uint64_t Address,
790 const MCDisassembler *Decoder) {
791 // We have:
792 // 0b111101 ttttt sssss iiiiiiiiiiiiiiii
793 // Invalid if rt == 0
794 // BLEZC_MMR6 if rs == 0 && rt != 0
795 // BGEZC_MMR6 if rs == rt && rt != 0
796 // BGEC_MMR6 if rs != rt && rs != 0 && rt != 0
797
798 InsnType Rt = fieldFromInstruction(insn, 21, 5);
799 InsnType Rs = fieldFromInstruction(insn, 16, 5);
800 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
801 bool HasRs = false;
802
803 if (Rt == 0)
804 return MCDisassembler::Fail;
805 else if (Rs == 0)
806 MI.setOpcode(Mips::BLEZC_MMR6);
807 else if (Rs == Rt)
808 MI.setOpcode(Mips::BGEZC_MMR6);
809 else {
810 HasRs = true;
811 MI.setOpcode(Mips::BGEC_MMR6);
812 }
813
814 if (HasRs)
815 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
816 Rs)));
817
818 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
819 Rt)));
820
821 MI.addOperand(MCOperand::createImm(Imm));
822
823 return MCDisassembler::Success;
824}
825
826template <typename InsnType>
827static DecodeStatus DecodeBlezlGroupBranch(MCInst &MI, InsnType insn,
828 uint64_t Address,
829 const MCDisassembler *Decoder) {
830 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
831 // (otherwise we would have matched the BLEZL instruction from the earlier
832 // ISA's instead).
833 //
834 // We have:
835 // 0b010110 sssss ttttt iiiiiiiiiiiiiiii
836 // Invalid if rs == 0
837 // BLEZC if rs == 0 && rt != 0
838 // BGEZC if rs == rt && rt != 0
839 // BGEC if rs != rt && rs != 0 && rt != 0
840
841 InsnType Rs = fieldFromInstruction(insn, 21, 5);
842 InsnType Rt = fieldFromInstruction(insn, 16, 5);
843 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
844 bool HasRs = false;
845
846 if (Rt == 0)
847 return MCDisassembler::Fail;
848 else if (Rs == 0)
849 MI.setOpcode(Mips::BLEZC);
850 else if (Rs == Rt)
851 MI.setOpcode(Mips::BGEZC);
852 else {
853 HasRs = true;
854 MI.setOpcode(Mips::BGEC);
855 }
856
857 if (HasRs)
858 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
859 Rs)));
860
861 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
862 Rt)));
863
864 MI.addOperand(MCOperand::createImm(Imm));
865
866 return MCDisassembler::Success;
867}
868
869template <typename InsnType>
870static DecodeStatus DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn,
871 uint64_t Address,
872 const MCDisassembler *Decoder) {
873 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
874 // (otherwise we would have matched the BGTZL instruction from the earlier
875 // ISA's instead).
876 //
877 // We have:
878 // 0b010111 sssss ttttt iiiiiiiiiiiiiiii
879 // Invalid if rs == 0
880 // BGTZC if rs == 0 && rt != 0
881 // BLTZC if rs == rt && rt != 0
882 // BLTC if rs != rt && rs != 0 && rt != 0
883
884 bool HasRs = false;
885
886 InsnType Rs = fieldFromInstruction(insn, 21, 5);
887 InsnType Rt = fieldFromInstruction(insn, 16, 5);
888 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
889
890 if (Rt == 0)
891 return MCDisassembler::Fail;
892 else if (Rs == 0)
893 MI.setOpcode(Mips::BGTZC);
894 else if (Rs == Rt)
895 MI.setOpcode(Mips::BLTZC);
896 else {
897 MI.setOpcode(Mips::BLTC);
898 HasRs = true;
899 }
900
901 if (HasRs)
902 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
903 Rs)));
904
905 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
906 Rt)));
907
908 MI.addOperand(MCOperand::createImm(Imm));
909
910 return MCDisassembler::Success;
911}
912
913template <typename InsnType>
914static DecodeStatus DecodeBgtzGroupBranch(MCInst &MI, InsnType insn,
915 uint64_t Address,
916 const MCDisassembler *Decoder) {
917 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
918 // (otherwise we would have matched the BGTZ instruction from the earlier
919 // ISA's instead).
920 //
921 // We have:
922 // 0b000111 sssss ttttt iiiiiiiiiiiiiiii
923 // BGTZ if rt == 0
924 // BGTZALC if rs == 0 && rt != 0
925 // BLTZALC if rs != 0 && rs == rt
926 // BLTUC if rs != 0 && rs != rt
927
928 InsnType Rs = fieldFromInstruction(insn, 21, 5);
929 InsnType Rt = fieldFromInstruction(insn, 16, 5);
930 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
931 bool HasRs = false;
932 bool HasRt = false;
933
934 if (Rt == 0) {
935 MI.setOpcode(Mips::BGTZ);
936 HasRs = true;
937 } else if (Rs == 0) {
938 MI.setOpcode(Mips::BGTZALC);
939 HasRt = true;
940 } else if (Rs == Rt) {
941 MI.setOpcode(Mips::BLTZALC);
942 HasRs = true;
943 } else {
944 MI.setOpcode(Mips::BLTUC);
945 HasRs = true;
946 HasRt = true;
947 }
948
949 if (HasRs)
950 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
951 Rs)));
952
953 if (HasRt)
954 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
955 Rt)));
956
957 MI.addOperand(MCOperand::createImm(Imm));
958
959 return MCDisassembler::Success;
960}
961
962template <typename InsnType>
963static DecodeStatus DecodeBlezGroupBranch(MCInst &MI, InsnType insn,
964 uint64_t Address,
965 const MCDisassembler *Decoder) {
966 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
967 // (otherwise we would have matched the BLEZL instruction from the earlier
968 // ISA's instead).
969 //
970 // We have:
971 // 0b000110 sssss ttttt iiiiiiiiiiiiiiii
972 // Invalid if rs == 0
973 // BLEZALC if rs == 0 && rt != 0
974 // BGEZALC if rs == rt && rt != 0
975 // BGEUC if rs != rt && rs != 0 && rt != 0
976
977 InsnType Rs = fieldFromInstruction(insn, 21, 5);
978 InsnType Rt = fieldFromInstruction(insn, 16, 5);
979 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
980 bool HasRs = false;
981
982 if (Rt == 0)
983 return MCDisassembler::Fail;
984 else if (Rs == 0)
985 MI.setOpcode(Mips::BLEZALC);
986 else if (Rs == Rt)
987 MI.setOpcode(Mips::BGEZALC);
988 else {
989 HasRs = true;
990 MI.setOpcode(Mips::BGEUC);
991 }
992
993 if (HasRs)
994 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
995 Rs)));
996 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
997 Rt)));
998
999 MI.addOperand(MCOperand::createImm(Imm));
1000
1001 return MCDisassembler::Success;
1002}
1003
1004// Override the generated disassembler to produce DEXT all the time. This is
1005// for feature / behaviour parity with binutils.
1006template <typename InsnType>
1007static DecodeStatus DecodeDEXT(MCInst &MI, InsnType Insn, uint64_t Address,
1008 const MCDisassembler *Decoder) {
1009 unsigned Msbd = fieldFromInstruction(Insn, 11, 5);
1010 unsigned Lsb = fieldFromInstruction(Insn, 6, 5);
1011 unsigned Size = 0;
1012 unsigned Pos = 0;
1013
1014 switch (MI.getOpcode()) {
1015 case Mips::DEXT:
1016 Pos = Lsb;
1017 Size = Msbd + 1;
1018 break;
1019 case Mips::DEXTM:
1020 Pos = Lsb;
1021 Size = Msbd + 1 + 32;
1022 break;
1023 case Mips::DEXTU:
1024 Pos = Lsb + 32;
1025 Size = Msbd + 1;
1026 break;
1027 default:
1028 llvm_unreachable("Unknown DEXT instruction!");
1029 }
1030
1031 MI.setOpcode(Mips::DEXT);
1032
1033 InsnType Rs = fieldFromInstruction(Insn, 21, 5);
1034 InsnType Rt = fieldFromInstruction(Insn, 16, 5);
1035
1036 MI.addOperand(
1037 MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rt)));
1038 MI.addOperand(
1039 MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rs)));
1040 MI.addOperand(MCOperand::createImm(Pos));
1041 MI.addOperand(MCOperand::createImm(Size));
1042
1043 return MCDisassembler::Success;
1044}
1045
1046// Override the generated disassembler to produce DINS all the time. This is
1047// for feature / behaviour parity with binutils.
1048template <typename InsnType>
1049static DecodeStatus DecodeDINS(MCInst &MI, InsnType Insn, uint64_t Address,
1050 const MCDisassembler *Decoder) {
1051 unsigned Msbd = fieldFromInstruction(Insn, 11, 5);
1052 unsigned Lsb = fieldFromInstruction(Insn, 6, 5);
1053 unsigned Size = 0;
1054 unsigned Pos = 0;
1055
1056 switch (MI.getOpcode()) {
1057 case Mips::DINS:
1058 Pos = Lsb;
1059 Size = Msbd + 1 - Pos;
1060 break;
1061 case Mips::DINSM:
1062 Pos = Lsb;
1063 Size = Msbd + 33 - Pos;
1064 break;
1065 case Mips::DINSU:
1066 Pos = Lsb + 32;
1067 // mbsd = pos + size - 33
1068 // mbsd - pos + 33 = size
1069 Size = Msbd + 33 - Pos;
1070 break;
1071 default:
1072 llvm_unreachable("Unknown DINS instruction!");
1073 }
1074
1075 InsnType Rs = fieldFromInstruction(Insn, 21, 5);
1076 InsnType Rt = fieldFromInstruction(Insn, 16, 5);
1077
1078 MI.setOpcode(Mips::DINS);
1079 MI.addOperand(
1080 MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rt)));
1081 MI.addOperand(
1082 MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rs)));
1083 MI.addOperand(MCOperand::createImm(Pos));
1084 MI.addOperand(MCOperand::createImm(Size));
1085
1086 return MCDisassembler::Success;
1087}
1088
1089// Auto-generated decoder wouldn't add the third operand for CRC32*.
1090template <typename InsnType>
1091static DecodeStatus DecodeCRC(MCInst &MI, InsnType Insn, uint64_t Address,
1092 const MCDisassembler *Decoder) {
1093 InsnType Rs = fieldFromInstruction(Insn, 21, 5);
1094 InsnType Rt = fieldFromInstruction(Insn, 16, 5);
1095 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
1096 Rt)));
1097 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
1098 Rs)));
1099 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
1100 Rt)));
1101 return MCDisassembler::Success;
1102}
1103
1104/// Read two bytes from the ArrayRef and return 16 bit halfword sorted
1105/// according to the given endianness.
1106static DecodeStatus readInstruction16(ArrayRef<uint8_t> Bytes, uint64_t Address,
1107 uint64_t &Size, uint32_t &Insn,
1108 bool IsBigEndian) {
1109 // We want to read exactly 2 Bytes of data.
1110 if (Bytes.size() < 2) {
1111 Size = 0;
1112 return MCDisassembler::Fail;
1113 }
1114
1115 if (IsBigEndian) {
1116 Insn = (Bytes[0] << 8) | Bytes[1];
1117 } else {
1118 Insn = (Bytes[1] << 8) | Bytes[0];
1119 }
1120
1121 return MCDisassembler::Success;
1122}
1123
1124/// Read four bytes from the ArrayRef and return 32 bit word sorted
1125/// according to the given endianness.
1126static DecodeStatus readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t Address,
1127 uint64_t &Size, uint32_t &Insn,
1128 bool IsBigEndian, bool IsMicroMips) {
1129 // We want to read exactly 4 Bytes of data.
1130 if (Bytes.size() < 4) {
1131 Size = 0;
1132 return MCDisassembler::Fail;
1133 }
1134
1135 // High 16 bits of a 32-bit microMIPS instruction (where the opcode is)
1136 // always precede the low 16 bits in the instruction stream (that is, they
1137 // are placed at lower addresses in the instruction stream).
1138 //
1139 // microMIPS byte ordering:
1140 // Big-endian: 0 | 1 | 2 | 3
1141 // Little-endian: 1 | 0 | 3 | 2
1142
1143 if (IsBigEndian) {
1144 // Encoded as a big-endian 32-bit word in the stream.
1145 Insn =
1146 (Bytes[3] << 0) | (Bytes[2] << 8) | (Bytes[1] << 16) | (Bytes[0] << 24);
1147 } else {
1148 if (IsMicroMips) {
1149 Insn = (Bytes[2] << 0) | (Bytes[3] << 8) | (Bytes[0] << 16) |
1150 (Bytes[1] << 24);
1151 } else {
1152 Insn = (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) |
1153 (Bytes[3] << 24);
1154 }
1155 }
1156
1157 return MCDisassembler::Success;
1158}
1159
1160DecodeStatus MipsDisassembler::getInstruction(MCInst &Instr, uint64_t &Size,
1161 ArrayRef<uint8_t> Bytes,
1162 uint64_t Address,
1163 raw_ostream &CStream) const {
1164 uint32_t Insn;
1165 DecodeStatus Result;
1166 Size = 0;
1167
1168 if (IsMicroMips) {
1169 Result = readInstruction16(Bytes, Address, Size, Insn, IsBigEndian);
1170 if (Result == MCDisassembler::Fail)
1171 return MCDisassembler::Fail;
1172
1173 if (hasMips32r6()) {
1174 LLVM_DEBUG(
1175 dbgs() << "Trying MicroMipsR616 table (16-bit instructions):\n");
1176 // Calling the auto-generated decoder function for microMIPS32R6
1177 // 16-bit instructions.
1178 Result = decodeInstruction(DecoderTableMicroMipsR616, Instr, Insn,
1179 Address, this, STI);
1180 if (Result != MCDisassembler::Fail) {
1181 Size = 2;
1182 return Result;
1183 }
1184 }
1185
1186 LLVM_DEBUG(dbgs() << "Trying MicroMips16 table (16-bit instructions):\n");
1187 // Calling the auto-generated decoder function for microMIPS 16-bit
1188 // instructions.
1189 Result = decodeInstruction(DecoderTableMicroMips16, Instr, Insn, Address,
1190 this, STI);
1191 if (Result != MCDisassembler::Fail) {
1192 Size = 2;
1193 return Result;
1194 }
1195
1196 Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, true);
1197 if (Result == MCDisassembler::Fail)
1198 return MCDisassembler::Fail;
1199
1200 if (hasMips32r6()) {
1201 LLVM_DEBUG(
1202 dbgs() << "Trying MicroMips32r632 table (32-bit instructions):\n");
1203 // Calling the auto-generated decoder function.
1204 Result = decodeInstruction(DecoderTableMicroMipsR632, Instr, Insn,
1205 Address, this, STI);
1206 if (Result != MCDisassembler::Fail) {
1207 Size = 4;
1208 return Result;
1209 }
1210 }
1211
1212 LLVM_DEBUG(dbgs() << "Trying MicroMips32 table (32-bit instructions):\n");
1213 // Calling the auto-generated decoder function.
1214 Result = decodeInstruction(DecoderTableMicroMips32, Instr, Insn, Address,
1215 this, STI);
1216 if (Result != MCDisassembler::Fail) {
1217 Size = 4;
1218 return Result;
1219 }
1220
1221 if (isFP64()) {
1222 LLVM_DEBUG(dbgs() << "Trying MicroMipsFP64 table (32-bit opcodes):\n");
1223 Result = decodeInstruction(DecoderTableMicroMipsFP6432, Instr, Insn,
1224 Address, this, STI);
1225 if (Result != MCDisassembler::Fail) {
1226 Size = 4;
1227 return Result;
1228 }
1229 }
1230
1231 // This is an invalid instruction. Claim that the Size is 2 bytes. Since
1232 // microMIPS instructions have a minimum alignment of 2, the next 2 bytes
1233 // could form a valid instruction. The two bytes we rejected as an
1234 // instruction could have actually beeen an inline constant pool that is
1235 // unconditionally branched over.
1236 Size = 2;
1237 return MCDisassembler::Fail;
1238 }
1239
1240 // Attempt to read the instruction so that we can attempt to decode it. If
1241 // the buffer is not 4 bytes long, let the higher level logic figure out
1242 // what to do with a size of zero and MCDisassembler::Fail.
1243 Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, false);
1244 if (Result == MCDisassembler::Fail)
1245 return MCDisassembler::Fail;
1246
1247 // The only instruction size for standard encoded MIPS.
1248 Size = 4;
1249
1250 if (hasCOP3()) {
1251 LLVM_DEBUG(dbgs() << "Trying COP3_ table (32-bit opcodes):\n");
1252 Result =
1253 decodeInstruction(DecoderTableCOP3_32, Instr, Insn, Address, this, STI);
1254 if (Result != MCDisassembler::Fail)
1255 return Result;
1256 }
1257
1258 if (hasMips32r6() && isGP64()) {
1259 LLVM_DEBUG(
1260 dbgs() << "Trying Mips32r6_64r6 (GPR64) table (32-bit opcodes):\n");
1261 Result = decodeInstruction(DecoderTableMips32r6_64r6_GP6432, Instr, Insn,
1262 Address, this, STI);
1263 if (Result != MCDisassembler::Fail)
1264 return Result;
1265 }
1266
1267 if (hasMips32r6() && isPTR64()) {
1268 LLVM_DEBUG(
1269 dbgs() << "Trying Mips32r6_64r6 (PTR64) table (32-bit opcodes):\n");
1270 Result = decodeInstruction(DecoderTableMips32r6_64r6_PTR6432, Instr, Insn,
1271 Address, this, STI);
1272 if (Result != MCDisassembler::Fail)
1273 return Result;
1274 }
1275
1276 if (hasMips32r6()) {
1277 LLVM_DEBUG(dbgs() << "Trying Mips32r6_64r6 table (32-bit opcodes):\n");
1278 Result = decodeInstruction(DecoderTableMips32r6_64r632, Instr, Insn,
1279 Address, this, STI);
1280 if (Result != MCDisassembler::Fail)
1281 return Result;
1282 }
1283
1284 if (hasMips2() && isPTR64()) {
1285 LLVM_DEBUG(
1286 dbgs() << "Trying Mips32r6_64r6 (PTR64) table (32-bit opcodes):\n");
1287 Result = decodeInstruction(DecoderTableMips32_64_PTR6432, Instr, Insn,
1288 Address, this, STI);
1289 if (Result != MCDisassembler::Fail)
1290 return Result;
1291 }
1292
1293 if (hasCnMips()) {
1294 LLVM_DEBUG(dbgs() << "Trying CnMips table (32-bit opcodes):\n");
1295 Result = decodeInstruction(DecoderTableCnMips32, Instr, Insn,
1296 Address, this, STI);
1297 if (Result != MCDisassembler::Fail)
1298 return Result;
1299 }
1300
1301 if (hasCnMipsP()) {
1302 LLVM_DEBUG(dbgs() << "Trying CnMipsP table (32-bit opcodes):\n");
1303 Result = decodeInstruction(DecoderTableCnMipsP32, Instr, Insn,
1304 Address, this, STI);
1305 if (Result != MCDisassembler::Fail)
1306 return Result;
1307 }
1308
1309 if (isGP64()) {
1310 LLVM_DEBUG(dbgs() << "Trying Mips64 (GPR64) table (32-bit opcodes):\n");
1311 Result = decodeInstruction(DecoderTableMips6432, Instr, Insn,
1312 Address, this, STI);
1313 if (Result != MCDisassembler::Fail)
1314 return Result;
1315 }
1316
1317 if (isFP64()) {
1318 LLVM_DEBUG(
1319 dbgs() << "Trying MipsFP64 (64 bit FPU) table (32-bit opcodes):\n");
1320 Result = decodeInstruction(DecoderTableMipsFP6432, Instr, Insn,
1321 Address, this, STI);
1322 if (Result != MCDisassembler::Fail)
1323 return Result;
1324 }
1325
1326 LLVM_DEBUG(dbgs() << "Trying Mips table (32-bit opcodes):\n");
1327 // Calling the auto-generated decoder function.
1328 Result =
1329 decodeInstruction(DecoderTableMips32, Instr, Insn, Address, this, STI);
1330 if (Result != MCDisassembler::Fail)
1331 return Result;
1332
1333 return MCDisassembler::Fail;
1334}
1335
1336static DecodeStatus
1337DecodeCPU16RegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
1338 const MCDisassembler *Decoder) {
1339 return MCDisassembler::Fail;
1340}
1341
1342static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo,
1343 uint64_t Address,
1344 const MCDisassembler *Decoder) {
1345 if (RegNo > 31)
1346 return MCDisassembler::Fail;
1347
1348 unsigned Reg = getReg(Decoder, Mips::GPR64RegClassID, RegNo);
1349 Inst.addOperand(MCOperand::createReg(Reg));
1350 return MCDisassembler::Success;
1351}
1352
1353static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst, unsigned RegNo,
1354 uint64_t Address,
1355 const MCDisassembler *Decoder) {
1356 if (RegNo > 7)
1357 return MCDisassembler::Fail;
1358 unsigned Reg = getReg(Decoder, Mips::GPRMM16RegClassID, RegNo);
1359 Inst.addOperand(MCOperand::createReg(Reg));
1360 return MCDisassembler::Success;
1361}
1362
1363static DecodeStatus
1364DecodeGPRMM16ZeroRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
1365 const MCDisassembler *Decoder) {
1366 if (RegNo > 7)
1367 return MCDisassembler::Fail;
1368 unsigned Reg = getReg(Decoder, Mips::GPRMM16ZeroRegClassID, RegNo);
1369 Inst.addOperand(MCOperand::createReg(Reg));
1370 return MCDisassembler::Success;
1371}
1372
1373static DecodeStatus
1374DecodeGPRMM16MovePRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
1375 const MCDisassembler *Decoder) {
1376 if (RegNo > 7)
1377 return MCDisassembler::Fail;
1378 unsigned Reg = getReg(Decoder, Mips::GPRMM16MovePRegClassID, RegNo);
1379 Inst.addOperand(MCOperand::createReg(Reg));
1380 return MCDisassembler::Success;
1381}
1382
1383static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo,
1384 uint64_t Address,
1385 const MCDisassembler *Decoder) {
1386 if (RegNo > 31)
1387 return MCDisassembler::Fail;
1388 unsigned Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo);
1389 Inst.addOperand(MCOperand::createReg(Reg));
1390 return MCDisassembler::Success;
1391}
1392
1393static DecodeStatus DecodePtrRegisterClass(MCInst &Inst, unsigned RegNo,
1394 uint64_t Address,
1395 const MCDisassembler *Decoder) {
1396 if (static_cast<const MipsDisassembler *>(Decoder)->isGP64())
1397 return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder);
1398
1399 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
1400}
1401
1402static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst, unsigned RegNo,
1403 uint64_t Address,
1404 const MCDisassembler *Decoder) {
1405 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
1406}
1407
1408static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst, unsigned RegNo,
1409 uint64_t Address,
1410 const MCDisassembler *Decoder) {
1411 if (RegNo > 31)
1412 return MCDisassembler::Fail;
1413
1414 unsigned Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo);
1415 Inst.addOperand(MCOperand::createReg(Reg));
1416 return MCDisassembler::Success;
1417}
1418
1419static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst, unsigned RegNo,
1420 uint64_t Address,
1421 const MCDisassembler *Decoder) {
1422 if (RegNo > 31)
1423 return MCDisassembler::Fail;
1424
1425 unsigned Reg = getReg(Decoder, Mips::FGR32RegClassID, RegNo);
1426 Inst.addOperand(MCOperand::createReg(Reg));
1427 return MCDisassembler::Success;
1428}
1429
1430static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst, unsigned RegNo,
1431 uint64_t Address,
1432 const MCDisassembler *Decoder) {
1433 if (RegNo > 31)
1434 return MCDisassembler::Fail;
1435 unsigned Reg = getReg(Decoder, Mips::CCRRegClassID, RegNo);
1436 Inst.addOperand(MCOperand::createReg(Reg));
1437 return MCDisassembler::Success;
1438}
1439
1440static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst, unsigned RegNo,
1441 uint64_t Address,
1442 const MCDisassembler *Decoder) {
1443 if (RegNo > 7)
1444 return MCDisassembler::Fail;
1445 unsigned Reg = getReg(Decoder, Mips::FCCRegClassID, RegNo);
1446 Inst.addOperand(MCOperand::createReg(Reg));
1447 return MCDisassembler::Success;
1448}
1449
1450static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo,
1451 uint64_t Address,
1452 const MCDisassembler *Decoder) {
1453 if (RegNo > 31)
1454 return MCDisassembler::Fail;
1455
1456 unsigned Reg = getReg(Decoder, Mips::FGRCCRegClassID, RegNo);
1457 Inst.addOperand(MCOperand::createReg(Reg));
1458 return MCDisassembler::Success;
1459}
1460
1461static DecodeStatus DecodeMem(MCInst &Inst, unsigned Insn, uint64_t Address,
1462 const MCDisassembler *Decoder) {
1463 int Offset = SignExtend32<16>(Insn & 0xffff);
1464 unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1465 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1466
1467 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1468 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1469
1470 if (Inst.getOpcode() == Mips::SC ||
1471 Inst.getOpcode() == Mips::SCD)
1472 Inst.addOperand(MCOperand::createReg(Reg));
1473
1474 Inst.addOperand(MCOperand::createReg(Reg));
1475 Inst.addOperand(MCOperand::createReg(Base));
1476 Inst.addOperand(MCOperand::createImm(Offset));
1477
1478 return MCDisassembler::Success;
1479}
1480
1481static DecodeStatus DecodeMemEVA(MCInst &Inst, unsigned Insn, uint64_t Address,
1482 const MCDisassembler *Decoder) {
1483 int Offset = SignExtend32<9>(Insn >> 7);
1484 unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1485 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1486
1487 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1488 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1489
1490 if (Inst.getOpcode() == Mips::SCE)
1491 Inst.addOperand(MCOperand::createReg(Reg));
1492
1493 Inst.addOperand(MCOperand::createReg(Reg));
1494 Inst.addOperand(MCOperand::createReg(Base));
1495 Inst.addOperand(MCOperand::createImm(Offset));
1496
1497 return MCDisassembler::Success;
1498}
1499
1500static DecodeStatus DecodeLoadByte15(MCInst &Inst, unsigned Insn,
1501 uint64_t Address,
1502 const MCDisassembler *Decoder) {
1503 int Offset = SignExtend32<16>(Insn & 0xffff);
1504 unsigned Base = fieldFromInstruction(Insn, 16, 5);
1505 unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1506
1507 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1508 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1509
1510 Inst.addOperand(MCOperand::createReg(Reg));
1511 Inst.addOperand(MCOperand::createReg(Base));
1512 Inst.addOperand(MCOperand::createImm(Offset));
1513
1514 return MCDisassembler::Success;
1515}
1516
1517static DecodeStatus DecodeCacheOp(MCInst &Inst, unsigned Insn, uint64_t Address,
1518 const MCDisassembler *Decoder) {
1519 int Offset = SignExtend32<16>(Insn & 0xffff);
1520 unsigned Hint = fieldFromInstruction(Insn, 16, 5);
1521 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1522
1523 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1524
1525 Inst.addOperand(MCOperand::createReg(Base));
1526 Inst.addOperand(MCOperand::createImm(Offset));
1527 Inst.addOperand(MCOperand::createImm(Hint));
1528
1529 return MCDisassembler::Success;
1530}
1531
1532static DecodeStatus DecodeCacheOpMM(MCInst &Inst, unsigned Insn,
1533 uint64_t Address,
1534 const MCDisassembler *Decoder) {
1535 int Offset = SignExtend32<12>(Insn & 0xfff);
1536 unsigned Base = fieldFromInstruction(Insn, 16, 5);
1537 unsigned Hint = fieldFromInstruction(Insn, 21, 5);
1538
1539 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1540
1541 Inst.addOperand(MCOperand::createReg(Base));
1542 Inst.addOperand(MCOperand::createImm(Offset));
1543 Inst.addOperand(MCOperand::createImm(Hint));
1544
1545 return MCDisassembler::Success;
1546}
1547
1548static DecodeStatus DecodePrefeOpMM(MCInst &Inst, unsigned Insn,
1549 uint64_t Address,
1550 const MCDisassembler *Decoder) {
1551 int Offset = SignExtend32<9>(Insn & 0x1ff);
1552 unsigned Base = fieldFromInstruction(Insn, 16, 5);
1553 unsigned Hint = fieldFromInstruction(Insn, 21, 5);
1554
1555 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1556
1557 Inst.addOperand(MCOperand::createReg(Base));
1558 Inst.addOperand(MCOperand::createImm(Offset));
1559 Inst.addOperand(MCOperand::createImm(Hint));
1560
1561 return MCDisassembler::Success;
1562}
1563
1564static DecodeStatus DecodeCacheeOp_CacheOpR6(MCInst &Inst, unsigned Insn,
1565 uint64_t Address,
1566 const MCDisassembler *Decoder) {
1567 int Offset = SignExtend32<9>(Insn >> 7);
1568 unsigned Hint = fieldFromInstruction(Insn, 16, 5);
1569 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1570
1571 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1572
1573 Inst.addOperand(MCOperand::createReg(Base));
1574 Inst.addOperand(MCOperand::createImm(Offset));
1575 Inst.addOperand(MCOperand::createImm(Hint));
1576
1577 return MCDisassembler::Success;
1578}
1579
1580static DecodeStatus DecodeSyncI(MCInst &Inst, unsigned Insn, uint64_t Address,
1581 const MCDisassembler *Decoder) {
1582 int Offset = SignExtend32<16>(Insn & 0xffff);
1583 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1584
1585 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1586
1587 Inst.addOperand(MCOperand::createReg(Base));
1588 Inst.addOperand(MCOperand::createImm(Offset));
1589
1590 return MCDisassembler::Success;
1591}
1592
1593static DecodeStatus DecodeSyncI_MM(MCInst &Inst, unsigned Insn,
1594 uint64_t Address,
1595 const MCDisassembler *Decoder) {
1596 int Offset = SignExtend32<16>(Insn & 0xffff);
1597 unsigned Base = fieldFromInstruction(Insn, 16, 5);
1598
1599 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1600
1601 Inst.addOperand(MCOperand::createReg(Base));
1602 Inst.addOperand(MCOperand::createImm(Offset));
1603
1604 return MCDisassembler::Success;
1605}
1606
1607static DecodeStatus DecodeSynciR6(MCInst &Inst, unsigned Insn, uint64_t Address,
1608 const MCDisassembler *Decoder) {
1609 int Immediate = SignExtend32<16>(Insn & 0xffff);
1610 unsigned Base = fieldFromInstruction(Insn, 16, 5);
1611
1612 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1613
1614 Inst.addOperand(MCOperand::createReg(Base));
1615 Inst.addOperand(MCOperand::createImm(Immediate));
1616
1617 return MCDisassembler::Success;
1618}
1619
1620static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
1621 uint64_t Address,
1622 const MCDisassembler *Decoder) {
1623 int Offset = SignExtend32<10>(fieldFromInstruction(Insn, 16, 10));
1624 unsigned Reg = fieldFromInstruction(Insn, 6, 5);
1625 unsigned Base = fieldFromInstruction(Insn, 11, 5);
1626
1627 Reg = getReg(Decoder, Mips::MSA128BRegClassID, Reg);
1628 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1629
1630 Inst.addOperand(MCOperand::createReg(Reg));
1631 Inst.addOperand(MCOperand::createReg(Base));
1632
1633 // The immediate field of an LD/ST instruction is scaled which means it must
1634 // be multiplied (when decoding) by the size (in bytes) of the instructions'
1635 // data format.
1636 // .b - 1 byte
1637 // .h - 2 bytes
1638 // .w - 4 bytes
1639 // .d - 8 bytes
1640 switch(Inst.getOpcode())
1641 {
1642 default:
1643 assert(false && "Unexpected instruction");
1644 return MCDisassembler::Fail;
1645 break;
1646 case Mips::LD_B:
1647 case Mips::ST_B:
1648 Inst.addOperand(MCOperand::createImm(Offset));
1649 break;
1650 case Mips::LD_H:
1651 case Mips::ST_H:
1652 Inst.addOperand(MCOperand::createImm(Offset * 2));
1653 break;
1654 case Mips::LD_W:
1655 case Mips::ST_W:
1656 Inst.addOperand(MCOperand::createImm(Offset * 4));
1657 break;
1658 case Mips::LD_D:
1659 case Mips::ST_D:
1660 Inst.addOperand(MCOperand::createImm(Offset * 8));
1661 break;
1662 }
1663
1664 return MCDisassembler::Success;
1665}
1666
1667static DecodeStatus DecodeMemMMImm4(MCInst &Inst, unsigned Insn,
1668 uint64_t Address,
1669 const MCDisassembler *Decoder) {
1670 unsigned Offset = Insn & 0xf;
1671 unsigned Reg = fieldFromInstruction(Insn, 7, 3);
1672 unsigned Base = fieldFromInstruction(Insn, 4, 3);
1673
1674 switch (Inst.getOpcode()) {
1675 case Mips::LBU16_MM:
1676 case Mips::LHU16_MM:
1677 case Mips::LW16_MM:
1678 if (DecodeGPRMM16RegisterClass(Inst, Reg, Address, Decoder)
1679 == MCDisassembler::Fail)
1680 return MCDisassembler::Fail;
1681 break;
1682 case Mips::SB16_MM:
1683 case Mips::SB16_MMR6:
1684 case Mips::SH16_MM:
1685 case Mips::SH16_MMR6:
1686 case Mips::SW16_MM:
1687 case Mips::SW16_MMR6:
1688 if (DecodeGPRMM16ZeroRegisterClass(Inst, Reg, Address, Decoder)
1689 == MCDisassembler::Fail)
1690 return MCDisassembler::Fail;
1691 break;
1692 }
1693
1694 if (DecodeGPRMM16RegisterClass(Inst, Base, Address, Decoder)
1695 == MCDisassembler::Fail)
1696 return MCDisassembler::Fail;
1697
1698 switch (Inst.getOpcode()) {
1699 case Mips::LBU16_MM:
1700 if (Offset == 0xf)
1701 Inst.addOperand(MCOperand::createImm(-1));
1702 else
1703 Inst.addOperand(MCOperand::createImm(Offset));
1704 break;
1705 case Mips::SB16_MM:
1706 case Mips::SB16_MMR6:
1707 Inst.addOperand(MCOperand::createImm(Offset));
1708 break;
1709 case Mips::LHU16_MM:
1710 case Mips::SH16_MM:
1711 case Mips::SH16_MMR6:
1712 Inst.addOperand(MCOperand::createImm(Offset << 1));
1713 break;
1714 case Mips::LW16_MM:
1715 case Mips::SW16_MM:
1716 case Mips::SW16_MMR6:
1717 Inst.addOperand(MCOperand::createImm(Offset << 2));
1718 break;
1719 }
1720
1721 return MCDisassembler::Success;
1722}
1723
1724static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst, unsigned Insn,
1725 uint64_t Address,
1726 const MCDisassembler *Decoder) {
1727 unsigned Offset = Insn & 0x1F;
1728 unsigned Reg = fieldFromInstruction(Insn, 5, 5);
1729
1730 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1731
1732 Inst.addOperand(MCOperand::createReg(Reg));
1733 Inst.addOperand(MCOperand::createReg(Mips::SP));
1734 Inst.addOperand(MCOperand::createImm(Offset << 2));
1735
1736 return MCDisassembler::Success;
1737}
1738
1739static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst, unsigned Insn,
1740 uint64_t Address,
1741 const MCDisassembler *Decoder) {
1742 unsigned Offset = Insn & 0x7F;
1743 unsigned Reg = fieldFromInstruction(Insn, 7, 3);
1744
1745 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1746
1747 Inst.addOperand(MCOperand::createReg(Reg));
1748 Inst.addOperand(MCOperand::createReg(Mips::GP));
1749 Inst.addOperand(MCOperand::createImm(Offset << 2));
1750
1751 return MCDisassembler::Success;
1752}
1753
1754static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst, unsigned Insn,
1755 uint64_t Address,
1756 const MCDisassembler *Decoder) {
1757 int Offset;
1758 switch (Inst.getOpcode()) {
1759 case Mips::LWM16_MMR6:
1760 case Mips::SWM16_MMR6:
1761 Offset = fieldFromInstruction(Insn, 4, 4);
1762 break;
1763 default:
1764 Offset = SignExtend32<4>(Insn & 0xf);
1765 break;
1766 }
1767
1768 if (DecodeRegListOperand16(Inst, Insn, Address, Decoder)
1769 == MCDisassembler::Fail)
1770 return MCDisassembler::Fail;
1771
1772 Inst.addOperand(MCOperand::createReg(Mips::SP));
1773 Inst.addOperand(MCOperand::createImm(Offset << 2));
1774
1775 return MCDisassembler::Success;
1776}
1777
1778static DecodeStatus DecodeMemMMImm9(MCInst &Inst, unsigned Insn,
1779 uint64_t Address,
1780 const MCDisassembler *Decoder) {
1781 int Offset = SignExtend32<9>(Insn & 0x1ff);
1782 unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1783 unsigned Base = fieldFromInstruction(Insn, 16, 5);
1784
1785 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1786 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1787
1788 if (Inst.getOpcode() == Mips::SCE_MM || Inst.getOpcode() == Mips::SC_MMR6)
1789 Inst.addOperand(MCOperand::createReg(Reg));
1790
1791 Inst.addOperand(MCOperand::createReg(Reg));
1792 Inst.addOperand(MCOperand::createReg(Base));
1793 Inst.addOperand(MCOperand::createImm(Offset));
1794
1795 return MCDisassembler::Success;
1796}
1797
1798static DecodeStatus DecodeMemMMImm12(MCInst &Inst, unsigned Insn,
1799 uint64_t Address,
1800 const MCDisassembler *Decoder) {
1801 int Offset = SignExtend32<12>(Insn & 0x0fff);
1802 unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1803 unsigned Base = fieldFromInstruction(Insn, 16, 5);
1804
1805 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1806 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1807
1808 switch (Inst.getOpcode()) {
1809 case Mips::SWM32_MM:
1810 case Mips::LWM32_MM:
1811 if (DecodeRegListOperand(Inst, Insn, Address, Decoder)
1812 == MCDisassembler::Fail)
1813 return MCDisassembler::Fail;
1814 Inst.addOperand(MCOperand::createReg(Base));
1815 Inst.addOperand(MCOperand::createImm(Offset));
1816 break;
1817 case Mips::SC_MM:
1818 Inst.addOperand(MCOperand::createReg(Reg));
1819 [[fallthrough]];
1820 default:
1821 Inst.addOperand(MCOperand::createReg(Reg));
1822 if (Inst.getOpcode() == Mips::LWP_MM || Inst.getOpcode() == Mips::SWP_MM)
1823 Inst.addOperand(MCOperand::createReg(Reg+1));
1824
1825 Inst.addOperand(MCOperand::createReg(Base));
1826 Inst.addOperand(MCOperand::createImm(Offset));
1827 }
1828
1829 return MCDisassembler::Success;
1830}
1831
1832static DecodeStatus DecodeMemMMImm16(MCInst &Inst, unsigned Insn,
1833 uint64_t Address,
1834 const MCDisassembler *Decoder) {
1835 int Offset = SignExtend32<16>(Insn & 0xffff);
1836 unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1837 unsigned Base = fieldFromInstruction(Insn, 16, 5);
1838
1839 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1840 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1841
1842 Inst.addOperand(MCOperand::createReg(Reg));
1843 Inst.addOperand(MCOperand::createReg(Base));
1844 Inst.addOperand(MCOperand::createImm(Offset));
1845
1846 return MCDisassembler::Success;
1847}
1848
1849static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn, uint64_t Address,
1850 const MCDisassembler *Decoder) {
1851 int Offset = SignExtend32<16>(Insn & 0xffff);
1852 unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1853 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1854
1855 Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg);
1856 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1857
1858 Inst.addOperand(MCOperand::createReg(Reg));
1859 Inst.addOperand(MCOperand::createReg(Base));
1860 Inst.addOperand(MCOperand::createImm(Offset));
1861
1862 return MCDisassembler::Success;
1863}
1864
1865static DecodeStatus DecodeFMemMMR2(MCInst &Inst, unsigned Insn,
1866 uint64_t Address,
1867 const MCDisassembler *Decoder) {
1868 // This function is the same as DecodeFMem but with the Reg and Base fields
1869 // swapped according to microMIPS spec.
1870 int Offset = SignExtend32<16>(Insn & 0xffff);
1871 unsigned Base = fieldFromInstruction(Insn, 16, 5);
1872 unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1873
1874 Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg);
1875 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1876
1877 Inst.addOperand(MCOperand::createReg(Reg));
1878 Inst.addOperand(MCOperand::createReg(Base));
1879 Inst.addOperand(MCOperand::createImm(Offset));
1880
1881 return MCDisassembler::Success;
1882}
1883
1884static DecodeStatus DecodeFMem2(MCInst &Inst, unsigned Insn, uint64_t Address,
1885 const MCDisassembler *Decoder) {
1886 int Offset = SignExtend32<16>(Insn & 0xffff);
1887 unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1888 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1889
1890 Reg = getReg(Decoder, Mips::COP2RegClassID, Reg);
1891 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1892
1893 Inst.addOperand(MCOperand::createReg(Reg));
1894 Inst.addOperand(MCOperand::createReg(Base));
1895 Inst.addOperand(MCOperand::createImm(Offset));
1896
1897 return MCDisassembler::Success;
1898}
1899
1900static DecodeStatus DecodeFMem3(MCInst &Inst, unsigned Insn, uint64_t Address,
1901 const MCDisassembler *Decoder) {
1902 int Offset = SignExtend32<16>(Insn & 0xffff);
1903 unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1904 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1905
1906 Reg = getReg(Decoder, Mips::COP3RegClassID, Reg);
1907 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1908
1909 Inst.addOperand(MCOperand::createReg(Reg));
1910 Inst.addOperand(MCOperand::createReg(Base));
1911 Inst.addOperand(MCOperand::createImm(Offset));
1912
1913 return MCDisassembler::Success;
1914}
1915
1916static DecodeStatus DecodeFMemCop2R6(MCInst &Inst, unsigned Insn,
1917 uint64_t Address,
1918 const MCDisassembler *Decoder) {
1919 int Offset = SignExtend32<11>(Insn & 0x07ff);
1920 unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1921 unsigned Base = fieldFromInstruction(Insn, 11, 5);
1922
1923 Reg = getReg(Decoder, Mips::COP2RegClassID, Reg);
1924 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1925
1926 Inst.addOperand(MCOperand::createReg(Reg));
1927 Inst.addOperand(MCOperand::createReg(Base));
1928 Inst.addOperand(MCOperand::createImm(Offset));
1929
1930 return MCDisassembler::Success;
1931}
1932
1933static DecodeStatus DecodeFMemCop2MMR6(MCInst &Inst, unsigned Insn,
1934 uint64_t Address,
1935 const MCDisassembler *Decoder) {
1936 int Offset = SignExtend32<11>(Insn & 0x07ff);
1937 unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1938 unsigned Base = fieldFromInstruction(Insn, 16, 5);
1939
1940 Reg = getReg(Decoder, Mips::COP2RegClassID, Reg);
1941 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1942
1943 Inst.addOperand(MCOperand::createReg(Reg));
1944 Inst.addOperand(MCOperand::createReg(Base));
1945 Inst.addOperand(MCOperand::createImm(Offset));
1946
1947 return MCDisassembler::Success;
1948}
1949
1950static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst, unsigned Insn,
1951 uint64_t Address,
1952 const MCDisassembler *Decoder) {
1953 int64_t Offset = SignExtend64<9>((Insn >> 7) & 0x1ff);
1954 unsigned Rt = fieldFromInstruction(Insn, 16, 5);
1955 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1956
1957 Rt = getReg(Decoder, Mips::GPR32RegClassID, Rt);
1958 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1959
1960 if(Inst.getOpcode() == Mips::SC_R6 || Inst.getOpcode() == Mips::SCD_R6){
1961 Inst.addOperand(MCOperand::createReg(Rt));
1962 }
1963
1964 Inst.addOperand(MCOperand::createReg(Rt));
1965 Inst.addOperand(MCOperand::createReg(Base));
1966 Inst.addOperand(MCOperand::createImm(Offset));
1967
1968 return MCDisassembler::Success;
1969}
1970
1971static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst, unsigned RegNo,
1972 uint64_t Address,
1973 const MCDisassembler *Decoder) {
1974 // Currently only hardware register 29 is supported.
1975 if (RegNo != 29)
1976 return MCDisassembler::Fail;
1977 Inst.addOperand(MCOperand::createReg(Mips::HWR29));
1978 return MCDisassembler::Success;
1979}
1980
1981static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst, unsigned RegNo,
1982 uint64_t Address,
1983 const MCDisassembler *Decoder) {
1984 if (RegNo > 30 || RegNo %2)
1985 return MCDisassembler::Fail;
1986
1987 unsigned Reg = getReg(Decoder, Mips::AFGR64RegClassID, RegNo /2);
1988 Inst.addOperand(MCOperand::createReg(Reg));
1989 return MCDisassembler::Success;
1990}
1991
1992static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst, unsigned RegNo,
1993 uint64_t Address,
1994 const MCDisassembler *Decoder) {
1995 if (RegNo >= 4)
1996 return MCDisassembler::Fail;
1997
1998 unsigned Reg = getReg(Decoder, Mips::ACC64DSPRegClassID, RegNo);
1999 Inst.addOperand(MCOperand::createReg(Reg));
2000 return MCDisassembler::Success;
2001}
2002
2003static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst, unsigned RegNo,
2004 uint64_t Address,
2005 const MCDisassembler *Decoder) {
2006 if (RegNo >= 4)
2007 return MCDisassembler::Fail;
2008
2009 unsigned Reg = getReg(Decoder, Mips::HI32DSPRegClassID, RegNo);
2010 Inst.addOperand(MCOperand::createReg(Reg));
2011 return MCDisassembler::Success;
2012}
2013
2014static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst, unsigned RegNo,
2015 uint64_t Address,
2016 const MCDisassembler *Decoder) {
2017 if (RegNo >= 4)
2018 return MCDisassembler::Fail;
2019
2020 unsigned Reg = getReg(Decoder, Mips::LO32DSPRegClassID, RegNo);
2021 Inst.addOperand(MCOperand::createReg(Reg));
2022 return MCDisassembler::Success;
2023}
2024
2025static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst, unsigned RegNo,
2026 uint64_t Address,
2027 const MCDisassembler *Decoder) {
2028 if (RegNo > 31)
2029 return MCDisassembler::Fail;
2030
2031 unsigned Reg = getReg(Decoder, Mips::MSA128BRegClassID, RegNo);
2032 Inst.addOperand(MCOperand::createReg(Reg));
2033 return MCDisassembler::Success;
2034}
2035
2036static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst, unsigned RegNo,
2037 uint64_t Address,
2038 const MCDisassembler *Decoder) {
2039 if (RegNo > 31)
2040 return MCDisassembler::Fail;
2041
2042 unsigned Reg = getReg(Decoder, Mips::MSA128HRegClassID, RegNo);
2043 Inst.addOperand(MCOperand::createReg(Reg));
2044 return MCDisassembler::Success;
2045}
2046
2047static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst, unsigned RegNo,
2048 uint64_t Address,
2049 const MCDisassembler *Decoder) {
2050 if (RegNo > 31)
2051 return MCDisassembler::Fail;
2052
2053 unsigned Reg = getReg(Decoder, Mips::MSA128WRegClassID, RegNo);
2054 Inst.addOperand(MCOperand::createReg(Reg));
2055 return MCDisassembler::Success;
2056}
2057
2058static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst, unsigned RegNo,
2059 uint64_t Address,
2060 const MCDisassembler *Decoder) {
2061 if (RegNo > 31)
2062 return MCDisassembler::Fail;
2063
2064 unsigned Reg = getReg(Decoder, Mips::MSA128DRegClassID, RegNo);
2065 Inst.addOperand(MCOperand::createReg(Reg));
2066 return MCDisassembler::Success;
2067}
2068
2069static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst, unsigned RegNo,
2070 uint64_t Address,
2071 const MCDisassembler *Decoder) {
2072 if (RegNo > 7)
2073 return MCDisassembler::Fail;
2074
2075 unsigned Reg = getReg(Decoder, Mips::MSACtrlRegClassID, RegNo);
2076 Inst.addOperand(MCOperand::createReg(Reg));
2077 return MCDisassembler::Success;
2078}
2079
2080static DecodeStatus DecodeCOP0RegisterClass(MCInst &Inst, unsigned RegNo,
2081 uint64_t Address,
2082 const MCDisassembler *Decoder) {
2083 if (RegNo > 31)
2084 return MCDisassembler::Fail;
2085
2086 unsigned Reg = getReg(Decoder, Mips::COP0RegClassID, RegNo);
2087 Inst.addOperand(MCOperand::createReg(Reg));
2088 return MCDisassembler::Success;
2089}
2090
2091static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst, unsigned RegNo,
2092 uint64_t Address,
2093 const MCDisassembler *Decoder) {
2094 if (RegNo > 31)
2095 return MCDisassembler::Fail;
2096
2097 unsigned Reg = getReg(Decoder, Mips::COP2RegClassID, RegNo);
2098 Inst.addOperand(MCOperand::createReg(Reg));
2099 return MCDisassembler::Success;
2100}
2101
2102static DecodeStatus DecodeBranchTarget(MCInst &Inst, unsigned Offset,
2103 uint64_t Address,
2104 const MCDisassembler *Decoder) {
2105 int32_t BranchOffset = (SignExtend32<16>(Offset) * 4) + 4;
2106 Inst.addOperand(MCOperand::createImm(BranchOffset));
2107 return MCDisassembler::Success;
2108}
2109
2110static DecodeStatus DecodeBranchTarget1SImm16(MCInst &Inst, unsigned Offset,
2111 uint64_t Address,
2112 const MCDisassembler *Decoder) {
2113 int32_t BranchOffset = (SignExtend32<16>(Offset) * 2);
2114 Inst.addOperand(MCOperand::createImm(BranchOffset));
2115 return MCDisassembler::Success;
2116}
2117
2118static DecodeStatus DecodeJumpTarget(MCInst &Inst, unsigned Insn,
2119 uint64_t Address,
2120 const MCDisassembler *Decoder) {
2121 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2;
2122 Inst.addOperand(MCOperand::createImm(JumpOffset));
2123 return MCDisassembler::Success;
2124}
2125
2126static DecodeStatus DecodeBranchTarget21(MCInst &Inst, unsigned Offset,
2127 uint64_t Address,
2128 const MCDisassembler *Decoder) {
2129 int32_t BranchOffset = SignExtend32<21>(Offset) * 4 + 4;
2130
2131 Inst.addOperand(MCOperand::createImm(BranchOffset));
2132 return MCDisassembler::Success;
2133}
2134
2135static DecodeStatus DecodeBranchTarget21MM(MCInst &Inst, unsigned Offset,
2136 uint64_t Address,
2137 const MCDisassembler *Decoder) {
2138 int32_t BranchOffset = SignExtend32<21>(Offset) * 4 + 4;
2139
2140 Inst.addOperand(MCOperand::createImm(BranchOffset));
2141 return MCDisassembler::Success;
2142}
2143
2144static DecodeStatus DecodeBranchTarget26(MCInst &Inst, unsigned Offset,
2145 uint64_t Address,
2146 const MCDisassembler *Decoder) {
2147 int32_t BranchOffset = SignExtend32<26>(Offset) * 4 + 4;
2148
2149 Inst.addOperand(MCOperand::createImm(BranchOffset));
2150 return MCDisassembler::Success;
2151}
2152
2153static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst, unsigned Offset,
2154 uint64_t Address,
2155 const MCDisassembler *Decoder) {
2156 int32_t BranchOffset = SignExtend32<8>(Offset << 1);
2157 Inst.addOperand(MCOperand::createImm(BranchOffset));
2158 return MCDisassembler::Success;
2159}
2160
2161static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst, unsigned Offset,
2162 uint64_t Address,
2163 const MCDisassembler *Decoder) {
2164 int32_t BranchOffset = SignExtend32<11>(Offset << 1);
2165 Inst.addOperand(MCOperand::createImm(BranchOffset));
2166 return MCDisassembler::Success;
2167}
2168
2169static DecodeStatus DecodeBranchTargetMM(MCInst &Inst, unsigned Offset,
2170 uint64_t Address,
2171 const MCDisassembler *Decoder) {
2172 int32_t BranchOffset = SignExtend32<16>(Offset) * 2 + 4;
2173 Inst.addOperand(MCOperand::createImm(BranchOffset));
2174 return MCDisassembler::Success;
2175}
2176
2177static DecodeStatus DecodeBranchTarget26MM(MCInst &Inst, unsigned Offset,
2178 uint64_t Address,
2179 const MCDisassembler *Decoder) {
2180 int32_t BranchOffset = SignExtend32<27>(Offset << 1);
2181
2182 Inst.addOperand(MCOperand::createImm(BranchOffset));
2183 return MCDisassembler::Success;
2184}
2185
2186static DecodeStatus DecodeJumpTargetMM(MCInst &Inst, unsigned Insn,
2187 uint64_t Address,
2188 const MCDisassembler *Decoder) {
2189 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 1;
2190 Inst.addOperand(MCOperand::createImm(JumpOffset));
2191 return MCDisassembler::Success;
2192}
2193
2194static DecodeStatus DecodeJumpTargetXMM(MCInst &Inst, unsigned Insn,
2195 uint64_t Address,
2196 const MCDisassembler *Decoder) {
2197 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2;
2198 Inst.addOperand(MCOperand::createImm(JumpOffset));
2199 return MCDisassembler::Success;
2200}
2201
2202static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst, unsigned Value,
2203 uint64_t Address,
2204 const MCDisassembler *Decoder) {
2205 if (Value == 0)
2206 Inst.addOperand(MCOperand::createImm(1));
2207 else if (Value == 0x7)
2208 Inst.addOperand(MCOperand::createImm(-1));
2209 else
2210 Inst.addOperand(MCOperand::createImm(Value << 2));
2211 return MCDisassembler::Success;
2212}
2213
2214static DecodeStatus DecodeLi16Imm(MCInst &Inst, unsigned Value,
2215 uint64_t Address,
2216 const MCDisassembler *Decoder) {
2217 if (Value == 0x7F)
2218 Inst.addOperand(MCOperand::createImm(-1));
2219 else
2220 Inst.addOperand(MCOperand::createImm(Value));
2221 return MCDisassembler::Success;
2222}
2223
2224static DecodeStatus DecodePOOL16BEncodedField(MCInst &Inst, unsigned Value,
2225 uint64_t Address,
2226 const MCDisassembler *Decoder) {
2227 Inst.addOperand(MCOperand::createImm(Value == 0x0 ? 8 : Value));
2228 return MCDisassembler::Success;
2229}
2230
2231template <unsigned Bits, int Offset, int Scale>
2232static DecodeStatus
2233DecodeUImmWithOffsetAndScale(MCInst &Inst, unsigned Value, uint64_t Address,
2234 const MCDisassembler *Decoder) {
2235 Value &= ((1 << Bits) - 1);
2236 Value *= Scale;
2237 Inst.addOperand(MCOperand::createImm(Value + Offset));
2238 return MCDisassembler::Success;
2239}
2240
2241template <unsigned Bits, int Offset, int ScaleBy>
2242static DecodeStatus
2243DecodeSImmWithOffsetAndScale(MCInst &Inst, unsigned Value, uint64_t Address,
2244 const MCDisassembler *Decoder) {
2245 int32_t Imm = SignExtend32<Bits>(Value) * ScaleBy;
2246 Inst.addOperand(MCOperand::createImm(Imm + Offset));
2247 return MCDisassembler::Success;
2248}
2249
2250static DecodeStatus DecodeInsSize(MCInst &Inst, unsigned Insn, uint64_t Address,
2251 const MCDisassembler *Decoder) {
2252 // First we need to grab the pos(lsb) from MCInst.
2253 // This function only handles the 32 bit variants of ins, as dins
2254 // variants are handled differently.
2255 int Pos = Inst.getOperand(2).getImm();
2256 int Size = (int) Insn - Pos + 1;
2257 Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Size)));
2258 return MCDisassembler::Success;
2259}
2260
2261static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn,
2262 uint64_t Address,
2263 const MCDisassembler *Decoder) {
2264 Inst.addOperand(MCOperand::createImm(SignExtend32<19>(Insn) * 4));
2265 return MCDisassembler::Success;
2266}
2267
2268static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn,
2269 uint64_t Address,
2270 const MCDisassembler *Decoder) {
2271 Inst.addOperand(MCOperand::createImm(SignExtend32<18>(Insn) * 8));
2272 return MCDisassembler::Success;
2273}
2274
2275static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn, uint64_t Address,
2276 const MCDisassembler *Decoder) {
2277 int32_t DecodedValue;
2278 switch (Insn) {
2279 case 0: DecodedValue = 256; break;
2280 case 1: DecodedValue = 257; break;
2281 case 510: DecodedValue = -258; break;
2282 case 511: DecodedValue = -257; break;
2283 default: DecodedValue = SignExtend32<9>(Insn); break;
2284 }
2285 Inst.addOperand(MCOperand::createImm(DecodedValue * 4));
2286 return MCDisassembler::Success;
2287}
2288
2289static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn,
2290 uint64_t Address,
2291 const MCDisassembler *Decoder) {
2292 // Insn must be >= 0, since it is unsigned that condition is always true.
2293 assert(Insn < 16);
2294 int32_t DecodedValues[] = {128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64,
2295 255, 32768, 65535};
2296 Inst.addOperand(MCOperand::createImm(DecodedValues[Insn]));
2297 return MCDisassembler::Success;
2298}
2299
2300static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Insn,
2301 uint64_t Address,
2302 const MCDisassembler *Decoder) {
2303 unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5,
2304 Mips::S6, Mips::S7, Mips::FP};
2305 unsigned RegNum;
2306
2307 unsigned RegLst = fieldFromInstruction(Insn, 21, 5);
2308
2309 // Empty register lists are not allowed.
2310 if (RegLst == 0)
2311 return MCDisassembler::Fail;
2312
2313 RegNum = RegLst & 0xf;
2314
2315 // RegLst values 10-15, and 26-31 are reserved.
2316 if (RegNum > 9)
2317 return MCDisassembler::Fail;
2318
2319 for (unsigned i = 0; i < RegNum; i++)
2320 Inst.addOperand(MCOperand::createReg(Regs[i]));
2321
2322 if (RegLst & 0x10)
2323 Inst.addOperand(MCOperand::createReg(Mips::RA));
2324
2325 return MCDisassembler::Success;
2326}
2327
2328static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn,
2329 uint64_t Address,
2330 const MCDisassembler *Decoder) {
2331 unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3};
2332 unsigned RegLst;
2333 switch(Inst.getOpcode()) {
2334 default:
2335 RegLst = fieldFromInstruction(Insn, 4, 2);
2336 break;
2337 case Mips::LWM16_MMR6:
2338 case Mips::SWM16_MMR6:
2339 RegLst = fieldFromInstruction(Insn, 8, 2);
2340 break;
2341 }
2342 unsigned RegNum = RegLst & 0x3;
2343
2344 for (unsigned i = 0; i <= RegNum; i++)
2345 Inst.addOperand(MCOperand::createReg(Regs[i]));
2346
2347 Inst.addOperand(MCOperand::createReg(Mips::RA));
2348
2349 return MCDisassembler::Success;
2350}
2351
2352static DecodeStatus DecodeMovePOperands(MCInst &Inst, unsigned Insn,
2353 uint64_t Address,
2354 const MCDisassembler *Decoder) {
2355 unsigned RegPair = fieldFromInstruction(Insn, 7, 3);
2356 if (DecodeMovePRegPair(Inst, RegPair, Address, Decoder) ==
2357 MCDisassembler::Fail)
2358 return MCDisassembler::Fail;
2359
2360 unsigned RegRs;
2361 if (static_cast<const MipsDisassembler*>(Decoder)->hasMips32r6())
2362 RegRs = fieldFromInstruction(Insn, 0, 2) |
2363 (fieldFromInstruction(Insn, 3, 1) << 2);
2364 else
2365 RegRs = fieldFromInstruction(Insn, 1, 3);
2366 if (DecodeGPRMM16MovePRegisterClass(Inst, RegRs, Address, Decoder) ==
2367 MCDisassembler::Fail)
2368 return MCDisassembler::Fail;
2369
2370 unsigned RegRt = fieldFromInstruction(Insn, 4, 3);
2371 if (DecodeGPRMM16MovePRegisterClass(Inst, RegRt, Address, Decoder) ==
2372 MCDisassembler::Fail)
2373 return MCDisassembler::Fail;
2374
2375 return MCDisassembler::Success;
2376}
2377
2378static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned RegPair,
2379 uint64_t Address,
2380 const MCDisassembler *Decoder) {
2381 switch (RegPair) {
2382 default:
2383 return MCDisassembler::Fail;
2384 case 0:
2385 Inst.addOperand(MCOperand::createReg(Mips::A1));
2386 Inst.addOperand(MCOperand::createReg(Mips::A2));
2387 break;
2388 case 1:
2389 Inst.addOperand(MCOperand::createReg(Mips::A1));
2390 Inst.addOperand(MCOperand::createReg(Mips::A3));
2391 break;
2392 case 2:
2393 Inst.addOperand(MCOperand::createReg(Mips::A2));
2394 Inst.addOperand(MCOperand::createReg(Mips::A3));
2395 break;
2396 case 3:
2397 Inst.addOperand(MCOperand::createReg(Mips::A0));
2398 Inst.addOperand(MCOperand::createReg(Mips::S5));
2399 break;
2400 case 4:
2401 Inst.addOperand(MCOperand::createReg(Mips::A0));
2402 Inst.addOperand(MCOperand::createReg(Mips::S6));
2403 break;
2404 case 5:
2405 Inst.addOperand(MCOperand::createReg(Mips::A0));
2406 Inst.addOperand(MCOperand::createReg(Mips::A1));
2407 break;
2408 case 6:
2409 Inst.addOperand(MCOperand::createReg(Mips::A0));
2410 Inst.addOperand(MCOperand::createReg(Mips::A2));
2411 break;
2412 case 7:
2413 Inst.addOperand(MCOperand::createReg(Mips::A0));
2414 Inst.addOperand(MCOperand::createReg(Mips::A3));
2415 break;
2416 }
2417
2418 return MCDisassembler::Success;
2419}
2420
2421static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn,
2422 uint64_t Address,
2423 const MCDisassembler *Decoder) {
2424 Inst.addOperand(MCOperand::createImm(SignExtend32<25>(Insn << 2)));
2425 return MCDisassembler::Success;
2426}
2427
2428template <typename InsnType>
2429static DecodeStatus DecodeBgtzGroupBranchMMR6(MCInst &MI, InsnType insn,
2430 uint64_t Address,
2431 const MCDisassembler *Decoder) {
2432 // We have:
2433 // 0b000111 ttttt sssss iiiiiiiiiiiiiiii
2434 // Invalid if rt == 0
2435 // BGTZALC_MMR6 if rs == 0 && rt != 0
2436 // BLTZALC_MMR6 if rs != 0 && rs == rt
2437 // BLTUC_MMR6 if rs != 0 && rs != rt
2438
2439 InsnType Rt = fieldFromInstruction(insn, 21, 5);
2440 InsnType Rs = fieldFromInstruction(insn, 16, 5);
2441 InsnType Imm = 0;
2442 bool HasRs = false;
2443 bool HasRt = false;
2444
2445 if (Rt == 0)
2446 return MCDisassembler::Fail;
2447 else if (Rs == 0) {
2448 MI.setOpcode(Mips::BGTZALC_MMR6);
2449 HasRt = true;
2450 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
2451 }
2452 else if (Rs == Rt) {
2453 MI.setOpcode(Mips::BLTZALC_MMR6);
2454 HasRs = true;
2455 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
2456 }
2457 else {
2458 MI.setOpcode(Mips::BLTUC_MMR6);
2459 HasRs = true;
2460 HasRt = true;
2461 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
2462 }
2463
2464 if (HasRs)
2465 MI.addOperand(
2466 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rs)));
2467
2468 if (HasRt)
2469 MI.addOperand(
2470 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rt)));
2471
2472 MI.addOperand(MCOperand::createImm(Imm));
2473
2474 return MCDisassembler::Success;
2475}
2476
2477template <typename InsnType>
2478static DecodeStatus DecodeBlezGroupBranchMMR6(MCInst &MI, InsnType insn,
2479 uint64_t Address,
2480 const MCDisassembler *Decoder) {
2481 // We have:
2482 // 0b000110 ttttt sssss iiiiiiiiiiiiiiii
2483 // Invalid if rt == 0
2484 // BLEZALC_MMR6 if rs == 0 && rt != 0
2485 // BGEZALC_MMR6 if rs == rt && rt != 0
2486 // BGEUC_MMR6 if rs != rt && rs != 0 && rt != 0
2487
2488 InsnType Rt = fieldFromInstruction(insn, 21, 5);
2489 InsnType Rs = fieldFromInstruction(insn, 16, 5);
2490 InsnType Imm = 0;
2491 bool HasRs = false;
2492
2493 if (Rt == 0)
2494 return MCDisassembler::Fail;
2495 else if (Rs == 0) {
2496 MI.setOpcode(Mips::BLEZALC_MMR6);
2497 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
2498 }
2499 else if (Rs == Rt) {
2500 MI.setOpcode(Mips::BGEZALC_MMR6);
2501 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
2502 }
2503 else {
2504 HasRs = true;
2505 MI.setOpcode(Mips::BGEUC_MMR6);
2506 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
2507 }
2508
2509 if (HasRs)
2510 MI.addOperand(
2511 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rs)));
2512 MI.addOperand(
2513 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rt)));
2514
2515 MI.addOperand(MCOperand::createImm(Imm));
2516
2517 return MCDisassembler::Success;
2518}
2519
2520// This instruction does not have a working decoder, and needs to be
2521// fixed. This "fixme" function was introduced to keep the backend compiling,
2522// while making changes to tablegen code.
2523static DecodeStatus DecodeFIXMEInstruction(MCInst &Inst, unsigned Insn,
2524 uint64_t Address,
2525 const MCDisassembler *Decoder) {
2526 return MCDisassembler::Fail;
2527}
Insn
SmallVector< AArch64_IMM::ImmInsnModel, 4 > Insn
Definition: AArch64MIPeepholeOpt.cpp:167
D
static GCRegistry::Add< StatepointGC > D("statepoint-example", "an example strategy for statepoint")
LLVM_EXTERNAL_VISIBILITY
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:128
LLVM_DEBUG
#define LLVM_DEBUG(...)
Definition: Debug.h:106
Size
uint64_t Size
Definition: ELFObjHandler.cpp:81
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:112
DecodePOOL16BEncodedField
static DecodeStatus DecodePOOL16BEncodedField(MCInst &Inst, unsigned Value, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:2224
DecodeFMemCop2MMR6
static DecodeStatus DecodeFMemCop2MMR6(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:1933
DecodeSimm19Lsl2
static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:2261
DecodeMemEVA
static DecodeStatus DecodeMemEVA(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:1481
DecodeBgtzlGroupBranch
static DecodeStatus DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:870
DecodeRegListOperand
static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:2300
readInstruction32
static DecodeStatus readInstruction32(ArrayRef< uint8_t > Bytes, uint64_t Address, uint64_t &Size, uint32_t &Insn, bool IsBigEndian, bool IsMicroMips)
Read four bytes from the ArrayRef and return 32 bit word sorted according to the given endianness.
Definition: MipsDisassembler.cpp:1126
DecodeBranchTarget21
static DecodeStatus DecodeBranchTarget21(MCInst &Inst, unsigned Offset, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:2126
DecodeJumpTargetXMM
static DecodeStatus DecodeJumpTargetXMM(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:2194
DecodeFGR32RegisterClass
static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:1419
DecodeCCRRegisterClass
static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:1430
DecodeCOP2RegisterClass
static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:2091
getReg
static unsigned getReg(const MCDisassembler *D, unsigned RC, unsigned RegNo)
Definition: MipsDisassembler.cpp:520
DecodeFCCRegisterClass
static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:1440
DecodeCacheOpMM
static DecodeStatus DecodeCacheOpMM(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:1532
readInstruction16
static DecodeStatus readInstruction16(ArrayRef< uint8_t > Bytes, uint64_t Address, uint64_t &Size, uint32_t &Insn, bool IsBigEndian)
Read two bytes from the ArrayRef and return 16 bit halfword sorted according to the given endianness.
Definition: MipsDisassembler.cpp:1106
DecodeGPRMM16RegisterClass
static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:1353
DecodeSImmWithOffsetAndScale
static DecodeStatus DecodeSImmWithOffsetAndScale(MCInst &Inst, unsigned Value, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:2243
DecodeSimm23Lsl2
static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:2421
DecodeGPRMM16MovePRegisterClass
static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:1374
DecodeBranchTarget1SImm16
static DecodeStatus DecodeBranchTarget1SImm16(MCInst &Inst, unsigned Offset, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:2110
DecodeMemMMImm9
static DecodeStatus DecodeMemMMImm9(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:1778
DecodeMovePOperands
static DecodeStatus DecodeMovePOperands(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:2352
DecodeCRC
static DecodeStatus DecodeCRC(MCInst &MI, InsnType Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:1091
DecodePOP75GroupBranchMMR6
static DecodeStatus DecodePOP75GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:788
DecodeDINS
static DecodeStatus DecodeDINS(MCInst &MI, InsnType Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:1049
DecodeMSA128Mem
static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:1620
DecodePrefeOpMM
static DecodeStatus DecodePrefeOpMM(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:1548
DecodeCPU16RegsRegisterClass
static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:1337
DecodeMSA128WRegisterClass
static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:2047
DecodeBranchTarget26
static DecodeStatus DecodeBranchTarget26(MCInst &Inst, unsigned Offset, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:2144
DecodeFMem
static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:1849
DecodeCacheOp
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Definition: MipsDisassembler.cpp:1517
DecodeSyncI_MM
static DecodeStatus DecodeSyncI_MM(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:1593
DecodeLoadByte15
static DecodeStatus DecodeLoadByte15(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:1500
DecodeSimm9SP
static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:2275
DecodeFMem2
static DecodeStatus DecodeFMem2(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:1884
DecodeUImmWithOffsetAndScale
static DecodeStatus DecodeUImmWithOffsetAndScale(MCInst &Inst, unsigned Value, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:2233
DecodeMemMMImm12
static DecodeStatus DecodeMemMMImm12(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:1798
DecodeDEXT
static DecodeStatus DecodeDEXT(MCInst &MI, InsnType Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:1007
DecodeGPRMM16ZeroRegisterClass
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Definition: MipsDisassembler.cpp:1364
DecodePtrRegisterClass
static DecodeStatus DecodePtrRegisterClass(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:1393
DecodeLi16Imm
static DecodeStatus DecodeLi16Imm(MCInst &Inst, unsigned Value, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:2214
createMipselDisassembler
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Definition: MipsDisassembler.cpp:499
DecodeSimm18Lsl3
static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:2268
DecodeFMem3
static DecodeStatus DecodeFMem3(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:1900
DecodeBlezlGroupBranch
static DecodeStatus DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:827
DecodeCOP0RegisterClass
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Definition: MipsDisassembler.cpp:2080
DecodeBranchTarget
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Definition: MipsDisassembler.cpp:2102
DecodeMemMMReglistImm4Lsl2
static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:1754
DecodeBgtzGroupBranch
static DecodeStatus DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:914
DecodeBranchTargetMM
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Definition: MipsDisassembler.cpp:2169
DecodePOP35GroupBranchMMR6
static DecodeStatus DecodePOP35GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:642
DecodeFIXMEInstruction
static DecodeStatus DecodeFIXMEInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:2523
DecodeBranchTarget10MM
static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst, unsigned Offset, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:2161
DecodeANDI16Imm
static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:2289
DecodeMSA128DRegisterClass
static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:2058
DecodeMemMMImm4
static DecodeStatus DecodeMemMMImm4(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:1667
createMipsDisassembler
static MCDisassembler * createMipsDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
Definition: MipsDisassembler.cpp:492
DecodeGPR32RegisterClass
static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:1383
DecodeMSA128BRegisterClass
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Definition: MipsDisassembler.cpp:2025
DecodeHWRegsRegisterClass
static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:1971
DecodeDaddiGroupBranch
static DecodeStatus DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:676
DecodeMovePRegPair
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Definition: MipsDisassembler.cpp:2378
DecodeDAHIDATIMMR6
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Definition: MipsDisassembler.cpp:574
DecodeBranchTarget21MM
static DecodeStatus DecodeBranchTarget21MM(MCInst &Inst, unsigned Offset, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:2135
DecodeBranchTarget26MM
static DecodeStatus DecodeBranchTarget26MM(MCInst &Inst, unsigned Offset, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:2177
DecodeAFGR64RegisterClass
static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:1981
DecodeDAHIDATI
static DecodeStatus DecodeDAHIDATI(MCInst &MI, InsnType insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:589
DecodeLO32DSPRegisterClass
static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:2014
DecodeSpecial3LlSc
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Definition: MipsDisassembler.cpp:1950
DecodeHI32DSPRegisterClass
static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:2003
DecodeStatus
MCDisassembler::DecodeStatus DecodeStatus
Definition: MipsDisassembler.cpp:35
DecodeSynciR6
static DecodeStatus DecodeSynciR6(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:1607
DecodeUImmWithOffset
static DecodeStatus DecodeUImmWithOffset(MCInst &Inst, unsigned Value, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:351
DecodeRegListOperand16
static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:2328
DecodeAddiGroupBranch
static DecodeStatus DecodeAddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:603
DecodeMemMMSPImm5Lsl2
static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:1724
DecodeAddiur2Simm7
static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst, unsigned Value, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:2202
DecodeMSACtrlRegisterClass
static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:2069
DecodeMSA128HRegisterClass
static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:2036
DecodeFMemMMR2
static DecodeStatus DecodeFMemMMR2(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:1865
DecodeCacheeOp_CacheOpR6
static DecodeStatus DecodeCacheeOp_CacheOpR6(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:1564
DecodeMemMMImm16
static DecodeStatus DecodeMemMMImm16(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:1832
DecodeBranchTarget7MM
static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst, unsigned Offset, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:2153
DecodeFGR64RegisterClass
static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:1408
DecodeGPR64RegisterClass
static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:1342
DecodeBlezGroupBranchMMR6
static DecodeStatus DecodeBlezGroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:2478
DecodeJumpTargetMM
static DecodeStatus DecodeJumpTargetMM(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:2186
DecodePOP37GroupBranchMMR6
static DecodeStatus DecodePOP37GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:715
DecodeSyncI
static DecodeStatus DecodeSyncI(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:1580
DecodeJumpTarget
static DecodeStatus DecodeJumpTarget(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:2118
DecodeACC64DSPRegisterClass
static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:1992
DecodeFMemCop2R6
static DecodeStatus DecodeFMemCop2R6(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:1916
DecodeBgtzGroupBranchMMR6
static DecodeStatus DecodeBgtzGroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:2429
DecodePOP65GroupBranchMMR6
static DecodeStatus DecodePOP65GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:749
DecodeDSPRRegisterClass
static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:1402
DecodeInsSize
static DecodeStatus DecodeInsSize(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:2250
LLVMInitializeMipsDisassembler
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeMipsDisassembler()
Definition: MipsDisassembler.cpp:506
DecodeBlezGroupBranch
static DecodeStatus DecodeBlezGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:963
DecodeMem
static DecodeStatus DecodeMem(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:1461
DecodeFGRCCRegisterClass
static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:1450
DecodeINSVE_DF
static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address, const MCDisassembler *Decoder)
INSVE_[BHWD] have an implicit operand that the generated decoder doesn't handle.
Definition: MipsDisassembler.cpp:526
DecodeMemMMGPImm7Lsl2
static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:1739
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
llvm::ArrayRef::size
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:168
llvm::MCContext
Context object for machine code objects.
Definition: MCContext.h:83
llvm::MCDisassembler
Superclass for all disassemblers.
Definition: MCDisassembler.h:84
llvm::MCDisassembler::DecodeStatus
DecodeStatus
Ternary decode status.
Definition: MCDisassembler.h:108
llvm::MCDisassembler::getInstruction
virtual DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address, raw_ostream &CStream) const =0
Returns the disassembly of a single instruction.
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:185
llvm::MCInst::getOpcode
unsigned getOpcode() const
Definition: MCInst.h:199
llvm::MCInst::addOperand
void addOperand(const MCOperand Op)
Definition: MCInst.h:211
llvm::MCInst::getOperand
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:207
llvm::MCOperand::getImm
int64_t getImm() const
Definition: MCInst.h:81
llvm::MCOperand::createReg
static MCOperand createReg(MCRegister Reg)
Definition: MCInst.h:135
llvm::MCOperand::createImm
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:142
llvm::MCRegisterInfo
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Definition: MCRegisterInfo.h:149
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition: MCSubtargetInfo.h:76
llvm::MCSubtargetInfo::hasFeature
bool hasFeature(unsigned Feature) const
Definition: MCSubtargetInfo.h:121
llvm::Target
Target - Wrapper for Target specific information.
Definition: TargetRegistry.h:144
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:52
uint32_t
uint64_t
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
llvm::ms_demangle::QualifierMangleMode::Result
@ Result
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::Offset
@ Offset
Definition: DWP.cpp:480
llvm::getTheMips64Target
Target & getTheMips64Target()
Definition: MipsTargetInfo.cpp:21
llvm::dbgs
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
llvm::getTheMips64elTarget
Target & getTheMips64elTarget()
Definition: MipsTargetInfo.cpp:25
llvm::getTheMipselTarget
Target & getTheMipselTarget()
Definition: MipsTargetInfo.cpp:17
llvm::SignExtend64
constexpr int64_t SignExtend64(uint64_t x)
Sign-extend the number in the bottom B bits of X to a 64-bit integer.
Definition: MathExtras.h:581
llvm::getTheMipsTarget
Target & getTheMipsTarget()
Definition: MipsTargetInfo.cpp:13
raw_ostream.h
llvm::TargetRegistry::RegisterMCDisassembler
static void RegisterMCDisassembler(Target &T, Target::MCDisassemblerCtorTy Fn)
RegisterMCDisassembler - Register a MCDisassembler implementation for the given target.
Definition: TargetRegistry.h:878
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