|
| file | AMDGPU.h [code] |
| |
| file | AMDGPUAliasAnalysis.cpp [code] |
| | This is the AMGPU address space based alias analysis pass.
|
| |
| file | AMDGPUAliasAnalysis.h [code] |
| | This is the AMGPU address space based alias analysis pass.
|
| |
| file | AMDGPUAlwaysInlinePass.cpp [code] |
| | This pass marks all internal functions as always_inline and creates duplicates of all other functions and marks the duplicates as always_inline.
|
| |
| file | AMDGPUAnnotateKernelFeatures.cpp [code] |
| |
| file | AMDGPUAnnotateUniformValues.cpp [code] |
| | This pass adds amdgpu.uniform metadata to IR values so this information can be used during instruction selection.
|
| |
| file | AMDGPUArgumentUsageInfo.cpp [code] |
| |
| file | AMDGPUArgumentUsageInfo.h [code] |
| |
| file | AMDGPUAsanInstrumentation.cpp [code] |
| |
| file | AMDGPUAsanInstrumentation.h [code] |
| |
| file | AMDGPUAsmPrinter.cpp [code] |
| | The AMDGPUAsmPrinter is used to print both assembly string and also binary code.
|
| |
| file | AMDGPUAsmPrinter.h [code] |
| | AMDGPU Assembly printer class.
|
| |
| file | AMDGPUAtomicOptimizer.cpp [code] |
| | This pass optimizes atomic operations by using a single lane of a wavefront to perform the atomic operation, thus reducing contention on that memory location.
|
| |
| file | AMDGPUAttributor.cpp [code] |
| |
| file | AMDGPUCallLowering.cpp [code] |
| | This file implements the lowering of LLVM calls to machine code calls for GlobalISel.
|
| |
| file | AMDGPUCallLowering.h [code] |
| | This file describes how to lower LLVM calls to machine code calls.
|
| |
| file | AMDGPUCodeGenPrepare.cpp [code] |
| | This pass does misc.
|
| |
| file | AMDGPUCombinerHelper.cpp [code] |
| |
| file | AMDGPUCombinerHelper.h [code] |
| | This contains common combine transformations that may be used in a combine pass.
|
| |
| file | AMDGPUCtorDtorLowering.cpp [code] |
| | This pass creates a unified init and fini kernel with the required metadata.
|
| |
| file | AMDGPUCtorDtorLowering.h [code] |
| |
| file | AMDGPUExportClustering.cpp [code] |
| |
| file | AMDGPUExportClustering.h [code] |
| |
| file | AMDGPUFrameLowering.cpp [code] |
| |
| file | AMDGPUFrameLowering.h [code] |
| | Interface to describe a layout of a stack frame on an AMDGPU target.
|
| |
| file | AMDGPUGlobalISelDivergenceLowering.cpp [code] |
| | GlobalISel pass that selects divergent i1 phis as lane mask phis.
|
| |
| file | AMDGPUGlobalISelUtils.cpp [code] |
| |
| file | AMDGPUGlobalISelUtils.h [code] |
| |
| file | AMDGPUHSAMetadataStreamer.cpp [code] |
| | AMDGPU HSA Metadata Streamer.
|
| |
| file | AMDGPUHSAMetadataStreamer.h [code] |
| | AMDGPU HSA Metadata Streamer.
|
| |
| file | AMDGPUIGroupLP.cpp [code] |
| |
| file | AMDGPUIGroupLP.h [code] |
| |
| file | AMDGPUImageIntrinsicOptimizer.cpp [code] |
| |
| file | AMDGPUInsertDelayAlu.cpp [code] |
| | Insert s_delay_alu instructions to avoid stalls on GFX11+.
|
| |
| file | AMDGPUInsertSingleUseVDST.cpp [code] |
| | Insert s_singleuse_vdst instructions on GFX11.5+ to mark regions of VALU instructions that produce single-use VGPR values.
|
| |
| file | AMDGPUInstCombineIntrinsic.cpp [code] |
| |
| file | AMDGPUInstrInfo.cpp [code] |
| | Implementation of the TargetInstrInfo class that is common to all AMD GPUs.
|
| |
| file | AMDGPUInstrInfo.h [code] |
| | Contains the definition of a TargetInstrInfo class that is common to all AMD GPUs.
|
| |
| file | AMDGPUInstructionSelector.cpp [code] |
| | This file implements the targeting of the InstructionSelector class for AMDGPU.
|
| |
| file | AMDGPUInstructionSelector.h [code] |
| | This file declares the targeting of the InstructionSelector class for AMDGPU.
|
| |
| file | AMDGPUISelDAGToDAG.cpp [code] |
| | Defines an instruction selector for the AMDGPU target.
|
| |
| file | AMDGPUISelDAGToDAG.h [code] |
| | Defines an instruction selector for the AMDGPU target.
|
| |
| file | AMDGPUISelLowering.cpp [code] |
| | This is the parent TargetLowering class for hardware code gen targets.
|
| |
| file | AMDGPUISelLowering.h [code] |
| | Interface definition of the TargetLowering class that is common to all AMD GPUs.
|
| |
| file | AMDGPULateCodeGenPrepare.cpp [code] |
| | This pass does misc.
|
| |
| file | AMDGPULegalizerInfo.cpp [code] |
| | This file implements the targeting of the Machinelegalizer class for AMDGPU.
|
| |
| file | AMDGPULegalizerInfo.h [code] |
| | This file declares the targeting of the Machinelegalizer class for AMDGPU.
|
| |
| file | AMDGPULibCalls.cpp [code] |
| | This file does AMD library function optimizations.
|
| |
| file | AMDGPULibFunc.cpp [code] |
| |
| file | AMDGPULibFunc.h [code] |
| |
| file | AMDGPULowerBufferFatPointers.cpp [code] |
| |
| file | AMDGPULowerKernelArguments.cpp [code] |
| |
| file | AMDGPULowerKernelAttributes.cpp [code] |
| |
| file | AMDGPULowerModuleLDSPass.cpp [code] |
| |
| file | AMDGPUMachineCFGStructurizer.cpp [code] |
| |
| file | AMDGPUMachineFunction.cpp [code] |
| |
| file | AMDGPUMachineFunction.h [code] |
| |
| file | AMDGPUMachineModuleInfo.cpp [code] |
| | AMDGPU Machine Module Info.
|
| |
| file | AMDGPUMachineModuleInfo.h [code] |
| | AMDGPU Machine Module Info.
|
| |
| file | AMDGPUMacroFusion.cpp [code] |
| |
| file | AMDGPUMacroFusion.h [code] |
| |
| file | AMDGPUMarkLastScratchLoad.cpp [code] |
| |
| file | AMDGPUMCInstLower.cpp [code] |
| | Code to lower AMDGPU MachineInstrs to their corresponding MCInst.
|
| |
| file | AMDGPUMCInstLower.h [code] |
| | Header of lower AMDGPU MachineInstrs to their corresponding MCInst.
|
| |
| file | AMDGPUMemoryUtils.cpp [code] |
| |
| file | AMDGPUMemoryUtils.h [code] |
| |
| file | AMDGPUMIRFormatter.cpp [code] |
| | Implementation of AMDGPU overrides of MIRFormatter.
|
| |
| file | AMDGPUMIRFormatter.h [code] |
| | AMDGPU specific overrides of MIRFormatter.
|
| |
| file | AMDGPUOpenCLEnqueuedBlockLowering.cpp [code] |
| |
| file | AMDGPUPerfHintAnalysis.cpp [code] |
| | Analyzes if a function potentially memory bound and if a kernel kernel may benefit from limiting number of waves to reduce cache thrashing.
|
| |
| file | AMDGPUPerfHintAnalysis.h [code] |
| | Analyzes if a function potentially memory bound and if a kernel kernel may benefit from limiting number of waves to reduce cache thrashing.
|
| |
| file | AMDGPUPostLegalizerCombiner.cpp [code] |
| |
| file | AMDGPUPreLegalizerCombiner.cpp [code] |
| |
| file | AMDGPUPrintfRuntimeBinding.cpp [code] |
| |
| file | AMDGPUPromoteAlloca.cpp [code] |
| |
| file | AMDGPUPromoteKernelArguments.cpp [code] |
| |
| file | AMDGPUPTNote.h [code] |
| | Enums and constants for AMDGPU PT_NOTE sections.
|
| |
| file | AMDGPURegBankCombiner.cpp [code] |
| |
| file | AMDGPURegBankSelect.cpp [code] |
| |
| file | AMDGPURegBankSelect.h [code] |
| |
| file | AMDGPURegisterBankInfo.cpp [code] |
| | This file implements the targeting of the RegisterBankInfo class for AMDGPU.
|
| |
| file | AMDGPURegisterBankInfo.h [code] |
| | This file declares the targeting of the RegisterBankInfo class for AMDGPU.
|
| |
| file | AMDGPURemoveIncompatibleFunctions.cpp [code] |
| | This pass replaces all uses of functions that use GPU features incompatible with the current GPU with null then deletes the function.
|
| |
| file | AMDGPUResourceUsageAnalysis.cpp [code] |
| | Analyzes how many registers and other resources are used by functions.
|
| |
| file | AMDGPUResourceUsageAnalysis.h [code] |
| | Analyzes how many registers and other resources are used by functions.
|
| |
| file | AMDGPURewriteOutArguments.cpp [code] |
| |
| file | AMDGPURewriteUndefForPHI.cpp [code] |
| |
| file | AMDGPUSetWavePriority.cpp [code] |
| | Pass to temporarily raise the wave priority beginning the start of the shader function until its last VMEM instructions to allow younger waves to issue their VMEM instructions as well.
|
| |
| file | AMDGPUSplitModule.cpp [code] |
| |
| file | AMDGPUSplitModule.h [code] |
| |
| file | AMDGPUSubtarget.cpp [code] |
| | Implements the AMDGPU specific subclass of TargetSubtarget.
|
| |
| file | AMDGPUSubtarget.h [code] |
| | Base class for AMDGPU specific classes of TargetSubtarget.
|
| |
| file | AMDGPUTargetMachine.cpp [code] |
| | This file contains both AMDGPU target machine and the CodeGen pass builder.
|
| |
| file | AMDGPUTargetMachine.h [code] |
| | The AMDGPU TargetMachine interface definition for hw codegen targets.
|
| |
| file | AMDGPUTargetObjectFile.cpp [code] |
| |
| file | AMDGPUTargetObjectFile.h [code] |
| | This file declares the AMDGPU-specific subclass of TargetLoweringObjectFile.
|
| |
| file | AMDGPUTargetTransformInfo.cpp [code] |
| |
| file | AMDGPUTargetTransformInfo.h [code] |
| | This file a TargetTransformInfo::Concept conforming object specific to the AMDGPU target machine.
|
| |
| file | AMDGPUUnifyDivergentExitNodes.cpp [code] |
| |
| file | AMDGPUUnifyDivergentExitNodes.h [code] |
| |
| file | AMDGPUUnifyMetadata.cpp [code] |
| |
| file | AMDKernelCodeT.h [code] |
| |
| file | GCNCreateVOPD.cpp [code] |
| | Combine VALU pairs into VOPD instructions Only works on wave32 Has register requirements, we reject creating VOPD if the requirements are not met.
|
| |
| file | GCNDPPCombine.cpp [code] |
| |
| file | GCNHazardRecognizer.cpp [code] |
| |
| file | GCNHazardRecognizer.h [code] |
| |
| file | GCNILPSched.cpp [code] |
| |
| file | GCNIterativeScheduler.cpp [code] |
| | This file implements the class GCNIterativeScheduler.
|
| |
| file | GCNIterativeScheduler.h [code] |
| | This file defines the class GCNIterativeScheduler, which uses an iterative approach to find a best schedule for GCN architecture.
|
| |
| file | GCNMinRegStrategy.cpp [code] |
| | This file defines and implements the class GCNMinRegScheduler, which implements an experimental, simple scheduler whose main goal is to learn ways about consuming less possible registers for a region.
|
| |
| file | GCNNSAReassign.cpp [code] |
| | Try to reassign registers on GFX10+ from non-sequential to sequential in NSA image instructions.
|
| |
| file | GCNPreRALongBranchReg.cpp [code] |
| |
| file | GCNPreRAOptimizations.cpp [code] |
| | This pass combines split register tuple initialization into a single pseudo:
|
| |
| file | GCNRegPressure.cpp [code] |
| | This file implements the GCNRegPressure class.
|
| |
| file | GCNRegPressure.h [code] |
| | This file defines the GCNRegPressure class, which tracks registry pressure by bookkeeping number of SGPR/VGPRs used, weights for large SGPR/VGPRs.
|
| |
| file | GCNRewritePartialRegUses.cpp [code] |
| | RenameIndependentSubregs pass leaves large partially used super registers, for example: undef %0.sub4:VReg_1024 = ... %0.sub5:VReg_1024 = ... %0.sub6:VReg_1024 = ... %0.sub7:VReg_1024 = ... use %0.sub4_sub5_sub6_sub7 use %0.sub6_sub7.
|
| |
| file | GCNSchedStrategy.cpp [code] |
| | This contains a MachineSchedStrategy implementation for maximizing wave occupancy on GCN hardware.
|
| |
| file | GCNSchedStrategy.h [code] |
| |
| file | GCNSubtarget.h [code] |
| | AMD GCN specific subclass of TargetSubtarget.
|
| |
| file | GCNVOPDUtils.cpp [code] |
| |
| file | GCNVOPDUtils.h [code] |
| |
| file | R600.h [code] |
| |
| file | R600AsmPrinter.cpp [code] |
| | The R600AsmPrinter is used to print both assembly string and also binary code.
|
| |
| file | R600AsmPrinter.h [code] |
| | R600 Assembly printer class.
|
| |
| file | R600ClauseMergePass.cpp [code] |
| | R600EmitClauseMarker pass emits CFAlu instruction in a conservative manner.
|
| |
| file | R600ControlFlowFinalizer.cpp [code] |
| | This pass compute turns all control flow pseudo instructions into native one computing their address on the fly; it also sets STACK_SIZE info.
|
| |
| file | R600Defines.h [code] |
| |
| file | R600EmitClauseMarkers.cpp [code] |
| | Add CF_ALU.
|
| |
| file | R600ExpandSpecialInstrs.cpp [code] |
| | Vector, Reduction, and Cube instructions need to fill the entire instruction group to work correctly.
|
| |
| file | R600FrameLowering.cpp [code] |
| |
| file | R600FrameLowering.h [code] |
| |
| file | R600InstrInfo.cpp [code] |
| | R600 Implementation of TargetInstrInfo.
|
| |
| file | R600InstrInfo.h [code] |
| | Interface definition for R600InstrInfo.
|
| |
| file | R600ISelDAGToDAG.cpp [code] |
| | Defines an instruction selector for the R600 subtarget.
|
| |
| file | R600ISelLowering.cpp [code] |
| | Custom DAG lowering for R600.
|
| |
| file | R600ISelLowering.h [code] |
| | R600 DAG Lowering interface definition.
|
| |
| file | R600MachineCFGStructurizer.cpp [code] |
| |
| file | R600MachineFunctionInfo.cpp [code] |
| |
| file | R600MachineFunctionInfo.h [code] |
| |
| file | R600MachineScheduler.cpp [code] |
| | R600 Machine Scheduler interface.
|
| |
| file | R600MachineScheduler.h [code] |
| | R600 Machine Scheduler interface.
|
| |
| file | R600MCInstLower.cpp [code] |
| | Code to lower R600 MachineInstrs to their corresponding MCInst.
|
| |
| file | R600OpenCLImageTypeLoweringPass.cpp [code] |
| | This pass resolves calls to OpenCL image attribute, image resource ID and sampler resource ID getter functions.
|
| |
| file | R600OptimizeVectorRegisters.cpp [code] |
| | This pass merges inputs of swizzeable instructions into vector sharing common data and/or have enough undef subreg using swizzle abilities.
|
| |
| file | R600Packetizer.cpp [code] |
| | This pass implements instructions packetization for R600.
|
| |
| file | R600RegisterInfo.cpp [code] |
| | R600 implementation of the TargetRegisterInfo class.
|
| |
| file | R600RegisterInfo.h [code] |
| | Interface definition for R600RegisterInfo.
|
| |
| file | R600Subtarget.cpp [code] |
| | Implements the R600 specific subclass of TargetSubtarget.
|
| |
| file | R600Subtarget.h [code] |
| | AMDGPU R600 specific subclass of TargetSubtarget.
|
| |
| file | R600TargetMachine.cpp [code] |
| | This file contains both AMDGPU-R600 target machine and the CodeGen pass builder.
|
| |
| file | R600TargetMachine.h [code] |
| | The AMDGPU TargetMachine interface definition for hw codegen targets.
|
| |
| file | R600TargetTransformInfo.cpp [code] |
| |
| file | R600TargetTransformInfo.h [code] |
| | This file a TargetTransformInfo::Concept conforming object specific to the R600 target machine.
|
| |
| file | SIAnnotateControlFlow.cpp [code] |
| | Annotates the control flow with hardware specific intrinsics.
|
| |
| file | SIDefines.h [code] |
| |
| file | SIFixSGPRCopies.cpp [code] |
| | Copies from VGPR to SGPR registers are illegal and the register coalescer will sometimes generate these illegal copies in situations like this:
|
| |
| file | SIFixSGPRCopies.h [code] |
| |
| file | SIFixVGPRCopies.cpp [code] |
| | Add implicit use of exec to vector register copies.
|
| |
| file | SIFoldOperands.cpp [code] |
| |
| file | SIFormMemoryClauses.cpp [code] |
| |
| file | SIFrameLowering.cpp [code] |
| |
| file | SIFrameLowering.h [code] |
| |
| file | SIInsertHardClauses.cpp [code] |
| | Insert s_clause instructions to form hard clauses.
|
| |
| file | SIInsertWaitcnts.cpp [code] |
| | Insert wait instructions for memory reads and writes.
|
| |
| file | SIInstrInfo.cpp [code] |
| | SI Implementation of TargetInstrInfo.
|
| |
| file | SIInstrInfo.h [code] |
| | Interface definition for SIInstrInfo.
|
| |
| file | SIISelLowering.cpp [code] |
| | Custom DAG lowering for SI.
|
| |
| file | SIISelLowering.h [code] |
| | SI DAG Lowering interface definition.
|
| |
| file | SILateBranchLowering.cpp [code] |
| | This pass mainly lowers early terminate pseudo instructions.
|
| |
| file | SILoadStoreOptimizer.cpp [code] |
| |
| file | SILowerControlFlow.cpp [code] |
| | This pass lowers the pseudo control flow instructions to real machine instructions.
|
| |
| file | SILowerI1Copies.cpp [code] |
| |
| file | SILowerI1Copies.h [code] |
| | Interface definition of the PhiLoweringHelper class that implements lane mask merging algorithm for divergent i1 phis.
|
| |
| file | SILowerSGPRSpills.cpp [code] |
| |
| file | SILowerWWMCopies.cpp [code] |
| | Lowering the WWM_COPY instructions for various register classes.
|
| |
| file | SIMachineFunctionInfo.cpp [code] |
| |
| file | SIMachineFunctionInfo.h [code] |
| |
| file | SIMachineScheduler.cpp [code] |
| | SI Machine Scheduler interface.
|
| |
| file | SIMachineScheduler.h [code] |
| | SI Machine Scheduler interface.
|
| |
| file | SIMemoryLegalizer.cpp [code] |
| | Memory legalizer - implements memory model.
|
| |
| file | SIModeRegister.cpp [code] |
| | This pass inserts changes to the Mode register settings as required.
|
| |
| file | SIModeRegisterDefaults.cpp [code] |
| |
| file | SIModeRegisterDefaults.h [code] |
| |
| file | SIOptimizeExecMasking.cpp [code] |
| |
| file | SIOptimizeExecMaskingPreRA.cpp [code] |
| | This pass performs exec mask handling peephole optimizations which needs to be done before register allocation to reduce register pressure.
|
| |
| file | SIOptimizeVGPRLiveRange.cpp [code] |
| | This pass tries to remove unnecessary VGPR live ranges in divergent if-else structures and waterfall loops.
|
| |
| file | SIPeepholeSDWA.cpp [code] |
| |
| file | SIPostRABundler.cpp [code] |
| | This pass creates bundles of memory instructions to protect adjacent loads and stores from being rescheduled apart from each other post-RA.
|
| |
| file | SIPreAllocateWWMRegs.cpp [code] |
| | Pass to pre-allocated WWM registers.
|
| |
| file | SIPreEmitPeephole.cpp [code] |
| | This pass performs the peephole optimizations before code emission.
|
| |
| file | SIProgramInfo.cpp [code] |
| | The SIProgramInfo tracks resource usage and hardware flags for kernels and entry functions.
|
| |
| file | SIProgramInfo.h [code] |
| | Defines struct to track resource usage and hardware flags for kernels and entry functions.
|
| |
| file | SIRegisterInfo.cpp [code] |
| | SI implementation of the TargetRegisterInfo class.
|
| |
| file | SIRegisterInfo.h [code] |
| | Interface definition for SIRegisterInfo.
|
| |
| file | SIShrinkInstructions.cpp [code] |
| |
| file | SIWholeQuadMode.cpp [code] |
| | This pass adds instructions to enable whole quad mode (strict or non-strict) for pixel shaders, and strict whole wavefront mode for all programs.
|
| |
