13#ifndef LLVM_LIB_TARGET_AMDGPU_SIMACHINEFUNCTIONINFO_H
14#define LLVM_LIB_TARGET_AMDGPU_SIMACHINEFUNCTIONINFO_H
97 std::optional<unsigned>
Mask;
113 if (
Other.IsRegister)
151 auto Keys = YamlIO.
keys();
158 YamlIO.
setError(
"missing required key 'reg' or 'offset'");
253 YamlIO.
mapOptional(
"fp32-input-denormals",
Mode.FP32InputDenormals,
true);
254 YamlIO.
mapOptional(
"fp32-output-denormals",
Mode.FP32OutputDenormals,
true);
255 YamlIO.
mapOptional(
"fp64-fp16-input-denormals",
Mode.FP64FP16InputDenormals,
true);
256 YamlIO.
mapOptional(
"fp64-fp16-output-denormals",
Mode.FP64FP16OutputDenormals,
true);
362 YamlIO.
mapOptional(
"scratchReservedForDynamicVGPRs",
404 const MCRegister FirstVGPRBlock = AMDGPU::VReg_1024RegClass.getRegister(0);
405 return Reg - FirstVGPRBlock;
420 Register ScratchRSrcReg = AMDGPU::PRIVATE_RSRC_REG;
424 Register FrameOffsetReg = AMDGPU::FP_REG;
429 Register StackPtrOffsetReg = AMDGPU::SP_REG;
439 unsigned PSInputAddr = 0;
440 unsigned PSInputEnable = 0;
451 unsigned BytesInStackArgArea = 0;
453 bool ReturnsVoid =
true;
457 std::pair<unsigned, unsigned> FlatWorkGroupSizes = {0, 0};
461 std::pair<unsigned, unsigned> WavesPerEU = {0, 0};
463 const AMDGPUGWSResourcePseudoSourceValue GWSResourcePSV;
466 SmallVector<unsigned> MaxNumWorkGroups = {0, 0, 0};
469 AMDGPU::ClusterDimsAttr ClusterDims;
472 unsigned NumUserSGPRs = 0;
473 unsigned NumSystemSGPRs = 0;
475 unsigned NumWaveDispatchSGPRs = 0;
476 unsigned NumWaveDispatchVGPRs = 0;
478 bool HasSpilledSGPRs =
false;
479 bool HasSpilledVGPRs =
false;
480 bool HasNonSpillStackObjects =
false;
481 bool IsStackRealigned =
false;
483 unsigned NumSpilledSGPRs = 0;
484 unsigned NumSpilledVGPRs = 0;
486 unsigned DynamicVGPRBlockSize = 0;
490 unsigned ScratchReservedForDynamicVGPRs = 0;
494 GCNUserSGPRUsageInfo UserSGPRInfo;
497 bool WorkGroupIDX : 1;
498 bool WorkGroupIDY : 1;
499 bool WorkGroupIDZ : 1;
500 bool WorkGroupInfo : 1;
501 bool LDSKernelId : 1;
502 bool PrivateSegmentWaveByteOffset : 1;
504 bool WorkItemIDX : 1;
505 bool WorkItemIDY : 1;
506 bool WorkItemIDZ : 1;
510 bool ImplicitArgPtr : 1;
514 unsigned MinNumAGPRs = ~0
u;
521 unsigned HighBitsOf32BitAddress;
524 IndexedMap<uint8_t, VirtReg2IndexFunctor> VRegFlags;
538 void MRI_NoteNewVirtualRegister(
Register Reg)
override;
539 void MRI_NoteCloneVirtualRegister(
Register NewReg,
Register SrcReg)
override;
554 SGPRSpillsToVirtualVGPRLanes;
558 SGPRSpillsToPhysicalVGPRLanes;
559 unsigned NumVirtualVGPRSpillLanes = 0;
560 unsigned NumPhysicalVGPRSpillLanes = 0;
570 WWMSpillsMap WWMSpills;
582 ReservedRegSet WWMReservedRegs;
584 bool IsWholeWaveFunction =
false;
586 using PrologEpilogSGPRSpill =
587 std::pair<Register, PrologEpilogSGPRSaveRestoreInfo>;
607 std::optional<int> ScavengeFI;
621 bool IsPrologEpilog);
625 return VGPRForAGPRCopy;
629 VGPRForAGPRCopy = NewVGPRForAGPRCopy;
635 MaskForVGPRBlockOps.grow(RegisterBlock);
636 MaskForVGPRBlockOps[RegisterBlock] = Mask;
640 return MaskForVGPRBlockOps[RegisterBlock];
644 return MaskForVGPRBlockOps.inBounds(RegisterBlock);
664 : WWMReservedRegs.contains(
Reg);
675 auto I = SGPRSpillsToVirtualVGPRLanes.find(FrameIndex);
676 return (
I == SGPRSpillsToVirtualVGPRLanes.end())
688 return WWMReservedRegs.contains(
Reg);
695 return PrologEpilogSGPRSpills;
708 PrologEpilogSGPRSpills.insert(
710 PrologEpilogSGPRSpills,
Reg,
711 [](
const auto &
LHS,
const auto &
RHS) {
return LHS <
RHS.first; }),
712 std::make_pair(
Reg,
SI));
718 const auto *
I =
find_if(PrologEpilogSGPRSpills, [&
Reg](
const auto &Spill) {
719 return Spill.first ==
Reg;
721 return I != PrologEpilogSGPRSpills.end();
726 const auto *
I =
find_if(PrologEpilogSGPRSpills, [&
Reg](
const auto &Spill) {
727 return Spill.first ==
Reg;
729 if (
I != PrologEpilogSGPRSpills.end() &&
731 return I->second.getReg();
733 return AMDGPU::NoRegister;
738 for (
const auto &
SI : PrologEpilogSGPRSpills) {
746 return find_if(PrologEpilogSGPRSpills,
749 return SI.second.getKind() ==
751 SI.second.getIndex() == FI;
752 }) != PrologEpilogSGPRSpills.end();
757 const auto *
I =
find_if(PrologEpilogSGPRSpills, [&
Reg](
const auto &Spill) {
758 return Spill.first ==
Reg;
760 assert(
I != PrologEpilogSGPRSpills.end());
767 auto I = SGPRSpillsToPhysicalVGPRLanes.find(FrameIndex);
768 return (
I == SGPRSpillsToPhysicalVGPRLanes.end())
775 if (VRegFlags.inBounds(
Reg))
776 VRegFlags[
Reg] |= Flag;
780 if (
Reg.isPhysical())
783 return VRegFlags.inBounds(
Reg) && VRegFlags[
Reg] & Flag;
809 auto I = VGPRToAGPRSpills.find(FrameIndex);
810 return (
I == VGPRToAGPRSpills.end()) ? (
MCPhysReg)AMDGPU::NoRegister
811 :
I->second.Lanes[Lane];
815 auto I = VGPRToAGPRSpills.find(FrameIndex);
816 if (
I != VGPRToAGPRSpills.end())
817 I->second.IsDead =
true;
827 bool SpillToPhysVGPRLane =
false,
828 bool IsPrologEpilog =
false);
834 bool ResetSGPRSpillStackIDs);
840 return BytesInStackArgArea;
844 BytesInStackArgArea = Bytes;
852 return ScratchReservedForDynamicVGPRs;
856 ScratchReservedForDynamicVGPRs = SizeInBytes;
871 unsigned AllocSizeDWord,
int KernArgIdx,
885 return ArgInfo.WorkGroupIDX.getRegister();
891 return ArgInfo.WorkGroupIDY.getRegister();
897 return ArgInfo.WorkGroupIDZ.getRegister();
903 return ArgInfo.WorkGroupInfo.getRegister();
910 ArgInfo.WorkItemIDX = Arg;
914 ArgInfo.WorkItemIDY = Arg;
918 ArgInfo.WorkItemIDZ = Arg;
922 ArgInfo.PrivateSegmentWaveByteOffset
925 return ArgInfo.PrivateSegmentWaveByteOffset.getRegister();
945 return WorkGroupInfo;
949 return PrivateSegmentWaveByteOffset;
965 return ImplicitArgPtr;
976 std::tuple<const ArgDescriptor *, const TargetRegisterClass *, LLT>
978 return ArgInfo.getPreloadedValue(
Value);
982 const auto *Arg = std::get<0>(ArgInfo.getPreloadedValue(
Value));
983 return Arg ? Arg->getRegister() :
MCRegister();
993 return HighBitsOf32BitAddress;
1001 return NumUserSGPRs + NumSystemSGPRs;
1005 return UserSGPRInfo.getNumKernargPreloadSGPRs();
1017 return ArgInfo.PrivateSegmentWaveByteOffset.getRegister();
1023 return ScratchRSrcReg;
1027 assert(
Reg != 0 &&
"Should never be unset");
1028 ScratchRSrcReg =
Reg;
1032 return FrameOffsetReg;
1036 assert(
Reg != 0 &&
"Should never be unset");
1037 FrameOffsetReg =
Reg;
1041 assert(
Reg != 0 &&
"Should never be unset");
1042 StackPtrOffsetReg =
Reg;
1052 return StackPtrOffsetReg;
1058 return ArgInfo.QueuePtr.getRegister();
1062 return ArgInfo.ImplicitBufferPtr.getRegister();
1066 return HasSpilledSGPRs;
1070 HasSpilledSGPRs = Spill;
1074 return HasSpilledVGPRs;
1078 HasSpilledVGPRs = Spill;
1082 return HasNonSpillStackObjects;
1086 HasNonSpillStackObjects = StackObject;
1090 return IsStackRealigned;
1094 IsStackRealigned = Realigned;
1098 return NumSpilledSGPRs;
1102 return NumSpilledVGPRs;
1106 NumSpilledSGPRs += num;
1110 NumSpilledVGPRs += num;
1118 return PSInputEnable;
1122 return PSInputAddr & (1 << Index);
1126 PSInputAddr |= 1 << Index;
1130 PSInputEnable |= 1 << Index;
1138 ReturnsVoid =
Value;
1144 return FlatWorkGroupSizes;
1149 return FlatWorkGroupSizes.first;
1154 return FlatWorkGroupSizes.second;
1165 return WavesPerEU.first;
1170 return WavesPerEU.second;
1175 return &GWSResourcePSV;
1185 return (Occupancy < 4) ? Occupancy : 4;
1191 if (Occupancy > Limit)
1196 if (Occupancy < Limit)
assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")
Provides AMDGPU specific target descriptions.
The AMDGPU TargetMachine interface definition for hw codegen targets.
static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")
AMD GCN specific subclass of TargetSubtarget.
static bool IsRegister(const MCParsedAsmOperand &op)
Register const TargetRegisterInfo * TRI
Promote Memory to Register
static cl::opt< RegAllocEvictionAdvisorAnalysisLegacy::AdvisorMode > Mode("regalloc-enable-advisor", cl::Hidden, cl::init(RegAllocEvictionAdvisorAnalysisLegacy::AdvisorMode::Default), cl::desc("Enable regalloc advisor mode"), cl::values(clEnumValN(RegAllocEvictionAdvisorAnalysisLegacy::AdvisorMode::Default, "default", "Default"), clEnumValN(RegAllocEvictionAdvisorAnalysisLegacy::AdvisorMode::Release, "release", "precompiled"), clEnumValN(RegAllocEvictionAdvisorAnalysisLegacy::AdvisorMode::Development, "development", "for training")))
Interface definition for SIInstrInfo.
static bool contains(SmallPtrSetImpl< ConstantExpr * > &Cache, ConstantExpr *Expr, Constant *C)
This file implements a set that has insertion order iteration characteristics.
This file defines the SmallVector class.
void printCustom(raw_ostream &OS) const override
Implement printing for PseudoSourceValue.
static bool classof(const PseudoSourceValue *V)
AMDGPUGWSResourcePseudoSourceValue(const AMDGPUTargetMachine &TM)
bool mayAlias(const MachineFrameInfo *) const override
Return true if the memory pointed to by this PseudoSourceValue can ever alias an LLVM IR Value.
bool isAliased(const MachineFrameInfo *) const override
Test whether the memory pointed to by this PseudoSourceValue may also be pointed to by an LLVM IR Val...
AMDGPUMachineFunction(const Function &F, const AMDGPUSubtarget &ST)
bool isMemoryBound() const
bool needsWaveLimiter() const
bool isConstant(const MachineFrameInfo *) const override
Test whether the memory pointed to by this PseudoSourceValue has a constant value.
AMDGPUPseudoSourceValue(unsigned Kind, const AMDGPUTargetMachine &TM)
bool mayAlias(const MachineFrameInfo *) const override
Return true if the memory pointed to by this PseudoSourceValue can ever alias an LLVM IR Value.
bool isAliased(const MachineFrameInfo *) const override
Test whether the memory pointed to by this PseudoSourceValue may also be pointed to by an LLVM IR Val...
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Lightweight error class with error context and mandatory checking.
Wrapper class representing physical registers. Should be passed by value.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
This class implements a map that also provides access to all stored values in a deterministic order.
PrologEpilogSGPRSaveRestoreInfo(SGPRSaveKind K, Register R)
PrologEpilogSGPRSaveRestoreInfo(SGPRSaveKind K, int I)
SGPRSaveKind getKind() const
Special value supplied for machine level alias analysis.
PseudoSourceValue(unsigned Kind, const TargetMachine &TM)
Wrapper class representing virtual and physical registers.
This class keeps track of the SPI_SP_INPUT_ADDR config register, which tells the hardware which inter...
unsigned getNumWaveDispatchVGPRs() const
bool hasNonSpillStackObjects() const
ArrayRef< PrologEpilogSGPRSpill > getPrologEpilogSGPRSpills() const
const WWMSpillsMap & getWWMSpills() const
bool isPSInputAllocated(unsigned Index) const
void getAllScratchSGPRCopyDstRegs(SmallVectorImpl< Register > &Regs) const
unsigned getMinNumAGPRs() const
ArrayRef< MCPhysReg > getAGPRSpillVGPRs() const
void setSGPRForEXECCopy(Register Reg)
bool initializeBaseYamlFields(const yaml::SIMachineFunctionInfo &YamlMFI, const MachineFunction &MF, PerFunctionMIParsingState &PFS, SMDiagnostic &Error, SMRange &SourceRange)
unsigned getOccupancy() const
unsigned getNumPreloadedSGPRs() const
void shiftWwmVGPRsToLowestRange(MachineFunction &MF, SmallVectorImpl< Register > &WWMVGPRs, BitVector &SavedVGPRs)
void setWorkItemIDY(ArgDescriptor Arg)
unsigned getNumSpilledVGPRs() const
bool hasLDSKernelId() const
void increaseOccupancy(const MachineFunction &MF, unsigned Limit)
unsigned getNumWaveDispatchSGPRs() const
Register addPrivateSegmentSize(const SIRegisterInfo &TRI)
void setWorkItemIDZ(ArgDescriptor Arg)
std::pair< unsigned, unsigned > getWavesPerEU() const
void setMaskForVGPRBlockOps(Register RegisterBlock, uint32_t Mask)
unsigned getMaxNumWorkGroupsZ() const
MCPhysReg getVGPRToAGPRSpill(int FrameIndex, unsigned Lane) const
unsigned getNumSpilledSGPRs() const
GCNUserSGPRUsageInfo & getUserSGPRInfo()
void allocateWWMSpill(MachineFunction &MF, Register VGPR, uint64_t Size=4, Align Alignment=Align(4))
Register addDispatchPtr(const SIRegisterInfo &TRI)
Register getLongBranchReservedReg() const
unsigned getDynamicVGPRBlockSize() const
bool hasSpilledVGPRs() const
void setFlag(Register Reg, uint8_t Flag)
void setVGPRToAGPRSpillDead(int FrameIndex)
unsigned getMaxFlatWorkGroupSize() const
bool isWholeWaveFunction() const
std::pair< unsigned, unsigned > getFlatWorkGroupSizes() const
Register getStackPtrOffsetReg() const
bool isStackRealigned() const
Register addFlatScratchInit(const SIRegisterInfo &TRI)
Register getScratchRSrcReg() const
Returns the physical register reserved for use as the resource descriptor for scratch accesses.
unsigned getMaxWavesPerEU() const
void setStackPtrOffsetReg(Register Reg)
Register addReservedUserSGPR()
Increment user SGPRs used for padding the argument list only.
ArrayRef< MCPhysReg > getVGPRSpillAGPRs() const
ArrayRef< Register > getSGPRSpillPhysVGPRs() const
int getScavengeFI(MachineFrameInfo &MFI, const SIRegisterInfo &TRI)
Register addQueuePtr(const SIRegisterInfo &TRI)
bool hasWorkGroupIDZ() const
Register getQueuePtrUserSGPR() const
ArrayRef< SIRegisterInfo::SpilledReg > getSGPRSpillToVirtualVGPRLanes(int FrameIndex) const
uint32_t getMaskForVGPRBlockOps(Register RegisterBlock) const
unsigned getMaxMemoryClusterDWords() const
SIMachineFunctionInfo(const SIMachineFunctionInfo &MFI)=default
bool hasMaskForVGPRBlockOps(Register RegisterBlock) const
AMDGPU::ClusterDimsAttr getClusterDims() const
SmallVector< unsigned > getMaxNumWorkGroups() const
void clearNonWWMRegAllocMask()
bool hasPrologEpilogSGPRSpillEntry(Register Reg) const
Register getGITPtrLoReg(const MachineFunction &MF) const
bool hasWorkGroupIDY() const
void setVGPRForAGPRCopy(Register NewVGPRForAGPRCopy)
bool allocateVGPRSpillToAGPR(MachineFunction &MF, int FI, bool isAGPRtoVGPR)
Reserve AGPRs or VGPRs to support spilling for FrameIndex FI.
Register addWorkGroupIDY()
void splitWWMSpillRegisters(MachineFunction &MF, SmallVectorImpl< std::pair< Register, int > > &CalleeSavedRegs, SmallVectorImpl< std::pair< Register, int > > &ScratchRegs) const
void setBytesInStackArgArea(unsigned Bytes)
void setNumWaveDispatchSGPRs(unsigned Count)
SIModeRegisterDefaults getMode() const
Register getSGPRForEXECCopy() const
void setFrameOffsetReg(Register Reg)
bool isWWMReservedRegister(Register Reg) const
ArrayRef< SIRegisterInfo::SpilledReg > getSGPRSpillToPhysicalVGPRLanes(int FrameIndex) const
Register addPrivateSegmentWaveByteOffset()
std::tuple< const ArgDescriptor *, const TargetRegisterClass *, LLT > getPreloadedValue(AMDGPUFunctionArgInfo::PreloadedValue Value) const
bool hasWorkGroupInfo() const
bool mayUseAGPRs(const Function &F) const
bool isCalleeSavedReg(const MCPhysReg *CSRegs, MCPhysReg Reg) const
friend class GCNTargetMachine
bool hasWorkItemIDY() const
unsigned getMinFlatWorkGroupSize() const
Register addLDSKernelId()
Register getVGPRForAGPRCopy() const
const GCNUserSGPRUsageInfo & getUserSGPRInfo() const
bool allocateSGPRSpillToVGPRLane(MachineFunction &MF, int FI, bool SpillToPhysVGPRLane=false, bool IsPrologEpilog=false)
void setPrivateSegmentWaveByteOffset(Register Reg)
unsigned getMinWavesPerEU() const
Register getFrameOffsetReg() const
void setLongBranchReservedReg(Register Reg)
bool hasWorkGroupIDX() const
const AMDGPUFunctionArgInfo & getArgInfo() const
unsigned getMaxNumWorkGroupsX() const
unsigned getBytesInStackArgArea() const
Register addKernargSegmentPtr(const SIRegisterInfo &TRI)
Register addDispatchID(const SIRegisterInfo &TRI)
void setHasSpilledVGPRs(bool Spill=true)
void setIfReturnsVoid(bool Value)
void limitOccupancy(unsigned Limit)
bool removeDeadFrameIndices(MachineFrameInfo &MFI, bool ResetSGPRSpillStackIDs)
If ResetSGPRSpillStackIDs is true, reset the stack ID from sgpr-spill to the default stack.
void setScratchReservedForDynamicVGPRs(unsigned SizeInBytes)
BitVector getNonWWMRegMask() const
void markPSInputAllocated(unsigned Index)
void setWorkItemIDX(ArgDescriptor Arg)
bool isWWMReg(Register Reg) const
MachineFunctionInfo * clone(BumpPtrAllocator &Allocator, MachineFunction &DestMF, const DenseMap< MachineBasicBlock *, MachineBasicBlock * > &Src2DstMBB) const override
Make a functionally equivalent copy of this MachineFunctionInfo in MF.
bool checkFlag(Register Reg, uint8_t Flag) const
void setNumWaveDispatchVGPRs(unsigned Count)
void markPSInputEnabled(unsigned Index)
void addToSpilledVGPRs(unsigned num)
MCRegister getPreloadedReg(AMDGPUFunctionArgInfo::PreloadedValue Value) const
uint32_t get32BitAddressHighBits() const
unsigned getMinAllowedOccupancy() const
void setHasSpilledSGPRs(bool Spill=true)
bool checkIndexInPrologEpilogSGPRSpills(int FI) const
void updateNonWWMRegMask(BitVector &RegMask)
unsigned getNumKernargPreloadedSGPRs() const
Register addPrivateSegmentBuffer(const SIRegisterInfo &TRI)
bool hasWorkItemIDX() const
unsigned getNumUserSGPRs() const
unsigned getScratchReservedForDynamicVGPRs() const
const ReservedRegSet & getWWMReservedRegs() const
Register getImplicitBufferPtrUserSGPR() const
std::optional< int > getOptionalScavengeFI() const
Register addImplicitBufferPtr(const SIRegisterInfo &TRI)
AMDGPUFunctionArgInfo & getArgInfo()
const PrologEpilogSGPRSaveRestoreInfo & getPrologEpilogSGPRSaveRestoreInfo(Register Reg) const
bool isDynamicVGPREnabled() const
void setHasNonSpillStackObjects(bool StackObject=true)
void setIsStackRealigned(bool Realigned=true)
unsigned getGITPtrHigh() const
void limitOccupancy(const MachineFunction &MF)
bool hasSpilledSGPRs() const
ArrayRef< Register > getSGPRSpillVGPRs() const
unsigned getPSInputAddr() const
SmallVectorImpl< MCRegister > * addPreloadedKernArg(const SIRegisterInfo &TRI, const TargetRegisterClass *RC, unsigned AllocSizeDWord, int KernArgIdx, int PaddingSGPRs)
void addToPrologEpilogSGPRSpills(Register Reg, PrologEpilogSGPRSaveRestoreInfo SI)
Register getScratchSGPRCopyDstReg(Register Reg) const
Register getPrivateSegmentWaveByteOffsetSystemSGPR() const
bool hasImplicitArgPtr() const
Register addWorkGroupIDZ()
Register addWorkGroupInfo()
bool hasWorkItemIDZ() const
unsigned getMaxNumWorkGroupsY() const
unsigned getPSInputEnable() const
void setScratchRSrcReg(Register Reg)
void addToSpilledSGPRs(unsigned num)
const AMDGPUGWSResourcePseudoSourceValue * getGWSPSV(const AMDGPUTargetMachine &TM)
void reserveWWMRegister(Register Reg)
bool hasPrivateSegmentWaveByteOffset() const
Register addWorkGroupIDX()
Instances of this class encapsulate one diagnostic report, allowing printing to a raw_ostream as a ca...
Represents a range in source code.
A SetVector that performs no allocations if smaller than a certain size.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
LLVM Value Representation.
This class implements an extremely fast bulk output stream that can only output to a stream.
virtual bool outputting() const =0
void mapOptional(StringRef Key, T &Val)
virtual void setError(const Twine &)=0
void mapRequired(StringRef Key, T &Val)
virtual std::vector< StringRef > keys()=0
This is an optimization pass for GlobalISel generic memory operations.
auto upper_bound(R &&Range, T &&Value)
Provide wrappers to std::upper_bound which take ranges instead of having to pass begin/end explicitly...
FunctionAddr VTableAddr Count
bool is_sorted(R &&Range, Compare C)
Wrapper function around std::is_sorted to check if elements in a range R are sorted with respect to a...
BumpPtrAllocatorImpl BumpPtrAllocator
The standard BumpPtrAllocator which just uses the default template parameters.
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
FunctionAddr VTableAddr Next
ArrayRef(const T &OneElt) -> ArrayRef< T >
constexpr unsigned DefaultMemoryClusterDWordsLimit
auto find_if(R &&Range, UnaryPredicate P)
Provide wrappers to std::find_if which take ranges instead of having to pass begin/end explicitly.
bool is_contained(R &&Range, const E &Element)
Returns true if Element is found in Range.
This struct is a compact representation of a valid (non-zero power of two) alignment.
static ArgDescriptor createRegister(Register Reg, unsigned Mask=~0u)
@ PreserveSign
The sign of a flushed-to-zero number is preserved in the sign of 0.
MachineFunctionInfo - This class can be derived from and used by targets to hold private target-speci...
SmallVector< MCPhysReg, 32 > Lanes
unsigned operator()(Register Reg) const
Function object to check whether the first component of a container supported by std::get (like std::...
Targets should override this in a way that mirrors the implementation of llvm::MachineFunctionInfo.
static void mapping(IO &YamlIO, SIArgumentInfo &AI)
static void mapping(IO &YamlIO, SIArgument &A)
static void mapping(IO &YamlIO, SIMachineFunctionInfo &MFI)
static void mapping(IO &YamlIO, SIMode &Mode)
This class should be specialized by any type that needs to be converted to/from a YAML mapping.
std::optional< SIArgument > PrivateSegmentWaveByteOffset
std::optional< SIArgument > WorkGroupIDY
std::optional< SIArgument > FlatScratchInit
std::optional< SIArgument > DispatchPtr
std::optional< SIArgument > DispatchID
std::optional< SIArgument > WorkItemIDY
std::optional< SIArgument > WorkGroupIDX
std::optional< SIArgument > ImplicitArgPtr
std::optional< SIArgument > QueuePtr
std::optional< SIArgument > WorkGroupInfo
std::optional< SIArgument > LDSKernelId
std::optional< SIArgument > ImplicitBufferPtr
std::optional< SIArgument > WorkItemIDX
std::optional< SIArgument > KernargSegmentPtr
std::optional< SIArgument > WorkItemIDZ
std::optional< SIArgument > PrivateSegmentSize
std::optional< SIArgument > PrivateSegmentBuffer
std::optional< SIArgument > WorkGroupIDZ
std::optional< unsigned > Mask
SIArgument(const SIArgument &Other)
SIArgument & operator=(const SIArgument &Other)
static SIArgument createArgument(bool IsReg)
unsigned MaxMemoryClusterDWords
StringValue SGPRForEXECCopy
SmallVector< StringValue > WWMReservedRegs
uint32_t HighBitsOf32BitAddress
SIMachineFunctionInfo()=default
StringValue FrameOffsetReg
StringValue LongBranchReservedReg
uint64_t ExplicitKernArgSize
uint16_t NumWaveDispatchSGPRs
void mappingImpl(yaml::IO &YamlIO) override
~SIMachineFunctionInfo()=default
unsigned DynamicVGPRBlockSize
StringValue VGPRForAGPRCopy
std::optional< SIArgumentInfo > ArgInfo
SmallVector< StringValue, 2 > SpillPhysVGPRS
std::optional< FrameIndex > ScavengeFI
uint16_t NumWaveDispatchVGPRs
unsigned BytesInStackArgArea
unsigned ScratchReservedForDynamicVGPRs
StringValue ScratchRSrcReg
StringValue StackPtrOffsetReg
SIMode(const SIModeRegisterDefaults &Mode)
bool FP64FP16OutputDenormals
bool operator==(const SIMode Other) const
bool FP64FP16InputDenormals
A wrapper around std::string which contains a source range that's being set during parsing.