LLVM 22.0.0git
SIMachineFunctionInfo.h
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1//==- SIMachineFunctionInfo.h - SIMachineFunctionInfo interface --*- C++ -*-==//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9/// \file
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_AMDGPU_SIMACHINEFUNCTIONINFO_H
14#define LLVM_LIB_TARGET_AMDGPU_SIMACHINEFUNCTIONINFO_H
15
18#include "AMDGPUTargetMachine.h"
19#include "GCNSubtarget.h"
21#include "SIInstrInfo.h"
23#include "llvm/ADT/SetVector.h"
28#include <optional>
29
30namespace llvm {
31
33class MachineFunction;
35class SIRegisterInfo;
37
39public:
44
45protected:
47 : PseudoSourceValue(Kind, TM) {}
48
49public:
50 bool isConstant(const MachineFrameInfo *) const override {
51 // This should probably be true for most images, but we will start by being
52 // conservative.
53 return false;
54 }
55
56 bool isAliased(const MachineFrameInfo *) const override {
57 return true;
58 }
59
60 bool mayAlias(const MachineFrameInfo *) const override {
61 return true;
62 }
63};
64
66public:
69
70 static bool classof(const PseudoSourceValue *V) {
71 return V->kind() == GWSResource;
72 }
73
74 // These are inaccessible memory from IR.
75 bool isAliased(const MachineFrameInfo *) const override {
76 return false;
77 }
78
79 // These are inaccessible memory from IR.
80 bool mayAlias(const MachineFrameInfo *) const override {
81 return false;
82 }
83
84 void printCustom(raw_ostream &OS) const override {
85 OS << "GWSResource";
86 }
87};
88
89namespace yaml {
90
91struct SIArgument {
93 union {
95 unsigned StackOffset;
96 };
97 std::optional<unsigned> Mask;
98
99 // Default constructor, which creates a stack argument.
102 IsRegister = Other.IsRegister;
103 if (IsRegister)
104 new (&RegisterName) StringValue(Other.RegisterName);
105 else
106 StackOffset = Other.StackOffset;
107 Mask = Other.Mask;
108 }
110 // Default-construct or destruct the old RegisterName in case of switching
111 // union members
112 if (IsRegister != Other.IsRegister) {
113 if (Other.IsRegister)
114 new (&RegisterName) StringValue();
115 else
116 RegisterName.~StringValue();
117 }
118 IsRegister = Other.IsRegister;
119 if (IsRegister)
120 RegisterName = Other.RegisterName;
121 else
122 StackOffset = Other.StackOffset;
123 Mask = Other.Mask;
124 return *this;
125 }
127 if (IsRegister)
128 RegisterName.~StringValue();
129 }
130
131 // Helper to create a register or stack argument.
132 static inline SIArgument createArgument(bool IsReg) {
133 if (IsReg)
134 return SIArgument(IsReg);
135 return SIArgument();
136 }
137
138private:
139 // Construct a register argument.
141};
142
143template <> struct MappingTraits<SIArgument> {
144 static void mapping(IO &YamlIO, SIArgument &A) {
145 if (YamlIO.outputting()) {
146 if (A.IsRegister)
147 YamlIO.mapRequired("reg", A.RegisterName);
148 else
149 YamlIO.mapRequired("offset", A.StackOffset);
150 } else {
151 auto Keys = YamlIO.keys();
152 if (is_contained(Keys, "reg")) {
154 YamlIO.mapRequired("reg", A.RegisterName);
155 } else if (is_contained(Keys, "offset"))
156 YamlIO.mapRequired("offset", A.StackOffset);
157 else
158 YamlIO.setError("missing required key 'reg' or 'offset'");
159 }
160 YamlIO.mapOptional("mask", A.Mask);
161 }
162 static const bool flow = true;
163};
164
166 std::optional<SIArgument> PrivateSegmentBuffer;
167 std::optional<SIArgument> DispatchPtr;
168 std::optional<SIArgument> QueuePtr;
169 std::optional<SIArgument> KernargSegmentPtr;
170 std::optional<SIArgument> DispatchID;
171 std::optional<SIArgument> FlatScratchInit;
172 std::optional<SIArgument> PrivateSegmentSize;
173
174 std::optional<SIArgument> WorkGroupIDX;
175 std::optional<SIArgument> WorkGroupIDY;
176 std::optional<SIArgument> WorkGroupIDZ;
177 std::optional<SIArgument> WorkGroupInfo;
178 std::optional<SIArgument> LDSKernelId;
179 std::optional<SIArgument> PrivateSegmentWaveByteOffset;
180
181 std::optional<SIArgument> ImplicitArgPtr;
182 std::optional<SIArgument> ImplicitBufferPtr;
183
184 std::optional<SIArgument> WorkItemIDX;
185 std::optional<SIArgument> WorkItemIDY;
186 std::optional<SIArgument> WorkItemIDZ;
187};
188
189template <> struct MappingTraits<SIArgumentInfo> {
190 static void mapping(IO &YamlIO, SIArgumentInfo &AI) {
191 YamlIO.mapOptional("privateSegmentBuffer", AI.PrivateSegmentBuffer);
192 YamlIO.mapOptional("dispatchPtr", AI.DispatchPtr);
193 YamlIO.mapOptional("queuePtr", AI.QueuePtr);
194 YamlIO.mapOptional("kernargSegmentPtr", AI.KernargSegmentPtr);
195 YamlIO.mapOptional("dispatchID", AI.DispatchID);
196 YamlIO.mapOptional("flatScratchInit", AI.FlatScratchInit);
197 YamlIO.mapOptional("privateSegmentSize", AI.PrivateSegmentSize);
198
199 YamlIO.mapOptional("workGroupIDX", AI.WorkGroupIDX);
200 YamlIO.mapOptional("workGroupIDY", AI.WorkGroupIDY);
201 YamlIO.mapOptional("workGroupIDZ", AI.WorkGroupIDZ);
202 YamlIO.mapOptional("workGroupInfo", AI.WorkGroupInfo);
203 YamlIO.mapOptional("LDSKernelId", AI.LDSKernelId);
204 YamlIO.mapOptional("privateSegmentWaveByteOffset",
206
207 YamlIO.mapOptional("implicitArgPtr", AI.ImplicitArgPtr);
208 YamlIO.mapOptional("implicitBufferPtr", AI.ImplicitBufferPtr);
209
210 YamlIO.mapOptional("workItemIDX", AI.WorkItemIDX);
211 YamlIO.mapOptional("workItemIDY", AI.WorkItemIDY);
212 YamlIO.mapOptional("workItemIDZ", AI.WorkItemIDZ);
213 }
214};
215
216// Default to default mode for default calling convention.
217struct SIMode {
218 bool IEEE = true;
219 bool DX10Clamp = true;
224
225 SIMode() = default;
226
228 IEEE = Mode.IEEE;
229 DX10Clamp = Mode.DX10Clamp;
230 FP32InputDenormals = Mode.FP32Denormals.Input != DenormalMode::PreserveSign;
232 Mode.FP32Denormals.Output != DenormalMode::PreserveSign;
234 Mode.FP64FP16Denormals.Input != DenormalMode::PreserveSign;
236 Mode.FP64FP16Denormals.Output != DenormalMode::PreserveSign;
237 }
238
239 bool operator ==(const SIMode Other) const {
240 return IEEE == Other.IEEE &&
241 DX10Clamp == Other.DX10Clamp &&
242 FP32InputDenormals == Other.FP32InputDenormals &&
243 FP32OutputDenormals == Other.FP32OutputDenormals &&
244 FP64FP16InputDenormals == Other.FP64FP16InputDenormals &&
245 FP64FP16OutputDenormals == Other.FP64FP16OutputDenormals;
246 }
247};
248
249template <> struct MappingTraits<SIMode> {
250 static void mapping(IO &YamlIO, SIMode &Mode) {
251 YamlIO.mapOptional("ieee", Mode.IEEE, true);
252 YamlIO.mapOptional("dx10-clamp", Mode.DX10Clamp, true);
253 YamlIO.mapOptional("fp32-input-denormals", Mode.FP32InputDenormals, true);
254 YamlIO.mapOptional("fp32-output-denormals", Mode.FP32OutputDenormals, true);
255 YamlIO.mapOptional("fp64-fp16-input-denormals", Mode.FP64FP16InputDenormals, true);
256 YamlIO.mapOptional("fp64-fp16-output-denormals", Mode.FP64FP16OutputDenormals, true);
257 }
258};
259
266 bool IsEntryFunction = false;
267 bool IsChainFunction = false;
269 bool MemoryBound = false;
270 bool WaveLimiter = false;
271 bool HasSpilledSGPRs = false;
272 bool HasSpilledVGPRs = false;
276
277 // TODO: 10 may be a better default since it's the maximum.
278 unsigned Occupancy = 0;
279
282
283 StringValue ScratchRSrcReg = "$private_rsrc_reg";
286
288 bool ReturnsVoid = true;
289
290 std::optional<SIArgumentInfo> ArgInfo;
291
292 unsigned PSInputAddr = 0;
293 unsigned PSInputEnable = 0;
295
297 std::optional<FrameIndex> ScavengeFI;
301
302 bool HasInitWholeWave = false;
304
307
310 const TargetRegisterInfo &TRI,
311 const llvm::MachineFunction &MF);
312
313 void mappingImpl(yaml::IO &YamlIO) override;
315};
316
318 static void mapping(IO &YamlIO, SIMachineFunctionInfo &MFI) {
319 YamlIO.mapOptional("explicitKernArgSize", MFI.ExplicitKernArgSize,
320 UINT64_C(0));
321 YamlIO.mapOptional("maxKernArgAlign", MFI.MaxKernArgAlign);
322 YamlIO.mapOptional("ldsSize", MFI.LDSSize, 0u);
323 YamlIO.mapOptional("gdsSize", MFI.GDSSize, 0u);
324 YamlIO.mapOptional("dynLDSAlign", MFI.DynLDSAlign, Align());
325 YamlIO.mapOptional("isEntryFunction", MFI.IsEntryFunction, false);
326 YamlIO.mapOptional("isChainFunction", MFI.IsChainFunction, false);
327 YamlIO.mapOptional("noSignedZerosFPMath", MFI.NoSignedZerosFPMath, false);
328 YamlIO.mapOptional("memoryBound", MFI.MemoryBound, false);
329 YamlIO.mapOptional("waveLimiter", MFI.WaveLimiter, false);
330 YamlIO.mapOptional("hasSpilledSGPRs", MFI.HasSpilledSGPRs, false);
331 YamlIO.mapOptional("hasSpilledVGPRs", MFI.HasSpilledVGPRs, false);
332 YamlIO.mapOptional("numWaveDispatchSGPRs", MFI.NumWaveDispatchSGPRs, false);
333 YamlIO.mapOptional("numWaveDispatchVGPRs", MFI.NumWaveDispatchVGPRs, false);
334 YamlIO.mapOptional("scratchRSrcReg", MFI.ScratchRSrcReg,
335 StringValue("$private_rsrc_reg"));
336 YamlIO.mapOptional("frameOffsetReg", MFI.FrameOffsetReg,
337 StringValue("$fp_reg"));
338 YamlIO.mapOptional("stackPtrOffsetReg", MFI.StackPtrOffsetReg,
339 StringValue("$sp_reg"));
340 YamlIO.mapOptional("bytesInStackArgArea", MFI.BytesInStackArgArea, 0u);
341 YamlIO.mapOptional("returnsVoid", MFI.ReturnsVoid, true);
342 YamlIO.mapOptional("argumentInfo", MFI.ArgInfo);
343 YamlIO.mapOptional("psInputAddr", MFI.PSInputAddr, 0u);
344 YamlIO.mapOptional("psInputEnable", MFI.PSInputEnable, 0u);
345 YamlIO.mapOptional("maxMemoryClusterDWords", MFI.MaxMemoryClusterDWords,
347 YamlIO.mapOptional("mode", MFI.Mode, SIMode());
348 YamlIO.mapOptional("highBitsOf32BitAddress",
349 MFI.HighBitsOf32BitAddress, 0u);
350 YamlIO.mapOptional("occupancy", MFI.Occupancy, 0);
351 YamlIO.mapOptional("spillPhysVGPRs", MFI.SpillPhysVGPRS);
352 YamlIO.mapOptional("wwmReservedRegs", MFI.WWMReservedRegs);
353 YamlIO.mapOptional("scavengeFI", MFI.ScavengeFI);
354 YamlIO.mapOptional("vgprForAGPRCopy", MFI.VGPRForAGPRCopy,
355 StringValue()); // Don't print out when it's empty.
356 YamlIO.mapOptional("sgprForEXECCopy", MFI.SGPRForEXECCopy,
357 StringValue()); // Don't print out when it's empty.
358 YamlIO.mapOptional("longBranchReservedReg", MFI.LongBranchReservedReg,
359 StringValue());
360 YamlIO.mapOptional("hasInitWholeWave", MFI.HasInitWholeWave, false);
361 YamlIO.mapOptional("dynamicVGPRBlockSize", MFI.DynamicVGPRBlockSize, false);
362 YamlIO.mapOptional("scratchReservedForDynamicVGPRs",
364 YamlIO.mapOptional("isWholeWaveFunction", MFI.IsWholeWaveFunction, false);
365 }
366};
367
368} // end namespace yaml
369
370// A CSR SGPR value can be preserved inside a callee using one of the following
371// methods.
372// 1. Copy to an unused scratch SGPR.
373// 2. Spill to a VGPR lane.
374// 3. Spill to memory via. a scratch VGPR.
375// class PrologEpilogSGPRSaveRestoreInfo represents the save/restore method used
376// for an SGPR at function prolog/epilog.
382
384 SGPRSaveKind Kind;
385 union {
386 int Index;
388 };
389
390public:
394 Register getReg() const { return Reg; }
395 int getIndex() const { return Index; }
396 SGPRSaveKind getKind() const { return Kind; }
397};
398
401 unsigned operator()(Register Reg) const {
402 assert(AMDGPU::VReg_1024RegClass.contains(Reg) && "Expecting a VGPR block");
403
404 const MCRegister FirstVGPRBlock = AMDGPU::VReg_1024RegClass.getRegister(0);
405 return Reg - FirstVGPRBlock;
406 }
407};
408
409/// This class keeps track of the SPI_SP_INPUT_ADDR config register, which
410/// tells the hardware which interpolation parameters to load.
413 friend class GCNTargetMachine;
414
415 // State of MODE register, assumed FP mode.
417
418 // Registers that may be reserved for spilling purposes. These may be the same
419 // as the input registers.
420 Register ScratchRSrcReg = AMDGPU::PRIVATE_RSRC_REG;
421
422 // This is the unswizzled offset from the current dispatch's scratch wave
423 // base to the beginning of the current function's frame.
424 Register FrameOffsetReg = AMDGPU::FP_REG;
425
426 // This is an ABI register used in the non-entry calling convention to
427 // communicate the unswizzled offset from the current dispatch's scratch wave
428 // base to the beginning of the new function's frame.
429 Register StackPtrOffsetReg = AMDGPU::SP_REG;
430
431 // Registers that may be reserved when RA doesn't allocate enough
432 // registers to plan for the case where an indirect branch ends up
433 // being needed during branch relaxation.
434 Register LongBranchReservedReg;
435
436 AMDGPUFunctionArgInfo ArgInfo;
437
438 // Graphics info.
439 unsigned PSInputAddr = 0;
440 unsigned PSInputEnable = 0;
441
442 /// Number of bytes of arguments this function has on the stack. If the callee
443 /// is expected to restore the argument stack this should be a multiple of 16,
444 /// all usable during a tail call.
445 ///
446 /// The alternative would forbid tail call optimisation in some cases: if we
447 /// want to transfer control from a function with 8-bytes of stack-argument
448 /// space to a function with 16-bytes then misalignment of this value would
449 /// make a stack adjustment necessary, which could not be undone by the
450 /// callee.
451 unsigned BytesInStackArgArea = 0;
452
453 bool ReturnsVoid = true;
454
455 // A pair of default/requested minimum/maximum flat work group sizes.
456 // Minimum - first, maximum - second.
457 std::pair<unsigned, unsigned> FlatWorkGroupSizes = {0, 0};
458
459 // A pair of default/requested minimum/maximum number of waves per execution
460 // unit. Minimum - first, maximum - second.
461 std::pair<unsigned, unsigned> WavesPerEU = {0, 0};
462
463 const AMDGPUGWSResourcePseudoSourceValue GWSResourcePSV;
464
465 // Default/requested number of work groups for the function.
466 SmallVector<unsigned> MaxNumWorkGroups = {0, 0, 0};
467
468 // Requested cluster dimensions.
469 AMDGPU::ClusterDimsAttr ClusterDims;
470
471private:
472 unsigned NumUserSGPRs = 0;
473 unsigned NumSystemSGPRs = 0;
474
475 unsigned NumWaveDispatchSGPRs = 0;
476 unsigned NumWaveDispatchVGPRs = 0;
477
478 bool HasSpilledSGPRs = false;
479 bool HasSpilledVGPRs = false;
480 bool HasNonSpillStackObjects = false;
481 bool IsStackRealigned = false;
482
483 unsigned NumSpilledSGPRs = 0;
484 unsigned NumSpilledVGPRs = 0;
485
486 unsigned DynamicVGPRBlockSize = 0;
487
488 // The size in bytes of the scratch space reserved for the CWSR trap handler
489 // to spill some of the dynamic VGPRs.
490 unsigned ScratchReservedForDynamicVGPRs = 0;
491
492 // Tracks information about user SGPRs that will be setup by hardware which
493 // will apply to all wavefronts of the grid.
494 GCNUserSGPRUsageInfo UserSGPRInfo;
495
496 // Feature bits required for inputs passed in system SGPRs.
497 bool WorkGroupIDX : 1; // Always initialized.
498 bool WorkGroupIDY : 1;
499 bool WorkGroupIDZ : 1;
500 bool WorkGroupInfo : 1;
501 bool LDSKernelId : 1;
502 bool PrivateSegmentWaveByteOffset : 1;
503
504 bool WorkItemIDX : 1; // Always initialized.
505 bool WorkItemIDY : 1;
506 bool WorkItemIDZ : 1;
507
508 // Pointer to where the ABI inserts special kernel arguments separate from the
509 // user arguments. This is an offset from the KernargSegmentPtr.
510 bool ImplicitArgPtr : 1;
511
512 /// Minimum number of AGPRs required to allocate in the function. Only
513 /// relevant for gfx90a-gfx950. For gfx908, this should be infinite.
514 unsigned MinNumAGPRs = ~0u;
515
516 // The hard-wired high half of the address of the global information table
517 // for AMDPAL OS type. 0xffffffff represents no hard-wired high half, since
518 // current hardware only allows a 16 bit value.
519 unsigned GITPtrHigh;
520
521 unsigned HighBitsOf32BitAddress;
522
523 // Flags associated with the virtual registers.
524 IndexedMap<uint8_t, VirtReg2IndexFunctor> VRegFlags;
525
526 // Current recorded maximum possible occupancy.
527 unsigned Occupancy;
528
529 // Maximum number of dwords that can be clusterred during instruction
530 // scheduler stage.
531 unsigned MaxMemoryClusterDWords = DefaultMemoryClusterDWordsLimit;
532
533 MCPhysReg getNextUserSGPR() const;
534
535 MCPhysReg getNextSystemSGPR() const;
536
537 // MachineRegisterInfo callback functions to notify events.
538 void MRI_NoteNewVirtualRegister(Register Reg) override;
539 void MRI_NoteCloneVirtualRegister(Register NewReg, Register SrcReg) override;
540
541public:
542 static bool MFMAVGPRForm;
543
549
550private:
551 // To track virtual VGPR + lane index for each subregister of the SGPR spilled
552 // to frameindex key during SILowerSGPRSpills pass.
554 SGPRSpillsToVirtualVGPRLanes;
555 // To track physical VGPR + lane index for CSR SGPR spills and special SGPRs
556 // like Frame Pointer identified during PrologEpilogInserter.
558 SGPRSpillsToPhysicalVGPRLanes;
559 unsigned NumVirtualVGPRSpillLanes = 0;
560 unsigned NumPhysicalVGPRSpillLanes = 0;
561 SmallVector<Register, 2> SpillVGPRs;
562 SmallVector<Register, 2> SpillPhysVGPRs;
563 using WWMSpillsMap = MapVector<Register, int>;
564 // To track the registers used in instructions that can potentially modify the
565 // inactive lanes. The WWM instructions and the writelane instructions for
566 // spilling SGPRs to VGPRs fall under such category of operations. The VGPRs
567 // modified by them should be spilled/restored at function prolog/epilog to
568 // avoid any undesired outcome. Each entry in this map holds a pair of values,
569 // the VGPR and its stack slot index.
570 WWMSpillsMap WWMSpills;
571
572 // Before allocation, the VGPR registers are partitioned into two distinct
573 // sets, the first one for WWM-values and the second set for non-WWM values.
574 // The latter set should be reserved during WWM-regalloc.
575 BitVector NonWWMRegMask;
576
577 using ReservedRegSet = SmallSetVector<Register, 8>;
578 // To track the VGPRs reserved for WWM instructions. They get stack slots
579 // later during PrologEpilogInserter and get added into the superset WWMSpills
580 // for actual spilling. A separate set makes the register reserved part and
581 // the serialization easier.
582 ReservedRegSet WWMReservedRegs;
583
584 bool IsWholeWaveFunction = false;
585
586 using PrologEpilogSGPRSpill =
587 std::pair<Register, PrologEpilogSGPRSaveRestoreInfo>;
588 // To track the SGPR spill method used for a CSR SGPR register during
589 // frame lowering. Even though the SGPR spills are handled during
590 // SILowerSGPRSpills pass, some special handling needed later during the
591 // PrologEpilogInserter.
592 SmallVector<PrologEpilogSGPRSpill, 3> PrologEpilogSGPRSpills;
593
594 // To save/restore EXEC MASK around WWM spills and copies.
595 Register SGPRForEXECCopy;
596
597 DenseMap<int, VGPRSpillToAGPR> VGPRToAGPRSpills;
598
599 // AGPRs used for VGPR spills.
601
602 // VGPRs used for AGPR spills.
604
605 // Emergency stack slot. Sometimes, we create this before finalizing the stack
606 // frame, so save it here and add it to the RegScavenger later.
607 std::optional<int> ScavengeFI;
608
609 // Map each VGPR CSR to the mask needed to save and restore it using block
610 // load/store instructions. Only used if the subtarget feature for VGPR block
611 // load/store is enabled.
613
614private:
615 Register VGPRForAGPRCopy;
616
617 bool allocateVirtualVGPRForSGPRSpills(MachineFunction &MF, int FI,
618 unsigned LaneIndex);
619 bool allocatePhysicalVGPRForSGPRSpills(MachineFunction &MF, int FI,
620 unsigned LaneIndex,
621 bool IsPrologEpilog);
622
623public:
625 return VGPRForAGPRCopy;
626 }
627
628 void setVGPRForAGPRCopy(Register NewVGPRForAGPRCopy) {
629 VGPRForAGPRCopy = NewVGPRForAGPRCopy;
630 }
631
632 bool isCalleeSavedReg(const MCPhysReg *CSRegs, MCPhysReg Reg) const;
633
634 void setMaskForVGPRBlockOps(Register RegisterBlock, uint32_t Mask) {
635 MaskForVGPRBlockOps.grow(RegisterBlock);
636 MaskForVGPRBlockOps[RegisterBlock] = Mask;
637 }
638
640 return MaskForVGPRBlockOps[RegisterBlock];
641 }
642
643 bool hasMaskForVGPRBlockOps(Register RegisterBlock) const {
644 return MaskForVGPRBlockOps.inBounds(RegisterBlock);
645 }
646
647public:
649 SIMachineFunctionInfo(const Function &F, const GCNSubtarget *STI);
650
654 const override;
655
657 const MachineFunction &MF,
659 SMDiagnostic &Error, SMRange &SourceRange);
660
661 void reserveWWMRegister(Register Reg) { WWMReservedRegs.insert(Reg); }
662 bool isWWMReg(Register Reg) const {
663 return Reg.isVirtual() ? checkFlag(Reg, AMDGPU::VirtRegFlag::WWM_REG)
664 : WWMReservedRegs.contains(Reg);
665 }
666
667 void updateNonWWMRegMask(BitVector &RegMask) { NonWWMRegMask = RegMask; }
668 BitVector getNonWWMRegMask() const { return NonWWMRegMask; }
669 void clearNonWWMRegAllocMask() { NonWWMRegMask.clear(); }
670
671 SIModeRegisterDefaults getMode() const { return Mode; }
672
674 getSGPRSpillToVirtualVGPRLanes(int FrameIndex) const {
675 auto I = SGPRSpillsToVirtualVGPRLanes.find(FrameIndex);
676 return (I == SGPRSpillsToVirtualVGPRLanes.end())
678 : ArrayRef(I->second);
679 }
680
681 ArrayRef<Register> getSGPRSpillVGPRs() const { return SpillVGPRs; }
682 ArrayRef<Register> getSGPRSpillPhysVGPRs() const { return SpillPhysVGPRs; }
683
684 const WWMSpillsMap &getWWMSpills() const { return WWMSpills; }
685 const ReservedRegSet &getWWMReservedRegs() const { return WWMReservedRegs; }
686
688 return WWMReservedRegs.contains(Reg);
689 }
690
691 bool isWholeWaveFunction() const { return IsWholeWaveFunction; }
692
694 assert(is_sorted(PrologEpilogSGPRSpills, llvm::less_first()));
695 return PrologEpilogSGPRSpills;
696 }
697
698 GCNUserSGPRUsageInfo &getUserSGPRInfo() { return UserSGPRInfo; }
699
700 const GCNUserSGPRUsageInfo &getUserSGPRInfo() const { return UserSGPRInfo; }
701
705
706 // Insert a new entry in the right place to keep the vector in sorted order.
707 // This should be cheap since the vector is expected to be very short.
708 PrologEpilogSGPRSpills.insert(
710 PrologEpilogSGPRSpills, Reg,
711 [](const auto &LHS, const auto &RHS) { return LHS < RHS.first; }),
712 std::make_pair(Reg, SI));
713 }
714
715 // Check if an entry created for \p Reg in PrologEpilogSGPRSpills. Return true
716 // on success and false otherwise.
718 const auto *I = find_if(PrologEpilogSGPRSpills, [&Reg](const auto &Spill) {
719 return Spill.first == Reg;
720 });
721 return I != PrologEpilogSGPRSpills.end();
722 }
723
724 // Get the scratch SGPR if allocated to save/restore \p Reg.
726 const auto *I = find_if(PrologEpilogSGPRSpills, [&Reg](const auto &Spill) {
727 return Spill.first == Reg;
728 });
729 if (I != PrologEpilogSGPRSpills.end() &&
730 I->second.getKind() == SGPRSaveKind::COPY_TO_SCRATCH_SGPR)
731 return I->second.getReg();
732
733 return AMDGPU::NoRegister;
734 }
735
736 // Get all scratch SGPRs allocated to copy/restore the SGPR spills.
738 for (const auto &SI : PrologEpilogSGPRSpills) {
739 if (SI.second.getKind() == SGPRSaveKind::COPY_TO_SCRATCH_SGPR)
740 Regs.push_back(SI.second.getReg());
741 }
742 }
743
744 // Check if \p FI is allocated for any SGPR spill to a VGPR lane during PEI.
746 return find_if(PrologEpilogSGPRSpills,
747 [FI](const std::pair<Register,
749 return SI.second.getKind() ==
751 SI.second.getIndex() == FI;
752 }) != PrologEpilogSGPRSpills.end();
753 }
754
757 const auto *I = find_if(PrologEpilogSGPRSpills, [&Reg](const auto &Spill) {
758 return Spill.first == Reg;
759 });
760 assert(I != PrologEpilogSGPRSpills.end());
761
762 return I->second;
763 }
764
766 getSGPRSpillToPhysicalVGPRLanes(int FrameIndex) const {
767 auto I = SGPRSpillsToPhysicalVGPRLanes.find(FrameIndex);
768 return (I == SGPRSpillsToPhysicalVGPRLanes.end())
770 : ArrayRef(I->second);
771 }
772
774 assert(Reg.isVirtual());
775 if (VRegFlags.inBounds(Reg))
776 VRegFlags[Reg] |= Flag;
777 }
778
779 bool checkFlag(Register Reg, uint8_t Flag) const {
780 if (Reg.isPhysical())
781 return false;
782
783 return VRegFlags.inBounds(Reg) && VRegFlags[Reg] & Flag;
784 }
785
786 bool hasVRegFlags() { return VRegFlags.size(); }
787
789 Align Alignment = Align(4));
790
792 MachineFunction &MF,
793 SmallVectorImpl<std::pair<Register, int>> &CalleeSavedRegs,
794 SmallVectorImpl<std::pair<Register, int>> &ScratchRegs) const;
795
797 return SpillAGPR;
798 }
799
800 Register getSGPRForEXECCopy() const { return SGPRForEXECCopy; }
801
802 void setSGPRForEXECCopy(Register Reg) { SGPRForEXECCopy = Reg; }
803
805 return SpillVGPR;
806 }
807
808 MCPhysReg getVGPRToAGPRSpill(int FrameIndex, unsigned Lane) const {
809 auto I = VGPRToAGPRSpills.find(FrameIndex);
810 return (I == VGPRToAGPRSpills.end()) ? (MCPhysReg)AMDGPU::NoRegister
811 : I->second.Lanes[Lane];
812 }
813
814 void setVGPRToAGPRSpillDead(int FrameIndex) {
815 auto I = VGPRToAGPRSpills.find(FrameIndex);
816 if (I != VGPRToAGPRSpills.end())
817 I->second.IsDead = true;
818 }
819
820 // To bring the allocated WWM registers in \p WWMVGPRs to the lowest available
821 // range.
824 BitVector &SavedVGPRs);
825
827 bool SpillToPhysVGPRLane = false,
828 bool IsPrologEpilog = false);
829 bool allocateVGPRSpillToAGPR(MachineFunction &MF, int FI, bool isAGPRtoVGPR);
830
831 /// If \p ResetSGPRSpillStackIDs is true, reset the stack ID from sgpr-spill
832 /// to the default stack.
834 bool ResetSGPRSpillStackIDs);
835
837 std::optional<int> getOptionalScavengeFI() const { return ScavengeFI; }
838
839 unsigned getBytesInStackArgArea() const {
840 return BytesInStackArgArea;
841 }
842
843 void setBytesInStackArgArea(unsigned Bytes) {
844 BytesInStackArgArea = Bytes;
845 }
846
847 bool isDynamicVGPREnabled() const { return DynamicVGPRBlockSize != 0; }
848 unsigned getDynamicVGPRBlockSize() const { return DynamicVGPRBlockSize; }
849
850 // This is only used if we need to save any dynamic VGPRs in scratch.
852 return ScratchReservedForDynamicVGPRs;
853 }
854
855 void setScratchReservedForDynamicVGPRs(unsigned SizeInBytes) {
856 ScratchReservedForDynamicVGPRs = SizeInBytes;
857 }
858
859 // Add user SGPRs.
871 unsigned AllocSizeDWord, int KernArgIdx,
872 int PaddingSGPRs);
873
874 /// Increment user SGPRs used for padding the argument list only.
876 Register Next = getNextUserSGPR();
877 ++NumUserSGPRs;
878 return Next;
879 }
880
881 // Add system SGPRs.
883 ArgInfo.WorkGroupIDX = ArgDescriptor::createRegister(getNextSystemSGPR());
884 NumSystemSGPRs += 1;
885 return ArgInfo.WorkGroupIDX.getRegister();
886 }
887
889 ArgInfo.WorkGroupIDY = ArgDescriptor::createRegister(getNextSystemSGPR());
890 NumSystemSGPRs += 1;
891 return ArgInfo.WorkGroupIDY.getRegister();
892 }
893
895 ArgInfo.WorkGroupIDZ = ArgDescriptor::createRegister(getNextSystemSGPR());
896 NumSystemSGPRs += 1;
897 return ArgInfo.WorkGroupIDZ.getRegister();
898 }
899
901 ArgInfo.WorkGroupInfo = ArgDescriptor::createRegister(getNextSystemSGPR());
902 NumSystemSGPRs += 1;
903 return ArgInfo.WorkGroupInfo.getRegister();
904 }
905
906 bool hasLDSKernelId() const { return LDSKernelId; }
907
908 // Add special VGPR inputs
910 ArgInfo.WorkItemIDX = Arg;
911 }
912
914 ArgInfo.WorkItemIDY = Arg;
915 }
916
918 ArgInfo.WorkItemIDZ = Arg;
919 }
920
922 ArgInfo.PrivateSegmentWaveByteOffset
923 = ArgDescriptor::createRegister(getNextSystemSGPR());
924 NumSystemSGPRs += 1;
925 return ArgInfo.PrivateSegmentWaveByteOffset.getRegister();
926 }
927
929 ArgInfo.PrivateSegmentWaveByteOffset = ArgDescriptor::createRegister(Reg);
930 }
931
932 bool hasWorkGroupIDX() const {
933 return WorkGroupIDX;
934 }
935
936 bool hasWorkGroupIDY() const {
937 return WorkGroupIDY;
938 }
939
940 bool hasWorkGroupIDZ() const {
941 return WorkGroupIDZ;
942 }
943
944 bool hasWorkGroupInfo() const {
945 return WorkGroupInfo;
946 }
947
949 return PrivateSegmentWaveByteOffset;
950 }
951
952 bool hasWorkItemIDX() const {
953 return WorkItemIDX;
954 }
955
956 bool hasWorkItemIDY() const {
957 return WorkItemIDY;
958 }
959
960 bool hasWorkItemIDZ() const {
961 return WorkItemIDZ;
962 }
963
964 bool hasImplicitArgPtr() const {
965 return ImplicitArgPtr;
966 }
967
969 return ArgInfo;
970 }
971
973 return ArgInfo;
974 }
975
976 std::tuple<const ArgDescriptor *, const TargetRegisterClass *, LLT>
978 return ArgInfo.getPreloadedValue(Value);
979 }
980
982 const auto *Arg = std::get<0>(ArgInfo.getPreloadedValue(Value));
983 return Arg ? Arg->getRegister() : MCRegister();
984 }
985
986 unsigned getGITPtrHigh() const {
987 return GITPtrHigh;
988 }
989
990 Register getGITPtrLoReg(const MachineFunction &MF) const;
991
993 return HighBitsOf32BitAddress;
994 }
995
996 unsigned getNumUserSGPRs() const {
997 return NumUserSGPRs;
998 }
999
1000 unsigned getNumPreloadedSGPRs() const {
1001 return NumUserSGPRs + NumSystemSGPRs;
1002 }
1003
1005 return UserSGPRInfo.getNumKernargPreloadSGPRs();
1006 }
1007
1008 unsigned getNumWaveDispatchSGPRs() const { return NumWaveDispatchSGPRs; }
1009
1010 void setNumWaveDispatchSGPRs(unsigned Count) { NumWaveDispatchSGPRs = Count; }
1011
1012 unsigned getNumWaveDispatchVGPRs() const { return NumWaveDispatchVGPRs; }
1013
1014 void setNumWaveDispatchVGPRs(unsigned Count) { NumWaveDispatchVGPRs = Count; }
1015
1017 return ArgInfo.PrivateSegmentWaveByteOffset.getRegister();
1018 }
1019
1020 /// Returns the physical register reserved for use as the resource
1021 /// descriptor for scratch accesses.
1023 return ScratchRSrcReg;
1024 }
1025
1027 assert(Reg != 0 && "Should never be unset");
1028 ScratchRSrcReg = Reg;
1029 }
1030
1032 return FrameOffsetReg;
1033 }
1034
1036 assert(Reg != 0 && "Should never be unset");
1037 FrameOffsetReg = Reg;
1038 }
1039
1041 assert(Reg != 0 && "Should never be unset");
1042 StackPtrOffsetReg = Reg;
1043 }
1044
1045 void setLongBranchReservedReg(Register Reg) { LongBranchReservedReg = Reg; }
1046
1047 // Note the unset value for this is AMDGPU::SP_REG rather than
1048 // NoRegister. This is mostly a workaround for MIR tests where state that
1049 // can't be directly computed from the function is not preserved in serialized
1050 // MIR.
1052 return StackPtrOffsetReg;
1053 }
1054
1055 Register getLongBranchReservedReg() const { return LongBranchReservedReg; }
1056
1058 return ArgInfo.QueuePtr.getRegister();
1059 }
1060
1062 return ArgInfo.ImplicitBufferPtr.getRegister();
1063 }
1064
1065 bool hasSpilledSGPRs() const {
1066 return HasSpilledSGPRs;
1067 }
1068
1069 void setHasSpilledSGPRs(bool Spill = true) {
1070 HasSpilledSGPRs = Spill;
1071 }
1072
1073 bool hasSpilledVGPRs() const {
1074 return HasSpilledVGPRs;
1075 }
1076
1077 void setHasSpilledVGPRs(bool Spill = true) {
1078 HasSpilledVGPRs = Spill;
1079 }
1080
1082 return HasNonSpillStackObjects;
1083 }
1084
1085 void setHasNonSpillStackObjects(bool StackObject = true) {
1086 HasNonSpillStackObjects = StackObject;
1087 }
1088
1089 bool isStackRealigned() const {
1090 return IsStackRealigned;
1091 }
1092
1093 void setIsStackRealigned(bool Realigned = true) {
1094 IsStackRealigned = Realigned;
1095 }
1096
1097 unsigned getNumSpilledSGPRs() const {
1098 return NumSpilledSGPRs;
1099 }
1100
1101 unsigned getNumSpilledVGPRs() const {
1102 return NumSpilledVGPRs;
1103 }
1104
1105 void addToSpilledSGPRs(unsigned num) {
1106 NumSpilledSGPRs += num;
1107 }
1108
1109 void addToSpilledVGPRs(unsigned num) {
1110 NumSpilledVGPRs += num;
1111 }
1112
1113 unsigned getPSInputAddr() const {
1114 return PSInputAddr;
1115 }
1116
1117 unsigned getPSInputEnable() const {
1118 return PSInputEnable;
1119 }
1120
1121 bool isPSInputAllocated(unsigned Index) const {
1122 return PSInputAddr & (1 << Index);
1123 }
1124
1125 void markPSInputAllocated(unsigned Index) {
1126 PSInputAddr |= 1 << Index;
1127 }
1128
1129 void markPSInputEnabled(unsigned Index) {
1130 PSInputEnable |= 1 << Index;
1131 }
1132
1133 bool returnsVoid() const {
1134 return ReturnsVoid;
1135 }
1136
1138 ReturnsVoid = Value;
1139 }
1140
1141 /// \returns A pair of default/requested minimum/maximum flat work group sizes
1142 /// for this function.
1143 std::pair<unsigned, unsigned> getFlatWorkGroupSizes() const {
1144 return FlatWorkGroupSizes;
1145 }
1146
1147 /// \returns Default/requested minimum flat work group size for this function.
1148 unsigned getMinFlatWorkGroupSize() const {
1149 return FlatWorkGroupSizes.first;
1150 }
1151
1152 /// \returns Default/requested maximum flat work group size for this function.
1153 unsigned getMaxFlatWorkGroupSize() const {
1154 return FlatWorkGroupSizes.second;
1155 }
1156
1157 /// \returns A pair of default/requested minimum/maximum number of waves per
1158 /// execution unit.
1159 std::pair<unsigned, unsigned> getWavesPerEU() const {
1160 return WavesPerEU;
1161 }
1162
1163 /// \returns Default/requested minimum number of waves per execution unit.
1164 unsigned getMinWavesPerEU() const {
1165 return WavesPerEU.first;
1166 }
1167
1168 /// \returns Default/requested maximum number of waves per execution unit.
1169 unsigned getMaxWavesPerEU() const {
1170 return WavesPerEU.second;
1171 }
1172
1175 return &GWSResourcePSV;
1176 }
1177
1178 unsigned getOccupancy() const {
1179 return Occupancy;
1180 }
1181
1182 unsigned getMinAllowedOccupancy() const {
1183 if (!isMemoryBound() && !needsWaveLimiter())
1184 return Occupancy;
1185 return (Occupancy < 4) ? Occupancy : 4;
1186 }
1187
1188 void limitOccupancy(const MachineFunction &MF);
1189
1190 void limitOccupancy(unsigned Limit) {
1191 if (Occupancy > Limit)
1192 Occupancy = Limit;
1193 }
1194
1195 void increaseOccupancy(const MachineFunction &MF, unsigned Limit) {
1196 if (Occupancy < Limit)
1197 Occupancy = Limit;
1198 limitOccupancy(MF);
1199 }
1200
1201 unsigned getMaxMemoryClusterDWords() const { return MaxMemoryClusterDWords; }
1202
1203 unsigned getMinNumAGPRs() const { return MinNumAGPRs; }
1204
1205 // \returns true if a function has a use of AGPRs via inline asm or
1206 // has a call which may use it.
1207 bool mayUseAGPRs(const Function &F) const;
1208
1209 /// \returns Default/requested number of work groups for this function.
1210 SmallVector<unsigned> getMaxNumWorkGroups() const { return MaxNumWorkGroups; }
1211
1212 unsigned getMaxNumWorkGroupsX() const { return MaxNumWorkGroups[0]; }
1213 unsigned getMaxNumWorkGroupsY() const { return MaxNumWorkGroups[1]; }
1214 unsigned getMaxNumWorkGroupsZ() const { return MaxNumWorkGroups[2]; }
1215
1216 AMDGPU::ClusterDimsAttr getClusterDims() const { return ClusterDims; }
1217};
1218
1219} // end namespace llvm
1220
1221#endif // LLVM_LIB_TARGET_AMDGPU_SIMACHINEFUNCTIONINFO_H
assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")
Provides AMDGPU specific target descriptions.
The AMDGPU TargetMachine interface definition for hw codegen targets.
static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")
AMD GCN specific subclass of TargetSubtarget.
static bool IsRegister(const MCParsedAsmOperand &op)
#define F(x, y, z)
Definition MD5.cpp:55
#define I(x, y, z)
Definition MD5.cpp:58
Register Reg
Register const TargetRegisterInfo * TRI
Promote Memory to Register
Definition Mem2Reg.cpp:110
Basic Register Allocator
static cl::opt< RegAllocEvictionAdvisorAnalysisLegacy::AdvisorMode > Mode("regalloc-enable-advisor", cl::Hidden, cl::init(RegAllocEvictionAdvisorAnalysisLegacy::AdvisorMode::Default), cl::desc("Enable regalloc advisor mode"), cl::values(clEnumValN(RegAllocEvictionAdvisorAnalysisLegacy::AdvisorMode::Default, "default", "Default"), clEnumValN(RegAllocEvictionAdvisorAnalysisLegacy::AdvisorMode::Release, "release", "precompiled"), clEnumValN(RegAllocEvictionAdvisorAnalysisLegacy::AdvisorMode::Development, "development", "for training")))
Interface definition for SIInstrInfo.
static bool contains(SmallPtrSetImpl< ConstantExpr * > &Cache, ConstantExpr *Expr, Constant *C)
Definition Value.cpp:480
This file implements a set that has insertion order iteration characteristics.
This file defines the SmallVector class.
Value * RHS
Value * LHS
void printCustom(raw_ostream &OS) const override
Implement printing for PseudoSourceValue.
static bool classof(const PseudoSourceValue *V)
AMDGPUGWSResourcePseudoSourceValue(const AMDGPUTargetMachine &TM)
bool mayAlias(const MachineFrameInfo *) const override
Return true if the memory pointed to by this PseudoSourceValue can ever alias an LLVM IR Value.
bool isAliased(const MachineFrameInfo *) const override
Test whether the memory pointed to by this PseudoSourceValue may also be pointed to by an LLVM IR Val...
AMDGPUMachineFunction(const Function &F, const AMDGPUSubtarget &ST)
bool isConstant(const MachineFrameInfo *) const override
Test whether the memory pointed to by this PseudoSourceValue has a constant value.
AMDGPUPseudoSourceValue(unsigned Kind, const AMDGPUTargetMachine &TM)
bool mayAlias(const MachineFrameInfo *) const override
Return true if the memory pointed to by this PseudoSourceValue can ever alias an LLVM IR Value.
bool isAliased(const MachineFrameInfo *) const override
Test whether the memory pointed to by this PseudoSourceValue may also be pointed to by an LLVM IR Val...
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition ArrayRef.h:41
Lightweight error class with error context and mandatory checking.
Definition Error.h:159
Wrapper class representing physical registers. Should be passed by value.
Definition MCRegister.h:33
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
This class implements a map that also provides access to all stored values in a deterministic order.
Definition MapVector.h:36
PrologEpilogSGPRSaveRestoreInfo(SGPRSaveKind K, Register R)
PrologEpilogSGPRSaveRestoreInfo(SGPRSaveKind K, int I)
Special value supplied for machine level alias analysis.
PseudoSourceValue(unsigned Kind, const TargetMachine &TM)
Wrapper class representing virtual and physical registers.
Definition Register.h:19
This class keeps track of the SPI_SP_INPUT_ADDR config register, which tells the hardware which inter...
ArrayRef< PrologEpilogSGPRSpill > getPrologEpilogSGPRSpills() const
const WWMSpillsMap & getWWMSpills() const
bool isPSInputAllocated(unsigned Index) const
void getAllScratchSGPRCopyDstRegs(SmallVectorImpl< Register > &Regs) const
ArrayRef< MCPhysReg > getAGPRSpillVGPRs() const
bool initializeBaseYamlFields(const yaml::SIMachineFunctionInfo &YamlMFI, const MachineFunction &MF, PerFunctionMIParsingState &PFS, SMDiagnostic &Error, SMRange &SourceRange)
void shiftWwmVGPRsToLowestRange(MachineFunction &MF, SmallVectorImpl< Register > &WWMVGPRs, BitVector &SavedVGPRs)
void setWorkItemIDY(ArgDescriptor Arg)
void increaseOccupancy(const MachineFunction &MF, unsigned Limit)
Register addPrivateSegmentSize(const SIRegisterInfo &TRI)
void setWorkItemIDZ(ArgDescriptor Arg)
std::pair< unsigned, unsigned > getWavesPerEU() const
void setMaskForVGPRBlockOps(Register RegisterBlock, uint32_t Mask)
MCPhysReg getVGPRToAGPRSpill(int FrameIndex, unsigned Lane) const
GCNUserSGPRUsageInfo & getUserSGPRInfo()
void allocateWWMSpill(MachineFunction &MF, Register VGPR, uint64_t Size=4, Align Alignment=Align(4))
Register addDispatchPtr(const SIRegisterInfo &TRI)
void setFlag(Register Reg, uint8_t Flag)
void setVGPRToAGPRSpillDead(int FrameIndex)
std::pair< unsigned, unsigned > getFlatWorkGroupSizes() const
Register addFlatScratchInit(const SIRegisterInfo &TRI)
Register getScratchRSrcReg() const
Returns the physical register reserved for use as the resource descriptor for scratch accesses.
Register addReservedUserSGPR()
Increment user SGPRs used for padding the argument list only.
ArrayRef< MCPhysReg > getVGPRSpillAGPRs() const
ArrayRef< Register > getSGPRSpillPhysVGPRs() const
int getScavengeFI(MachineFrameInfo &MFI, const SIRegisterInfo &TRI)
Register addQueuePtr(const SIRegisterInfo &TRI)
ArrayRef< SIRegisterInfo::SpilledReg > getSGPRSpillToVirtualVGPRLanes(int FrameIndex) const
uint32_t getMaskForVGPRBlockOps(Register RegisterBlock) const
SIMachineFunctionInfo(const SIMachineFunctionInfo &MFI)=default
bool hasMaskForVGPRBlockOps(Register RegisterBlock) const
AMDGPU::ClusterDimsAttr getClusterDims() const
SmallVector< unsigned > getMaxNumWorkGroups() const
bool hasPrologEpilogSGPRSpillEntry(Register Reg) const
Register getGITPtrLoReg(const MachineFunction &MF) const
void setVGPRForAGPRCopy(Register NewVGPRForAGPRCopy)
bool allocateVGPRSpillToAGPR(MachineFunction &MF, int FI, bool isAGPRtoVGPR)
Reserve AGPRs or VGPRs to support spilling for FrameIndex FI.
void splitWWMSpillRegisters(MachineFunction &MF, SmallVectorImpl< std::pair< Register, int > > &CalleeSavedRegs, SmallVectorImpl< std::pair< Register, int > > &ScratchRegs) const
void setBytesInStackArgArea(unsigned Bytes)
void setNumWaveDispatchSGPRs(unsigned Count)
SIModeRegisterDefaults getMode() const
bool isWWMReservedRegister(Register Reg) const
ArrayRef< SIRegisterInfo::SpilledReg > getSGPRSpillToPhysicalVGPRLanes(int FrameIndex) const
std::tuple< const ArgDescriptor *, const TargetRegisterClass *, LLT > getPreloadedValue(AMDGPUFunctionArgInfo::PreloadedValue Value) const
bool mayUseAGPRs(const Function &F) const
bool isCalleeSavedReg(const MCPhysReg *CSRegs, MCPhysReg Reg) const
const GCNUserSGPRUsageInfo & getUserSGPRInfo() const
bool allocateSGPRSpillToVGPRLane(MachineFunction &MF, int FI, bool SpillToPhysVGPRLane=false, bool IsPrologEpilog=false)
void setPrivateSegmentWaveByteOffset(Register Reg)
void setLongBranchReservedReg(Register Reg)
const AMDGPUFunctionArgInfo & getArgInfo() const
Register addKernargSegmentPtr(const SIRegisterInfo &TRI)
Register addDispatchID(const SIRegisterInfo &TRI)
void setHasSpilledVGPRs(bool Spill=true)
bool removeDeadFrameIndices(MachineFrameInfo &MFI, bool ResetSGPRSpillStackIDs)
If ResetSGPRSpillStackIDs is true, reset the stack ID from sgpr-spill to the default stack.
void setScratchReservedForDynamicVGPRs(unsigned SizeInBytes)
void markPSInputAllocated(unsigned Index)
void setWorkItemIDX(ArgDescriptor Arg)
bool isWWMReg(Register Reg) const
MachineFunctionInfo * clone(BumpPtrAllocator &Allocator, MachineFunction &DestMF, const DenseMap< MachineBasicBlock *, MachineBasicBlock * > &Src2DstMBB) const override
Make a functionally equivalent copy of this MachineFunctionInfo in MF.
bool checkFlag(Register Reg, uint8_t Flag) const
void setNumWaveDispatchVGPRs(unsigned Count)
void markPSInputEnabled(unsigned Index)
MCRegister getPreloadedReg(AMDGPUFunctionArgInfo::PreloadedValue Value) const
void setHasSpilledSGPRs(bool Spill=true)
bool checkIndexInPrologEpilogSGPRSpills(int FI) const
void updateNonWWMRegMask(BitVector &RegMask)
Register addPrivateSegmentBuffer(const SIRegisterInfo &TRI)
unsigned getScratchReservedForDynamicVGPRs() const
const ReservedRegSet & getWWMReservedRegs() const
std::optional< int > getOptionalScavengeFI() const
Register addImplicitBufferPtr(const SIRegisterInfo &TRI)
AMDGPUFunctionArgInfo & getArgInfo()
const PrologEpilogSGPRSaveRestoreInfo & getPrologEpilogSGPRSaveRestoreInfo(Register Reg) const
void setHasNonSpillStackObjects(bool StackObject=true)
void setIsStackRealigned(bool Realigned=true)
void limitOccupancy(const MachineFunction &MF)
ArrayRef< Register > getSGPRSpillVGPRs() const
SmallVectorImpl< MCRegister > * addPreloadedKernArg(const SIRegisterInfo &TRI, const TargetRegisterClass *RC, unsigned AllocSizeDWord, int KernArgIdx, int PaddingSGPRs)
void addToPrologEpilogSGPRSpills(Register Reg, PrologEpilogSGPRSaveRestoreInfo SI)
Register getScratchSGPRCopyDstReg(Register Reg) const
Register getPrivateSegmentWaveByteOffsetSystemSGPR() const
const AMDGPUGWSResourcePseudoSourceValue * getGWSPSV(const AMDGPUTargetMachine &TM)
Instances of this class encapsulate one diagnostic report, allowing printing to a raw_ostream as a ca...
Definition SourceMgr.h:282
Represents a range in source code.
Definition SMLoc.h:48
A SetVector that performs no allocations if smaller than a certain size.
Definition SetVector.h:338
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
LLVM Value Representation.
Definition Value.h:75
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition raw_ostream.h:53
virtual bool outputting() const =0
void mapOptional(StringRef Key, T &Val)
Definition YAMLTraits.h:799
virtual void setError(const Twine &)=0
void mapRequired(StringRef Key, T &Val)
Definition YAMLTraits.h:789
virtual std::vector< StringRef > keys()=0
This is an optimization pass for GlobalISel generic memory operations.
auto upper_bound(R &&Range, T &&Value)
Provide wrappers to std::upper_bound which take ranges instead of having to pass begin/end explicitly...
Definition STLExtras.h:2009
FunctionAddr VTableAddr Count
Definition InstrProf.h:139
bool is_sorted(R &&Range, Compare C)
Wrapper function around std::is_sorted to check if elements in a range R are sorted with respect to a...
Definition STLExtras.h:1922
BumpPtrAllocatorImpl BumpPtrAllocator
The standard BumpPtrAllocator which just uses the default template parameters.
Definition Allocator.h:383
@ Other
Any other memory.
Definition ModRef.h:68
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
Definition MCRegister.h:21
FunctionAddr VTableAddr Next
Definition InstrProf.h:141
ArrayRef(const T &OneElt) -> ArrayRef< T >
constexpr unsigned DefaultMemoryClusterDWordsLimit
Definition SIInstrInfo.h:40
auto find_if(R &&Range, UnaryPredicate P)
Provide wrappers to std::find_if which take ranges instead of having to pass begin/end explicitly.
Definition STLExtras.h:1760
bool is_contained(R &&Range, const E &Element)
Returns true if Element is found in Range.
Definition STLExtras.h:1899
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition Alignment.h:39
static ArgDescriptor createRegister(Register Reg, unsigned Mask=~0u)
@ PreserveSign
The sign of a flushed-to-zero number is preserved in the sign of 0.
MachineFunctionInfo - This class can be derived from and used by targets to hold private target-speci...
unsigned operator()(Register Reg) const
Function object to check whether the first component of a container supported by std::get (like std::...
Definition STLExtras.h:1427
Targets should override this in a way that mirrors the implementation of llvm::MachineFunctionInfo.
static void mapping(IO &YamlIO, SIArgumentInfo &AI)
static void mapping(IO &YamlIO, SIArgument &A)
static void mapping(IO &YamlIO, SIMachineFunctionInfo &MFI)
static void mapping(IO &YamlIO, SIMode &Mode)
This class should be specialized by any type that needs to be converted to/from a YAML mapping.
Definition YAMLTraits.h:62
std::optional< SIArgument > PrivateSegmentWaveByteOffset
std::optional< SIArgument > WorkGroupIDY
std::optional< SIArgument > FlatScratchInit
std::optional< SIArgument > DispatchPtr
std::optional< SIArgument > DispatchID
std::optional< SIArgument > WorkItemIDY
std::optional< SIArgument > WorkGroupIDX
std::optional< SIArgument > ImplicitArgPtr
std::optional< SIArgument > QueuePtr
std::optional< SIArgument > WorkGroupInfo
std::optional< SIArgument > LDSKernelId
std::optional< SIArgument > ImplicitBufferPtr
std::optional< SIArgument > WorkItemIDX
std::optional< SIArgument > KernargSegmentPtr
std::optional< SIArgument > WorkItemIDZ
std::optional< SIArgument > PrivateSegmentSize
std::optional< SIArgument > PrivateSegmentBuffer
std::optional< SIArgument > WorkGroupIDZ
std::optional< unsigned > Mask
SIArgument(const SIArgument &Other)
SIArgument & operator=(const SIArgument &Other)
static SIArgument createArgument(bool IsReg)
SmallVector< StringValue > WWMReservedRegs
void mappingImpl(yaml::IO &YamlIO) override
std::optional< SIArgumentInfo > ArgInfo
SmallVector< StringValue, 2 > SpillPhysVGPRS
std::optional< FrameIndex > ScavengeFI
SIMode(const SIModeRegisterDefaults &Mode)
bool operator==(const SIMode Other) const
A wrapper around std::string which contains a source range that's being set during parsing.