llvm::SIModeRegisterDefaults Struct Reference

#include "Target/AMDGPU/SIModeRegisterDefaults.h"

Public Member Functions
	SIModeRegisterDefaults ()
	SIModeRegisterDefaults (const Function &F, const GCNSubtarget &ST)
bool	operator== (const SIModeRegisterDefaults Other) const
uint32_t	fpDenormModeSPValue () const
	Get the encoding value for the FP_DENORM bits of the mode register for the FP32 denormal mode.
uint32_t	fpDenormModeDPValue () const
	Get the encoding value for the FP_DENORM bits of the mode register for the FP64/FP16 denormal mode.
bool	isInlineCompatible (SIModeRegisterDefaults CalleeMode) const

Static Public Member Functions
static SIModeRegisterDefaults	getDefaultForCallingConv (CallingConv::ID CC)

Public Attributes
bool	IEEE: 1
	Floating point opcodes that support exception flag gathering quiet and propagate signaling NaN inputs per IEEE 754-2008.
bool	DX10Clamp: 1
	Used by the vector ALU to force DX10-style treatment of NaNs: when set, clamp NaN to zero; otherwise, pass NaN through.
DenormalMode	FP32Denormals
	If this is set, neither input or output denormals are flushed for most f32 instructions.
DenormalMode	FP64FP16Denormals
	If this is set, neither input or output denormals are flushed for both f64 and f16/v2f16 instructions.

Detailed Description

Definition at line 20 of file SIModeRegisterDefaults.h.

Constructor & Destructor Documentation

SIModeRegisterDefaults() [1/2]

llvm::SIModeRegisterDefaults::SIModeRegisterDefaults ( )

inline

Definition at line 39 of file SIModeRegisterDefaults.h.

SIModeRegisterDefaults() [2/2]

SIModeRegisterDefaults::SIModeRegisterDefaults	(	const Function &	F,
		const GCNSubtarget &	ST
	)

Definition at line 14 of file SIModeRegisterDefaults.cpp.

References DX10Clamp, llvm::StringRef::empty(), F, FP32Denormals, FP64FP16Denormals, getDefaultForCallingConv(), IEEE, and llvm::parseDenormalFPAttribute().

Member Function Documentation

fpDenormModeDPValue()

uint32_t llvm::SIModeRegisterDefaults::fpDenormModeDPValue ( ) const

inline

Get the encoding value for the FP_DENORM bits of the mode register for the FP64/FP16 denormal mode.

Definition at line 73 of file SIModeRegisterDefaults.h.

References FP64FP16Denormals, FP_DENORM_FLUSH_IN, FP_DENORM_FLUSH_IN_FLUSH_OUT, FP_DENORM_FLUSH_NONE, FP_DENORM_FLUSH_OUT, llvm::DenormalMode::getPreserveSign(), llvm::DenormalMode::Input, llvm::DenormalMode::Output, and llvm::DenormalMode::PreserveSign.

fpDenormModeSPValue()

uint32_t llvm::SIModeRegisterDefaults::fpDenormModeSPValue ( ) const

inline

Get the encoding value for the FP_DENORM bits of the mode register for the FP32 denormal mode.

Definition at line 61 of file SIModeRegisterDefaults.h.

References FP32Denormals, FP_DENORM_FLUSH_IN, FP_DENORM_FLUSH_IN_FLUSH_OUT, FP_DENORM_FLUSH_NONE, FP_DENORM_FLUSH_OUT, llvm::DenormalMode::getPreserveSign(), llvm::DenormalMode::Input, llvm::DenormalMode::Output, and llvm::DenormalMode::PreserveSign.

getDefaultForCallingConv()

static SIModeRegisterDefaults llvm::SIModeRegisterDefaults::getDefaultForCallingConv ( CallingConv::ID  CC )

inlinestatic

Definition at line 47 of file SIModeRegisterDefaults.h.

References CC, llvm::AMDGPU::isShader(), and Mode.

Referenced by SIModeRegisterDefaults().

isInlineCompatible()

bool llvm::SIModeRegisterDefaults::isInlineCompatible ( SIModeRegisterDefaults  CalleeMode ) const

inline

Definition at line 85 of file SIModeRegisterDefaults.h.

References DX10Clamp, and IEEE.

Referenced by llvm::GCNTTIImpl::areInlineCompatible().

operator==()

bool llvm::SIModeRegisterDefaults::operator== ( const SIModeRegisterDefaults  Other ) const

inline

Definition at line 53 of file SIModeRegisterDefaults.h.

References DX10Clamp, FP32Denormals, FP64FP16Denormals, IEEE, and llvm::Other.

Member Data Documentation

DX10Clamp

bool llvm::SIModeRegisterDefaults::DX10Clamp

Used by the vector ALU to force DX10-style treatment of NaNs: when set, clamp NaN to zero; otherwise, pass NaN through.

Definition at line 29 of file SIModeRegisterDefaults.h.

Referenced by isInlineCompatible(), operator==(), llvm::GCNTargetMachine::parseMachineFunctionInfo(), and SIModeRegisterDefaults().

FP32Denormals

DenormalMode llvm::SIModeRegisterDefaults::FP32Denormals

If this is set, neither input or output denormals are flushed for most f32 instructions.

Definition at line 33 of file SIModeRegisterDefaults.h.

Referenced by fpDenormModeSPValue(), llvm::AMDGPULegalizerInfo::legalizeFMad(), llvm::AMDGPUTargetLowering::LowerDIVREM24(), llvm::AMDGPUTargetLowering::LowerUDIVREM64(), operator==(), llvm::GCNTargetMachine::parseMachineFunctionInfo(), and SIModeRegisterDefaults().

FP64FP16Denormals

DenormalMode llvm::SIModeRegisterDefaults::FP64FP16Denormals

If this is set, neither input or output denormals are flushed for both f64 and f16/v2f16 instructions.

Definition at line 37 of file SIModeRegisterDefaults.h.

Referenced by fpDenormModeDPValue(), llvm::AMDGPULegalizerInfo::legalizeFMad(), operator==(), llvm::GCNTargetMachine::parseMachineFunctionInfo(), and SIModeRegisterDefaults().

IEEE

bool llvm::SIModeRegisterDefaults::IEEE

Floating point opcodes that support exception flag gathering quiet and propagate signaling NaN inputs per IEEE 754-2008.

Min_dx10 and max_dx10 become IEEE 754- 2008 compliant due to signaling NaN propagation and quieting.

Definition at line 25 of file SIModeRegisterDefaults.h.

Referenced by isInlineCompatible(), llvm::AMDGPULegalizerInfo::legalizeFFloor(), llvm::AMDGPULegalizerInfo::legalizeMinNumMaxNum(), llvm::AMDGPULegalizerInfo::legalizeRsqClampIntrinsic(), operator==(), llvm::GCNTargetMachine::parseMachineFunctionInfo(), and SIModeRegisterDefaults().

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The documentation for this struct was generated from the following files:

• lib/Target/AMDGPU/SIModeRegisterDefaults.h
• lib/Target/AMDGPU/SIModeRegisterDefaults.cpp