LLVM 20.0.0git
Public Member Functions | Public Attributes | List of all members
llvm::yaml::SIMachineFunctionInfo Struct Referencefinal

#include "Target/AMDGPU/SIMachineFunctionInfo.h"

Inheritance diagram for llvm::yaml::SIMachineFunctionInfo:
Inheritance graph
[legend]

Public Member Functions

 SIMachineFunctionInfo ()=default
 
 SIMachineFunctionInfo (const llvm::SIMachineFunctionInfo &, const TargetRegisterInfo &TRI, const llvm::MachineFunction &MF)
 
void mappingImpl (yaml::IO &YamlIO) override
 
 ~SIMachineFunctionInfo ()=default
 
- Public Member Functions inherited from llvm::yaml::MachineFunctionInfo
virtual ~MachineFunctionInfo ()=default
 
virtual void mappingImpl (IO &YamlIO)
 

Public Attributes

uint64_t ExplicitKernArgSize = 0
 
Align MaxKernArgAlign
 
uint32_t LDSSize = 0
 
uint32_t GDSSize = 0
 
Align DynLDSAlign
 
bool IsEntryFunction = false
 
bool IsChainFunction = false
 
bool NoSignedZerosFPMath = false
 
bool MemoryBound = false
 
bool WaveLimiter = false
 
bool HasSpilledSGPRs = false
 
bool HasSpilledVGPRs = false
 
uint32_t HighBitsOf32BitAddress = 0
 
unsigned Occupancy = 0
 
SmallVector< StringValue, 2 > SpillPhysVGPRS
 
SmallVector< StringValueWWMReservedRegs
 
StringValue ScratchRSrcReg = "$private_rsrc_reg"
 
StringValue FrameOffsetReg = "$fp_reg"
 
StringValue StackPtrOffsetReg = "$sp_reg"
 
unsigned BytesInStackArgArea = 0
 
bool ReturnsVoid = true
 
std::optional< SIArgumentInfoArgInfo
 
unsigned PSInputAddr = 0
 
unsigned PSInputEnable = 0
 
unsigned MaxMemoryClusterDWords = DefaultMemoryClusterDWordsLimit
 
SIMode Mode
 
std::optional< FrameIndexScavengeFI
 
StringValue VGPRForAGPRCopy
 
StringValue SGPRForEXECCopy
 
StringValue LongBranchReservedReg
 
bool HasInitWholeWave = false
 

Detailed Description

Definition at line 260 of file SIMachineFunctionInfo.h.

Constructor & Destructor Documentation

◆ SIMachineFunctionInfo() [1/2]

llvm::yaml::SIMachineFunctionInfo::SIMachineFunctionInfo ( )
default

◆ SIMachineFunctionInfo() [2/2]

yaml::SIMachineFunctionInfo::SIMachineFunctionInfo ( const llvm::SIMachineFunctionInfo MFI,
const TargetRegisterInfo TRI,
const llvm::MachineFunction MF 
)

◆ ~SIMachineFunctionInfo()

llvm::yaml::SIMachineFunctionInfo::~SIMachineFunctionInfo ( )
default

Member Function Documentation

◆ mappingImpl()

void yaml::SIMachineFunctionInfo::mappingImpl ( yaml::IO &  YamlIO)
override

Definition at line 736 of file SIMachineFunctionInfo.cpp.

References YamlIO.

Member Data Documentation

◆ ArgInfo

std::optional<SIArgumentInfo> llvm::yaml::SIMachineFunctionInfo::ArgInfo

◆ BytesInStackArgArea

unsigned llvm::yaml::SIMachineFunctionInfo::BytesInStackArgArea = 0

◆ DynLDSAlign

Align llvm::yaml::SIMachineFunctionInfo::DynLDSAlign

◆ ExplicitKernArgSize

uint64_t llvm::yaml::SIMachineFunctionInfo::ExplicitKernArgSize = 0

◆ FrameOffsetReg

StringValue llvm::yaml::SIMachineFunctionInfo::FrameOffsetReg = "$fp_reg"

◆ GDSSize

uint32_t llvm::yaml::SIMachineFunctionInfo::GDSSize = 0

◆ HasInitWholeWave

bool llvm::yaml::SIMachineFunctionInfo::HasInitWholeWave = false

◆ HasSpilledSGPRs

bool llvm::yaml::SIMachineFunctionInfo::HasSpilledSGPRs = false

◆ HasSpilledVGPRs

bool llvm::yaml::SIMachineFunctionInfo::HasSpilledVGPRs = false

◆ HighBitsOf32BitAddress

uint32_t llvm::yaml::SIMachineFunctionInfo::HighBitsOf32BitAddress = 0

◆ IsChainFunction

bool llvm::yaml::SIMachineFunctionInfo::IsChainFunction = false

◆ IsEntryFunction

bool llvm::yaml::SIMachineFunctionInfo::IsEntryFunction = false

◆ LDSSize

uint32_t llvm::yaml::SIMachineFunctionInfo::LDSSize = 0

◆ LongBranchReservedReg

StringValue llvm::yaml::SIMachineFunctionInfo::LongBranchReservedReg

◆ MaxKernArgAlign

Align llvm::yaml::SIMachineFunctionInfo::MaxKernArgAlign

◆ MaxMemoryClusterDWords

unsigned llvm::yaml::SIMachineFunctionInfo::MaxMemoryClusterDWords = DefaultMemoryClusterDWordsLimit

◆ MemoryBound

bool llvm::yaml::SIMachineFunctionInfo::MemoryBound = false

◆ Mode

SIMode llvm::yaml::SIMachineFunctionInfo::Mode

◆ NoSignedZerosFPMath

bool llvm::yaml::SIMachineFunctionInfo::NoSignedZerosFPMath = false

◆ Occupancy

unsigned llvm::yaml::SIMachineFunctionInfo::Occupancy = 0

◆ PSInputAddr

unsigned llvm::yaml::SIMachineFunctionInfo::PSInputAddr = 0

◆ PSInputEnable

unsigned llvm::yaml::SIMachineFunctionInfo::PSInputEnable = 0

◆ ReturnsVoid

bool llvm::yaml::SIMachineFunctionInfo::ReturnsVoid = true

◆ ScavengeFI

std::optional<FrameIndex> llvm::yaml::SIMachineFunctionInfo::ScavengeFI

◆ ScratchRSrcReg

StringValue llvm::yaml::SIMachineFunctionInfo::ScratchRSrcReg = "$private_rsrc_reg"

◆ SGPRForEXECCopy

StringValue llvm::yaml::SIMachineFunctionInfo::SGPRForEXECCopy

◆ SpillPhysVGPRS

SmallVector<StringValue, 2> llvm::yaml::SIMachineFunctionInfo::SpillPhysVGPRS

◆ StackPtrOffsetReg

StringValue llvm::yaml::SIMachineFunctionInfo::StackPtrOffsetReg = "$sp_reg"

◆ VGPRForAGPRCopy

StringValue llvm::yaml::SIMachineFunctionInfo::VGPRForAGPRCopy

◆ WaveLimiter

bool llvm::yaml::SIMachineFunctionInfo::WaveLimiter = false

◆ WWMReservedRegs

SmallVector<StringValue> llvm::yaml::SIMachineFunctionInfo::WWMReservedRegs

The documentation for this struct was generated from the following files: