18#define DEBUG_TYPE "si-shrink-instructions"
21 "Number of 64-bit instruction reduced to 32-bit.");
23 "Number of literal constants folded into 32-bit instructions.");
43 bool foldImmediates(
MachineInstr &
MI,
bool TryToCommute =
true)
const;
47 bool isKImmOrKUImmOperand(
const MachineOperand &Src,
bool &IsUnsigned)
const;
48 bool isReverseInlineImm(
const MachineOperand &Src, int32_t &ReverseImm)
const;
79 "SI Shrink Instructions",
false,
false)
81char SIShrinkInstructions::
ID = 0;
84 return new SIShrinkInstructions();
91 bool TryToCommute)
const {
100 if (
Reg.isVirtual()) {
102 if (Def &&
Def->isMoveImmediate()) {
104 bool ConstantFolded =
false;
106 if (
TII->isOperandLegal(
MI, Src0Idx, &MovSrc)) {
107 if (MovSrc.
isImm()) {
109 ConstantFolded =
true;
110 }
else if (MovSrc.
isFI()) {
112 ConstantFolded =
true;
116 ConstantFolded =
true;
120 if (ConstantFolded) {
121 if (
MRI->use_nodbg_empty(Reg))
122 Def->eraseFromParent();
123 ++NumLiteralConstantsFolded;
131 if (TryToCommute &&
MI.isCommutable()) {
132 if (
TII->commuteInstruction(
MI)) {
133 if (foldImmediates(
MI,
false))
137 TII->commuteInstruction(
MI);
146bool SIShrinkInstructions::shouldShrinkTrue16(
MachineInstr &
MI)
const {
147 for (
unsigned I = 0, E =
MI.getNumExplicitOperands();
I != E; ++
I) {
151 assert(!
Reg.isVirtual() &&
"Prior checks should ensure we only shrink "
152 "True16 Instructions post-RA");
153 if (AMDGPU::VGPR_32RegClass.
contains(Reg) &&
154 !AMDGPU::VGPR_32_Lo128RegClass.
contains(Reg))
161bool SIShrinkInstructions::isKImmOperand(
const MachineOperand &Src)
const {
163 !
TII->isInlineConstant(*Src.getParent(), Src.getOperandNo());
166bool SIShrinkInstructions::isKUImmOperand(
const MachineOperand &Src)
const {
167 return isUInt<16>(Src.getImm()) &&
168 !
TII->isInlineConstant(*Src.getParent(), Src.getOperandNo());
171bool SIShrinkInstructions::isKImmOrKUImmOperand(
const MachineOperand &Src,
172 bool &IsUnsigned)
const {
175 return !
TII->isInlineConstant(Src);
178 if (isUInt<16>(Src.getImm())) {
180 return !
TII->isInlineConstant(Src);
188bool SIShrinkInstructions::isReverseInlineImm(
const MachineOperand &Src,
189 int32_t &ReverseImm)
const {
190 if (!isInt<32>(Src.getImm()) ||
TII->isInlineConstant(Src))
193 ReverseImm = reverseBits<int32_t>(
static_cast<int32_t
>(Src.getImm()));
194 return ReverseImm >= -16 && ReverseImm <= 64;
199void SIShrinkInstructions::copyExtraImplicitOps(
MachineInstr &NewMI,
202 for (
unsigned i =
MI.getDesc().getNumOperands() +
203 MI.getDesc().implicit_uses().size() +
204 MI.getDesc().implicit_defs().size(),
205 e =
MI.getNumOperands();
213void SIShrinkInstructions::shrinkScalarCompare(
MachineInstr &
MI)
const {
219 if (!
MI.getOperand(0).isReg())
220 TII->commuteInstruction(
MI,
false, 0, 1);
237 if (SOPKOpc == AMDGPU::S_CMPK_EQ_U32 || SOPKOpc == AMDGPU::S_CMPK_LG_U32) {
239 if (isKImmOrKUImmOperand(Src1, HasUImm)) {
241 SOPKOpc = (SOPKOpc == AMDGPU::S_CMPK_EQ_U32) ?
242 AMDGPU::S_CMPK_EQ_I32 : AMDGPU::S_CMPK_LG_I32;
246 MI.setDesc(
TII->get(SOPKOpc));
269 switch (
Info->MIMGEncoding) {
270 case AMDGPU::MIMGEncGfx10NSA:
271 NewEncoding = AMDGPU::MIMGEncGfx10Default;
273 case AMDGPU::MIMGEncGfx11NSA:
274 NewEncoding = AMDGPU::MIMGEncGfx11Default;
282 unsigned NewAddrDwords =
Info->VAddrDwords;
285 if (
Info->VAddrDwords == 2) {
286 RC = &AMDGPU::VReg_64RegClass;
287 }
else if (
Info->VAddrDwords == 3) {
288 RC = &AMDGPU::VReg_96RegClass;
289 }
else if (
Info->VAddrDwords == 4) {
290 RC = &AMDGPU::VReg_128RegClass;
291 }
else if (
Info->VAddrDwords == 5) {
292 RC = &AMDGPU::VReg_160RegClass;
293 }
else if (
Info->VAddrDwords == 6) {
294 RC = &AMDGPU::VReg_192RegClass;
295 }
else if (
Info->VAddrDwords == 7) {
296 RC = &AMDGPU::VReg_224RegClass;
297 }
else if (
Info->VAddrDwords == 8) {
298 RC = &AMDGPU::VReg_256RegClass;
299 }
else if (
Info->VAddrDwords == 9) {
300 RC = &AMDGPU::VReg_288RegClass;
301 }
else if (
Info->VAddrDwords == 10) {
302 RC = &AMDGPU::VReg_320RegClass;
303 }
else if (
Info->VAddrDwords == 11) {
304 RC = &AMDGPU::VReg_352RegClass;
305 }
else if (
Info->VAddrDwords == 12) {
306 RC = &AMDGPU::VReg_384RegClass;
308 RC = &AMDGPU::VReg_512RegClass;
312 unsigned VgprBase = 0;
313 unsigned NextVgpr = 0;
315 bool IsKill = NewAddrDwords ==
Info->VAddrDwords;
316 const unsigned NSAMaxSize =
ST->getNSAMaxSize();
317 const bool IsPartialNSA = NewAddrDwords > NSAMaxSize;
318 const unsigned EndVAddr = IsPartialNSA ? NSAMaxSize :
Info->VAddrOperands;
319 for (
unsigned Idx = 0;
Idx < EndVAddr; ++
Idx) {
321 unsigned Vgpr =
TRI->getHWRegIndex(
Op.getReg());
322 unsigned Dwords =
TRI->getRegSizeInBits(
Op.getReg(), *
MRI) / 32;
323 assert(Dwords > 0 &&
"Un-implemented for less than 32 bit regs");
327 NextVgpr = Vgpr + Dwords;
328 }
else if (Vgpr == NextVgpr) {
329 NextVgpr = Vgpr + Dwords;
340 if (VgprBase + NewAddrDwords > 256)
347 unsigned TFEVal = (TFEIdx == -1) ? 0 :
MI.getOperand(TFEIdx).getImm();
348 unsigned LWEVal = (LWEIdx == -1) ? 0 :
MI.getOperand(LWEIdx).getImm();
350 if (TFEVal || LWEVal) {
352 for (
unsigned i = LWEIdx + 1, e =
MI.getNumOperands(); i !=
e; ++i) {
353 if (
MI.getOperand(i).isReg() &&
MI.getOperand(i).isTied() &&
354 MI.getOperand(i).isImplicit()) {
358 "found more than one tied implicit operand when expecting only 1");
360 MI.untieRegOperand(ToUntie);
366 Info->VDataDwords, NewAddrDwords);
367 MI.setDesc(
TII->get(NewOpcode));
369 MI.getOperand(VAddr0Idx).setIsUndef(IsUndef);
370 MI.getOperand(VAddr0Idx).setIsKill(IsKill);
372 for (
unsigned i = 1; i < EndVAddr; ++i)
373 MI.removeOperand(VAddr0Idx + 1);
378 ToUntie - (EndVAddr - 1));
386 if (!
ST->hasVOP3Literal())
391 MachineFunctionProperties::Property::NoVRegs))
394 if (
TII->hasAnyModifiersSet(
MI))
397 const unsigned Opcode =
MI.getOpcode();
401 unsigned NewOpcode = AMDGPU::INSTRUCTION_LIST_END;
406 if (Src2.
isImm() && !
TII->isInlineConstant(Src2)) {
417 case AMDGPU::V_MAD_F32_e64:
418 NewOpcode = AMDGPU::V_MADAK_F32;
420 case AMDGPU::V_FMA_F32_e64:
421 NewOpcode = AMDGPU::V_FMAAK_F32;
423 case AMDGPU::V_MAD_F16_e64:
424 NewOpcode = AMDGPU::V_MADAK_F16;
426 case AMDGPU::V_FMA_F16_e64:
427 case AMDGPU::V_FMA_F16_gfx9_e64:
428 NewOpcode =
ST->hasTrue16BitInsts() ? AMDGPU::V_FMAAK_F16_t16
429 : AMDGPU::V_FMAAK_F16;
436 if (Src1.
isImm() && !
TII->isInlineConstant(Src1))
438 else if (Src0.
isImm() && !
TII->isInlineConstant(Src0))
446 case AMDGPU::V_MAD_F32_e64:
447 NewOpcode = AMDGPU::V_MADMK_F32;
449 case AMDGPU::V_FMA_F32_e64:
450 NewOpcode = AMDGPU::V_FMAMK_F32;
452 case AMDGPU::V_MAD_F16_e64:
453 NewOpcode = AMDGPU::V_MADMK_F16;
455 case AMDGPU::V_FMA_F16_e64:
456 case AMDGPU::V_FMA_F16_gfx9_e64:
457 NewOpcode =
ST->hasTrue16BitInsts() ? AMDGPU::V_FMAMK_F16_t16
458 : AMDGPU::V_FMAMK_F16;
463 if (NewOpcode == AMDGPU::INSTRUCTION_LIST_END)
472 MI.getOperand(0).getReg())
477 MI.eraseFromParent();
479 TII->removeModOperands(
MI);
480 MI.setDesc(
TII->get(NewOpcode));
489bool SIShrinkInstructions::shrinkScalarLogicOp(
MachineInstr &
MI)
const {
490 unsigned Opc =
MI.getOpcode();
497 if (!SrcImm->
isImm() ||
504 if (Opc == AMDGPU::S_AND_B32) {
507 Opc = AMDGPU::S_BITSET0_B32;
510 Opc = AMDGPU::S_ANDN2_B32;
512 }
else if (Opc == AMDGPU::S_OR_B32) {
515 Opc = AMDGPU::S_BITSET1_B32;
518 Opc = AMDGPU::S_ORN2_B32;
520 }
else if (Opc == AMDGPU::S_XOR_B32) {
523 Opc = AMDGPU::S_XNOR_B32;
537 const bool IsUndef = SrcReg->
isUndef();
538 const bool IsKill = SrcReg->
isKill();
539 MI.setDesc(
TII->get(Opc));
540 if (Opc == AMDGPU::S_BITSET0_B32 ||
541 Opc == AMDGPU::S_BITSET1_B32) {
544 MI.getOperand(2).ChangeToRegister(Dest->
getReg(),
false,
547 MI.tieOperands(0, 2);
559bool SIShrinkInstructions::instAccessReg(
569 }
else if (MO.
getReg() == Reg &&
Reg.isVirtual()) {
579bool SIShrinkInstructions::instReadsReg(
const MachineInstr *
MI,
unsigned Reg,
581 return instAccessReg(
MI->uses(), Reg,
SubReg);
584bool SIShrinkInstructions::instModifiesReg(
const MachineInstr *
MI,
unsigned Reg,
586 return instAccessReg(
MI->defs(), Reg,
SubReg);
590SIShrinkInstructions::getSubRegForIndex(
Register Reg,
unsigned Sub,
592 if (
TRI->getRegSizeInBits(Reg, *
MRI) != 32) {
593 if (
Reg.isPhysical()) {
594 Reg =
TRI->getSubReg(Reg,
TRI->getSubRegFromChannel(
I));
596 Sub =
TRI->getSubRegFromChannel(
I +
TRI->getChannelFromSubReg(Sub));
602void SIShrinkInstructions::dropInstructionKeepingImpDefs(
604 for (
unsigned i =
MI.getDesc().getNumOperands() +
605 MI.getDesc().implicit_uses().size() +
606 MI.getDesc().implicit_defs().size(),
607 e =
MI.getNumOperands();
613 TII->get(AMDGPU::IMPLICIT_DEF),
Op.getReg());
616 MI.eraseFromParent();
651 unsigned Size =
TII->getOpSize(MovT, 0) / 4;
656 const unsigned SearchLimit = 16;
658 bool KilledT =
false;
661 Iter != E && Count < SearchLimit && !KilledT; ++Iter, ++Count) {
666 if ((MovY->
getOpcode() != AMDGPU::V_MOV_B32_e32 &&
682 if (instReadsReg(&*
I,
X, Xsub) || instModifiesReg(&*
I,
Y, Ysub) ||
683 instModifiesReg(&*
I,
T, Tsub) ||
684 (MovX && instModifiesReg(&*
I,
X, Xsub))) {
688 if (!instReadsReg(&*
I,
Y, Ysub)) {
689 if (!MovX && instModifiesReg(&*
I,
X, Xsub)) {
696 (
I->getOpcode() != AMDGPU::V_MOV_B32_e32 &&
697 I->getOpcode() != AMDGPU::COPY) ||
698 I->getOperand(0).getReg() !=
X ||
699 I->getOperand(0).getSubReg() != Xsub) {
704 if (
Size > 1 && (
I->getNumImplicitOperands() > (
I->isCopy() ? 0U : 1U)))
713 LLVM_DEBUG(
dbgs() <<
"Matched v_swap_b32:\n" << MovT << *MovX << *MovY);
715 for (
unsigned I = 0;
I <
Size; ++
I) {
717 X1 = getSubRegForIndex(
X, Xsub,
I);
718 Y1 = getSubRegForIndex(
Y, Ysub,
I);
721 TII->get(AMDGPU::V_SWAP_B32))
733 dropInstructionKeepingImpDefs(*MovY);
736 if (
T.isVirtual() &&
MRI->use_nodbg_empty(
T)) {
737 dropInstructionKeepingImpDefs(MovT);
743 if (
Op.isKill() &&
TRI->regsOverlap(
X,
Op.getReg()))
755bool SIShrinkInstructions::tryReplaceDeadSDST(
MachineInstr &
MI)
const {
756 if (!
ST->hasGFX10_3Insts())
766 Op->setReg(
ST->isWave32() ? AMDGPU::SGPR_NULL : AMDGPU::SGPR_NULL64);
777 TII =
ST->getInstrInfo();
778 TRI = &
TII->getRegisterInfo();
780 unsigned VCCReg =
ST->isWave32() ? AMDGPU::VCC_LO : AMDGPU::VCC;
782 std::vector<unsigned> I1Defs;
793 if (
MI.getOpcode() == AMDGPU::V_MOV_B32_e32) {
803 if (Src.isImm() &&
MI.getOperand(0).getReg().isPhysical()) {
805 if (isReverseInlineImm(Src, ReverseImm)) {
806 MI.setDesc(
TII->get(AMDGPU::V_BFREV_B32_e32));
807 Src.setImm(ReverseImm);
813 if (
ST->hasSwap() && (
MI.getOpcode() == AMDGPU::V_MOV_B32_e32 ||
814 MI.getOpcode() == AMDGPU::COPY)) {
815 if (
auto *NextMI = matchSwap(
MI)) {
816 Next = NextMI->getIterator();
822 if (
MI.getOpcode() == AMDGPU::S_ADD_I32 ||
823 MI.getOpcode() == AMDGPU::S_MUL_I32) {
829 if (
TII->commuteInstruction(
MI,
false, 1, 2))
844 unsigned Opc = (
MI.getOpcode() == AMDGPU::S_ADD_I32) ?
845 AMDGPU::S_ADDK_I32 : AMDGPU::S_MULK_I32;
848 MI.setDesc(
TII->get(Opc));
849 MI.tieOperands(0, 1);
855 if (
MI.isCompare() &&
TII->isSOPC(
MI)) {
856 shrinkScalarCompare(
MI);
861 if (
MI.getOpcode() == AMDGPU::S_MOV_B32) {
865 if (Src.isImm() && Dst.getReg().isPhysical()) {
868 MI.setDesc(
TII->get(AMDGPU::S_MOVK_I32));
870 }
else if (isReverseInlineImm(Src, ReverseImm)) {
871 MI.setDesc(
TII->get(AMDGPU::S_BREV_B32));
872 Src.setImm(ReverseImm);
880 if (
MI.getOpcode() == AMDGPU::S_AND_B32 ||
881 MI.getOpcode() == AMDGPU::S_OR_B32 ||
882 MI.getOpcode() == AMDGPU::S_XOR_B32) {
883 if (shrinkScalarLogicOp(
MI))
887 if (
TII->isMIMG(
MI.getOpcode()) &&
890 MachineFunctionProperties::Property::NoVRegs)) {
895 if (!
TII->isVOP3(
MI))
898 if (
MI.getOpcode() == AMDGPU::V_MAD_F32_e64 ||
899 MI.getOpcode() == AMDGPU::V_FMA_F32_e64 ||
900 MI.getOpcode() == AMDGPU::V_MAD_F16_e64 ||
901 MI.getOpcode() == AMDGPU::V_FMA_F16_e64 ||
902 MI.getOpcode() == AMDGPU::V_FMA_F16_gfx9_e64) {
907 if (!
TII->hasVALU32BitEncoding(
MI.getOpcode())) {
910 tryReplaceDeadSDST(
MI);
917 if (!
MI.isCommutable() || !
TII->commuteInstruction(
MI) ||
919 tryReplaceDeadSDST(
MI);
926 if (
TII->isVOPC(Op32)) {
942 MRI->setRegAllocationHint(DstReg, 0, VCCReg);
945 if (DstReg != VCCReg)
950 if (Op32 == AMDGPU::V_CNDMASK_B32_e32) {
954 TII->getNamedOperand(
MI, AMDGPU::OpName::src2);
959 MRI->setRegAllocationHint(SReg, 0, VCCReg);
968 AMDGPU::OpName::sdst);
973 if (SDst->
getReg() != VCCReg) {
975 MRI->setRegAllocationHint(SDst->
getReg(), 0, VCCReg);
982 AMDGPU::OpName::src2);
983 if (Src2 && Src2->
getReg() != VCCReg) {
985 MRI->setRegAllocationHint(Src2->
getReg(), 0, VCCReg);
997 if (
ST->hasVOP3Literal() &&
999 MachineFunctionProperties::Property::NoVRegs))
1003 !shouldShrinkTrue16(
MI))
1010 ++NumInstructionsShrunk;
1013 copyExtraImplicitOps(*Inst32,
MI);
1016 if (SDst && SDst->
isDead())
1019 MI.eraseFromParent();
1020 foldImmediates(*Inst32);
unsigned const MachineRegisterInfo * MRI
Provides AMDGPU specific target descriptions.
Analysis containing CSE Info
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
AMD GCN specific subclass of TargetSubtarget.
const HexagonInstrInfo * TII
unsigned const TargetRegisterInfo * TRI
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
#define DEBUG_TYPE
The pass tries to use the 32-bit encoding for instructions when possible.
This file defines the 'Statistic' class, which is designed to be an easy way to expose various metric...
#define STATISTIC(VARNAME, DESC)
static bool contains(SmallPtrSetImpl< ConstantExpr * > &Cache, ConstantExpr *Expr, Constant *C)
Represent the analysis usage information of a pass.
void setPreservesCFG()
This function should be called by the pass, iff they do not:
This class represents an Operation in the Expression.
FunctionPass class - This class is used to implement most global optimizations.
Describe properties that are true of each instruction in the target description file.
instr_iterator instr_end()
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
virtual bool runOnMachineFunction(MachineFunction &MF)=0
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
bool hasProperty(Property P) const
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Function & getFunction()
Return the LLVM function that this machine code represents.
const MachineFunctionProperties & getProperties() const
Get the function properties.
const MachineInstrBuilder & add(const MachineOperand &MO) const
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
const MachineInstrBuilder & setMIFlags(unsigned Flags) const
MachineInstr * getInstr() const
If conversion operators fail, use this method to get the MachineInstr explicitly.
const MachineInstrBuilder & addDef(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register definition operand.
Representation of each machine instruction.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
unsigned getNumImplicitOperands() const
Returns the implicit operands number.
const MachineBasicBlock * getParent() const
void addOperand(MachineFunction &MF, const MachineOperand &Op)
Add the specified operand to the instruction.
unsigned getNumExplicitOperands() const
Returns the number of non-implicit operands.
bool killsRegister(Register Reg, const TargetRegisterInfo *TRI) const
Return true if the MachineInstr kills the specified register.
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
void removeOperand(unsigned OpNo)
Erase an operand from an instruction, leaving it with one fewer operand than it started with.
const MachineOperand & getOperand(unsigned i) const
bool hasRegisterImplicitUseOperand(Register Reg) const
Returns true if the MachineInstr has an implicit-use operand of exactly the given register (not consi...
MachineOperand * findRegisterDefOperand(Register Reg, const TargetRegisterInfo *TRI, bool isDead=false, bool Overlap=false)
Wrapper for findRegisterDefOperandIdx, it returns a pointer to the MachineOperand rather than an inde...
MachineOperand class - Representation of each machine instruction operand.
unsigned getSubReg() const
const GlobalValue * getGlobal() const
void ChangeToFrameIndex(int Idx, unsigned TargetFlags=0)
Replace this operand with a frame index.
void setImm(int64_t immVal)
bool isReg() const
isReg - Tests if this is a MO_Register operand.
bool isRegMask() const
isRegMask - Tests if this is a MO_RegisterMask operand.
void setIsDead(bool Val=true)
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
void ChangeToImmediate(int64_t ImmVal, unsigned TargetFlags=0)
ChangeToImmediate - Replace this operand with a new immediate operand of the specified value.
void ChangeToGA(const GlobalValue *GV, int64_t Offset, unsigned TargetFlags=0)
ChangeToGA - Replace this operand with a new global address operand.
void setIsKill(bool Val=true)
unsigned getTargetFlags() const
bool isGlobal() const
isGlobal - Tests if this is a MO_GlobalAddress operand.
Register getReg() const
getReg - Returns the register number.
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
int64_t getOffset() const
Return the offset from the symbol in this operand.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
virtual StringRef getPassName() const
getPassName - Return a nice clean name for a pass.
Wrapper class representing virtual and physical registers.
constexpr bool isVirtual() const
Return true if the specified register number is in the virtual register namespace.
constexpr bool isPhysical() const
Return true if the specified register number is in the physical register namespace.
static bool sopkIsZext(unsigned Opcode)
StringRef - Represent a constant reference to a string, i.e.
MCRegister getRegister(unsigned i) const
Return the specified register in the class.
self_iterator getIterator()
A range adaptor for a pair of iterators.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
LLVM_READONLY int getSOPKOp(uint16_t Opcode)
LLVM_READONLY const MIMGInfo * getMIMGInfo(unsigned Opc)
int getMIMGOpcode(unsigned BaseOpcode, unsigned MIMGEncoding, unsigned VDataDwords, unsigned VAddrDwords)
LLVM_READONLY int getVOPe32(uint16_t Opcode)
LLVM_READONLY int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx)
bool isKImmOperand(const MCInstrDesc &Desc, unsigned OpNo)
Is this a KImm operand?
bool isTrue16Inst(unsigned Opc)
bool isInlinableLiteral32(int32_t Literal, bool HasInv2Pi)
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Reg
All possible values of the reg field in the ModR/M byte.
NodeAddr< DefNode * > Def
This is an optimization pass for GlobalISel generic memory operations.
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
int countr_one(T Value)
Count the number of ones from the least significant bit to the first zero bit.
int countr_zero(T Val)
Count number of 0's from the least significant bit to the most stopping at the first 1.
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
FunctionPass * createSIShrinkInstructionsPass()
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
constexpr int32_t SignExtend32(uint32_t X)
Sign-extend the number in the bottom B bits of X to a 32-bit integer.
constexpr int64_t SignExtend64(uint64_t x)
Sign-extend the number in the bottom B bits of X to a 64-bit integer.
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
constexpr bool any() const
A pair composed of a register and a sub-register index.