#include "Target/AMDGPU/SIInstrInfo.h"
Public Types | |
| enum | TargetOperandFlags { MO_MASK = 0xf , MO_NONE = 0 , MO_GOTPCREL = 1 , MO_GOTPCREL32 = 2 , MO_GOTPCREL32_LO = 2 , MO_GOTPCREL32_HI = 3 , MO_REL32 = 4 , MO_REL32_LO = 4 , MO_REL32_HI = 5 , MO_FAR_BRANCH_OFFSET = 6 , MO_ABS32_LO = 8 , MO_ABS32_HI = 9 } |
Protected Member Functions | |
| std::optional< DestSourcePair > | isCopyInstrImpl (const MachineInstr &MI) const override |
| If the specific machine instruction is a instruction that moves/copies value from one register to another register return destination and source registers as machine operands. | |
| bool | swapSourceModifiers (MachineInstr &MI, MachineOperand &Src0, unsigned Src0OpName, MachineOperand &Src1, unsigned Src1OpName) const |
| MachineInstr * | commuteInstructionImpl (MachineInstr &MI, bool NewMI, unsigned OpIdx0, unsigned OpIdx1) const override |
Detailed Description
Definition at line 85 of file SIInstrInfo.h.
Member Enumeration Documentation
◆ TargetOperandFlags
| Enumerator | |
|---|---|
| MO_MASK | |
| MO_NONE | |
| MO_GOTPCREL | |
| MO_GOTPCREL32 | |
| MO_GOTPCREL32_LO | |
| MO_GOTPCREL32_HI | |
| MO_REL32 | |
| MO_REL32_LO | |
| MO_REL32_HI | |
| MO_FAR_BRANCH_OFFSET | |
| MO_ABS32_LO | |
| MO_ABS32_HI | |
Definition at line 202 of file SIInstrInfo.h.
Constructor & Destructor Documentation
◆ SIInstrInfo()
|
explicit |
Definition at line 63 of file SIInstrInfo.cpp.
References llvm::TargetSchedModel::init().
Member Function Documentation
◆ allowNegativeFlatOffset()
Returns true if negative offsets are allowed for the given FlatVariant.
Definition at line 9250 of file SIInstrInfo.cpp.
References llvm::SIInstrFlags::FLAT, llvm::SIInstrFlags::FlatScratch, llvm::GCNSubtarget::hasNegativeScratchOffsetBug(), and llvm::AMDGPU::isGFX12Plus().
Referenced by isLegalFLATOffset(), and splitFlatOffset().
◆ analyzeBranch()
|
override |
Definition at line 3068 of file SIInstrInfo.cpp.
References analyzeBranchImpl(), Cond, llvm::MachineBasicBlock::end(), llvm::MachineBasicBlock::getFirstTerminator(), I, llvm_unreachable, MBB, and TBB.
◆ analyzeBranchImpl()
| bool SIInstrInfo::analyzeBranchImpl | ( | MachineBasicBlock & | MBB, |
| MachineBasicBlock::iterator | I, | ||
| MachineBasicBlock *& | TBB, | ||
| MachineBasicBlock *& | FBB, | ||
| SmallVectorImpl< MachineOperand > & | Cond, | ||
| bool | AllowModify | ||
| ) | const |
Definition at line 3031 of file SIInstrInfo.cpp.
References Cond, llvm::MachineOperand::CreateImm(), llvm::MachineBasicBlock::end(), I, MBB, and TBB.
Referenced by analyzeBranch().
◆ analyzeCompare()
|
override |
Definition at line 9811 of file SIInstrInfo.cpp.
References MI.
◆ areLoadsFromSameBasePtr()
|
override |
Definition at line 230 of file SIInstrInfo.cpp.
References assert(), llvm::get(), llvm::SDNode::getAsZExtVal(), llvm::SDNode::getConstantOperandVal(), llvm::SDNode::getMachineOpcode(), llvm::AMDGPU::getNamedOperandIdx(), getNumOperandsNoGlue(), llvm::SDNode::getOperand(), llvm::ConstantSDNode::getZExtValue(), llvm::AMDGPU::hasNamedOperand(), isDS(), llvm::SDNode::isMachineOpcode(), isMTBUF(), isMUBUF(), isSMRD(), and nodesHaveSameOperandValue().
◆ areMemAccessesTriviallyDisjoint()
|
override |
Definition at line 3709 of file SIInstrInfo.cpp.
References assert(), llvm::MachineInstr::hasOrderedMemoryRef(), llvm::MachineInstr::hasUnmodeledSideEffects(), isDS(), isFLAT(), isFLATGlobal(), isFLATScratch(), isLDSDMA(), isMTBUF(), isMUBUF(), isSegmentSpecificFLAT(), isSMRD(), and llvm::MachineInstr::mayLoadOrStore().
◆ buildExtractSubReg()
| unsigned SIInstrInfo::buildExtractSubReg | ( | MachineBasicBlock::iterator | MI, |
| MachineRegisterInfo & | MRI, | ||
| const MachineOperand & | SuperReg, | ||
| const TargetRegisterClass * | SuperRC, | ||
| unsigned | SubIdx, | ||
| const TargetRegisterClass * | SubRC | ||
| ) | const |
Definition at line 5750 of file SIInstrInfo.cpp.
References llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), DL, llvm::get(), llvm::MachineOperand::getReg(), llvm::MachineOperand::getSubReg(), llvm::Register::isVirtual(), MBB, MI, MRI, and SubReg.
Referenced by buildExtractSubRegOrImm().
◆ buildExtractSubRegOrImm()
| MachineOperand SIInstrInfo::buildExtractSubRegOrImm | ( | MachineBasicBlock::iterator | MI, |
| MachineRegisterInfo & | MRI, | ||
| const MachineOperand & | SuperReg, | ||
| const TargetRegisterClass * | SuperRC, | ||
| unsigned | SubIdx, | ||
| const TargetRegisterClass * | SubRC | ||
| ) | const |
Definition at line 5767 of file SIInstrInfo.cpp.
References buildExtractSubReg(), llvm::MachineOperand::CreateImm(), llvm::MachineOperand::CreateReg(), llvm_unreachable, MRI, and SubReg.
◆ buildShrunkInst()
| MachineInstr * SIInstrInfo::buildShrunkInst | ( | MachineInstr & | MI, |
| unsigned | NewOpcode | ||
| ) | const |
Definition at line 4524 of file SIInstrInfo.cpp.
References llvm::MachineInstrBuilder::add(), llvm::BuildMI(), copyFlagsToImplicitVCC(), fixImplicitOperands(), llvm::get(), getNamedOperand(), llvm::AMDGPU::getNamedOperandIdx(), llvm::MCInstrDesc::getNumDefs(), I, Idx, MBB, MI, llvm::MCOI::OPERAND_IMMEDIATE, llvm::AMDGPU::OPERAND_INPUT_MODS, and llvm::MachineInstrBuilder::setMIFlags().
◆ canInsertSelect()
|
override |
Definition at line 3205 of file SIInstrInfo.cpp.
References Cond, llvm::MachineBasicBlock::getParent(), llvm::AMDGPU::getRegBitWidth(), llvm::MachineFunction::getRegInfo(), llvm::SIRegisterInfo::hasVGPRs(), llvm::SIRegisterInfo::isSGPRClass(), MBB, and MRI.
◆ canShrink()
| bool SIInstrInfo::canShrink | ( | const MachineInstr & | MI, |
| const MachineRegisterInfo & | MRI | ||
| ) | const |
Definition at line 4449 of file SIInstrInfo.cpp.
References getNamedOperand(), llvm::MachineOperand::getReg(), hasModifiersSet(), hasVALU32BitEncoding(), llvm::MachineOperand::isReg(), llvm::SIRegisterInfo::isVGPR(), MI, and MRI.
◆ commuteInstructionImpl()
|
overrideprotected |
Definition at line 2752 of file SIInstrInfo.cpp.
References assert(), llvm::TargetInstrInfo::commuteInstructionImpl(), commuteOpcode(), llvm::get(), llvm::AMDGPU::getNamedOperandIdx(), isOperandLegal(), llvm::MachineOperand::isReg(), MI, llvm::MachineInstr::setDesc(), std::swap(), swapRegAndNonRegOperand(), and swapSourceModifiers().
◆ commuteOpcode() [1/2]
|
inline |
Definition at line 326 of file SIInstrInfo.h.
References commuteOpcode(), and MI.
◆ commuteOpcode() [2/2]
| int SIInstrInfo::commuteOpcode | ( | unsigned | Opc | ) | const |
Definition at line 1155 of file SIInstrInfo.cpp.
References llvm::AMDGPU::getCommuteOrig(), llvm::AMDGPU::getCommuteRev(), and pseudoToMCOpcode().
Referenced by commuteInstructionImpl(), commuteOpcode(), and legalizeOperandsVOP2().
◆ convertToThreeAddress()
|
override |
Definition at line 3838 of file SIInstrInfo.cpp.
References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstr::addOperand(), llvm::LiveVariables::VarInfo::AliveBlocks, assert(), llvm::BuildMI(), llvm::SparseBitVector< ElementSize >::clear(), DefMI, llvm::LiveRange::find(), llvm::get(), llvm::GCNSubtarget::getConstantBusLimit(), getFoldableImm(), llvm::MachineOperand::getImm(), llvm::LiveIntervals::getInstructionIndex(), llvm::LiveIntervals::getInterval(), llvm::AMDGPU::getMFMAEarlyClobberOp(), getNamedOperand(), llvm::AMDGPU::getNamedOperandIdx(), getNewFMAInst(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), llvm::SlotIndex::getRegSlot(), llvm::LiveVariables::getVarInfo(), llvm::LiveIntervals::hasInterval(), llvm::AMDGPU::hasNamedOperand(), llvm::AMDGPUSubtarget::hasTrue16BitInsts(), llvm::GCNSubtarget::hasVOP3Literal(), I, llvm::MachineOperand::isImm(), isInlineConstant(), isOperandLegal(), llvm::MachineOperand::isReg(), llvm::SIRegisterInfo::isSGPRReg(), isWMMA(), llvm::AMDGPU::mapWMMA2AddrTo3AddrOpcode(), MBB, MI, MRI, pseudoToMCOpcode(), llvm::MachineInstr::removeOperand(), llvm::LiveIntervals::ReplaceMachineInstrInMaps(), llvm::MachineInstr::setDesc(), llvm::MachineOperand::setIsDead(), llvm::MachineInstrBuilder::setMIFlags(), llvm::LiveIntervals::shrinkToUses(), and updateLiveVariables().
◆ copyPhysReg()
|
override |
Definition at line 801 of file SIInstrInfo.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), contains(), copyPhysReg(), llvm::RegState::Define, DL, expandSGPRCopy(), Fix16BitCopies, llvm::get(), llvm::SIRegisterInfo::get32BitRegister(), llvm::SIRegisterInfo::getHWRegIndex(), llvm::getKillRegState(), llvm::SIRegisterInfo::getRegSplitParts(), llvm::SIRegisterInfo::getVGPR64Class(), llvm::GCNSubtarget::hasGFX90AInsts(), llvm::GCNSubtarget::hasMovB64(), llvm::GCNSubtarget::hasPkMovB32(), llvm::GCNSubtarget::hasScalarCompareEq64(), llvm::GCNSubtarget::hasSDWAScalar(), llvm::AMDGPUSubtarget::hasTrue16BitInsts(), llvm::SIRegisterInfo::hasVGPRs(), Idx, llvm::RegState::Implicit, indirectCopyToAGPR(), llvm::SIRegisterInfo::isAGPRClass(), llvm::AMDGPU::isHi16Reg(), llvm::SIRegisterInfo::isProperlyAlignedRC(), llvm::SIRegisterInfo::isSGPRClass(), MBB, MI, llvm::SISrcMods::OP_SEL_0, llvm::SISrcMods::OP_SEL_1, reportIllegalCopy(), llvm::ArrayRef< T >::size(), Size, SubReg, llvm::MachineInstr::tieOperands(), llvm::RegState::Undef, llvm::AMDGPU::SDWA::UNUSED_PRESERVE, llvm::AMDGPU::SDWA::WORD_0, and llvm::AMDGPU::SDWA::WORD_1.
Referenced by copyPhysReg().
◆ createPHIDestinationCopy()
|
override |
Definition at line 9563 of file SIInstrInfo.cpp.
References llvm::MachineInstrBuilder::addReg(), llvm::MachineBasicBlock::begin(), llvm::BuildMI(), llvm::TargetInstrInfo::createPHIDestinationCopy(), DL, llvm::MachineBasicBlock::end(), llvm::get(), and MBB.
◆ createPHISourceCopy()
|
override |
Definition at line 9578 of file SIInstrInfo.cpp.
References llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::TargetInstrInfo::createPHISourceCopy(), DL, llvm::MachineBasicBlock::end(), llvm::get(), llvm::RegState::Implicit, llvm::GCNSubtarget::isWave32(), and MBB.
◆ CreateTargetMIHazardRecognizer()
|
override |
Definition at line 8938 of file SIInstrInfo.cpp.
References llvm::TargetInstrInfo::CreateTargetMIHazardRecognizer(), llvm::ScheduleDAGMI::hasVRegLiveness(), II, and llvm::ScheduleDAG::MF.
◆ CreateTargetPostRAHazardRecognizer() [1/2]
|
override |
This is used by the post-RA scheduler (SchedulePostRAList.cpp).
The post-RA version of misched uses CreateTargetMIHazardRecognizer.
Definition at line 8923 of file SIInstrInfo.cpp.
References llvm::ScheduleDAG::MF.
◆ CreateTargetPostRAHazardRecognizer() [2/2]
|
override |
This is the hazard recognizer used at -O0 by the PostRAHazardRecognizer pass.
Definition at line 8931 of file SIInstrInfo.cpp.
◆ decomposeMachineOperandsTargetFlags()
|
override |
Definition at line 8950 of file SIInstrInfo.cpp.
References MO_MASK.
◆ doesNotReadTiedSource() [1/2]
|
inlinestatic |
Definition at line 965 of file SIInstrInfo.h.
References MI, and llvm::SIInstrFlags::TiedSourceNotRead.
◆ doesNotReadTiedSource() [2/2]
Definition at line 969 of file SIInstrInfo.h.
References llvm::get(), and llvm::SIInstrFlags::TiedSourceNotRead.
◆ enforceOperandRCAlignment()
| void SIInstrInfo::enforceOperandRCAlignment | ( | MachineInstr & | MI, |
| unsigned | OpName | ||
| ) | const |
Definition at line 10021 of file SIInstrInfo.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::MachineOperand::CreateReg(), DL, llvm::get(), llvm::AMDGPU::getNamedOperandIdx(), getOpSize(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), llvm::SIRegisterInfo::isAGPR(), MI, MRI, and llvm::GCNSubtarget::needsAlignedVGPRs().
◆ expandMovDPP64()
| std::pair< MachineInstr *, MachineInstr * > SIInstrInfo::expandMovDPP64 | ( | MachineInstr & | MI | ) | const |
Definition at line 2631 of file SIInstrInfo.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), DL, llvm::drop_begin(), llvm::MachineBasicBlock::findDebugLoc(), llvm::get(), llvm::SrcOp::getImm(), getNamedOperand(), llvm::MachineBasicBlock::getParent(), llvm::SrcOp::getReg(), getReg(), llvm::MachineFunction::getRegInfo(), llvm::GCNSubtarget::hasMovB64(), I, llvm::AMDGPU::isLegalDPALU_DPPControl(), MBB, MI, MRI, and llvm::RegState::Undef.
Referenced by expandPostRAPseudo().
◆ expandPostRAPseudo()
|
override |
Definition at line 2107 of file SIInstrInfo.cpp.
References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addDef(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::MIBundleBuilder::append(), assert(), llvm::MIBundleBuilder::begin(), llvm::BuildMI(), llvm::MachineInstrBuilder::copyImplicitOps(), llvm::RegState::Define, DL, llvm::AMDGPU::VGPRIndexMode::DST_ENABLE, expandMovDPP64(), llvm::TargetInstrInfo::expandPostRAPseudo(), llvm::finalizeBundle(), llvm::MachineBasicBlock::findDebugLoc(), llvm::get(), llvm::SrcOp::getImm(), llvm::ilist_node_impl< OptionsT >::getIterator(), llvm::MCInstrDesc::getNumOperands(), llvm::MachineOperand::getOffset(), llvm::MachineInstr::getOperand(), getOpRegClass(), llvm::MachineBasicBlock::getParent(), llvm::SrcOp::getReg(), llvm::MachineFunction::getRegInfo(), llvm::MachineFunction::getSubtarget(), llvm::GCNSubtarget::hasGetPCZeroExtension(), llvm::GCNSubtarget::hasMovB64(), llvm::GCNSubtarget::hasPkMovB32(), llvm::SIRegisterInfo::hasVGPRs(), llvm::Hi, Idx, llvm::RegState::Implicit, llvm::MCInstrDesc::implicit_uses(), llvm::RegState::ImplicitDefine, llvm::SIRegisterInfo::isAGPR(), llvm::MachineOperand::isGlobal(), isInlineConstant(), llvm::GCNSubtarget::isWave32(), llvm::Lo, MBB, MI, llvm::SISrcMods::OP_SEL_0, llvm::SISrcMods::OP_SEL_1, llvm::MachineOperand::setIsUndef(), llvm::MachineOperand::setOffset(), llvm::AMDGPU::VGPRIndexMode::SRC0_ENABLE, SubReg, llvm::MachineInstr::tieOperands(), TRI, llvm::RegState::Undef, and llvm::GCNSubtarget::useVGPRIndexMode().
◆ findCommutedOpIndices() [1/2]
|
override |
Definition at line 2809 of file SIInstrInfo.cpp.
References findCommutedOpIndices(), and MI.
Referenced by findCommutedOpIndices().
◆ findCommutedOpIndices() [2/2]
| bool SIInstrInfo::findCommutedOpIndices | ( | const MCInstrDesc & | Desc, |
| unsigned & | SrcOpIdx0, | ||
| unsigned & | SrcOpIdx1 | ||
| ) | const |
Definition at line 2815 of file SIInstrInfo.cpp.
References llvm::AMDGPU::getNamedOperandIdx().
◆ fixImplicitOperands()
| void SIInstrInfo::fixImplicitOperands | ( | MachineInstr & | MI | ) | const |
Definition at line 9086 of file SIInstrInfo.cpp.
References llvm::GCNSubtarget::isWave32(), and MI.
Referenced by buildShrunkInst(), insertBranch(), insertSelect(), legalizeOperandsVOP2(), llvm::GCNSubtarget::mirFileLoaded(), and moveToVALUImpl().
◆ foldImmediate()
|
final |
Definition at line 3391 of file SIInstrInfo.cpp.
References assert(), llvm::MachineOperand::ChangeToImmediate(), llvm::TargetRegisterClass::contains(), DefMI, llvm::get(), llvm::SIRegisterInfo::get32BitRegister(), llvm::GCNSubtarget::getConstantBusLimit(), llvm::MachineOperand::getImm(), getNamedOperand(), llvm::AMDGPU::getNamedOperandIdx(), getOpSize(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::MachineInstrBuilder::getReg(), llvm::SIRegisterInfo::getRegClass(), llvm::MachineOperand::getSubReg(), hasAnyModifiersSet(), llvm::AMDGPUSubtarget::hasTrue16BitInsts(), llvm::Hi_32(), llvm::SIRegisterInfo::isAGPR(), llvm::MachineOperand::isImm(), isInlineConstant(), llvm::MachineOperand::isKill(), llvm::Register::isPhysical(), llvm::MachineOperand::isReg(), llvm::SIRegisterInfo::isSGPRClass(), llvm::SIRegisterInfo::isSGPRReg(), llvm::SIRegisterInfo::isVGPR(), isVGPRCopy(), llvm::Register::isVirtual(), legalizeOperands(), llvm::Lo_32(), MRI, llvm::MCInstrDesc::operands(), pseudoToMCOpcode(), removeModOperands(), llvm::MachineOperand::setIsKill(), llvm::MachineOperand::setReg(), llvm::MachineOperand::setSubReg(), and UseMI.
Referenced by legalizeGenericOperand().
◆ foldMemoryOperandImpl()
|
override |
Definition at line 9600 of file SIInstrInfo.cpp.
References llvm::MachineFunction::getRegInfo(), llvm::TargetRegisterClass::hasSuperClassEq(), llvm::Register::isVirtual(), MI, and MRI.
◆ getAddNoCarry() [1/2]
| MachineInstrBuilder SIInstrInfo::getAddNoCarry | ( | MachineBasicBlock & | MBB, |
| MachineBasicBlock::iterator | I, | ||
| const DebugLoc & | DL, | ||
| Register | DestReg | ||
| ) | const |
Return a partially built integer add instruction without carry.
Caller must add source operands. For pre-GFX9 it will generate unused carry destination operand. TODO: After GFX9 it should return a no-carry operation.
Definition at line 9016 of file SIInstrInfo.cpp.
References llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::RegState::Dead, llvm::RegState::Define, DL, llvm::get(), llvm::SIRegisterInfo::getBoolRC(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), llvm::SIRegisterInfo::getVCC(), llvm::GCNSubtarget::hasAddNoCarry(), I, MBB, and MRI.
◆ getAddNoCarry() [2/2]
| MachineInstrBuilder SIInstrInfo::getAddNoCarry | ( | MachineBasicBlock & | MBB, |
| MachineBasicBlock::iterator | I, | ||
| const DebugLoc & | DL, | ||
| Register | DestReg, | ||
| RegScavenger & | RS | ||
| ) | const |
Definition at line 9031 of file SIInstrInfo.cpp.
References llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::RegState::Dead, llvm::RegState::Define, DL, llvm::get(), llvm::SIRegisterInfo::getBoolRC(), llvm::SIRegisterInfo::getVCC(), llvm::GCNSubtarget::hasAddNoCarry(), I, llvm::RegScavenger::isRegUsed(), llvm::Register::isValid(), MBB, and llvm::RegScavenger::scavengeRegisterBackwards().
◆ getBranchDestBlock()
|
override |
Definition at line 2850 of file SIInstrInfo.cpp.
References MI.
◆ getClampMask()
|
inline |
Definition at line 908 of file SIInstrInfo.h.
References llvm::SIInstrFlags::ClampHi, llvm::SIInstrFlags::ClampLo, llvm::SIInstrFlags::FPClamp, llvm::SIInstrFlags::IntClamp, and MI.
◆ getDefaultRsrcDataFormat()
| uint64_t SIInstrInfo::getDefaultRsrcDataFormat | ( | ) | const |
Definition at line 8713 of file SIInstrInfo.cpp.
References llvm::Format, llvm::GCNSubtarget::getGeneration(), llvm::AMDGPUSubtarget::GFX10, llvm::AMDGPUSubtarget::GFX11, llvm::AMDGPUSubtarget::isAmdHsaOS(), llvm::AMDGPU::RSRC_DATA_FORMAT, llvm::AMDGPU::UfmtGFX10::UFMT_32_FLOAT, llvm::AMDGPU::UfmtGFX11::UFMT_32_FLOAT, and llvm::AMDGPUSubtarget::VOLCANIC_ISLANDS.
Referenced by getScratchRsrcWords23().
◆ getDSShaderTypeValue()
|
static |
Definition at line 9789 of file SIInstrInfo.cpp.
References llvm::CallingConv::AMDGPU_CS, llvm::CallingConv::AMDGPU_ES, llvm::CallingConv::AMDGPU_GS, llvm::CallingConv::AMDGPU_HS, llvm::CallingConv::AMDGPU_KERNEL, llvm::CallingConv::AMDGPU_LS, llvm::CallingConv::AMDGPU_PS, llvm::CallingConv::AMDGPU_VS, llvm::CallingConv::C, llvm::CallingConv::Fast, llvm::Function::getCallingConv(), llvm::MachineFunction::getFunction(), and llvm::report_fatal_error().
◆ getGenericInstructionUniformity()
| InstructionUniformity SIInstrInfo::getGenericInstructionUniformity | ( | const MachineInstr & | MI | ) | const |
Definition at line 9656 of file SIInstrInfo.cpp.
References llvm::AlwaysUniform, llvm::any_of(), llvm::Default, llvm::AMDGPU::isGenericAtomic(), llvm::AMDGPU::isIntrinsicAlwaysUniform(), llvm::AMDGPU::isIntrinsicSourceOfDivergence(), MI, and llvm::NeverUniform.
Referenced by getInstructionUniformity().
◆ getIndirectGPRIDXPseudo()
| const MCInstrDesc & SIInstrInfo::getIndirectGPRIDXPseudo | ( | unsigned | VecSize, |
| bool | IsIndirectSrc | ||
| ) | const |
Definition at line 1404 of file SIInstrInfo.cpp.
References llvm::get(), and llvm_unreachable.
◆ getIndirectRegWriteMovRelPseudo()
| const MCInstrDesc & SIInstrInfo::getIndirectRegWriteMovRelPseudo | ( | unsigned | VecSize, |
| unsigned | EltSize, | ||
| bool | IsSGPR | ||
| ) | const |
Definition at line 1537 of file SIInstrInfo.cpp.
References assert(), llvm::get(), getIndirectSGPRWriteMovRelPseudo32(), getIndirectSGPRWriteMovRelPseudo64(), getIndirectVGPRWriteMovRelPseudoOpc(), and llvm_unreachable.
◆ getInstBundleSize()
| unsigned SIInstrInfo::getInstBundleSize | ( | const MachineInstr & | MI | ) | const |
Definition at line 8822 of file SIInstrInfo.cpp.
References assert(), getInstSizeInBytes(), I, MI, and Size.
Referenced by getInstSizeInBytes().
◆ getInstrLatency()
|
override |
Definition at line 9638 of file SIInstrInfo.cpp.
Referenced by llvm::GCNSubtarget::adjustSchedDependency().
◆ getInstructionUniformity()
|
finaloverride |
Definition at line 9705 of file SIInstrInfo.cpp.
References llvm::AlwaysUniform, llvm::any_of(), llvm::Default, getGenericInstructionUniformity(), llvm::RegisterBank::getID(), llvm::SrcOp::getReg(), llvm::MachineOperand::getReg(), llvm::RegisterBankInfo::getRegBank(), llvm::GCNSubtarget::getRegBankInfo(), I, isAtomic(), isFLAT(), isNeverUniform(), llvm::Register::isPhysical(), llvm::MachineOperand::isReg(), llvm::SIRegisterInfo::isSGPRClass(), MI, MRI, and llvm::NeverUniform.
◆ getInstSizeInBytes()
|
override |
Definition at line 8834 of file SIInstrInfo.cpp.
References getInstBundleSize(), llvm::TargetMachine::getMCAsmInfo(), getMCOpcodeFromPseudo(), llvm::AMDGPU::getNamedOperandIdx(), llvm::MachineFunction::getTarget(), llvm::GCNSubtarget::hasOffset3fBug(), I, isDPP(), isFixedSize(), isInlineConstant(), isMIMG(), isSALU(), isVALU(), MI, and Size.
Referenced by llvm::AMDGPUAsmPrinter::emitInstruction(), getInstBundleSize(), and removeBranch().
◆ getKillTerminatorFromPseudo()
| const MCInstrDesc & SIInstrInfo::getKillTerminatorFromPseudo | ( | unsigned | Opcode | ) | const |
Definition at line 9064 of file SIInstrInfo.cpp.
References llvm::get(), and llvm_unreachable.
◆ getLiveRangeSplitOpcode()
|
override |
Definition at line 8980 of file SIInstrInfo.cpp.
References assert(), llvm::SIMachineFunctionInfo::checkFlag(), llvm::MachineFunction::getInfo(), llvm::Register::isVirtual(), and llvm::AMDGPU::VirtRegFlag::WWM_REG.
◆ getMachineCSELookAheadLimit()
|
inlineoverride |
Definition at line 407 of file SIInstrInfo.h.
◆ getMaxMUBUFImmOffset()
|
static |
Definition at line 9079 of file SIInstrInfo.cpp.
References llvm::AMDGPUSubtarget::GFX12.
Referenced by isLegalMUBUFImmOffset(), llvm::AMDGPURegisterBankInfo::splitBufferOffsets(), llvm::AMDGPULegalizerInfo::splitBufferOffsets(), and splitMUBUFOffset().
◆ getMCOpcodeFromPseudo()
|
inline |
Return the descriptor of the target-specific machine instruction that corresponds to the specified pseudo or native opcode.
Definition at line 1316 of file SIInstrInfo.h.
References llvm::get(), and pseudoToMCOpcode().
Referenced by getInstSizeInBytes().
◆ getMemOperandsWithOffsetWidth()
|
final |
Definition at line 356 of file SIInstrInfo.cpp.
References assert(), llvm::MachineOperand::getImm(), getNamedOperand(), llvm::AMDGPU::getNamedOperandIdx(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), getOpRegClass(), getOpSize(), llvm::LocationSize::getValue(), I, isDS(), llvm::MachineOperand::isFI(), isFLAT(), isImage(), isMIMG(), isMTBUF(), isMUBUF(), llvm::MachineOperand::isReg(), isSMRD(), isStride64(), llvm::MachineInstr::mayLoad(), llvm::MachineInstr::mayLoadOrStore(), llvm::MachineInstr::mayStore(), llvm::Offset, llvm::SmallVectorTemplateBase< T, bool >::push_back(), and TRI.
◆ getMIRFormatter()
|
inlineoverride |
Definition at line 1448 of file SIInstrInfo.h.
◆ getMovOpcode()
| unsigned SIInstrInfo::getMovOpcode | ( | const TargetRegisterClass * | DstRC | ) | const |
Definition at line 1385 of file SIInstrInfo.cpp.
References llvm::SIRegisterInfo::isAGPRClass(), and llvm::SIRegisterInfo::isSGPRClass().
◆ getNamedImmOperand()
|
inline |
Get required immediate operand.
Definition at line 1303 of file SIInstrInfo.h.
References llvm::AMDGPU::getNamedOperandIdx(), Idx, and MI.
Referenced by legalizeOperands().
◆ getNamedOperand() [1/2]
|
inline |
Definition at line 1297 of file SIInstrInfo.h.
References getNamedOperand(), and MI.
◆ getNamedOperand() [2/2]
| MachineOperand * SIInstrInfo::getNamedOperand | ( | MachineInstr & | MI, |
| unsigned | OperandName | ||
| ) | const |
Returns the operand named Op.
If MI does not have an operand named Op, this function returns nullptr.
Definition at line 8704 of file SIInstrInfo.cpp.
References llvm::AMDGPU::getNamedOperandIdx(), Idx, and MI.
Referenced by buildShrunkInst(), canShrink(), convertToThreeAddress(), expandMovDPP64(), foldImmediate(), getMemOperandsWithOffsetWidth(), getNamedOperand(), hasModifiersSet(), isSGPRStackAccess(), isStackAccess(), legalizeOperands(), legalizeOperandsFLAT(), legalizeOperandsSMRD(), reMaterialize(), swapSourceModifiers(), and verifyInstruction().
◆ getNonSoftWaitcntOpcode()
Definition at line 980 of file SIInstrInfo.h.
Referenced by isWaitcnt(), isWaitInstr(), and pseudoToMCOpcode().
◆ getNumWaitStates()
|
static |
Return the number of wait states that result from executing this instruction.
Definition at line 2093 of file SIInstrInfo.cpp.
References MI.
Referenced by llvm::GCNHazardRecognizer::AdvanceCycle().
◆ getOpRegClass()
| const TargetRegisterClass * SIInstrInfo::getOpRegClass | ( | const MachineInstr & | MI, |
| unsigned | OpNo | ||
| ) | const |
Return the correct register class for OpNo.
For target-specific instructions, this will return the register class that has been defined in tablegen. For generic instructions, like REG_SEQUENCE it will return the register class of its machine operand. to infer the correct register class base on the other operands.
Definition at line 5710 of file SIInstrInfo.cpp.
References adjustAllocatableRegClass(), llvm::get(), MI, and MRI.
Referenced by expandPostRAPseudo(), getMemOperandsWithOffsetWidth(), getOpSize(), legalizeOperands(), and verifyInstruction().
◆ getOpSize() [1/2]
|
inline |
This form should usually be preferred since it handles operands with unknown register classes.
Definition at line 1187 of file SIInstrInfo.h.
References getOpRegClass(), llvm::MachineOperand::getSubReg(), llvm::MachineOperand::isReg(), MI, and SubReg.
◆ getOpSize() [2/2]
Return the size in bytes of the operand OpNo on the given.
Definition at line 1173 of file SIInstrInfo.h.
References assert(), llvm::get(), llvm::SIRegisterInfo::getRegClass(), llvm::MCOI::OPERAND_IMMEDIATE, llvm::MCOperandInfo::OperandType, and llvm::MCOperandInfo::RegClass.
Referenced by enforceOperandRCAlignment(), foldImmediate(), getMemOperandsWithOffsetWidth(), isInlineConstant(), and verifyInstruction().
◆ getPreferredSelectRegClass()
| const TargetRegisterClass * SIInstrInfo::getPreferredSelectRegClass | ( | unsigned | Size | ) | const |
Definition at line 1230 of file SIInstrInfo.cpp.
◆ getRegClass()
|
override |
Definition at line 5680 of file SIInstrInfo.cpp.
References adjustAllocatableRegClass(), llvm::SIInstrFlags::DS, llvm::SIInstrFlags::FLAT, llvm::AMDGPU::getNamedOperandIdx(), llvm::MCInstrDesc::getNumOperands(), llvm::MachineFunction::getRegInfo(), llvm::AMDGPU::hasNamedOperand(), llvm::MCInstrDesc::Opcode, llvm::MCInstrDesc::operands(), and llvm::MCInstrDesc::TSFlags.
Referenced by legalizeOperandsFLAT(), and reMaterialize().
◆ getRegisterInfo()
|
inline |
Definition at line 227 of file SIInstrInfo.h.
Referenced by llvm::GCNSubtarget::getRegisterInfo(), and llvm::PhiLoweringHelper::isLaneMaskReg().
◆ getSchedModel()
|
inline |
Definition at line 1456 of file SIInstrInfo.h.
Referenced by llvm::GCNSubtarget::adjustSchedDependency(), and llvm::GCNSchedStage::getScheduleMetrics().
◆ getScratchRsrcWords23()
| uint64_t SIInstrInfo::getScratchRsrcWords23 | ( | ) | const |
Definition at line 8738 of file SIInstrInfo.cpp.
References getDefaultRsrcDataFormat(), llvm::GCNSubtarget::getGeneration(), llvm::GCNSubtarget::getMaxPrivateElementSize(), llvm::AMDGPUSubtarget::GFX9, llvm::GCNSubtarget::isWave64(), llvm::Log2_32(), llvm::AMDGPU::RSRC_ELEMENT_SIZE_SHIFT, llvm::AMDGPU::RSRC_INDEX_STRIDE_SHIFT, llvm::AMDGPU::RSRC_TID_ENABLE, and llvm::AMDGPUSubtarget::VOLCANIC_ISLANDS.
◆ getSerializableDirectMachineOperandTargetFlags()
|
override |
Definition at line 8955 of file SIInstrInfo.cpp.
References MO_ABS32_HI, MO_ABS32_LO, MO_GOTPCREL, MO_GOTPCREL32_HI, MO_GOTPCREL32_LO, MO_REL32_HI, and MO_REL32_LO.
◆ getSerializableMachineMemOperandTargetFlags()
|
override |
Definition at line 8970 of file SIInstrInfo.cpp.
References llvm::MOLastUse, and llvm::MONoClobber.
◆ getSerializableTargetIndices()
|
override |
Definition at line 8910 of file SIInstrInfo.cpp.
References llvm::AMDGPU::TI_CONSTDATA_START, llvm::AMDGPU::TI_SCRATCH_RSRC_DWORD0, llvm::AMDGPU::TI_SCRATCH_RSRC_DWORD1, llvm::AMDGPU::TI_SCRATCH_RSRC_DWORD2, and llvm::AMDGPU::TI_SCRATCH_RSRC_DWORD3.
◆ getSubtarget()
|
inline |
Definition at line 231 of file SIInstrInfo.h.
◆ getVALUOp()
| unsigned SIInstrInfo::getVALUOp | ( | const MachineInstr & | MI | ) | const |
Definition at line 5406 of file SIInstrInfo.cpp.
References llvm::GCNSubtarget::hasAddNoCarry(), llvm::GCNSubtarget::hasDLInsts(), llvm::SIRegisterInfo::isAGPR(), llvm_unreachable, MI, MRI, and llvm::AMDGPUSubtarget::useRealTrue16Insts().
Referenced by moveToVALUImpl().
◆ hasAnyModifiersSet()
| bool SIInstrInfo::hasAnyModifiersSet | ( | const MachineInstr & | MI | ) | const |
Definition at line 4444 of file SIInstrInfo.cpp.
References llvm::any_of(), hasModifiersSet(), MI, ModifierOpNames, and Name.
Referenced by foldImmediate().
◆ hasDivergentBranch()
| bool SIInstrInfo::hasDivergentBranch | ( | const MachineBasicBlock * | MBB | ) | const |
Return whether the block terminate with divergent branch.
Note this only work before lowering the pseudo control flow instructions.
Definition at line 2854 of file SIInstrInfo.cpp.
References MBB, MI, and llvm::MachineBasicBlock::terminators().
Referenced by isSafeToSink().
◆ hasFPClamp() [1/2]
|
inlinestatic |
Definition at line 896 of file SIInstrInfo.h.
References llvm::SIInstrFlags::FPClamp, and MI.
◆ hasFPClamp() [2/2]
Definition at line 900 of file SIInstrInfo.h.
References llvm::SIInstrFlags::FPClamp, and llvm::get().
◆ hasIntClamp()
|
inlinestatic |
Definition at line 904 of file SIInstrInfo.h.
References llvm::SIInstrFlags::IntClamp, and MI.
◆ hasModifiers()
Return true if this instruction has any modifiers.
e.g. src[012]_mod, omod, clamp.
Definition at line 4431 of file SIInstrInfo.cpp.
References llvm::AMDGPU::hasNamedOperand().
◆ hasModifiersSet()
| bool SIInstrInfo::hasModifiersSet | ( | const MachineInstr & | MI, |
| unsigned | OpName | ||
| ) | const |
Definition at line 4438 of file SIInstrInfo.cpp.
References llvm::MachineOperand::getImm(), getNamedOperand(), and MI.
Referenced by canShrink(), and hasAnyModifiersSet().
◆ hasUnwantedEffectsWhenEXECEmpty()
| bool SIInstrInfo::hasUnwantedEffectsWhenEXECEmpty | ( | const MachineInstr & | MI | ) | const |
This function is used to determine if an instruction can be safely executed under EXEC = 0 without hardware error, indeterminate results, and/or visible effects on future vector execution or outside the shader.
Note: as of 2024 the only use of this is SIPreEmitPeephole where it is used in removing branches over short EXEC = 0 sequences. As such it embeds certain assumptions which may not apply to every case of EXEC = 0 execution.
Definition at line 4153 of file SIInstrInfo.cpp.
References isBarrier(), isEXP(), isSMRD(), MI, and modifiesModeRegister().
◆ hasVALU32BitEncoding()
Return true if this 64-bit VALU instruction has a 32-bit encoding.
This function will return false if you pass it a 32-bit instruction.
Definition at line 4419 of file SIInstrInfo.cpp.
References llvm::AMDGPU::getVOPe32(), llvm::GCNSubtarget::hasGFX90AInsts(), and pseudoToMCOpcode().
Referenced by canShrink().
◆ hasVGPRUses()
|
inline |
Definition at line 1034 of file SIInstrInfo.h.
References llvm::any_of(), llvm::MachineFunction::getRegInfo(), MI, and MRI.
◆ insertBranch()
|
override |
Definition at line 3139 of file SIInstrInfo.cpp.
References llvm::MachineInstrBuilder::addMBB(), assert(), llvm::BuildMI(), Cond, DL, fixImplicitOperands(), llvm::get(), llvm::MachineInstr::getOperand(), llvm::GCNSubtarget::hasOffset3fBug(), isImm(), isUndef(), MBB, preserveCondRegFlags(), llvm::MachineOperand::setIsKill(), llvm::MachineOperand::setIsUndef(), and TBB.
◆ insertEQ()
| Register SIInstrInfo::insertEQ | ( | MachineBasicBlock * | MBB, |
| MachineBasicBlock::iterator | I, | ||
| const DebugLoc & | DL, | ||
| Register | SrcReg, | ||
| int | Value | ||
| ) | const |
Definition at line 1359 of file SIInstrInfo.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), DL, llvm::get(), llvm::SIRegisterInfo::getBoolRC(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), I, MBB, and MRI.
◆ insertIndirectBranch()
|
override |
Definition at line 2863 of file SIInstrInfo.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::MachineInstrBuilder::addSym(), assert(), llvm::BuildMI(), llvm::MCSymbolRefExpr::create(), llvm::MCConstantExpr::create(), llvm::MCBinaryExpr::createAnd(), llvm::MCBinaryExpr::createAShr(), llvm::MCBinaryExpr::createSub(), llvm::RegState::Define, DL, llvm::MachineBasicBlock::empty(), llvm::AMDGPU::DepCtr::encodeFieldSaSdst(), llvm::MachineBasicBlock::end(), llvm::RegScavenger::enterBasicBlock(), llvm::RegScavenger::enterBasicBlockEnd(), llvm::get(), llvm::MachineFunction::getContext(), llvm::MachineFunction::getInfo(), llvm::SIMachineFunctionInfo::getLongBranchReservedReg(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), llvm::MachineFunction::getSubtarget(), llvm::MachineBasicBlock::getSymbol(), llvm::GCNSubtarget::hasVALUMaskWriteHazard(), llvm::GCNSubtarget::hasVALUReadSGPRHazard(), I, llvm::GCNSubtarget::isWave64(), MBB, MO_FAR_BRANCH_OFFSET, MRI, llvm::Offset, llvm::MachineBasicBlock::pred_size(), llvm::RegScavenger::scavengeRegisterBackwards(), llvm::MachineInstr::setPostInstrSymbol(), llvm::RegScavenger::setRegUsed(), llvm::MCSymbol::setVariableValue(), and TRI.
◆ insertNE()
| Register SIInstrInfo::insertNE | ( | MachineBasicBlock * | MBB, |
| MachineBasicBlock::iterator | I, | ||
| const DebugLoc & | DL, | ||
| Register | SrcReg, | ||
| int | Value | ||
| ) | const |
Definition at line 1372 of file SIInstrInfo.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), DL, llvm::get(), llvm::SIRegisterInfo::getBoolRC(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), I, MBB, and MRI.
◆ insertNoop()
|
override |
Definition at line 2001 of file SIInstrInfo.cpp.
References insertNoops(), MBB, and MI.
◆ insertNoops()
|
override |
Definition at line 2006 of file SIInstrInfo.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::BuildMI(), DL, llvm::MachineBasicBlock::findDebugLoc(), llvm::get(), MBB, and MI.
Referenced by insertNoop().
◆ insertReturn()
| void SIInstrInfo::insertReturn | ( | MachineBasicBlock & | MBB | ) | const |
Definition at line 2017 of file SIInstrInfo.cpp.
References llvm::MachineInstrBuilder::addImm(), assert(), llvm::BuildMI(), llvm::MachineBasicBlock::end(), llvm::get(), llvm::MachineBasicBlock::getFirstTerminator(), llvm::MachineBasicBlock::getParent(), Info, MBB, and llvm::MachineBasicBlock::succ_empty().
◆ insertScratchExecCopy()
| void SIInstrInfo::insertScratchExecCopy | ( | MachineFunction & | MF, |
| MachineBasicBlock & | MBB, | ||
| MachineBasicBlock::iterator | MBBI, | ||
| const DebugLoc & | DL, | ||
| Register | Reg, | ||
| bool | IsSCCLive, | ||
| SlotIndexes * | Indexes = nullptr |
||
| ) | const |
Definition at line 5599 of file SIInstrInfo.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), DL, llvm::MachineInstr::getOperand(), llvm::MachineFunction::getSubtarget(), llvm::SlotIndexes::insertMachineInstrInMaps(), llvm::RegState::Kill, MBB, MBBI, llvm::MachineOperand::setIsDead(), and TII.
◆ insertSelect()
|
override |
Definition at line 3247 of file SIInstrInfo.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), Cond, DL, fixImplicitOperands(), llvm::get(), llvm::ilist_node_impl< OptionsT >::getIterator(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), I, Idx, MBB, MRI, preserveCondRegFlags(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), Select, and std::swap().
◆ insertSimulatedTrap()
| MachineBasicBlock * SIInstrInfo::insertSimulatedTrap | ( | MachineRegisterInfo & | MRI, |
| MachineBasicBlock & | MBB, | ||
| MachineInstr & | MI, | ||
| const DebugLoc & | DL | ||
| ) | const |
Build instructions that simulate the behavior of a s_trap 2 instructions for hardware (namely, gfx11) that runs in PRIV=1 mode.
There, s_trap is interpreted as a nop.
Definition at line 2035 of file SIInstrInfo.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMBB(), llvm::MachineBasicBlock::addSuccessor(), llvm::MachineInstrBuilder::addUse(), llvm::BuildMI(), llvm::MachineFunction::CreateMachineBasicBlock(), DL, llvm::MachineBasicBlock::end(), llvm::get(), llvm::MachineBasicBlock::getParent(), llvm::AMDGPU::SendMsg::ID_INTERRUPT, llvm::AMDGPU::SendMsg::ID_RTN_GET_DOORBELL, llvm::GCNSubtarget::LLVMAMDHSATrap, MBB, MI, MRI, llvm::MachineFunction::push_back(), llvm::MachineBasicBlock::splitAt(), and llvm::MachineBasicBlock::succ_empty().
Referenced by llvm::AMDGPULegalizerInfo::legalizeTrapHsa().
◆ insertVectorSelect()
| void SIInstrInfo::insertVectorSelect | ( | MachineBasicBlock & | MBB, |
| MachineBasicBlock::iterator | I, | ||
| const DebugLoc & | DL, | ||
| Register | DstReg, | ||
| ArrayRef< MachineOperand > | Cond, | ||
| Register | TrueReg, | ||
| Register | FalseReg | ||
| ) | const |
Definition at line 1234 of file SIInstrInfo.cpp.
References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), Cond, DL, llvm::get(), llvm::SIRegisterInfo::getBoolRC(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), llvm::SIRegisterInfo::getWaveMaskRegClass(), I, isImm(), llvm::GCNSubtarget::isWave32(), llvm_unreachable, MBB, MRI, and llvm::MachineOperand::setImplicit().
◆ isAlwaysGDS()
Definition at line 4142 of file SIInstrInfo.cpp.
References isGWS().
◆ isAsmOnlyOpcode()
| bool SIInstrInfo::isAsmOnlyOpcode | ( | int | MCOp | ) | const |
Check if this instruction should only be used by assembler.
Return true if this opcode should not be used by codegen.
Definition at line 9278 of file SIInstrInfo.cpp.
Referenced by pseudoToMCOpcode().
◆ isAtomic() [1/2]
|
inlinestatic |
Definition at line 689 of file SIInstrInfo.h.
References llvm::SIInstrFlags::IsAtomicNoRet, llvm::SIInstrFlags::IsAtomicRet, and MI.
Referenced by getInstructionUniformity(), and isValidClauseInst().
◆ isAtomic() [2/2]
Definition at line 694 of file SIInstrInfo.h.
References llvm::get(), llvm::SIInstrFlags::IsAtomicNoRet, and llvm::SIInstrFlags::IsAtomicRet.
◆ isAtomicNoRet() [1/2]
|
inlinestatic |
Definition at line 673 of file SIInstrInfo.h.
References llvm::SIInstrFlags::IsAtomicNoRet, and MI.
◆ isAtomicNoRet() [2/2]
Definition at line 677 of file SIInstrInfo.h.
References llvm::get(), and llvm::SIInstrFlags::IsAtomicNoRet.
◆ isAtomicRet() [1/2]
|
inlinestatic |
Definition at line 681 of file SIInstrInfo.h.
References llvm::SIInstrFlags::IsAtomicRet, and MI.
◆ isAtomicRet() [2/2]
Definition at line 685 of file SIInstrInfo.h.
References llvm::get(), and llvm::SIInstrFlags::IsAtomicRet.
◆ isBarrier()
Definition at line 947 of file SIInstrInfo.h.
References isBarrierStart().
Referenced by hasUnwantedEffectsWhenEXECEmpty().
◆ isBarrierStart()
Definition at line 939 of file SIInstrInfo.h.
Referenced by isBarrier().
◆ isBasicBlockPrologue()
|
override |
Definition at line 8990 of file SIInstrInfo.cpp.
References llvm::MachineFunction::getInfo(), llvm::SIRegisterInfo::getRegClassForReg(), llvm::MachineFunction::getRegInfo(), llvm::SIRegisterInfo::isSGPRClass(), isSGPRSpill(), llvm::SIMachineFunctionInfo::isWWMReg(), isWWMRegSpillOpcode(), MI, and MRI.
◆ isBranchOffsetInRange()
Definition at line 2833 of file SIInstrInfo.cpp.
References assert(), BranchOffsetBits, and llvm::isIntN().
◆ isBufferSMRD()
| bool SIInstrInfo::isBufferSMRD | ( | const MachineInstr & | MI | ) | const |
Definition at line 9099 of file SIInstrInfo.cpp.
References llvm::AMDGPU::getNamedOperandIdx(), llvm::SIRegisterInfo::getRegClass(), llvm::TargetRegisterClass::hasSubClassEq(), Idx, isSMRD(), and MI.
◆ isChainCallOpcode()
Definition at line 763 of file SIInstrInfo.h.
◆ isCopyInstrImpl()
|
overrideprotected |
If the specific machine instruction is a instruction that moves/copies value from one register to another register return destination and source registers as machine operands.
Definition at line 2695 of file SIInstrInfo.cpp.
References MI.
◆ isDisableWQM() [1/2]
|
inlinestatic |
Definition at line 711 of file SIInstrInfo.h.
References llvm::SIInstrFlags::DisableWQM, and MI.
◆ isDisableWQM() [2/2]
Definition at line 715 of file SIInstrInfo.h.
References llvm::SIInstrFlags::DisableWQM, and llvm::get().
◆ isDOT() [1/2]
|
inlinestatic |
Definition at line 813 of file SIInstrInfo.h.
References llvm::SIInstrFlags::IsDOT, and MI.
◆ isDOT() [2/2]
Definition at line 837 of file SIInstrInfo.h.
References llvm::get(), and llvm::SIInstrFlags::IsDOT.
◆ isDPP() [1/2]
|
inlinestatic |
Definition at line 768 of file SIInstrInfo.h.
References llvm::SIInstrFlags::DPP, and MI.
Referenced by llvm::GCNHazardRecognizer::getHazardType(), getInstSizeInBytes(), and llvm::GCNHazardRecognizer::PreEmitNoopsCommon().
◆ isDPP() [2/2]
Definition at line 772 of file SIInstrInfo.h.
References llvm::SIInstrFlags::DPP, and llvm::get().
◆ isDS() [1/2]
|
inlinestatic |
Definition at line 562 of file SIInstrInfo.h.
References llvm::SIInstrFlags::DS, and MI.
Referenced by areLoadsFromSameBasePtr(), areMemAccessesTriviallyDisjoint(), llvm::GCNHazardRecognizer::getHazardType(), getMemOperandsWithOffsetWidth(), isOperandLegal(), llvm::GCNHazardRecognizer::PreEmitNoopsCommon(), shouldRunLdsBranchVmemWARHazardFixup(), and verifyInstruction().
◆ isDS() [2/2]
Definition at line 566 of file SIInstrInfo.h.
References llvm::SIInstrFlags::DS, and llvm::get().
◆ isDualSourceBlendEXP()
|
inlinestatic |
Definition at line 661 of file SIInstrInfo.h.
References llvm::AMDGPU::Exp::ET_DUAL_SRC_BLEND0, llvm::AMDGPU::Exp::ET_DUAL_SRC_BLEND1, isEXP(), and MI.
◆ isEXP() [1/2]
|
inlinestatic |
Definition at line 657 of file SIInstrInfo.h.
References llvm::SIInstrFlags::EXP, and MI.
Referenced by llvm::GCNHazardRecognizer::getHazardType(), hasUnwantedEffectsWhenEXECEmpty(), isDualSourceBlendEXP(), and llvm::GCNHazardRecognizer::PreEmitNoopsCommon().
◆ isEXP() [2/2]
Definition at line 669 of file SIInstrInfo.h.
References llvm::SIInstrFlags::EXP, and llvm::get().
◆ isF16PseudoScalarTrans()
Definition at line 957 of file SIInstrInfo.h.
Referenced by isOperandLegal().
◆ isFixedSize() [1/2]
|
inlinestatic |
Definition at line 888 of file SIInstrInfo.h.
References llvm::SIInstrFlags::FIXED_SIZE, and MI.
Referenced by getInstSizeInBytes().
◆ isFixedSize() [2/2]
Definition at line 892 of file SIInstrInfo.h.
References llvm::SIInstrFlags::FIXED_SIZE, and llvm::get().
◆ isFLAT() [1/2]
|
inlinestatic |
Definition at line 620 of file SIInstrInfo.h.
References llvm::SIInstrFlags::FLAT, and MI.
Referenced by areMemAccessesTriviallyDisjoint(), breaksVMEMSoftClause(), llvm::GCNHazardRecognizer::getHazardType(), getInstructionUniformity(), getMemOperandsWithOffsetWidth(), isHighLatencyDef(), isLdsDma(), isLDSDMA(), isVMEMClauseInst(), legalizeOperands(), mayAccessFlatAddressSpace(), llvm::GCNHazardRecognizer::PreEmitNoopsCommon(), and verifyInstruction().
◆ isFLAT() [2/2]
Definition at line 653 of file SIInstrInfo.h.
References llvm::SIInstrFlags::FLAT, and llvm::get().
◆ isFLATGlobal() [1/2]
|
inlinestatic |
Definition at line 636 of file SIInstrInfo.h.
References llvm::SIInstrFlags::FlatGlobal, and MI.
Referenced by areMemAccessesTriviallyDisjoint().
◆ isFLATGlobal() [2/2]
Definition at line 640 of file SIInstrInfo.h.
References llvm::SIInstrFlags::FlatGlobal, and llvm::get().
◆ isFLATScratch() [1/2]
|
inlinestatic |
Definition at line 644 of file SIInstrInfo.h.
References llvm::SIInstrFlags::FlatScratch, and MI.
Referenced by areMemAccessesTriviallyDisjoint(), llvm::SIRegisterInfo::getFrameIndexInstrOffset(), llvm::SIRegisterInfo::getScratchInstrOffset(), llvm::SIRegisterInfo::isFrameOffsetLegal(), and llvm::SIRegisterInfo::needsFrameBaseReg().
◆ isFLATScratch() [2/2]
Definition at line 648 of file SIInstrInfo.h.
References llvm::SIInstrFlags::FlatScratch, and llvm::get().
◆ isFoldableCopy()
|
static |
◆ isFPAtomic() [1/2]
|
inlinestatic |
Definition at line 924 of file SIInstrInfo.h.
References llvm::SIInstrFlags::FPAtomic, and MI.
◆ isFPAtomic() [2/2]
Definition at line 928 of file SIInstrInfo.h.
References llvm::SIInstrFlags::FPAtomic, and llvm::get().
◆ isGather4() [1/2]
|
inlinestatic |
Definition at line 612 of file SIInstrInfo.h.
References llvm::SIInstrFlags::Gather4, and MI.
Referenced by verifyInstruction().
◆ isGather4() [2/2]
Definition at line 616 of file SIInstrInfo.h.
References llvm::SIInstrFlags::Gather4, and llvm::get().
◆ isGlobalMemoryObject()
|
override |
Definition at line 10055 of file SIInstrInfo.cpp.
References llvm::TargetInstrInfo::isGlobalMemoryObject(), isIGLP(), and MI.
◆ isGWS() [1/2]
|
inlinestatic |
Definition at line 578 of file SIInstrInfo.h.
References llvm::SIInstrFlags::GWS, and MI.
Referenced by isAlwaysGDS().
◆ isGWS() [2/2]
Definition at line 582 of file SIInstrInfo.h.
References llvm::get(), and llvm::SIInstrFlags::GWS.
◆ isHighLatencyDef()
|
override |
Definition at line 8768 of file SIInstrInfo.cpp.
References llvm::get(), isFLAT(), isMIMG(), isMTBUF(), and isMUBUF().
Referenced by llvm::SIScheduleDAGMI::schedule().
◆ isIGLP() [1/2]
|
inline |
◆ isIGLP() [2/2]
Definition at line 973 of file SIInstrInfo.h.
Referenced by isGlobalMemoryObject().
◆ isIgnorableUse()
|
override |
Definition at line 184 of file SIInstrInfo.cpp.
References llvm::MachineOperand::getParent(), llvm::MachineOperand::getReg(), llvm::MachineOperand::isImplicit(), isVALU(), and resultDependsOnExec().
◆ isImage() [1/2]
|
inlinestatic |
Definition at line 432 of file SIInstrInfo.h.
References isMIMG(), isVIMAGE(), isVSAMPLE(), and MI.
Referenced by getMemOperandsWithOffsetWidth(), isVMEM(), legalizeOperands(), and verifyInstruction().
◆ isImage() [2/2]
Definition at line 436 of file SIInstrInfo.h.
References isMIMG(), isVIMAGE(), and isVSAMPLE().
◆ isImmOperandLegal()
| bool SIInstrInfo::isImmOperandLegal | ( | const MachineInstr & | MI, |
| unsigned | OpNo, | ||
| const MachineOperand & | MO | ||
| ) | const |
Definition at line 4389 of file SIInstrInfo.cpp.
References assert(), llvm::AMDGPU::getNamedOperandIdx(), llvm::GCNSubtarget::hasMFMAInlineLiteralBug(), llvm::GCNSubtarget::hasVOP3Literal(), llvm::MachineOperand::isFI(), llvm::MachineOperand::isGlobal(), llvm::MachineOperand::isImm(), isInlineConstant(), isMAI(), llvm::AMDGPU::isSISrcOperand(), llvm::MachineOperand::isTargetIndex(), isVOP3(), MI, llvm::SIRegisterInfo::opCanUseInlineConstant(), llvm::SIRegisterInfo::opCanUseLiteralConstant(), llvm::MCOI::OPERAND_IMMEDIATE, llvm::MCInstrDesc::operands(), llvm::MCOperandInfo::OperandType, and llvm::MCOperandInfo::RegClass.
Referenced by isOperandLegal().
◆ isInlineConstant() [1/8]
Definition at line 4244 of file SIInstrInfo.cpp.
References llvm::APInt::getSExtValue(), llvm::AMDGPUSubtarget::has16BitInsts(), llvm::AMDGPUSubtarget::hasInv2PiInlineImm(), llvm::AMDGPU::isInlinableLiteralBF16(), llvm::AMDGPU::isInlinableLiteralFP16(), isInlineConstant(), llvm_unreachable, llvm::APFloatBase::S_BFloat, llvm::APFloatBase::S_IEEEdouble, llvm::APFloatBase::S_IEEEhalf, llvm::APFloatBase::S_IEEEsingle, and llvm::APFloatBase::SemanticsToEnum().
◆ isInlineConstant() [2/8]
Definition at line 4224 of file SIInstrInfo.cpp.
References llvm::AMDGPUSubtarget::has16BitInsts(), llvm::AMDGPUSubtarget::hasInv2PiInlineImm(), llvm::AMDGPU::isInlinableLiteral32(), llvm::AMDGPU::isInlinableLiteral64(), llvm::AMDGPU::isInlinableLiteralI16(), and llvm_unreachable.
Referenced by convertToThreeAddress(), expandPostRAPseudo(), foldImmediate(), getInstSizeInBytes(), isImmOperandLegal(), isInlineConstant(), isOperandLegal(), legalizeOperandsVOP3(), llvm::AMDGPUCombinerHelper::matchCombineFmulWithSelectToFldexp(), usesConstantBus(), and verifyInstruction().
◆ isInlineConstant() [3/8]
|
inline |
returns true if UseMO is substituted with DefMO in MI it would be an inline immediate.
Definition at line 1078 of file SIInstrInfo.h.
References assert(), llvm::MachineOperand::getOperandNo(), llvm::MachineOperand::getParent(), isInlineConstant(), and MI.
◆ isInlineConstant() [4/8]
|
inline |
returns true if the operand OpIdx in MI is a valid inline immediate.
Definition at line 1091 of file SIInstrInfo.h.
References isInlineConstant(), and MI.
◆ isInlineConstant() [5/8]
|
inline |
Definition at line 1096 of file SIInstrInfo.h.
References assert(), getOpSize(), isInlineConstant(), MI, llvm::AMDGPU::OPERAND_REG_IMM_INT32, llvm::AMDGPU::OPERAND_REG_IMM_INT64, and Size.
◆ isInlineConstant() [6/8]
|
inline |
Definition at line 1113 of file SIInstrInfo.h.
References llvm::MachineOperand::getOperandNo(), llvm::MachineOperand::getParent(), and isInlineConstant().
◆ isInlineConstant() [7/8]
|
inline |
Definition at line 1071 of file SIInstrInfo.h.
References isInlineConstant(), and llvm::MCOperandInfo::OperandType.
◆ isInlineConstant() [8/8]
| bool SIInstrInfo::isInlineConstant | ( | const MachineOperand & | MO, |
| uint8_t | OperandType | ||
| ) | const |
Definition at line 4263 of file SIInstrInfo.cpp.
References assert(), llvm::MachineOperand::getImm(), llvm::AMDGPUSubtarget::has16BitInsts(), llvm::AMDGPUSubtarget::hasInv2PiInlineImm(), llvm::MachineOperand::isImm(), llvm::AMDGPU::isInlinableIntLiteral(), llvm::AMDGPU::isInlinableLiteral32(), llvm::AMDGPU::isInlinableLiteral64(), llvm::AMDGPU::isInlinableLiteralBF16(), llvm::AMDGPU::isInlinableLiteralFP16(), llvm::AMDGPU::isInlinableLiteralV2BF16(), llvm::AMDGPU::isInlinableLiteralV2F16(), llvm::AMDGPU::isInlinableLiteralV2I16(), llvm::MachineOperand::isReg(), llvm_unreachable, llvm::MCOI::OPERAND_GENERIC_0, llvm::MCOI::OPERAND_GENERIC_1, llvm::MCOI::OPERAND_GENERIC_2, llvm::MCOI::OPERAND_GENERIC_3, llvm::MCOI::OPERAND_GENERIC_4, llvm::MCOI::OPERAND_GENERIC_5, llvm::MCOI::OPERAND_IMMEDIATE, llvm::AMDGPU::OPERAND_INLINE_SPLIT_BARRIER_INT32, llvm::AMDGPU::OPERAND_INPUT_MODS, llvm::AMDGPU::OPERAND_KIMM16, llvm::AMDGPU::OPERAND_KIMM32, llvm::MCOI::OPERAND_PCREL, llvm::AMDGPU::OPERAND_REG_IMM_BF16, llvm::AMDGPU::OPERAND_REG_IMM_BF16_DEFERRED, llvm::AMDGPU::OPERAND_REG_IMM_FP16, llvm::AMDGPU::OPERAND_REG_IMM_FP16_DEFERRED, llvm::AMDGPU::OPERAND_REG_IMM_FP32, llvm::AMDGPU::OPERAND_REG_IMM_FP32_DEFERRED, llvm::AMDGPU::OPERAND_REG_IMM_FP64, llvm::AMDGPU::OPERAND_REG_IMM_INT16, llvm::AMDGPU::OPERAND_REG_IMM_INT32, llvm::AMDGPU::OPERAND_REG_IMM_INT64, llvm::AMDGPU::OPERAND_REG_IMM_V2BF16, llvm::AMDGPU::OPERAND_REG_IMM_V2FP16, llvm::AMDGPU::OPERAND_REG_IMM_V2FP32, llvm::AMDGPU::OPERAND_REG_IMM_V2INT16, llvm::AMDGPU::OPERAND_REG_IMM_V2INT32, llvm::AMDGPU::OPERAND_REG_INLINE_AC_BF16, llvm::AMDGPU::OPERAND_REG_INLINE_AC_FP16, llvm::AMDGPU::OPERAND_REG_INLINE_AC_FP32, llvm::AMDGPU::OPERAND_REG_INLINE_AC_FP64, llvm::AMDGPU::OPERAND_REG_INLINE_AC_INT16, llvm::AMDGPU::OPERAND_REG_INLINE_AC_INT32, llvm::AMDGPU::OPERAND_REG_INLINE_AC_V2BF16, llvm::AMDGPU::OPERAND_REG_INLINE_AC_V2FP16, llvm::AMDGPU::OPERAND_REG_INLINE_AC_V2INT16, llvm::AMDGPU::OPERAND_REG_INLINE_C_BF16, llvm::AMDGPU::OPERAND_REG_INLINE_C_FP16, llvm::AMDGPU::OPERAND_REG_INLINE_C_FP32, llvm::AMDGPU::OPERAND_REG_INLINE_C_FP64, llvm::AMDGPU::OPERAND_REG_INLINE_C_INT16, llvm::AMDGPU::OPERAND_REG_INLINE_C_INT32, llvm::AMDGPU::OPERAND_REG_INLINE_C_INT64, llvm::AMDGPU::OPERAND_REG_INLINE_C_V2BF16, llvm::AMDGPU::OPERAND_REG_INLINE_C_V2FP16, llvm::AMDGPU::OPERAND_REG_INLINE_C_V2FP32, llvm::AMDGPU::OPERAND_REG_INLINE_C_V2INT16, llvm::AMDGPU::OPERAND_REG_INLINE_C_V2INT32, llvm::MCOI::OPERAND_REGISTER, and llvm::MCOI::OPERAND_UNKNOWN.
◆ isKillTerminator()
Definition at line 9054 of file SIInstrInfo.cpp.
◆ isLDSDIR() [1/2]
|
inlinestatic |
Definition at line 841 of file SIInstrInfo.h.
References llvm::SIInstrFlags::LDSDIR, and MI.
◆ isLDSDIR() [2/2]
Definition at line 845 of file SIInstrInfo.h.
References llvm::get(), and llvm::SIInstrFlags::LDSDIR.
◆ isLDSDMA() [1/2]
|
inlinestatic |
Definition at line 570 of file SIInstrInfo.h.
References isFLAT(), isMUBUF(), isVALU(), and MI.
Referenced by areMemAccessesTriviallyDisjoint(), and mayWriteLDSThroughDMA().
◆ isLDSDMA() [2/2]
Definition at line 574 of file SIInstrInfo.h.
◆ isLegalFLATOffset()
| bool SIInstrInfo::isLegalFLATOffset | ( | int64_t | Offset, |
| unsigned | AddrSpace, | ||
| uint64_t | FlatVariant | ||
| ) | const |
Returns if Offset is legal for the subtarget as the offset to a FLAT encoded instruction.
If Signed, this is for an instruction that interprets the offset as signed.
Definition at line 9195 of file SIInstrInfo.cpp.
References allowNegativeFlatOffset(), llvm::SIInstrFlags::FLAT, llvm::AMDGPUAS::FLAT_ADDRESS, llvm::SIInstrFlags::FlatScratch, llvm::AMDGPU::getNumFlatOffsetBits(), llvm::AMDGPUAS::GLOBAL_ADDRESS, llvm::GCNSubtarget::hasFlatInstOffsets(), llvm::GCNSubtarget::hasFlatSegmentOffsetBug(), llvm::GCNSubtarget::hasNegativeUnalignedScratchOffsetBug(), llvm::isIntN(), N, and llvm::Offset.
Referenced by llvm::SITargetLowering::isLegalFlatAddressingMode(), and splitFlatOffset().
◆ isLegalMUBUFImmOffset()
Definition at line 9075 of file SIInstrInfo.cpp.
References getMaxMUBUFImmOffset().
◆ isLegalRegOperand()
| bool SIInstrInfo::isLegalRegOperand | ( | const MachineRegisterInfo & | MRI, |
| const MCOperandInfo & | OpInfo, | ||
| const MachineOperand & | MO | ||
| ) | const |
Check if MO (a register operand) is a legal register for the given operand description.
Definition at line 5793 of file SIInstrInfo.cpp.
References llvm::TargetRegisterClass::contains(), llvm::SIRegisterInfo::getLargestLegalSuperClass(), llvm::MachineOperand::getParent(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::SIRegisterInfo::getRegClass(), llvm::MachineOperand::getSubReg(), llvm::TargetRegisterClass::hasSuperClassEq(), llvm::MachineOperand::isReg(), MRI, and llvm::MCOperandInfo::RegClass.
Referenced by isLegalVSrcOperand(), isOperandLegal(), and legalizeOperandsVOP2().
◆ isLegalVSrcOperand()
| bool SIInstrInfo::isLegalVSrcOperand | ( | const MachineRegisterInfo & | MRI, |
| const MCOperandInfo & | OpInfo, | ||
| const MachineOperand & | MO | ||
| ) | const |
Check if MO would be a valid operand for the given operand definition OpInfo.
Note this does not attempt to validate constant bus restrictions (e.g. literal constant usage).
Definition at line 5820 of file SIInstrInfo.cpp.
References assert(), llvm::MachineOperand::isFI(), llvm::MachineOperand::isGlobal(), llvm::MachineOperand::isImm(), isLegalRegOperand(), llvm::MachineOperand::isReg(), llvm::MachineOperand::isTargetIndex(), and MRI.
◆ isLoadFromStackSlot()
|
override |
Definition at line 8794 of file SIInstrInfo.cpp.
References isMUBUF(), isSGPRSpill(), isSGPRStackAccess(), isStackAccess(), isVGPRSpill(), and MI.
◆ isLowLatencyInstruction()
| bool SIInstrInfo::isLowLatencyInstruction | ( | const MachineInstr & | MI | ) | const |
Definition at line 8762 of file SIInstrInfo.cpp.
Referenced by llvm::SIScheduleDAGMI::schedule().
◆ isMAI() [1/2]
|
inlinestatic |
Definition at line 800 of file SIInstrInfo.h.
References llvm::SIInstrFlags::IsMAI, and MI.
Referenced by llvm::GCNHazardRecognizer::getHazardType(), isImmOperandLegal(), isMFMA(), isXDL(), llvm::GCNHazardRecognizer::PreEmitNoopsCommon(), and pseudoToMCOpcode().
◆ isMAI() [2/2]
Definition at line 804 of file SIInstrInfo.h.
References llvm::get(), and llvm::SIInstrFlags::IsMAI.
◆ isMFMA()
|
inlinestatic |
Definition at line 808 of file SIInstrInfo.h.
Referenced by isMFMAorWMMA(), and llvm::GCNHazardRecognizer::ShouldPreferAnother().
◆ isMFMAorWMMA()
|
inlinestatic |
Definition at line 825 of file SIInstrInfo.h.
References isMFMA(), isSWMMAC(), isWMMA(), and MI.
◆ isMIMG() [1/2]
|
inlinestatic |
Definition at line 588 of file SIInstrInfo.h.
References MI, and llvm::SIInstrFlags::MIMG.
Referenced by getInstSizeInBytes(), getMemOperandsWithOffsetWidth(), isHighLatencyDef(), isImage(), isOperandLegal(), legalizeOperands(), and verifyInstruction().
◆ isMIMG() [2/2]
Definition at line 592 of file SIInstrInfo.h.
References llvm::get(), and llvm::SIInstrFlags::MIMG.
◆ isMTBUF() [1/2]
|
inlinestatic |
Definition at line 544 of file SIInstrInfo.h.
References MI, and llvm::SIInstrFlags::MTBUF.
Referenced by areLoadsFromSameBasePtr(), areMemAccessesTriviallyDisjoint(), getMemOperandsWithOffsetWidth(), isHighLatencyDef(), isVMEM(), and legalizeOperands().
◆ isMTBUF() [2/2]
Definition at line 548 of file SIInstrInfo.h.
References llvm::get(), and llvm::SIInstrFlags::MTBUF.
◆ isMUBUF() [1/2]
|
inlinestatic |
Definition at line 536 of file SIInstrInfo.h.
References MI, and llvm::SIInstrFlags::MUBUF.
Referenced by areLoadsFromSameBasePtr(), areMemAccessesTriviallyDisjoint(), llvm::SIRegisterInfo::getFrameIndexInstrOffset(), getMemOperandsWithOffsetWidth(), llvm::SIRegisterInfo::getScratchInstrOffset(), llvm::SIRegisterInfo::isFrameOffsetLegal(), isHighLatencyDef(), isLdsDma(), isLDSDMA(), isLoadFromStackSlot(), isStoreToStackSlot(), isVMEM(), legalizeOperands(), and llvm::SIRegisterInfo::needsFrameBaseReg().
◆ isMUBUF() [2/2]
Definition at line 540 of file SIInstrInfo.h.
References llvm::get(), and llvm::SIInstrFlags::MUBUF.
◆ isNeverUniform()
|
inlinestatic |
Definition at line 932 of file SIInstrInfo.h.
References llvm::SIInstrFlags::IsNeverUniform, and MI.
Referenced by getInstructionUniformity().
◆ isOperandLegal()
| bool SIInstrInfo::isOperandLegal | ( | const MachineInstr & | MI, |
| unsigned | OpIdx, | ||
| const MachineOperand * | MO = nullptr |
||
| ) | const |
Check if MO is a legal operand if it was the OpIdx Operand for MI.
Definition at line 5831 of file SIInstrInfo.cpp.
References assert(), llvm::detail::DenseSetImpl< ValueT, MapTy, ValueInfoT >::count(), llvm::GCNSubtarget::getConstantBusLimit(), llvm::MachineOperand::getImm(), llvm::AMDGPU::getNamedOperandIdx(), llvm::MachineOperand::getReg(), llvm::SIRegisterInfo::getRegClass(), llvm::MachineFunction::getRegInfo(), llvm::MachineOperand::getSubReg(), llvm::GCNSubtarget::hasGFX90AInsts(), llvm::AMDGPUSubtarget::hasInv2PiInlineImm(), llvm::GCNSubtarget::hasMAIInsts(), llvm::GCNSubtarget::hasNoF16PseudoScalarTransInlineConstants(), llvm::GCNSubtarget::hasVOP3Literal(), llvm::detail::DenseSetImpl< ValueT, MapTy, ValueInfoT >::insert(), llvm::SIRegisterInfo::isAGPR(), isDS(), isF16PseudoScalarTrans(), llvm::MachineOperand::isFI(), llvm::MachineOperand::isGlobal(), llvm::MachineOperand::isImm(), isImmOperandLegal(), llvm::AMDGPU::isInlinableLiteral64(), isInlineConstant(), isLegalRegOperand(), isMIMG(), llvm::MachineOperand::isReg(), llvm::SIRegisterInfo::isSGPRReg(), llvm::AMDGPU::isSISrcOperand(), llvm::MachineOperand::isTargetIndex(), llvm::AMDGPU::isValid32BitLiteral(), isVALU(), isVOP3(), MI, MRI, llvm::AMDGPU::OPERAND_REG_IMM_FP64, llvm::AMDGPU::OPERAND_REG_IMM_INT64, llvm::AMDGPU::OPERAND_REG_IMM_V2FP32, llvm::AMDGPU::OPERAND_REG_IMM_V2INT32, llvm::MCOI::OPERAND_UNKNOWN, llvm::MCInstrDesc::operands(), llvm::MCOperandInfo::OperandType, llvm::MCOperandInfo::RegClass, and usesConstantBus().
Referenced by commuteInstructionImpl(), convertToThreeAddress(), and legalizeOperandsVOP3().
◆ isPacked() [1/2]
|
inlinestatic |
Definition at line 488 of file SIInstrInfo.h.
References llvm::SIInstrFlags::IsPacked, and MI.
◆ isPacked() [2/2]
Definition at line 492 of file SIInstrInfo.h.
References llvm::get(), and llvm::SIInstrFlags::IsPacked.
◆ isReallyTriviallyReMaterializable()
|
override |
Definition at line 124 of file SIInstrInfo.cpp.
References canRemat(), llvm::TargetInstrInfo::isReallyTriviallyReMaterializable(), and MI.
◆ isSafeToSink()
|
override |
Definition at line 190 of file SIInstrInfo.cpp.
References llvm::GenericCycle< ContextT >::contains(), llvm::GenericCycleInfo< ContextT >::getCycle(), llvm::GenericCycle< ContextT >::getExitingBlocks(), llvm::MachineInstr::getParent(), llvm::GenericCycle< ContextT >::getParentCycle(), hasDivergentBranch(), llvm::SIRegisterInfo::isSGPRClass(), MI, and MRI.
◆ isSALU() [1/2]
|
inlinestatic |
Definition at line 416 of file SIInstrInfo.h.
References MI, and llvm::SIInstrFlags::SALU.
Referenced by canRemat(), getInstSizeInBytes(), isSGPRSpill(), mayReadEXEC(), and shouldReadExec().
◆ isSALU() [2/2]
Definition at line 420 of file SIInstrInfo.h.
References llvm::get(), and llvm::SIInstrFlags::SALU.
◆ isScalarStore() [1/2]
|
inlinestatic |
- Returns
- true if this is an s_store_dword* instruction. This is more specific than isSMEM && mayStore.
Definition at line 880 of file SIInstrInfo.h.
References MI, and llvm::SIInstrFlags::SCALAR_STORE.
◆ isScalarStore() [2/2]
Definition at line 884 of file SIInstrInfo.h.
References llvm::get(), and llvm::SIInstrFlags::SCALAR_STORE.
◆ isScalarUnit()
|
inlinestatic |
Definition at line 857 of file SIInstrInfo.h.
References MI, llvm::SIInstrFlags::SALU, and llvm::SIInstrFlags::SMRD.
◆ isSchedulingBoundary()
|
override |
Definition at line 4111 of file SIInstrInfo.cpp.
References changesVGPRIndexingMode(), and MI.
◆ isSDWA() [1/2]
|
inlinestatic |
Definition at line 520 of file SIInstrInfo.h.
References MI, and llvm::SIInstrFlags::SDWA.
Referenced by canRemat(), getDstSelForwardingOperand(), and verifyInstruction().
◆ isSDWA() [2/2]
Definition at line 524 of file SIInstrInfo.h.
References llvm::get(), and llvm::SIInstrFlags::SDWA.
◆ isSegmentSpecificFLAT() [1/2]
|
inlinestatic |
Definition at line 626 of file SIInstrInfo.h.
References llvm::SIInstrFlags::FlatGlobal, llvm::SIInstrFlags::FlatScratch, and MI.
Referenced by areMemAccessesTriviallyDisjoint(), legalizeOperandsFLAT(), moveFlatAddrToVGPR(), and shouldRunLdsBranchVmemWARHazardFixup().
◆ isSegmentSpecificFLAT() [2/2]
Definition at line 631 of file SIInstrInfo.h.
References llvm::SIInstrFlags::FlatGlobal, llvm::SIInstrFlags::FlatScratch, and llvm::get().
◆ isSGPRSpill() [1/2]
|
inlinestatic |
Definition at line 736 of file SIInstrInfo.h.
References isSALU(), isSpill(), and MI.
Referenced by isBasicBlockPrologue(), isLoadFromStackSlot(), and isStoreToStackSlot().
◆ isSGPRSpill() [2/2]
Definition at line 742 of file SIInstrInfo.h.
◆ isSGPRStackAccess()
| unsigned SIInstrInfo::isSGPRStackAccess | ( | const MachineInstr & | MI, |
| int & | FrameIndex | ||
| ) | const |
Definition at line 8786 of file SIInstrInfo.cpp.
References Addr, assert(), getNamedOperand(), llvm::MachineOperand::getReg(), and MI.
Referenced by isLoadFromStackSlot(), and isStoreToStackSlot().
◆ isSMRD() [1/2]
|
inlinestatic |
Definition at line 552 of file SIInstrInfo.h.
References MI, and llvm::SIInstrFlags::SMRD.
Referenced by areLoadsFromSameBasePtr(), areMemAccessesTriviallyDisjoint(), breaksSMEMSoftClause(), canRemat(), llvm::GCNHazardRecognizer::getHazardType(), getMemOperandsWithOffsetWidth(), hasUnwantedEffectsWhenEXECEmpty(), isBufferSMRD(), isLowLatencyInstruction(), isSMEMClauseInst(), legalizeOperands(), llvm::GCNHazardRecognizer::PreEmitNoopsCommon(), shouldReadExec(), and verifyInstruction().
◆ isSMRD() [2/2]
Definition at line 556 of file SIInstrInfo.h.
References llvm::get(), and llvm::SIInstrFlags::SMRD.
◆ isSOP1() [1/2]
|
inlinestatic |
Definition at line 448 of file SIInstrInfo.h.
References MI, and llvm::SIInstrFlags::SOP1.
◆ isSOP1() [2/2]
Definition at line 452 of file SIInstrInfo.h.
References llvm::get(), and llvm::SIInstrFlags::SOP1.
◆ isSOP2() [1/2]
|
inlinestatic |
Definition at line 456 of file SIInstrInfo.h.
References MI, and llvm::SIInstrFlags::SOP2.
Referenced by verifyInstruction().
◆ isSOP2() [2/2]
Definition at line 460 of file SIInstrInfo.h.
References llvm::get(), and llvm::SIInstrFlags::SOP2.
◆ isSOPC() [1/2]
|
inlinestatic |
Definition at line 464 of file SIInstrInfo.h.
References MI, and llvm::SIInstrFlags::SOPC.
Referenced by verifyInstruction().
◆ isSOPC() [2/2]
Definition at line 468 of file SIInstrInfo.h.
References llvm::get(), and llvm::SIInstrFlags::SOPC.
◆ isSOPK() [1/2]
|
inlinestatic |
Definition at line 472 of file SIInstrInfo.h.
References MI, and llvm::SIInstrFlags::SOPK.
Referenced by verifyInstruction().
◆ isSOPK() [2/2]
Definition at line 476 of file SIInstrInfo.h.
References llvm::get(), and llvm::SIInstrFlags::SOPK.
◆ isSOPP() [1/2]
|
inlinestatic |
Definition at line 480 of file SIInstrInfo.h.
References MI, and llvm::SIInstrFlags::SOPP.
◆ isSOPP() [2/2]
Definition at line 484 of file SIInstrInfo.h.
References llvm::get(), and llvm::SIInstrFlags::SOPP.
◆ isSpill() [1/2]
|
inlinestatic |
Definition at line 752 of file SIInstrInfo.h.
References MI, and llvm::SIInstrFlags::Spill.
◆ isSpill() [2/2]
Definition at line 748 of file SIInstrInfo.h.
References llvm::get(), and llvm::SIInstrFlags::Spill.
Referenced by isSGPRSpill(), and isVGPRSpill().
◆ isStackAccess()
| unsigned SIInstrInfo::isStackAccess | ( | const MachineInstr & | MI, |
| int & | FrameIndex | ||
| ) | const |
Definition at line 8773 of file SIInstrInfo.cpp.
References Addr, assert(), getNamedOperand(), llvm::MachineOperand::getReg(), MI, and llvm::AMDGPUAS::PRIVATE_ADDRESS.
Referenced by isLoadFromStackSlot(), and isStoreToStackSlot().
◆ isStoreToStackSlot()
|
override |
Definition at line 8808 of file SIInstrInfo.cpp.
References isMUBUF(), isSGPRSpill(), isSGPRStackAccess(), isStackAccess(), isVGPRSpill(), and MI.
◆ isSWMMAC() [1/2]
|
inlinestatic |
Definition at line 829 of file SIInstrInfo.h.
References llvm::SIInstrFlags::IsSWMMAC, and MI.
Referenced by isMFMAorWMMA().
◆ isSWMMAC() [2/2]
Definition at line 833 of file SIInstrInfo.h.
References llvm::get(), and llvm::SIInstrFlags::IsSWMMAC.
◆ isTRANS() [1/2]
|
inlinestatic |
Definition at line 776 of file SIInstrInfo.h.
References MI, and llvm::SIInstrFlags::TRANS.
◆ isTRANS() [2/2]
Definition at line 780 of file SIInstrInfo.h.
References llvm::get(), and llvm::SIInstrFlags::TRANS.
◆ isVALU() [1/2]
|
inlinestatic |
Definition at line 424 of file SIInstrInfo.h.
References MI, and llvm::SIInstrFlags::VALU.
Referenced by getDstSelForwardingOperand(), llvm::GCNHazardRecognizer::getHazardType(), getInstSizeInBytes(), isIgnorableUse(), isLdsDma(), isLDSDMA(), isOperandLegal(), isVGPRSpill(), llvm::GCNHazardRecognizer::PreEmitNoopsCommon(), shouldReadExec(), and verifyInstruction().
◆ isVALU() [2/2]
Definition at line 428 of file SIInstrInfo.h.
References llvm::get(), and llvm::SIInstrFlags::VALU.
◆ isVGPRCopy()
|
inline |
Definition at line 1026 of file SIInstrInfo.h.
References assert(), llvm::MachineFunction::getRegInfo(), llvm::SIRegisterInfo::isSGPRReg(), MI, and MRI.
Referenced by foldImmediate().
◆ isVGPRSpill() [1/2]
|
inlinestatic |
Definition at line 724 of file SIInstrInfo.h.
References isSpill(), isVALU(), and MI.
Referenced by isLoadFromStackSlot(), isStoreToStackSlot(), and verifyInstruction().
◆ isVGPRSpill() [2/2]
Definition at line 730 of file SIInstrInfo.h.
◆ isVIMAGE() [1/2]
|
inlinestatic |
Definition at line 596 of file SIInstrInfo.h.
References MI, and llvm::SIInstrFlags::VIMAGE.
Referenced by isImage(), and legalizeOperands().
◆ isVIMAGE() [2/2]
Definition at line 600 of file SIInstrInfo.h.
References llvm::get(), and llvm::SIInstrFlags::VIMAGE.
◆ isVINTERP() [1/2]
|
inlinestatic |
Definition at line 849 of file SIInstrInfo.h.
References MI, and llvm::SIInstrFlags::VINTERP.
◆ isVINTERP() [2/2]
Definition at line 853 of file SIInstrInfo.h.
References llvm::get(), and llvm::SIInstrFlags::VINTERP.
◆ isVINTRP() [1/2]
|
inlinestatic |
Definition at line 792 of file SIInstrInfo.h.
References MI, and llvm::SIInstrFlags::VINTRP.
Referenced by llvm::GCNHazardRecognizer::getHazardType(), and llvm::GCNHazardRecognizer::PreEmitNoopsCommon().
◆ isVINTRP() [2/2]
Definition at line 796 of file SIInstrInfo.h.
References llvm::get(), and llvm::SIInstrFlags::VINTRP.
◆ isVMEM() [1/2]
|
inlinestatic |
Definition at line 440 of file SIInstrInfo.h.
References isImage(), isMTBUF(), isMUBUF(), and MI.
Referenced by breaksVMEMSoftClause(), llvm::GCNHazardRecognizer::getHazardType(), isVMEMClauseInst(), isVMEMLoad(), llvm::GCNHazardRecognizer::PreEmitNoopsCommon(), and shouldRunLdsBranchVmemWARHazardFixup().
◆ isVMEM() [2/2]
Definition at line 444 of file SIInstrInfo.h.
◆ isVOP1() [1/2]
|
inlinestatic |
Definition at line 496 of file SIInstrInfo.h.
References MI, and llvm::SIInstrFlags::VOP1.
Referenced by canRemat().
◆ isVOP1() [2/2]
Definition at line 500 of file SIInstrInfo.h.
References llvm::get(), and llvm::SIInstrFlags::VOP1.
◆ isVOP2() [1/2]
|
inlinestatic |
Definition at line 504 of file SIInstrInfo.h.
References MI, and llvm::SIInstrFlags::VOP2.
Referenced by canRemat(), legalizeOperands(), and verifyInstruction().
◆ isVOP2() [2/2]
Definition at line 508 of file SIInstrInfo.h.
References llvm::get(), and llvm::SIInstrFlags::VOP2.
◆ isVOP3() [1/2]
|
inlinestatic |
Definition at line 512 of file SIInstrInfo.h.
References MI, and llvm::SIInstrFlags::VOP3.
Referenced by canRemat(), llvm::SIRegisterInfo::eliminateFrameIndex(), isImmOperandLegal(), isOperandLegal(), legalizeOperands(), moveToVALUImpl(), and verifyInstruction().
◆ isVOP3() [2/2]
Definition at line 516 of file SIInstrInfo.h.
References llvm::get(), and llvm::SIInstrFlags::VOP3.
◆ isVOP3P() [1/2]
|
inlinestatic |
Definition at line 784 of file SIInstrInfo.h.
References MI, and llvm::SIInstrFlags::VOP3P.
◆ isVOP3P() [2/2]
Definition at line 788 of file SIInstrInfo.h.
References llvm::get(), and llvm::SIInstrFlags::VOP3P.
◆ isVOPC() [1/2]
|
inlinestatic |
Definition at line 528 of file SIInstrInfo.h.
References MI, and llvm::SIInstrFlags::VOPC.
Referenced by legalizeOperands(), and verifyInstruction().
◆ isVOPC() [2/2]
Definition at line 532 of file SIInstrInfo.h.
References llvm::get(), and llvm::SIInstrFlags::VOPC.
◆ isVSAMPLE() [1/2]
|
inlinestatic |
Definition at line 604 of file SIInstrInfo.h.
References MI, and llvm::SIInstrFlags::VSAMPLE.
Referenced by isImage(), legalizeOperands(), and verifyInstruction().
◆ isVSAMPLE() [2/2]
Definition at line 608 of file SIInstrInfo.h.
References llvm::get(), and llvm::SIInstrFlags::VSAMPLE.
◆ isWaitcnt()
Definition at line 1003 of file SIInstrInfo.h.
References getNonSoftWaitcntOpcode().
◆ isWave32()
| bool llvm::SIInstrInfo::isWave32 | ( | ) | const |
Definition at line 9598 of file SIInstrInfo.cpp.
References llvm::GCNSubtarget::isWave32().
Referenced by restoreExec().
◆ isWMMA() [1/2]
|
inlinestatic |
Definition at line 817 of file SIInstrInfo.h.
References llvm::SIInstrFlags::IsWMMA, and MI.
Referenced by convertToThreeAddress(), and isMFMAorWMMA().
◆ isWMMA() [2/2]
Definition at line 821 of file SIInstrInfo.h.
References llvm::get(), and llvm::SIInstrFlags::IsWMMA.
◆ isWQM() [1/2]
|
inlinestatic |
Definition at line 703 of file SIInstrInfo.h.
References MI, and llvm::SIInstrFlags::WQM.
◆ isWQM() [2/2]
Definition at line 707 of file SIInstrInfo.h.
References llvm::get(), and llvm::SIInstrFlags::WQM.
◆ isWWMRegSpillOpcode()
Definition at line 756 of file SIInstrInfo.h.
Referenced by isBasicBlockPrologue().
◆ legalizeGenericOperand()
| void SIInstrInfo::legalizeGenericOperand | ( | MachineBasicBlock & | InsertMBB, |
| MachineBasicBlock::iterator | I, | ||
| const TargetRegisterClass * | DstRC, | ||
| MachineOperand & | Op, | ||
| MachineRegisterInfo & | MRI, | ||
| const DebugLoc & | DL | ||
| ) | const |
Definition at line 6326 of file SIInstrInfo.cpp.
References llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), DL, foldImmediate(), llvm::get(), llvm::SIRegisterInfo::getRegClassForReg(), I, llvm::RegState::Implicit, llvm::SIRegisterInfo::isSGPRClass(), and MRI.
Referenced by legalizeOperands().
◆ legalizeOperands()
| MachineBasicBlock * SIInstrInfo::legalizeOperands | ( | MachineInstr & | MI, |
| MachineDominatorTree * | MDT = nullptr |
||
| ) | const |
Legalize all operands in this instruction.
This function may create new instructions and control-flow around MI. If present, MDT is updated.
- Returns
- A new basic block that contains
MIif new blocks were created.
Definition at line 6664 of file SIInstrInfo.cpp.
References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addDef(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), llvm::MachineOperand::ChangeToRegister(), llvm::MachineInstrBuilder::cloneMemRefs(), llvm::RegState::Dead, DL, llvm::MachineBasicBlock::end(), End, extractRsrcPtr(), llvm::get(), llvm::AMDGPU::getAddr64Inst(), llvm::Function::getCallingConv(), llvm::MachineInstr::getDebugLoc(), llvm::SIRegisterInfo::getEquivalentAGPRClass(), llvm::SIRegisterInfo::getEquivalentVGPRClass(), llvm::MachineBasicBlock::getFirstTerminator(), llvm::MachineFunction::getFunction(), llvm::GCNSubtarget::getGeneration(), llvm::AMDGPU::getIfAddr64Inst(), getNamedImmOperand(), getNamedOperand(), llvm::AMDGPU::getNamedOperandIdx(), getOpRegClass(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), llvm::SIRegisterInfo::getWaveMaskRegClass(), llvm::GCNSubtarget::hasAddr64(), llvm::SIRegisterInfo::hasVectorRegisters(), llvm::SIRegisterInfo::hasVGPRs(), I, llvm::SIRegisterInfo::isAGPRClass(), isFLAT(), llvm::AMDGPU::isGraphics(), isImage(), isMIMG(), isMTBUF(), isMUBUF(), llvm::MachineOperand::isReg(), llvm::SIRegisterInfo::isSGPRClass(), llvm::SIRegisterInfo::isSGPRReg(), isSMRD(), isVIMAGE(), llvm::Register::isVirtual(), isVOP2(), isVOP3(), isVOPC(), isVSAMPLE(), llvm::RegState::Kill, legalizeGenericOperand(), legalizeOperandsFLAT(), legalizeOperandsSMRD(), legalizeOperandsVOP2(), legalizeOperandsVOP3(), loadMBUFScalarOperandsFromVGPR(), MBB, MI, MRI, llvm::Offset, readlaneVGPRToSGPR(), llvm::MachineOperand::setReg(), and llvm::AMDGPUSubtarget::VOLCANIC_ISLANDS.
Referenced by foldImmediate(), and moveToVALUImpl().
◆ legalizeOperandsFLAT()
| void SIInstrInfo::legalizeOperandsFLAT | ( | MachineRegisterInfo & | MRI, |
| MachineInstr & | MI | ||
| ) | const |
Definition at line 6305 of file SIInstrInfo.cpp.
References getNamedOperand(), llvm::MachineOperand::getOperandNo(), llvm::MachineOperand::getReg(), getRegClass(), isSegmentSpecificFLAT(), llvm::SIRegisterInfo::isSGPRClass(), MI, moveFlatAddrToVGPR(), MRI, readlaneVGPRToSGPR(), and llvm::MachineOperand::setReg().
Referenced by legalizeOperands().
◆ legalizeOperandsSMRD()
| void SIInstrInfo::legalizeOperandsSMRD | ( | MachineRegisterInfo & | MRI, |
| MachineInstr & | MI | ||
| ) | const |
Definition at line 6205 of file SIInstrInfo.cpp.
References getNamedOperand(), llvm::MachineOperand::getReg(), llvm::SIRegisterInfo::isSGPRClass(), llvm::SIRegisterInfo::isSGPRReg(), MI, MRI, readlaneVGPRToSGPR(), and llvm::MachineOperand::setReg().
Referenced by legalizeOperands().
◆ legalizeOperandsVOP2()
| void SIInstrInfo::legalizeOperandsVOP2 | ( | MachineRegisterInfo & | MRI, |
| MachineInstr & | MI | ||
| ) | const |
Legalize operands in MI by either commuting it or inserting a copy of src1.
Definition at line 5950 of file SIInstrInfo.cpp.
References llvm::MachineInstrBuilder::add(), llvm::BuildMI(), llvm::MachineOperand::ChangeToImmediate(), llvm::MachineOperand::ChangeToRegister(), commuteOpcode(), DL, findImplicitSGPRRead(), fixImplicitOperands(), llvm::get(), llvm::GCNSubtarget::getConstantBusLimit(), llvm::MachineOperand::getImm(), llvm::AMDGPU::getNamedOperandIdx(), llvm::MachineOperand::getReg(), llvm::MachineOperand::getSubReg(), llvm::SIRegisterInfo::isAGPR(), llvm::MachineOperand::isImm(), llvm::MachineOperand::isKill(), isLegalRegOperand(), llvm::MachineOperand::isReg(), llvm::SIRegisterInfo::isSGPRReg(), llvm::SIRegisterInfo::isVGPR(), legalizeOpWithMove(), llvm_unreachable, MI, MRI, llvm::MCInstrDesc::operands(), and llvm::MachineOperand::setSubReg().
Referenced by legalizeOperands().
◆ legalizeOperandsVOP3()
| void SIInstrInfo::legalizeOperandsVOP3 | ( | MachineRegisterInfo & | MRI, |
| MachineInstr & | MI | ||
| ) | const |
Fix operands in MI to satisfy constant bus requirements.
Definition at line 6068 of file SIInstrInfo.cpp.
References llvm::MachineInstrBuilder::add(), llvm::BuildMI(), llvm::MachineOperand::ChangeToRegister(), llvm::detail::DenseSetImpl< ValueT, MapTy, ValueInfoT >::count(), DL, llvm::get(), llvm::GCNSubtarget::getConstantBusLimit(), llvm::AMDGPU::getNamedOperandIdx(), llvm::MachineOperand::getReg(), llvm::SIRegisterInfo::getRegClassForReg(), llvm::SIRegisterInfo::hasAGPRs(), llvm::GCNSubtarget::hasVOP3Literal(), Idx, llvm::detail::DenseSetImpl< ValueT, MapTy, ValueInfoT >::insert(), isInlineConstant(), isOperandLegal(), llvm::MachineOperand::isReg(), llvm::SIRegisterInfo::isSGPRClass(), llvm::SIRegisterInfo::isVGPR(), legalizeOpWithMove(), MI, and MRI.
Referenced by legalizeOperands().
◆ legalizeOpWithMove()
| void SIInstrInfo::legalizeOpWithMove | ( | MachineInstr & | MI, |
| unsigned | OpIdx | ||
| ) | const |
Legalize the OpIndex operand of this instruction by inserting a MOV.
For example: ADD_I32_e32 VGPR0, 15 to MOV VGPR1, 15 ADD_I32_e32 VGPR0, VGPR1
If the operand being legalized is a register, then a COPY will be used instead of MOV.
Definition at line 5727 of file SIInstrInfo.cpp.
References llvm::MachineInstrBuilder::add(), llvm::BuildMI(), llvm::MachineOperand::ChangeToRegister(), DL, llvm::MachineBasicBlock::findDebugLoc(), llvm::get(), llvm::SIRegisterInfo::getEquivalentVGPRClass(), llvm::MachineBasicBlock::getParent(), llvm::SIRegisterInfo::getRegClass(), llvm::MachineFunction::getRegInfo(), I, llvm::MachineOperand::isReg(), llvm::SIRegisterInfo::isSGPRClass(), MBB, MI, MRI, and Size.
Referenced by legalizeOperandsVOP2(), and legalizeOperandsVOP3().
◆ loadRegFromStackSlot()
|
override |
Definition at line 1949 of file SIInstrInfo.cpp.
References llvm::MachineInstrBuilder::addFrameIndex(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMemOperand(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), DL, llvm::MachineBasicBlock::findDebugLoc(), llvm::get(), llvm::MachinePointerInfo::getFixedStack(), llvm::MachineFunction::getFrameInfo(), llvm::MachineFunction::getInfo(), llvm::MachineFunction::getMachineMemOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), getSGPRSpillRestoreOpcode(), llvm::SIMachineFunctionInfo::getStackPtrOffsetReg(), getVectorRegSpillRestoreOpcode(), llvm::RegState::Implicit, llvm::SIRegisterInfo::isSGPRClass(), llvm::Register::isVirtual(), MBB, MI, llvm::MachineMemOperand::MOLoad, MRI, llvm::SIMachineFunctionInfo::setHasSpilledSGPRs(), llvm::TargetStackID::SGPRSpill, llvm::SIRegisterInfo::spillSGPRToVGPR(), and TRI.
◆ materializeImmediate()
| void SIInstrInfo::materializeImmediate | ( | MachineBasicBlock & | MBB, |
| MachineBasicBlock::iterator | MI, | ||
| const DebugLoc & | DL, | ||
| Register | DestReg, | ||
| int64_t | Value | ||
| ) | const |
Definition at line 1173 of file SIInstrInfo.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::BuildMI(), DL, llvm::get(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), llvm::SIRegisterInfo::getRegSplitParts(), llvm::TargetRegisterClass::hasSuperClassEq(), Idx, llvm::SIRegisterInfo::isSGPRClass(), MBB, MI, MRI, and llvm::ArrayRef< T >::size().
◆ mayAccessFlatAddressSpace()
| bool SIInstrInfo::mayAccessFlatAddressSpace | ( | const MachineInstr & | MI | ) | const |
Definition at line 8895 of file SIInstrInfo.cpp.
References llvm::AMDGPUAS::FLAT_ADDRESS, isFLAT(), and MI.
◆ mayReadEXEC()
| bool SIInstrInfo::mayReadEXEC | ( | const MachineRegisterInfo & | MRI, |
| const MachineInstr & | MI | ||
| ) | const |
Returns true if the instruction could potentially depend on the value of exec.
If false, exec dependencies may safely be ignored.
Definition at line 4199 of file SIInstrInfo.cpp.
References isSALU(), llvm::SIRegisterInfo::isSGPRReg(), llvm::isTargetSpecificOpcode(), MI, and MRI.
◆ mayWriteLDSThroughDMA()
|
inlinestatic |
Definition at line 699 of file SIInstrInfo.h.
References isLDSDMA(), and MI.
◆ modifiesModeRegister()
|
static |
Return true if the instruction modifies the mode register.q.
Definition at line 4146 of file SIInstrInfo.cpp.
References llvm::is_contained(), and MI.
Referenced by hasUnwantedEffectsWhenEXECEmpty().
◆ moveFlatAddrToVGPR()
| bool SIInstrInfo::moveFlatAddrToVGPR | ( | MachineInstr & | Inst | ) | const |
Change SADDR form of a FLAT Inst to its VADDR form if saddr operand was moved to VGPR.
- Returns
- true if succeeded.
Definition at line 6224 of file SIInstrInfo.cpp.
References assert(), llvm::MachineInstr::eraseFromParent(), llvm::get(), llvm::AMDGPU::getFlatScratchInstSVfromSS(), llvm::AMDGPU::getGlobalVaddrOp(), llvm::MachineOperand::getImm(), llvm::MachineInstr::getMF(), llvm::AMDGPU::getNamedOperandIdx(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), llvm::MachineOperand::isImm(), isSegmentSpecificFLAT(), llvm::SIRegisterInfo::isSGPRReg(), MRI, llvm::MachineInstr::removeOperand(), llvm::MachineInstr::setDesc(), llvm::MachineInstr::tieOperands(), and llvm::MachineInstr::untieRegOperand().
Referenced by legalizeOperandsFLAT().
◆ moveToVALU()
| void SIInstrInfo::moveToVALU | ( | SIInstrWorklist & | Worklist, |
| MachineDominatorTree * | MDT | ||
| ) | const |
Replace the instructions opcode with the equivalent VALU opcode.
This function will also move the users of MachineInstruntions in the WorkList to the VALU if necessary. If present, MDT is updated.
Definition at line 7060 of file SIInstrInfo.cpp.
References assert(), llvm::SIInstrWorklist::empty(), llvm::SIInstrWorklist::erase_top(), llvm::SIInstrWorklist::getDeferredList(), llvm::SIInstrWorklist::isDeferred(), moveToVALUImpl(), and llvm::SIInstrWorklist::top().
◆ moveToVALUImpl()
| void SIInstrInfo::moveToVALUImpl | ( | SIInstrWorklist & | Worklist, |
| MachineDominatorTree * | MDT, | ||
| MachineInstr & | Inst | ||
| ) | const |
Definition at line 7081 of file SIInstrInfo.cpp.
References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstr::addOperand(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BitWidth, llvm::BuildMI(), llvm::RegState::Define, DL, llvm::MachineInstr::eraseFromParent(), llvm::MachineInstr::explicit_operands(), llvm::MachineInstr::findRegisterDefOperandIdx(), fixImplicitOperands(), llvm::get(), llvm::MachineInstr::getDebugLoc(), llvm::SIRegisterInfo::getEquivalentVGPRClass(), llvm::MachineInstr::getFlags(), llvm::GCNSubtarget::getGeneration(), llvm::MachineOperand::getImm(), llvm::AMDGPU::getNamedOperandIdx(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::SIRegisterInfo::getRegClassForReg(), llvm::MachineFunction::getRegInfo(), getVALUOp(), llvm::SIRegisterInfo::getVCC(), llvm::SIRegisterInfo::getWaveMaskRegClass(), llvm::AMDGPUSubtarget::GFX12, llvm::GCNSubtarget::hasDLInsts(), llvm::AMDGPU::hasNamedOperand(), llvm::GCNSubtarget::hasOnlyRevVALUShifts(), I, llvm::MachineInstr::implicit_operands(), llvm::MachineInstr::isCopy(), llvm::MachineOperand::isImm(), llvm::Register::isPhysical(), llvm::AMDGPU::isTrue16Inst(), llvm::SIRegisterInfo::isVGPR(), llvm::Register::isVirtual(), isVOP3(), llvm::GCNSubtarget::isWave32(), legalizeOperands(), llvm_unreachable, MBB, MRI, llvm::Offset, llvm::MachineInstr::removeOperand(), llvm::MachineInstr::setDesc(), llvm::MachineInstrBuilder::setMIFlags(), llvm::MachineOperand::setReg(), Size, and llvm::AMDGPUSubtarget::useRealTrue16Insts().
Referenced by moveToVALU().
◆ optimizeCompareInstr()
|
override |
Definition at line 9870 of file SIInstrInfo.cpp.
References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addImm(), assert(), llvm::BuildMI(), llvm::countr_zero(), llvm::MachineInstr::eraseFromParent(), llvm::get(), getFoldableImm(), llvm::MachineOperand::getImm(), llvm::ilist_node_impl< OptionsT >::getIterator(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getParent(), I, llvm::MachineOperand::isImm(), llvm::Register::isPhysical(), llvm::isPowerOf2_64(), llvm::maxUIntN(), MBB, MRI, and llvm::MachineOperand::setIsDead().
◆ pseudoToMCOpcode()
| int SIInstrInfo::pseudoToMCOpcode | ( | int | Opcode | ) | const |
Return a target-specific opcode if Opcode is a pseudo instruction.
Return -1 if the target-specific opcode for the pseudo instruction does not exist. If Opcode is not a pseudo instruction, this is identity.
Definition at line 9331 of file SIInstrInfo.cpp.
References llvm::SIInstrFlags::D16Buf, llvm::get(), llvm::GCNSubtarget::getGeneration(), llvm::AMDGPU::getMCOpcode(), llvm::AMDGPU::getMFMAEarlyClobberOp(), getNonSoftWaitcntOpcode(), llvm::AMDGPUSubtarget::GFX10, llvm::SIEncodingFamily::GFX80, llvm::AMDGPUSubtarget::GFX9, llvm::SIEncodingFamily::GFX9, llvm::SIEncodingFamily::GFX90A, llvm::SIEncodingFamily::GFX940, llvm::GCNSubtarget::hasGFX90AInsts(), llvm::GCNSubtarget::hasGFX940Insts(), llvm::GCNSubtarget::hasUnpackedD16VMem(), isAsmOnlyOpcode(), isMAI(), isRenamedInGFX9(), llvm::SIEncodingFamily::SDWA, llvm::SIInstrFlags::SDWA, llvm::SIEncodingFamily::SDWA10, llvm::SIEncodingFamily::SDWA9, and subtargetEncodingFamily().
Referenced by commuteOpcode(), convertToThreeAddress(), foldImmediate(), getMCOpcodeFromPseudo(), llvm::GCNSubtarget::hasMadF16(), and hasVALU32BitEncoding().
◆ readlaneVGPRToSGPR()
| Register SIInstrInfo::readlaneVGPRToSGPR | ( | Register | SrcReg, |
| MachineInstr & | UseMI, | ||
| MachineRegisterInfo & | MRI, | ||
| const TargetRegisterClass * | DstRC = nullptr |
||
| ) | const |
Copy a value from a VGPR (SrcReg) to SGPR.
The desired register class for the dst register (DstRC) can be optionally supplied. This function can only be used when it is know that the value in SrcReg is same across all threads in the wave.
- Returns
- The SGPR register that
SrcRegwas copied to.
Definition at line 6159 of file SIInstrInfo.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::get(), llvm::SIRegisterInfo::getEquivalentSGPRClass(), llvm::SIRegisterInfo::getEquivalentVGPRClass(), llvm::SIRegisterInfo::getSubRegFromChannel(), llvm::SIRegisterInfo::hasAGPRs(), MRI, llvm::SmallVectorTemplateBase< T, bool >::push_back(), and UseMI.
Referenced by legalizeOperands(), legalizeOperandsFLAT(), and legalizeOperandsSMRD().
◆ reMaterialize()
|
override |
Definition at line 2544 of file SIInstrInfo.cpp.
References assert(), llvm::MachineFunction::CloneMachineInstr(), llvm::MachineBasicBlock::end(), llvm::get(), llvm::TargetRegisterInfo::getAllocatableClass(), llvm::MachineOperand::getImm(), llvm::MachineFunction::getMachineMemOperand(), getNamedOperand(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getReg(), getRegClass(), llvm::MachineFunction::getRegInfo(), llvm::MachineOperand::getSubReg(), llvm::TargetRegisterInfo::getSubRegIdxOffset(), llvm::TargetRegisterInfo::getSubRegIdxSize(), I, llvm::MachineBasicBlock::insert(), MBB, llvm::MachineInstr::memoperands(), MI, MRI, llvm::Offset, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::TargetInstrInfo::reMaterialize(), llvm::MachineOperand::setImm(), llvm::MachineOperand::setReg(), and llvm::MachineOperand::setSubReg().
◆ removeBranch()
|
override |
Definition at line 3113 of file SIInstrInfo.cpp.
References getInstSizeInBytes(), llvm::make_early_inc_range(), MBB, MI, and llvm::MachineBasicBlock::terminators().
◆ removeModOperands()
| void SIInstrInfo::removeModOperands | ( | MachineInstr & | MI | ) | const |
Definition at line 3382 of file SIInstrInfo.cpp.
References llvm::AMDGPU::getNamedOperandIdx(), Idx, MI, ModifierOpNames, Name, and llvm::reverse().
Referenced by foldImmediate().
◆ restoreExec()
| void SIInstrInfo::restoreExec | ( | MachineFunction & | MF, |
| MachineBasicBlock & | MBB, | ||
| MachineBasicBlock::iterator | MBBI, | ||
| const DebugLoc & | DL, | ||
| Register | Reg, | ||
| SlotIndexes * | Indexes = nullptr |
||
| ) | const |
Definition at line 5632 of file SIInstrInfo.cpp.
References llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), DL, llvm::get(), llvm::SlotIndexes::insertMachineInstrInMaps(), isWave32(), llvm::RegState::Kill, MBB, and MBBI.
◆ reverseBranchCondition()
|
override |
Definition at line 3191 of file SIInstrInfo.cpp.
◆ shouldClusterMemOps()
|
override |
Definition at line 549 of file SIInstrInfo.cpp.
References llvm::DefaultMemoryClusterDWordsLimit, llvm::ArrayRef< T >::empty(), llvm::ArrayRef< T >::front(), llvm::MachineFunction::getInfo(), llvm::SIMachineFunctionInfo::getMaxMemoryClusterDWords(), llvm::MachineInstr::getMF(), and memOpsHaveSameBasePtr().
◆ shouldScheduleLoadsNear()
|
override |
Definition at line 601 of file SIInstrInfo.cpp.
References assert().
◆ sopkIsZext()
Definition at line 871 of file SIInstrInfo.h.
Referenced by verifyInstruction().
◆ splitFlatOffset()
| std::pair< int64_t, int64_t > SIInstrInfo::splitFlatOffset | ( | int64_t | COffsetVal, |
| unsigned | AddrSpace, | ||
| uint64_t | FlatVariant | ||
| ) | const |
Split COffsetVal into {immediate offset field, remainder offset} values.
Definition at line 9219 of file SIInstrInfo.cpp.
References allowNegativeFlatOffset(), assert(), D, llvm::SIInstrFlags::FlatScratch, llvm::AMDGPU::getNumFlatOffsetBits(), llvm::GCNSubtarget::hasNegativeUnalignedScratchOffsetBug(), and isLegalFLATOffset().
◆ splitMUBUFOffset()
| bool SIInstrInfo::splitMUBUFOffset | ( | uint32_t | Imm, |
| uint32_t & | SOffset, | ||
| uint32_t & | ImmOffset, | ||
| Align | Alignment = Align(4) |
||
| ) | const |
Definition at line 9119 of file SIInstrInfo.cpp.
References llvm::alignDown(), llvm::GCNSubtarget::getGeneration(), getMaxMUBUFImmOffset(), llvm::GCNSubtarget::hasRestrictedSOffset(), High, llvm::Low, llvm::AMDGPUSubtarget::SEA_ISLANDS, and llvm::Align::value().
Referenced by llvm::AMDGPURegisterBankInfo::setBufferOffsets().
◆ storeRegToStackSlot()
|
override |
Definition at line 1724 of file SIInstrInfo.cpp.
References llvm::MachineInstrBuilder::addFrameIndex(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMemOperand(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), DL, llvm::MachineBasicBlock::findDebugLoc(), llvm::get(), llvm::MachinePointerInfo::getFixedStack(), llvm::MachineFunction::getFrameInfo(), llvm::MachineFunction::getInfo(), llvm::getKillRegState(), llvm::MachineFunction::getMachineMemOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), getSGPRSpillSaveOpcode(), llvm::SIMachineFunctionInfo::getStackPtrOffsetReg(), getVectorRegSpillSaveOpcode(), llvm::RegState::Implicit, llvm::SIRegisterInfo::isSGPRClass(), llvm::Register::isVirtual(), MBB, MI, llvm::MachineMemOperand::MOStore, MRI, llvm::SIMachineFunctionInfo::setHasSpilledSGPRs(), llvm::SIMachineFunctionInfo::setHasSpilledVGPRs(), llvm::TargetStackID::SGPRSpill, llvm::SIRegisterInfo::spillSGPRToVGPR(), and TRI.
◆ swapSourceModifiers()
|
protected |
Definition at line 2702 of file SIInstrInfo.cpp.
References assert(), llvm::MachineOperand::getImm(), getNamedOperand(), MI, and llvm::MachineOperand::setImm().
Referenced by commuteInstructionImpl().
◆ usesConstantBus() [1/2]
|
inline |
Definition at line 1129 of file SIInstrInfo.h.
References MI, MRI, and usesConstantBus().
◆ usesConstantBus() [2/2]
| bool SIInstrInfo::usesConstantBus | ( | const MachineRegisterInfo & | MRI, |
| const MachineOperand & | MO, | ||
| const MCOperandInfo & | OpInfo | ||
| ) | const |
Returns true if this operand uses the constant bus.
Definition at line 4569 of file SIInstrInfo.cpp.
References llvm::MachineOperand::getReg(), llvm::MachineOperand::isImplicit(), isInlineConstant(), llvm::MachineOperand::isReg(), llvm::SIRegisterInfo::isSGPRClass(), llvm::MachineOperand::isUse(), llvm::Register::isVirtual(), and MRI.
Referenced by isOperandLegal(), usesConstantBus(), and verifyInstruction().
◆ usesFPDPRounding() [1/2]
|
inlinestatic |
Definition at line 916 of file SIInstrInfo.h.
References llvm::SIInstrFlags::FPDPRounding, and MI.
◆ usesFPDPRounding() [2/2]
Definition at line 920 of file SIInstrInfo.h.
References llvm::SIInstrFlags::FPDPRounding, and llvm::get().
◆ usesLGKM_CNT()
|
inlinestatic |
Definition at line 865 of file SIInstrInfo.h.
References llvm::SIInstrFlags::LGKM_CNT, and MI.
◆ usesVM_CNT()
|
inlinestatic |
Definition at line 861 of file SIInstrInfo.h.
References MI, and llvm::SIInstrFlags::VM_CNT.
◆ verifyInstruction()
|
override |
Definition at line 4667 of file SIInstrInfo.cpp.
References llvm::SISrcMods::ABS, llvm::all_of(), assert(), compareMachineOp(), llvm::TargetRegisterClass::contains(), llvm::Data, llvm::dbgs(), llvm::divideCeil(), findImplicitSGPRRead(), llvm::get(), llvm::AMDGPU::getAddrSizeMIMGOp(), llvm::AMDGPU::getBasicFromSDWAOp(), llvm::SIRegisterInfo::getChannelFromSubReg(), llvm::SIRegisterInfo::getCompatibleSubRegClass(), llvm::GCNSubtarget::getConstantBusLimit(), llvm::GCNSubtarget::getGeneration(), llvm::SIRegisterInfo::getHWRegIndex(), llvm::MachineOperand::getImm(), llvm::AMDGPU::getMIMGBaseOpcodeInfo(), llvm::AMDGPU::getMIMGDimInfoByEncoding(), llvm::AMDGPU::getMIMGInfo(), getNamedOperand(), llvm::AMDGPU::getNamedOperandIdx(), llvm::GCNSubtarget::getNSAMaxSize(), getOpRegClass(), getOpSize(), llvm::SrcOp::getReg(), llvm::MachineOperand::getReg(), llvm::SIRegisterInfo::getRegClass(), llvm::SIRegisterInfo::getRegClassForReg(), llvm::MachineFunction::getRegInfo(), llvm::MachineOperand::getSubReg(), llvm::AMDGPUSubtarget::GFX10, llvm::GCNSubtarget::hasA16(), llvm::GCNSubtarget::hasFlatInstOffsets(), llvm::GCNSubtarget::hasG16(), llvm::GCNSubtarget::hasGDS(), llvm::GCNSubtarget::hasGFX90AInsts(), llvm::GCNSubtarget::hasPartialNSAEncoding(), llvm::GCNSubtarget::hasR128A16(), llvm::AMDGPUSubtarget::hasSDWA(), llvm::GCNSubtarget::hasSDWAOmod(), llvm::GCNSubtarget::hasSDWAOutModsVOPC(), llvm::GCNSubtarget::hasSDWAScalar(), llvm::GCNSubtarget::hasSDWASdst(), llvm::GCNSubtarget::hasUnpackedD16VMem(), llvm::SIRegisterInfo::hasVectorRegisters(), llvm::SIRegisterInfo::hasVGPRs(), llvm::GCNSubtarget::hasVOP3Literal(), I, Info, llvm::is_contained(), llvm::SIRegisterInfo::isAGPR(), llvm::AMDGPU::isDPALU_DPP(), isDS(), llvm::MachineOperand::isFI(), isFLAT(), llvm::MachineOperand::isFPImm(), isGather4(), llvm::MachineOperand::isIdenticalTo(), isImage(), llvm::MachineOperand::isImm(), llvm::MachineOperand::isImplicit(), isInlineConstant(), llvm::AMDGPU::isLegalDPALU_DPPControl(), isMIMG(), llvm::Register::isPhysical(), llvm::SIRegisterInfo::isProperlyAlignedRC(), llvm::MachineOperand::isReg(), isRegOrFI(), isSDWA(), llvm::SIRegisterInfo::isSGPRReg(), isSMRD(), isSOP2(), isSOPC(), isSOPK(), isSubRegOf(), llvm::MachineOperand::isUse(), isVALU(), isVGPRSpill(), llvm::Register::isVirtual(), isVOP2(), isVOP3(), isVOPC(), isVSAMPLE(), LLVM_DEBUG, MI, llvm::InlineAsm::MIOp_FirstOperand, MRI, llvm::GCNSubtarget::needsAlignedVGPRs(), llvm::SISrcMods::NEG, llvm::Offset, llvm::MCOI::OPERAND_IMMEDIATE, llvm::AMDGPU::OPERAND_INLINE_SPLIT_BARRIER_INT32, llvm::AMDGPU::OPERAND_KIMM32, llvm::AMDGPU::OPERAND_REG_IMM_FP32, llvm::AMDGPU::OPERAND_REG_IMM_FP32_DEFERRED, llvm::AMDGPU::OPERAND_REG_IMM_INT32, llvm::AMDGPU::OPERAND_REG_IMM_V2FP32, llvm::AMDGPU::OPERAND_REG_INLINE_AC_FP16, llvm::AMDGPU::OPERAND_REG_INLINE_AC_FP32, llvm::AMDGPU::OPERAND_REG_INLINE_AC_FP64, llvm::AMDGPU::OPERAND_REG_INLINE_AC_INT16, llvm::AMDGPU::OPERAND_REG_INLINE_AC_INT32, llvm::AMDGPU::OPERAND_REG_INLINE_C_FP16, llvm::AMDGPU::OPERAND_REG_INLINE_C_FP32, llvm::AMDGPU::OPERAND_REG_INLINE_C_FP64, llvm::AMDGPU::OPERAND_REG_INLINE_C_INT16, llvm::AMDGPU::OPERAND_REG_INLINE_C_INT32, llvm::AMDGPU::OPERAND_REG_INLINE_C_INT64, llvm::MCOI::OPERAND_REGISTER, llvm::popcount(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::SISrcMods::SEXT, shouldReadExec(), sopkIsZext(), llvm::AMDGPU::SDWA::UNUSED_PRESERVE, usesConstantBus(), and llvm::AMDGPUSubtarget::VOLCANIC_ISLANDS.
Referenced by llvm::AMDGPUAsmPrinter::emitInstruction().
The documentation for this class was generated from the following files:
- lib/Target/AMDGPU/SIInstrInfo.h
- lib/Target/AMDGPU/SIInstrInfo.cpp
