#include "Target/AMDGPU/SIInstrInfo.h"
Classes | |
| struct | ThreeAddressUpdates |
| Helper struct for the implementation of 3-address conversion to communicate updates made to instruction operands. More... | |
Public Types | |
| enum | TargetOperandFlags { MO_MASK = 0xf , MO_NONE = 0 , MO_GOTPCREL = 1 , MO_GOTPCREL32 = 2 , MO_GOTPCREL32_LO = 2 , MO_GOTPCREL32_HI = 3 , MO_GOTPCREL64 = 4 , MO_REL32 = 5 , MO_REL32_LO = 5 , MO_REL32_HI = 6 , MO_REL64 = 7 , MO_FAR_BRANCH_OFFSET = 8 , MO_ABS32_LO = 9 , MO_ABS32_HI = 10 , MO_ABS64 = 11 } |
Protected Member Functions | |
| std::optional< DestSourcePair > | isCopyInstrImpl (const MachineInstr &MI) const override |
| If the specific machine instruction is a instruction that moves/copies value from one register to another register return destination and source registers as machine operands. | |
| bool | swapSourceModifiers (MachineInstr &MI, MachineOperand &Src0, AMDGPU::OpName Src0OpName, MachineOperand &Src1, AMDGPU::OpName Src1OpName) const |
| bool | isLegalToSwap (const MachineInstr &MI, unsigned fromIdx, unsigned toIdx) const |
| MachineInstr * | commuteInstructionImpl (MachineInstr &MI, bool NewMI, unsigned OpIdx0, unsigned OpIdx1) const override |
Detailed Description
Definition at line 90 of file SIInstrInfo.h.
Member Enumeration Documentation
◆ TargetOperandFlags
| Enumerator | |
|---|---|
| MO_MASK | |
| MO_NONE | |
| MO_GOTPCREL | |
| MO_GOTPCREL32 | |
| MO_GOTPCREL32_LO | |
| MO_GOTPCREL32_HI | |
| MO_GOTPCREL64 | |
| MO_REL32 | |
| MO_REL32_LO | |
| MO_REL32_HI | |
| MO_REL64 | |
| MO_FAR_BRANCH_OFFSET | |
| MO_ABS32_LO | |
| MO_ABS32_HI | |
| MO_ABS64 | |
Definition at line 222 of file SIInstrInfo.h.
Constructor & Destructor Documentation
◆ SIInstrInfo()
|
explicit |
Definition at line 65 of file SIInstrInfo.cpp.
Referenced by insertScratchExecCopy().
Member Function Documentation
◆ allowNegativeFlatOffset()
Returns true if negative offsets are allowed for the given FlatVariant.
Definition at line 10220 of file SIInstrInfo.cpp.
References llvm::SIInstrFlags::FLAT, llvm::SIInstrFlags::FlatScratch, and llvm::AMDGPU::isGFX12Plus().
Referenced by isLegalFLATOffset(), and splitFlatOffset().
◆ analyzeBranch()
|
override |
Definition at line 3150 of file SIInstrInfo.cpp.
References analyzeBranchImpl(), Cond, I, llvm_unreachable, MBB, and TBB.
◆ analyzeBranchImpl()
| bool SIInstrInfo::analyzeBranchImpl | ( | MachineBasicBlock & | MBB, |
| MachineBasicBlock::iterator | I, | ||
| MachineBasicBlock *& | TBB, | ||
| MachineBasicBlock *& | FBB, | ||
| SmallVectorImpl< MachineOperand > & | Cond, | ||
| bool | AllowModify ) const |
Definition at line 3113 of file SIInstrInfo.cpp.
References Cond, llvm::MachineOperand::CreateImm(), I, MBB, and TBB.
Referenced by analyzeBranch().
◆ analyzeCompare()
|
override |
Definition at line 10822 of file SIInstrInfo.cpp.
◆ areLoadsFromSameBasePtr()
|
override |
Definition at line 239 of file SIInstrInfo.cpp.
References AbstractManglingParser< Derived, Alloc >::NumOps, assert(), llvm::dyn_cast(), llvm::get(), llvm::SDNode::getAsZExtVal(), llvm::SDNode::getConstantOperandVal(), llvm::SDNode::getMachineOpcode(), getNumOperandsNoGlue(), llvm::SDNode::getOperand(), llvm::ConstantSDNode::getZExtValue(), llvm::AMDGPU::hasNamedOperand(), llvm::isa(), isDS(), llvm::SDNode::isMachineOpcode(), isMTBUF(), isMUBUF(), isSMRD(), and nodesHaveSameOperandValue().
◆ areMemAccessesTriviallyDisjoint()
|
override |
Definition at line 4004 of file SIInstrInfo.cpp.
References assert(), llvm::MachineInstr::hasOrderedMemoryRef(), llvm::MachineInstr::hasUnmodeledSideEffects(), llvm::MachineInstr::isBundle(), isDS(), isFLAT(), isFLATGlobal(), isFLATScratch(), isLDSDMA(), isMTBUF(), isMUBUF(), isSegmentSpecificFLAT(), isSMRD(), and llvm::MachineInstr::mayLoadOrStore().
◆ buildExtractSubReg()
| unsigned SIInstrInfo::buildExtractSubReg | ( | MachineBasicBlock::iterator | MI, |
| MachineRegisterInfo & | MRI, | ||
| const MachineOperand & | SuperReg, | ||
| const TargetRegisterClass * | SuperRC, | ||
| unsigned | SubIdx, | ||
| const TargetRegisterClass * | SubRC ) const |
Definition at line 6231 of file SIInstrInfo.cpp.
References llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), DL, llvm::get(), llvm::MachineOperand::getReg(), llvm::MachineOperand::getSubReg(), llvm::Register::isVirtual(), MBB, MI, MRI, and SubReg.
Referenced by buildExtractSubRegOrImm().
◆ buildExtractSubRegOrImm()
| MachineOperand SIInstrInfo::buildExtractSubRegOrImm | ( | MachineBasicBlock::iterator | MI, |
| MachineRegisterInfo & | MRI, | ||
| const MachineOperand & | SuperReg, | ||
| const TargetRegisterClass * | SuperRC, | ||
| unsigned | SubIdx, | ||
| const TargetRegisterClass * | SubRC ) const |
Definition at line 6248 of file SIInstrInfo.cpp.
References buildExtractSubReg(), llvm::MachineOperand::CreateImm(), llvm::MachineOperand::CreateReg(), llvm_unreachable, MRI, and SubReg.
◆ buildShrunkInst()
| MachineInstr * SIInstrInfo::buildShrunkInst | ( | MachineInstr & | MI, |
| unsigned | NewOpcode ) const |
Definition at line 4948 of file SIInstrInfo.cpp.
References llvm::MachineInstrBuilder::add(), llvm::BuildMI(), copyFlagsToImplicitVCC(), fixImplicitOperands(), llvm::get(), getNamedOperand(), llvm::MCInstrDesc::getNumDefs(), I, MBB, MI, llvm::MCOI::OPERAND_IMMEDIATE, llvm::AMDGPU::OPERAND_INPUT_MODS, and llvm::MachineInstrBuilder::setMIFlags().
◆ canAddToBBProlog()
| bool SIInstrInfo::canAddToBBProlog | ( | const MachineInstr & | MI | ) | const |
Definition at line 9940 of file SIInstrInfo.cpp.
References llvm::MachineFunction::getInfo(), llvm::MachineFunction::getRegInfo(), isSGPRSpill(), llvm::SIMachineFunctionInfo::isWWMReg(), isWWMRegSpillOpcode(), llvm::MachineInstr::LRSplit, MI, and MRI.
Referenced by isBasicBlockPrologue().
◆ canInsertSelect()
|
override |
Definition at line 3287 of file SIInstrInfo.cpp.
References Cond, llvm::getImm(), llvm::AMDGPU::getRegBitWidth(), MBB, and MRI.
◆ canShrink()
| bool SIInstrInfo::canShrink | ( | const MachineInstr & | MI, |
| const MachineRegisterInfo & | MRI ) const |
Definition at line 4872 of file SIInstrInfo.cpp.
References getNamedOperand(), llvm::MachineOperand::getReg(), hasModifiersSet(), hasVALU32BitEncoding(), llvm::MachineOperand::isReg(), MI, and MRI.
◆ commuteInstructionImpl()
|
overrideprotected |
Definition at line 2820 of file SIInstrInfo.cpp.
References assert(), llvm::TargetInstrInfo::commuteInstructionImpl(), commuteOpcode(), llvm::get(), llvm::MachineOperand::isImm(), isLegalToSwap(), llvm::MachineOperand::isReg(), MI, Opc, llvm::MachineInstr::setDesc(), std::swap(), swapImmOperands(), swapRegAndNonRegOperand(), and swapSourceModifiers().
◆ commuteOpcode() [1/2]
|
inline |
Definition at line 355 of file SIInstrInfo.h.
References commuteOpcode(), and MI.
◆ commuteOpcode() [2/2]
| int SIInstrInfo::commuteOpcode | ( | unsigned | Opc | ) | const |
Definition at line 1157 of file SIInstrInfo.cpp.
References llvm::AMDGPU::getCommuteOrig(), llvm::AMDGPU::getCommuteRev(), and pseudoToMCOpcode().
Referenced by commuteInstructionImpl(), commuteOpcode(), and legalizeOperandsVOP2().
◆ convertToThreeAddress()
|
override |
Definition at line 4147 of file SIInstrInfo.cpp.
References llvm::LiveVariables::VarInfo::AliveBlocks, llvm::AnalyzeVirtRegInBundle(), assert(), llvm::SparseBitVector< ElementSize >::clear(), llvm::MachineOperand::CreateReg(), llvm::MachineInstr::eraseFromBundle(), llvm::get(), llvm::LiveIntervals::getInstructionIndex(), llvm::LiveIntervals::getInterval(), llvm::MachineInstr::getOperand(), llvm::SlotIndex::getRegSlot(), llvm::LiveVariables::getVarInfo(), llvm::LiveIntervals::hasInterval(), I, MBB, MI, MRI, llvm::VirtRegInfo::Reads, llvm::LiveIntervals::ReplaceMachineInstrInMaps(), llvm::LiveIntervals::shrinkToUses(), updateLiveVariables(), and llvm::VirtRegInfo::Writes.
◆ copyPhysReg()
|
override |
Definition at line 815 of file SIInstrInfo.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), contains(), copyPhysReg(), llvm::RegState::Define, DL, expandSGPRCopy(), Fix16BitCopies, llvm::get(), llvm::getKillRegState(), llvm::RegState::Implicit, indirectCopyToAGPR(), llvm::AMDGPU::isHi16Reg(), MBB, MI, llvm::SISrcMods::OP_SEL_0, llvm::SISrcMods::OP_SEL_1, Opc, Register, reportIllegalCopy(), Size, llvm::ArrayRef< T >::size(), SubReg, llvm::MachineInstr::tieOperands(), llvm::RegState::Undef, llvm::AMDGPU::SDWA::UNUSED_PRESERVE, llvm::AMDGPU::SDWA::WORD_0, and llvm::AMDGPU::SDWA::WORD_1.
Referenced by copyPhysReg().
◆ createPHIDestinationCopy()
|
override |
Definition at line 10538 of file SIInstrInfo.cpp.
References llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::TargetInstrInfo::createPHIDestinationCopy(), DL, llvm::get(), and MBB.
◆ createPHISourceCopy()
|
override |
Definition at line 10553 of file SIInstrInfo.cpp.
References llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::TargetInstrInfo::createPHISourceCopy(), DL, llvm::AMDGPU::LaneMaskConstants::get(), llvm::get(), llvm::RegState::Implicit, and MBB.
◆ CreateTargetMIHazardRecognizer()
|
override |
Definition at line 9884 of file SIInstrInfo.cpp.
References llvm::TargetInstrInfo::CreateTargetMIHazardRecognizer(), llvm::ScheduleDAGMI::hasVRegLiveness(), II, and llvm::ScheduleDAG::MF.
◆ CreateTargetPostRAHazardRecognizer() [1/2]
|
override |
This is used by the post-RA scheduler (SchedulePostRAList.cpp).
The post-RA version of misched uses CreateTargetMIHazardRecognizer.
Definition at line 9869 of file SIInstrInfo.cpp.
References II, and llvm::ScheduleDAG::MF.
◆ CreateTargetPostRAHazardRecognizer() [2/2]
|
override |
This is the hazard recognizer used at -O0 by the PostRAHazardRecognizer pass.
Definition at line 9877 of file SIInstrInfo.cpp.
◆ decomposeMachineOperandsTargetFlags()
|
override |
Definition at line 9896 of file SIInstrInfo.cpp.
References MO_MASK.
◆ doesNotReadTiedSource() [1/2]
|
inlinestatic |
Definition at line 1129 of file SIInstrInfo.h.
References MI, and llvm::SIInstrFlags::TiedSourceNotRead.
◆ doesNotReadTiedSource() [2/2]
Definition at line 1133 of file SIInstrInfo.h.
References llvm::get(), and llvm::SIInstrFlags::TiedSourceNotRead.
◆ enforceOperandRCAlignment()
| void SIInstrInfo::enforceOperandRCAlignment | ( | MachineInstr & | MI, |
| AMDGPU::OpName | OpName ) const |
Definition at line 11181 of file SIInstrInfo.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::MachineOperand::CreateReg(), DL, llvm::get(), getOpSize(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), MI, and MRI.
◆ expandMovDPP64()
| std::pair< MachineInstr *, MachineInstr * > SIInstrInfo::expandMovDPP64 | ( | MachineInstr & | MI | ) | const |
Definition at line 2643 of file SIInstrInfo.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), DL, llvm::drop_begin(), llvm::get(), llvm::getImm(), llvm::SrcOp::getImm(), getNamedOperand(), getReg(), llvm::SrcOp::getReg(), llvm::MachineFunction::getRegInfo(), I, llvm::AMDGPU::isLegalDPALU_DPPControl(), MBB, MI, MRI, llvm::Sub, and llvm::RegState::Undef.
Referenced by expandPostRAPseudo().
◆ expandPostRAPseudo()
|
override |
Definition at line 2050 of file SIInstrInfo.cpp.
References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addDef(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::MIBundleBuilder::append(), assert(), llvm::MIBundleBuilder::begin(), llvm::BuildMI(), llvm::MachineInstrBuilder::copyImplicitOps(), llvm::MachineOperand::CreateImm(), llvm::RegState::Define, DL, llvm::AMDGPU::VGPRIndexMode::DST_ENABLE, llvm::AMDGPU::LaneMaskConstants::ExecReg, expandMovDPP64(), llvm::TargetInstrInfo::expandPostRAPseudo(), llvm::finalizeBundle(), llvm::AMDGPU::LaneMaskConstants::get(), llvm::get(), llvm::SrcOp::getImm(), llvm::ilist_node_impl< OptionsT >::getIterator(), getNamedOperand(), llvm::MCInstrDesc::getNumOperands(), llvm::MachineOperand::getOffset(), llvm::MachineInstr::getOperand(), getOpRegClass(), llvm::SrcOp::getReg(), llvm::MachineFunction::getSubtarget(), llvm::Hi, llvm::RegState::Implicit, llvm::MCInstrDesc::implicit_uses(), llvm::RegState::ImplicitDefine, llvm::SIRegisterInfo::isAGPRClass(), llvm::MachineOperand::isGlobal(), isInlineConstant(), llvm::isUInt(), llvm::Lo, MBB, MI, llvm::AMDGPU::LaneMaskConstants::MovOpc, llvm::SISrcMods::OP_SEL_0, llvm::SISrcMods::OP_SEL_1, Opc, llvm::AMDGPU::LaneMaskConstants::OrSaveExecOpc, llvm::MachineOperand::setIsUndef(), llvm::MachineOperand::setOffset(), llvm::SignExtend64(), llvm::AMDGPU::VGPRIndexMode::SRC0_ENABLE, SubReg, llvm::MachineInstr::tieOperands(), TRI, llvm::RegState::Undef, and llvm::AMDGPU::LaneMaskConstants::WQMOpc.
◆ extractSubregFromImm()
|
static |
Return the extracted immediate value in a subregister use from a constant materialized in a super register.
e.g. imm = S_MOV_B64 K[0:63] USE imm.sub1 This will return K[32:63]
Definition at line 3516 of file SIInstrInfo.cpp.
References llvm_unreachable, and llvm::SignExtend64().
Referenced by foldImmediate().
◆ findCommutedOpIndices() [1/2]
|
override |
Definition at line 2876 of file SIInstrInfo.cpp.
References findCommutedOpIndices(), and MI.
Referenced by findCommutedOpIndices().
◆ findCommutedOpIndices() [2/2]
| bool SIInstrInfo::findCommutedOpIndices | ( | const MCInstrDesc & | Desc, |
| unsigned & | SrcOpIdx0, | ||
| unsigned & | SrcOpIdx1 ) const |
Definition at line 2882 of file SIInstrInfo.cpp.
References Opc.
◆ fixImplicitOperands()
| void SIInstrInfo::fixImplicitOperands | ( | MachineInstr & | MI | ) | const |
Definition at line 10056 of file SIInstrInfo.cpp.
References MI.
Referenced by buildShrunkInst(), insertBranch(), insertSelect(), legalizeOperandsVOP2(), and moveToVALUImpl().
◆ foldImmediate()
|
final |
Definition at line 3608 of file SIInstrInfo.cpp.
References llvm::MachineInstrBuilder::addReg(), llvm::Register::asMCReg(), assert(), llvm::BuildMI(), llvm::MachineOperand::ChangeToImmediate(), llvm::TargetRegisterClass::contains(), DefMI, extractSubregFromImm(), llvm::get(), getConstValDefinedInReg(), getNamedOperand(), getNewFMAAKInst(), getNewFMAMKInst(), llvm::MachineOperand::getReg(), getRegClass(), llvm::MachineOperand::getSubReg(), hasAnyModifiersSet(), isInlineConstant(), llvm::MachineOperand::isKill(), llvm::Register::isPhysical(), llvm::MachineOperand::isReg(), llvm::Register::isVirtual(), llvm::RegState::Kill, legalizeOperands(), MRI, Opc, llvm::AMDGPU::OPERAND_REG_IMM_INT32, llvm::MCInstrDesc::operands(), pseudoToMCOpcode(), removeModOperands(), llvm::MachineOperand::setIsKill(), llvm::MachineOperand::setReg(), llvm::MachineOperand::setSubReg(), and UseMI.
Referenced by legalizeGenericOperand().
◆ foldMemoryOperandImpl()
|
override |
Definition at line 10573 of file SIInstrInfo.cpp.
References AbstractManglingParser< Derived, Alloc >::Ops, llvm::MachineFunction::getRegInfo(), llvm::TargetRegisterClass::hasSuperClassEq(), llvm::Register::isVirtual(), MI, and MRI.
◆ getAddNoCarry() [1/2]
| MachineInstrBuilder SIInstrInfo::getAddNoCarry | ( | MachineBasicBlock & | MBB, |
| MachineBasicBlock::iterator | I, | ||
| const DebugLoc & | DL, | ||
| Register | DestReg ) const |
Return a partially built integer add instruction without carry.
Caller must add source operands. For pre-GFX9 it will generate unused carry destination operand. TODO: After GFX9 it should return a no-carry operation.
Definition at line 9986 of file SIInstrInfo.cpp.
References llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::RegState::Dead, llvm::RegState::Define, DL, llvm::get(), I, MBB, and MRI.
◆ getAddNoCarry() [2/2]
| MachineInstrBuilder SIInstrInfo::getAddNoCarry | ( | MachineBasicBlock & | MBB, |
| MachineBasicBlock::iterator | I, | ||
| const DebugLoc & | DL, | ||
| Register | DestReg, | ||
| RegScavenger & | RS ) const |
Definition at line 10001 of file SIInstrInfo.cpp.
References llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::RegState::Dead, llvm::RegState::Define, DL, llvm::get(), I, llvm::Register::isValid(), MBB, and Register.
◆ getBranchDestBlock()
|
override |
Definition at line 2917 of file SIInstrInfo.cpp.
References MI.
◆ getCalleeOperand()
|
override |
Definition at line 10629 of file SIInstrInfo.cpp.
References llvm::TargetInstrInfo::getCalleeOperand(), getNamedOperand(), and MI.
◆ getClampMask()
|
inline |
Definition at line 1068 of file SIInstrInfo.h.
References llvm::SIInstrFlags::ClampHi, llvm::SIInstrFlags::ClampLo, llvm::SIInstrFlags::FPClamp, llvm::SIInstrFlags::IntClamp, and MI.
◆ getConstValDefinedInReg()
|
override |
Definition at line 1316 of file SIInstrInfo.cpp.
References llvm::MachineOperand::getImm(), llvm::MachineOperand::isImm(), MI, and llvm::reverseBits().
Referenced by foldImmediate().
◆ getDefaultRsrcDataFormat()
| uint64_t SIInstrInfo::getDefaultRsrcDataFormat | ( | ) | const |
Definition at line 9627 of file SIInstrInfo.cpp.
References llvm::Format, llvm::AMDGPUSubtarget::GFX10, llvm::AMDGPUSubtarget::GFX11, llvm::AMDGPU::RSRC_DATA_FORMAT, llvm::AMDGPU::UfmtGFX10::UFMT_32_FLOAT, llvm::AMDGPU::UfmtGFX11::UFMT_32_FLOAT, and llvm::AMDGPUSubtarget::VOLCANIC_ISLANDS.
Referenced by getScratchRsrcWords23().
◆ getDSShaderTypeValue()
|
static |
Definition at line 10796 of file SIInstrInfo.cpp.
References llvm::CallingConv::AMDGPU_CS, llvm::CallingConv::AMDGPU_ES, llvm::CallingConv::AMDGPU_GS, llvm::CallingConv::AMDGPU_HS, llvm::CallingConv::AMDGPU_KERNEL, llvm::CallingConv::AMDGPU_LS, llvm::CallingConv::AMDGPU_PS, llvm::CallingConv::AMDGPU_VS, llvm::CallingConv::C, F, llvm::CallingConv::Fast, llvm::Function::getCallingConv(), and llvm::MachineFunction::getFunction().
◆ getFoldableCopySrcIdx()
|
static |
Definition at line 3461 of file SIInstrInfo.cpp.
References llvm_unreachable, and MI.
◆ getGenericInstructionUniformity()
| InstructionUniformity SIInstrInfo::getGenericInstructionUniformity | ( | const MachineInstr & | MI | ) | const |
Definition at line 10637 of file SIInstrInfo.cpp.
References llvm::AlwaysUniform, llvm::any_of(), llvm::Default, llvm::dyn_cast(), llvm::AMDGPUAS::FLAT_ADDRESS, llvm::LLT::getAddressSpace(), llvm::isa(), llvm::AMDGPU::isGenericAtomic(), llvm::AMDGPU::isIntrinsicAlwaysUniform(), llvm::AMDGPU::isIntrinsicSourceOfDivergence(), MI, MRI, llvm::NeverUniform, and llvm::AMDGPUAS::PRIVATE_ADDRESS.
Referenced by getInstructionUniformity().
◆ getIndirectGPRIDXPseudo()
| const MCInstrDesc & SIInstrInfo::getIndirectGPRIDXPseudo | ( | unsigned | VecSize, |
| bool | IsIndirectSrc ) const |
Definition at line 1394 of file SIInstrInfo.cpp.
References llvm::get(), and llvm_unreachable.
◆ getIndirectRegWriteMovRelPseudo()
| const MCInstrDesc & SIInstrInfo::getIndirectRegWriteMovRelPseudo | ( | unsigned | VecSize, |
| unsigned | EltSize, | ||
| bool | IsSGPR ) const |
Definition at line 1543 of file SIInstrInfo.cpp.
References assert(), llvm::get(), getIndirectSGPRWriteMovRelPseudo32(), getIndirectSGPRWriteMovRelPseudo64(), getIndirectVGPRWriteMovRelPseudoOpc(), and llvm_unreachable.
◆ getInstBundleSize()
| unsigned SIInstrInfo::getInstBundleSize | ( | const MachineInstr & | MI | ) | const |
Definition at line 9736 of file SIInstrInfo.cpp.
References assert(), getInstSizeInBytes(), I, MI, and Size.
Referenced by getInstSizeInBytes().
◆ getInstrLatency()
|
override |
Definition at line 10611 of file SIInstrInfo.cpp.
References llvm::Count, E(), I, and MI.
◆ getInstructionUniformity()
|
final |
Definition at line 10712 of file SIInstrInfo.cpp.
References llvm::AlwaysUniform, llvm::any_of(), llvm::Default, getGenericInstructionUniformity(), llvm::RegisterBank::getID(), llvm::MachineOperand::getReg(), llvm::SrcOp::getReg(), llvm::RegisterBankInfo::getRegBank(), I, isAtomic(), isFLAT(), isNeverUniform(), llvm::Register::isPhysical(), llvm::MachineOperand::isReg(), MI, MRI, and llvm::NeverUniform.
◆ getInstSizeInBytes()
|
override |
Definition at line 9748 of file SIInstrInfo.cpp.
References getInstBundleSize(), llvm::TargetMachine::getMCAsmInfo(), getMCOpcodeFromPseudo(), llvm::MachineFunction::getTarget(), I, isDPP(), isFixedSize(), isInlineConstant(), isMIMG(), isSALU(), llvm::AMDGPU::isValid32BitLiteral(), isVALU(), MI, Opc, llvm::AMDGPU::OPERAND_REG_IMM_FP64, llvm::AMDGPU::OPERAND_REG_IMM_INT64, and Size.
Referenced by llvm::AMDGPUAsmPrinter::emitInstruction(), getInstBundleSize(), and removeBranch().
◆ getKillTerminatorFromPseudo()
| const MCInstrDesc & SIInstrInfo::getKillTerminatorFromPseudo | ( | unsigned | Opcode | ) | const |
Definition at line 10034 of file SIInstrInfo.cpp.
References llvm::get(), and llvm_unreachable.
◆ getLiveRangeSplitOpcode()
|
override |
Definition at line 9930 of file SIInstrInfo.cpp.
References assert(), llvm::SIMachineFunctionInfo::checkFlag(), llvm::MachineFunction::getInfo(), llvm::Register::isVirtual(), and llvm::AMDGPU::VirtRegFlag::WWM_REG.
◆ getMachineCSELookAheadLimit()
|
inlineoverride |
Definition at line 449 of file SIInstrInfo.h.
◆ getMaxMUBUFImmOffset()
|
static |
Definition at line 10049 of file SIInstrInfo.cpp.
References llvm::AMDGPUSubtarget::GFX12.
Referenced by isLegalMUBUFImmOffset(), llvm::AMDGPULegalizerInfo::splitBufferOffsets(), llvm::AMDGPURegisterBankInfo::splitBufferOffsets(), and splitMUBUFOffset().
◆ getMCOpcodeFromPseudo()
|
inline |
Return the descriptor of the target-specific machine instruction that corresponds to the specified pseudo or native opcode.
Definition at line 1542 of file SIInstrInfo.h.
References llvm::get(), and pseudoToMCOpcode().
Referenced by getInstSizeInBytes().
◆ getMemOperandsWithOffsetWidth()
|
final |
Definition at line 365 of file SIInstrInfo.cpp.
References assert(), llvm::TypeSize::getFixed(), llvm::MachineOperand::getImm(), getNamedOperand(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), getOpRegClass(), getOpSize(), llvm::LocationSize::getValue(), I, isDS(), llvm::MachineOperand::isFI(), isFLAT(), isImage(), isMIMG(), isMTBUF(), isMUBUF(), llvm::MachineOperand::isReg(), isSMRD(), isStride64(), llvm::MachineInstr::mayLoad(), llvm::MachineInstr::mayLoadOrStore(), llvm::MachineInstr::mayStore(), llvm::Offset, Opc, llvm::LocationSize::precise(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), and TRI.
◆ getMIRFormatter()
|
inlineoverride |
Definition at line 1672 of file SIInstrInfo.h.
◆ getMovOpcode()
| unsigned SIInstrInfo::getMovOpcode | ( | const TargetRegisterClass * | DstRC | ) | const |
Definition at line 1375 of file SIInstrInfo.cpp.
◆ getNamedImmOperand()
|
inline |
Get required immediate operand.
Definition at line 1528 of file SIInstrInfo.h.
References MI.
Referenced by legalizeOperands().
◆ getNamedOperand() [1/2]
|
inline |
Definition at line 1522 of file SIInstrInfo.h.
References getNamedOperand(), and MI.
◆ getNamedOperand() [2/2]
| MachineOperand * SIInstrInfo::getNamedOperand | ( | MachineInstr & | MI, |
| AMDGPU::OpName | OperandName ) const |
Returns the operand named Op.
If MI does not have an operand named Op, this function returns nullptr.
Definition at line 9615 of file SIInstrInfo.cpp.
References MI.
Referenced by buildShrunkInst(), canShrink(), expandMovDPP64(), expandPostRAPseudo(), foldImmediate(), getCalleeOperand(), getMemOperandsWithOffsetWidth(), getNamedOperand(), hasModifiersSet(), isLegalRegOperand(), isSGPRStackAccess(), isStackAccess(), legalizeOperands(), legalizeOperandsFLAT(), legalizeOperandsSMRD(), reMaterialize(), swapSourceModifiers(), and verifyInstruction().
◆ getNonSoftWaitcntOpcode()
Definition at line 1150 of file SIInstrInfo.h.
Referenced by isWaitcnt(), isWaitInstr(), and pseudoToMCOpcode().
◆ getNumWaitStates()
|
static |
Return the number of wait states that result from executing this instruction.
Definition at line 2036 of file SIInstrInfo.cpp.
References MI.
Referenced by getWaitStatesSince(), and getWaitStatesSince().
◆ getOpRegClass()
| const TargetRegisterClass * SIInstrInfo::getOpRegClass | ( | const MachineInstr & | MI, |
| unsigned | OpNo ) const |
Return the correct register class for OpNo.
For target-specific instructions, this will return the register class that has been defined in tablegen. For generic instructions, like REG_SEQUENCE it will return the register class of its machine operand. to infer the correct register class base on the other operands.
Definition at line 6190 of file SIInstrInfo.cpp.
References llvm::get(), MI, and MRI.
Referenced by expandPostRAPseudo(), getMemOperandsWithOffsetWidth(), getOpSize(), legalizeOperands(), moveToVALUImpl(), and verifyInstruction().
◆ getOpSize() [1/2]
|
inline |
This form should usually be preferred since it handles operands with unknown register classes.
Definition at line 1390 of file SIInstrInfo.h.
References getOpRegClass(), llvm::MachineOperand::getSubReg(), llvm::MachineOperand::isReg(), MI, and SubReg.
◆ getOpSize() [2/2]
Return the size in bytes of the operand OpNo on the given.
Definition at line 1376 of file SIInstrInfo.h.
References assert(), llvm::get(), and llvm::MCOI::OPERAND_IMMEDIATE.
Referenced by enforceOperandRCAlignment(), getMemOperandsWithOffsetWidth(), isInlineConstant(), and verifyInstruction().
◆ getPreferredSelectRegClass()
| const TargetRegisterClass * SIInstrInfo::getPreferredSelectRegClass | ( | unsigned | Size | ) | const |
Definition at line 1176 of file SIInstrInfo.cpp.
References Size.
◆ getRegisterInfo()
|
inline |
Definition at line 251 of file SIInstrInfo.h.
◆ getSchedModel()
|
inline |
Definition at line 1680 of file SIInstrInfo.h.
◆ getScratchRsrcWords23()
| uint64_t SIInstrInfo::getScratchRsrcWords23 | ( | ) | const |
Definition at line 9652 of file SIInstrInfo.cpp.
References getDefaultRsrcDataFormat(), llvm::AMDGPUSubtarget::GFX9, llvm::Log2_32(), llvm::AMDGPU::RSRC_ELEMENT_SIZE_SHIFT, llvm::AMDGPU::RSRC_INDEX_STRIDE_SHIFT, llvm::AMDGPU::RSRC_TID_ENABLE, and llvm::AMDGPUSubtarget::VOLCANIC_ISLANDS.
◆ getSerializableDirectMachineOperandTargetFlags()
|
override |
Definition at line 9901 of file SIInstrInfo.cpp.
References llvm::ArrayRef(), MO_ABS32_HI, MO_ABS32_LO, MO_ABS64, MO_GOTPCREL, MO_GOTPCREL32_HI, MO_GOTPCREL32_LO, MO_GOTPCREL64, MO_REL32_HI, MO_REL32_LO, and MO_REL64.
◆ getSerializableMachineMemOperandTargetFlags()
|
override |
Definition at line 9919 of file SIInstrInfo.cpp.
References llvm::ArrayRef(), llvm::MOCooperative, llvm::MOLastUse, and llvm::MONoClobber.
◆ getSerializableTargetIndices()
|
override |
Definition at line 9856 of file SIInstrInfo.cpp.
References llvm::ArrayRef(), llvm::AMDGPU::TI_CONSTDATA_START, llvm::AMDGPU::TI_SCRATCH_RSRC_DWORD0, llvm::AMDGPU::TI_SCRATCH_RSRC_DWORD1, llvm::AMDGPU::TI_SCRATCH_RSRC_DWORD2, and llvm::AMDGPU::TI_SCRATCH_RSRC_DWORD3.
◆ getSubtarget()
|
inline |
Definition at line 255 of file SIInstrInfo.h.
Referenced by shouldScheduleVOPDAdjacent().
◆ getVALUOp()
| unsigned SIInstrInfo::getVALUOp | ( | const MachineInstr & | MI | ) | const |
Definition at line 5911 of file SIInstrInfo.cpp.
References llvm_unreachable, MI, and MRI.
Referenced by moveToVALUImpl().
◆ getVectorRegSpillRestoreOpcode()
| unsigned SIInstrInfo::getVectorRegSpillRestoreOpcode | ( | Register | Reg, |
| const TargetRegisterClass * | RC, | ||
| unsigned | Size, | ||
| const SIMachineFunctionInfo & | MFI ) const |
Definition at line 1870 of file SIInstrInfo.cpp.
References assert(), llvm::SIMachineFunctionInfo::checkFlag(), getAVSpillRestoreOpcode(), getVGPRSpillRestoreOpcode(), getWWMRegSpillRestoreOpcode(), Size, and llvm::AMDGPU::VirtRegFlag::WWM_REG.
Referenced by loadRegFromStackSlot().
◆ getVectorRegSpillSaveOpcode()
| unsigned SIInstrInfo::getVectorRegSpillSaveOpcode | ( | Register | Reg, |
| const TargetRegisterClass * | RC, | ||
| unsigned | Size, | ||
| const SIMachineFunctionInfo & | MFI ) const |
Definition at line 1679 of file SIInstrInfo.cpp.
References llvm::SIMachineFunctionInfo::checkFlag(), getAVSpillSaveOpcode(), getVGPRSpillSaveOpcode(), getWWMRegSpillSaveOpcode(), Size, and llvm::AMDGPU::VirtRegFlag::WWM_REG.
Referenced by storeRegToStackSlot().
◆ getWholeWaveFunctionSetup()
| MachineInstr * SIInstrInfo::getWholeWaveFunctionSetup | ( | MachineFunction & | MF | ) | const |
Definition at line 6178 of file SIInstrInfo.cpp.
References assert(), llvm::MachineFunction::begin(), llvm::MachineFunction::getInfo(), llvm::SIMachineFunctionInfo::isWholeWaveFunction(), llvm_unreachable, MBB, and MI.
◆ hasAnyModifiersSet()
| bool SIInstrInfo::hasAnyModifiersSet | ( | const MachineInstr & | MI | ) | const |
Definition at line 4867 of file SIInstrInfo.cpp.
References llvm::any_of(), hasModifiersSet(), MI, and ModifierOpNames.
Referenced by foldImmediate().
◆ hasDivergentBranch()
| bool SIInstrInfo::hasDivergentBranch | ( | const MachineBasicBlock * | MBB | ) | const |
Return whether the block terminate with divergent branch.
Note this only work before lowering the pseudo control flow instructions.
Definition at line 2921 of file SIInstrInfo.cpp.
Referenced by isSafeToSink().
◆ hasFPClamp() [1/2]
|
inlinestatic |
Definition at line 1056 of file SIInstrInfo.h.
References llvm::SIInstrFlags::FPClamp, and MI.
◆ hasFPClamp() [2/2]
Definition at line 1060 of file SIInstrInfo.h.
References llvm::SIInstrFlags::FPClamp, and llvm::get().
◆ hasIntClamp()
|
inlinestatic |
Definition at line 1064 of file SIInstrInfo.h.
References llvm::SIInstrFlags::IntClamp, and MI.
◆ hasModifiers()
Return true if this instruction has any modifiers.
e.g. src[012]_mod, omod, clamp.
Definition at line 4854 of file SIInstrInfo.cpp.
References llvm::AMDGPU::hasNamedOperand().
◆ hasModifiersSet()
| bool SIInstrInfo::hasModifiersSet | ( | const MachineInstr & | MI, |
| AMDGPU::OpName | OpName ) const |
Definition at line 4861 of file SIInstrInfo.cpp.
References llvm::MachineOperand::getImm(), getNamedOperand(), and MI.
Referenced by canShrink(), and hasAnyModifiersSet().
◆ hasUnwantedEffectsWhenEXECEmpty()
| bool SIInstrInfo::hasUnwantedEffectsWhenEXECEmpty | ( | const MachineInstr & | MI | ) | const |
This function is used to determine if an instruction can be safely executed under EXEC = 0 without hardware error, indeterminate results, and/or visible effects on future vector execution or outside the shader.
Note: as of 2024 the only use of this is SIPreEmitPeephole where it is used in removing branches over short EXEC = 0 sequences. As such it embeds certain assumptions which may not apply to every case of EXEC = 0 execution.
Definition at line 4575 of file SIInstrInfo.cpp.
References isBarrier(), isEXP(), isSMRD(), MI, and modifiesModeRegister().
◆ hasVALU32BitEncoding()
Return true if this 64-bit VALU instruction has a 32-bit encoding.
This function will return false if you pass it a 32-bit instruction.
Definition at line 4842 of file SIInstrInfo.cpp.
References llvm::AMDGPU::getVOPe32(), and pseudoToMCOpcode().
Referenced by canShrink().
◆ hasVGPRUses()
|
inline |
Definition at line 1206 of file SIInstrInfo.h.
References llvm::any_of(), llvm::MachineFunction::getRegInfo(), MI, and MRI.
◆ insertBranch()
|
override |
Definition at line 3221 of file SIInstrInfo.cpp.
References llvm::MachineInstrBuilder::addMBB(), assert(), llvm::BuildMI(), Cond, DL, fixImplicitOperands(), llvm::get(), llvm::getImm(), llvm::MachineInstr::getOperand(), isUndef(), MBB, preserveCondRegFlags(), llvm::MachineOperand::setIsKill(), llvm::MachineOperand::setIsUndef(), and TBB.
◆ insertEQ()
| Register SIInstrInfo::insertEQ | ( | MachineBasicBlock * | MBB, |
| MachineBasicBlock::iterator | I, | ||
| const DebugLoc & | DL, | ||
| Register | SrcReg, | ||
| int | Value ) const |
Definition at line 1290 of file SIInstrInfo.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), DL, llvm::get(), I, MBB, and MRI.
◆ insertIndirectBranch()
|
override |
Definition at line 2930 of file SIInstrInfo.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::MachineInstrBuilder::addSym(), assert(), llvm::BuildMI(), llvm::MCConstantExpr::create(), llvm::MCSymbolRefExpr::create(), llvm::MCBinaryExpr::createAnd(), llvm::MCBinaryExpr::createAShr(), llvm::MCBinaryExpr::createSub(), llvm::RegState::Define, DL, llvm::MachineBasicBlock::empty(), llvm::AMDGPU::DepCtr::encodeFieldSaSdst(), llvm::get(), llvm::MachineFunction::getContext(), llvm::MachineFunction::getInfo(), llvm::SIMachineFunctionInfo::getLongBranchReservedReg(), llvm::MachineFunction::getRegInfo(), llvm::MachineFunction::getSubtarget(), llvm::MachineBasicBlock::getSymbol(), I, MBB, MO_FAR_BRANCH_OFFSET, MRI, llvm::Offset, llvm::MachineInstr::setPostInstrSymbol(), llvm::MCSymbol::setVariableValue(), and TRI.
◆ insertNE()
| Register SIInstrInfo::insertNE | ( | MachineBasicBlock * | MBB, |
| MachineBasicBlock::iterator | I, | ||
| const DebugLoc & | DL, | ||
| Register | SrcReg, | ||
| int | Value ) const |
Definition at line 1303 of file SIInstrInfo.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), DL, llvm::get(), I, MBB, and MRI.
◆ insertNoop()
|
override |
Definition at line 1939 of file SIInstrInfo.cpp.
References insertNoops(), MBB, and MI.
◆ insertNoops()
|
override |
Definition at line 1944 of file SIInstrInfo.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::BuildMI(), DL, llvm::get(), MBB, and MI.
Referenced by insertNoop().
◆ insertReturn()
| void SIInstrInfo::insertReturn | ( | MachineBasicBlock & | MBB | ) | const |
Definition at line 1956 of file SIInstrInfo.cpp.
References llvm::MachineInstrBuilder::addImm(), assert(), llvm::BuildMI(), llvm::get(), and MBB.
◆ insertScratchExecCopy()
| void SIInstrInfo::insertScratchExecCopy | ( | MachineFunction & | MF, |
| MachineBasicBlock & | MBB, | ||
| MachineBasicBlock::iterator | MBBI, | ||
| const DebugLoc & | DL, | ||
| Register | Reg, | ||
| bool | IsSCCLive, | ||
| SlotIndexes * | Indexes = nullptr ) const |
Definition at line 6136 of file SIInstrInfo.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), DL, llvm::AMDGPU::LaneMaskConstants::ExecReg, llvm::AMDGPU::LaneMaskConstants::get(), llvm::MachineInstr::getOperand(), llvm::MachineFunction::getSubtarget(), llvm::SlotIndexes::insertMachineInstrInMaps(), llvm::RegState::Kill, MBB, MBBI, llvm::AMDGPU::LaneMaskConstants::MovOpc, llvm::AMDGPU::LaneMaskConstants::OrSaveExecOpc, llvm::MachineOperand::setIsDead(), SIInstrInfo(), and TII.
◆ insertSelect()
|
override |
Definition at line 3329 of file SIInstrInfo.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), Cond, DL, fixImplicitOperands(), llvm::get(), llvm::ilist_node_impl< OptionsT >::getIterator(), I, MBB, MRI, preserveCondRegFlags(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), Select, and std::swap().
◆ insertSimulatedTrap()
| MachineBasicBlock * SIInstrInfo::insertSimulatedTrap | ( | MachineRegisterInfo & | MRI, |
| MachineBasicBlock & | MBB, | ||
| MachineInstr & | MI, | ||
| const DebugLoc & | DL ) const |
Build instructions that simulate the behavior of a s_trap 2 instructions for hardware (namely, gfx11) that runs in PRIV=1 mode.
There, s_trap is interpreted as a nop.
Definition at line 1974 of file SIInstrInfo.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMBB(), llvm::MachineBasicBlock::addSuccessor(), llvm::MachineInstrBuilder::addUse(), llvm::BuildMI(), llvm::MachineFunction::CreateMachineBasicBlock(), DL, llvm::MachineBasicBlock::end(), llvm::get(), llvm::AMDGPU::SendMsg::ID_INTERRUPT, llvm::AMDGPU::SendMsg::ID_RTN_GET_DOORBELL, llvm::GCNSubtarget::LLVMAMDHSATrap, MBB, MI, MRI, and llvm::MachineFunction::push_back().
◆ insertVectorSelect()
| void SIInstrInfo::insertVectorSelect | ( | MachineBasicBlock & | MBB, |
| MachineBasicBlock::iterator | I, | ||
| const DebugLoc & | DL, | ||
| Register | DstReg, | ||
| ArrayRef< MachineOperand > | Cond, | ||
| Register | TrueReg, | ||
| Register | FalseReg ) const |
Definition at line 1180 of file SIInstrInfo.cpp.
References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), Cond, llvm::AMDGPU::LaneMaskConstants::CSelectOpc, DL, llvm::AMDGPU::LaneMaskConstants::get(), llvm::get(), llvm::getImm(), I, llvm_unreachable, MBB, MRI, llvm::AMDGPU::LaneMaskConstants::OrSaveExecOpc, and llvm::MachineOperand::setImplicit().
◆ isAlwaysGDS()
Definition at line 4479 of file SIInstrInfo.cpp.
References isGWS().
◆ isAsmOnlyOpcode()
| bool SIInstrInfo::isAsmOnlyOpcode | ( | int | MCOp | ) | const |
Check if this instruction should only be used by assembler.
Return true if this opcode should not be used by codegen.
Definition at line 10249 of file SIInstrInfo.cpp.
Referenced by pseudoToMCOpcode().
◆ isAtomic() [1/2]
|
inlinestatic |
Definition at line 815 of file SIInstrInfo.h.
References llvm::SIInstrFlags::IsAtomicNoRet, llvm::SIInstrFlags::IsAtomicRet, and MI.
Referenced by getInstructionUniformity(), and isValidClauseInst().
◆ isAtomic() [2/2]
Definition at line 820 of file SIInstrInfo.h.
References llvm::get(), llvm::SIInstrFlags::IsAtomicNoRet, and llvm::SIInstrFlags::IsAtomicRet.
◆ isAtomicNoRet() [1/2]
|
inlinestatic |
Definition at line 799 of file SIInstrInfo.h.
References llvm::SIInstrFlags::IsAtomicNoRet, and MI.
◆ isAtomicNoRet() [2/2]
Definition at line 803 of file SIInstrInfo.h.
References llvm::get(), and llvm::SIInstrFlags::IsAtomicNoRet.
◆ isAtomicRet() [1/2]
|
inlinestatic |
Definition at line 807 of file SIInstrInfo.h.
References llvm::SIInstrFlags::IsAtomicRet, and MI.
◆ isAtomicRet() [2/2]
Definition at line 811 of file SIInstrInfo.h.
References llvm::get(), and llvm::SIInstrFlags::IsAtomicRet.
◆ isBarrier()
Definition at line 1107 of file SIInstrInfo.h.
References isBarrierStart().
Referenced by hasUnwantedEffectsWhenEXECEmpty().
◆ isBarrierStart()
Definition at line 1099 of file SIInstrInfo.h.
Referenced by isBarrier().
◆ isBasicBlockPrologue()
|
override |
Definition at line 9964 of file SIInstrInfo.cpp.
References canAddToBBProlog(), llvm::MachineFunction::getRegInfo(), MI, and MRI.
◆ isBlockLoadStore()
Definition at line 723 of file SIInstrInfo.h.
Referenced by llvm::AMDGPUAsmPrinter::emitInstruction().
◆ isBranchOffsetInRange()
Definition at line 2900 of file SIInstrInfo.cpp.
References assert(), BranchOffsetBits, llvm::isIntN(), isSOPK(), and isSOPP().
◆ isBUF()
|
inlinestatic |
Definition at line 600 of file SIInstrInfo.h.
References isMTBUF(), isMUBUF(), and MI.
Referenced by mayAccessScratch().
◆ isBufferSMRD()
| bool SIInstrInfo::isBufferSMRD | ( | const MachineInstr & | MI | ) | const |
Definition at line 10069 of file SIInstrInfo.cpp.
◆ isCBranchVCCZRead()
|
inlinestatic |
Definition at line 839 of file SIInstrInfo.h.
◆ isChainCallOpcode()
Definition at line 907 of file SIInstrInfo.h.
◆ isCopyInstrImpl()
|
overrideprotected |
If the specific machine instruction is a instruction that moves/copies value from one register to another register return destination and source registers as machine operands.
Definition at line 2707 of file SIInstrInfo.cpp.
References MI.
◆ isDGEMM()
Definition at line 998 of file SIInstrInfo.h.
References llvm::AMDGPU::getMAIIsDGEMM().
Referenced by isXDL().
◆ isDisableWQM() [1/2]
|
inlinestatic |
Definition at line 853 of file SIInstrInfo.h.
References llvm::SIInstrFlags::DisableWQM, and MI.
◆ isDisableWQM() [2/2]
Definition at line 857 of file SIInstrInfo.h.
References llvm::SIInstrFlags::DisableWQM, and llvm::get().
◆ isDOT() [1/2]
|
inlinestatic |
Definition at line 962 of file SIInstrInfo.h.
References llvm::SIInstrFlags::IsDOT, and MI.
Referenced by isNeverCoissue(), and isXDL().
◆ isDOT() [2/2]
Definition at line 990 of file SIInstrInfo.h.
References llvm::get(), and llvm::SIInstrFlags::IsDOT.
◆ isDPP() [1/2]
|
inlinestatic |
Definition at line 912 of file SIInstrInfo.h.
References llvm::SIInstrFlags::DPP, and MI.
Referenced by llvm::GCNHazardRecognizer::getHazardType(), getInstSizeInBytes(), and llvm::GCNHazardRecognizer::PreEmitNoopsCommon().
◆ isDPP() [2/2]
Definition at line 916 of file SIInstrInfo.h.
References llvm::SIInstrFlags::DPP, and llvm::get().
◆ isDS() [1/2]
|
inlinestatic |
Definition at line 614 of file SIInstrInfo.h.
References llvm::SIInstrFlags::DS, and MI.
Referenced by areLoadsFromSameBasePtr(), areMemAccessesTriviallyDisjoint(), llvm::GCNHazardRecognizer::getHazardType(), getMemOperandsWithOffsetWidth(), isLegalRegOperand(), llvm::GCNHazardRecognizer::PreEmitNoopsCommon(), shouldRunLdsBranchVmemWARHazardFixup(), and verifyInstruction().
◆ isDS() [2/2]
Definition at line 618 of file SIInstrInfo.h.
References llvm::SIInstrFlags::DS, and llvm::get().
◆ isDualSourceBlendEXP()
|
inlinestatic |
Definition at line 787 of file SIInstrInfo.h.
References llvm::AMDGPU::Exp::ET_DUAL_SRC_BLEND0, llvm::AMDGPU::Exp::ET_DUAL_SRC_BLEND1, isEXP(), and MI.
◆ isEXP() [1/2]
|
inlinestatic |
Definition at line 783 of file SIInstrInfo.h.
References llvm::SIInstrFlags::EXP, and MI.
Referenced by llvm::GCNHazardRecognizer::getHazardType(), hasUnwantedEffectsWhenEXECEmpty(), isDualSourceBlendEXP(), and llvm::GCNHazardRecognizer::PreEmitNoopsCommon().
◆ isEXP() [2/2]
Definition at line 795 of file SIInstrInfo.h.
References llvm::SIInstrFlags::EXP, and llvm::get().
◆ isF16PseudoScalarTrans()
Definition at line 1121 of file SIInstrInfo.h.
Referenced by isOperandLegal().
◆ isFixedSize() [1/2]
|
inlinestatic |
Definition at line 1048 of file SIInstrInfo.h.
References llvm::SIInstrFlags::FIXED_SIZE, and MI.
Referenced by getInstSizeInBytes().
◆ isFixedSize() [2/2]
Definition at line 1052 of file SIInstrInfo.h.
References llvm::SIInstrFlags::FIXED_SIZE, and llvm::get().
◆ isFLAT() [1/2]
|
inlinestatic |
Definition at line 674 of file SIInstrInfo.h.
References llvm::SIInstrFlags::FLAT, and MI.
Referenced by areMemAccessesTriviallyDisjoint(), getInstructionUniformity(), getMemOperandsWithOffsetWidth(), isHighLatencyDef(), isLDSDMA(), isLDSDMA(), isLdsDma(), isVMEM(), legalizeOperands(), mayAccessFlatAddressSpace(), mayAccessLDSThroughFlat(), mayAccessScratch(), mayAccessVMEMThroughFlat(), moveFlatAddrToVGPR(), and verifyInstruction().
◆ isFLAT() [2/2]
Definition at line 707 of file SIInstrInfo.h.
References llvm::SIInstrFlags::FLAT, and llvm::get().
◆ isFLATGlobal() [1/2]
|
inlinestatic |
Definition at line 690 of file SIInstrInfo.h.
References llvm::SIInstrFlags::FlatGlobal, and MI.
Referenced by areMemAccessesTriviallyDisjoint(), and mayAccessScratch().
◆ isFLATGlobal() [2/2]
Definition at line 694 of file SIInstrInfo.h.
References llvm::SIInstrFlags::FlatGlobal, and llvm::get().
◆ isFLATScratch() [1/2]
|
inlinestatic |
Definition at line 698 of file SIInstrInfo.h.
References llvm::SIInstrFlags::FlatScratch, and MI.
Referenced by areMemAccessesTriviallyDisjoint(), llvm::SIRegisterInfo::getFrameIndexInstrOffset(), llvm::SIRegisterInfo::getScratchInstrOffset(), llvm::SIRegisterInfo::isFrameOffsetLegal(), mayAccessScratch(), and llvm::SIRegisterInfo::needsFrameBaseReg().
◆ isFLATScratch() [2/2]
Definition at line 702 of file SIInstrInfo.h.
References llvm::SIInstrFlags::FlatScratch, and llvm::get().
◆ isFoldableCopy()
|
static |
◆ isFPAtomic() [1/2]
|
inlinestatic |
Definition at line 1084 of file SIInstrInfo.h.
References llvm::SIInstrFlags::FPAtomic, and MI.
◆ isFPAtomic() [2/2]
Definition at line 1088 of file SIInstrInfo.h.
References llvm::SIInstrFlags::FPAtomic, and llvm::get().
◆ isGather4() [1/2]
|
inlinestatic |
Definition at line 666 of file SIInstrInfo.h.
References llvm::SIInstrFlags::Gather4, and MI.
Referenced by verifyInstruction().
◆ isGather4() [2/2]
Definition at line 670 of file SIInstrInfo.h.
References llvm::SIInstrFlags::Gather4, and llvm::get().
◆ isGFX12CacheInvOrWBInst()
Definition at line 1116 of file SIInstrInfo.h.
References Opc.
◆ isGlobalMemoryObject()
|
override |
Definition at line 11215 of file SIInstrInfo.cpp.
References llvm::TargetInstrInfo::isGlobalMemoryObject(), isIGLP(), and MI.
◆ isGWS() [1/2]
|
inlinestatic |
Definition at line 632 of file SIInstrInfo.h.
References llvm::SIInstrFlags::GWS, and MI.
Referenced by isAlwaysGDS().
◆ isGWS() [2/2]
Definition at line 636 of file SIInstrInfo.h.
References llvm::get(), and llvm::SIInstrFlags::GWS.
◆ isHighLatencyDef()
|
override |
Definition at line 9682 of file SIInstrInfo.cpp.
References llvm::get(), isFLAT(), isMIMG(), isMTBUF(), isMUBUF(), and Opc.
◆ isIGLP() [1/2]
|
inline |
◆ isIGLP() [2/2]
Definition at line 1137 of file SIInstrInfo.h.
Referenced by isGlobalMemoryObject().
◆ isIGLPMutationOnly()
Definition at line 1146 of file SIInstrInfo.h.
Referenced by hasIGLPInstrs(), llvm::GCNSchedStage::initGCNRegion(), and llvm::GCNIterativeScheduler::swapIGLPMutations().
◆ isIgnorableUse()
|
override |
Definition at line 193 of file SIInstrInfo.cpp.
References llvm::MachineOperand::getParent(), llvm::MachineOperand::getReg(), llvm::MachineOperand::isImplicit(), and isVALU().
◆ isImage() [1/2]
|
inlinestatic |
Definition at line 480 of file SIInstrInfo.h.
References isMIMG(), isVIMAGE(), isVSAMPLE(), and MI.
Referenced by getMemOperandsWithOffsetWidth(), isVMEM(), isVMEM(), legalizeOperands(), and verifyInstruction().
◆ isImage() [2/2]
Definition at line 484 of file SIInstrInfo.h.
References isMIMG(), isVIMAGE(), and isVSAMPLE().
◆ isImmOperandLegal() [1/3]
|
inline |
Definition at line 1308 of file SIInstrInfo.h.
References isImmOperandLegal(), and MI.
◆ isImmOperandLegal() [2/3]
| bool SIInstrInfo::isImmOperandLegal | ( | const MCInstrDesc & | InstDesc, |
| unsigned | OpNo, | ||
| const MachineOperand & | MO ) const |
Definition at line 4825 of file SIInstrInfo.cpp.
References assert(), llvm::MachineOperand::getImm(), llvm::MachineOperand::isFI(), llvm::MachineOperand::isGlobal(), llvm::MachineOperand::isImm(), isImmOperandLegal(), isLiteralOperandLegal(), llvm::MachineOperand::isTargetIndex(), and llvm::MCInstrDesc::operands().
Referenced by isImmOperandLegal(), isImmOperandLegal(), isLegalToSwap(), and isOperandLegal().
◆ isImmOperandLegal() [3/3]
| bool SIInstrInfo::isImmOperandLegal | ( | const MCInstrDesc & | InstDesc, |
| unsigned | OpNo, | ||
| int64_t | ImmVal ) const |
Definition at line 4811 of file SIInstrInfo.cpp.
References llvm::MCInstrDesc::getOpcode(), isInlineConstant(), isLiteralOperandLegal(), isMAI(), and llvm::MCInstrDesc::operands().
◆ isInlineConstant() [1/10]
Definition at line 4666 of file SIInstrInfo.cpp.
References llvm::APInt::getSExtValue(), llvm::AMDGPU::isInlinableLiteralBF16(), llvm::AMDGPU::isInlinableLiteralFP16(), isInlineConstant(), llvm_unreachable, llvm::APFloatBase::S_BFloat, llvm::APFloatBase::S_IEEEdouble, llvm::APFloatBase::S_IEEEhalf, llvm::APFloatBase::S_IEEEsingle, and llvm::APFloatBase::SemanticsToEnum().
◆ isInlineConstant() [2/10]
Definition at line 4646 of file SIInstrInfo.cpp.
References llvm::AMDGPU::isInlinableLiteral32(), llvm::AMDGPU::isInlinableLiteral64(), llvm::AMDGPU::isInlinableLiteralI16(), and llvm_unreachable.
Referenced by expandPostRAPseudo(), foldImmediate(), getInstSizeInBytes(), isImmOperandLegal(), isInlineConstant(), isInlineConstant(), isInlineConstant(), isInlineConstant(), isInlineConstant(), isInlineConstant(), isInlineConstant(), isInlineConstant(), isLegalToSwap(), isOperandLegal(), legalizeOperandsVOP3(), usesConstantBus(), and verifyInstruction().
◆ isInlineConstant() [3/10]
|
inline |
returns true if UseMO is substituted with DefMO in MI it would be an inline immediate.
Definition at line 1255 of file SIInstrInfo.h.
References assert(), llvm::MachineOperand::getOperandNo(), llvm::MachineOperand::getParent(), isInlineConstant(), MI, and OpIdx.
◆ isInlineConstant() [4/10]
|
inline |
returns true if the operand OpIdx in MI is a valid inline immediate.
Definition at line 1268 of file SIInstrInfo.h.
References isInlineConstant(), MI, and OpIdx.
◆ isInlineConstant() [5/10]
|
inline |
Definition at line 1290 of file SIInstrInfo.h.
References llvm::MachineOperand::getImm(), isInlineConstant(), MI, and OpIdx.
◆ isInlineConstant() [6/10]
|
inline |
Definition at line 1273 of file SIInstrInfo.h.
References assert(), getOpSize(), isInlineConstant(), MI, llvm::AMDGPU::OPERAND_REG_IMM_INT32, llvm::AMDGPU::OPERAND_REG_IMM_INT64, OpIdx, and Size.
◆ isInlineConstant() [7/10]
|
inline |
Definition at line 1295 of file SIInstrInfo.h.
References llvm::MachineOperand::getOperandNo(), llvm::MachineOperand::getParent(), and isInlineConstant().
◆ isInlineConstant() [8/10]
|
inline |
Definition at line 1248 of file SIInstrInfo.h.
References isInlineConstant().
◆ isInlineConstant() [9/10]
|
inline |
Definition at line 1241 of file SIInstrInfo.h.
References llvm::MachineOperand::getImm(), llvm::MachineOperand::isImm(), and isInlineConstant().
◆ isInlineConstant() [10/10]
Definition at line 4685 of file SIInstrInfo.cpp.
References llvm::AMDGPU::isInlinableIntLiteral(), llvm::AMDGPU::isInlinableLiteral32(), llvm::AMDGPU::isInlinableLiteral64(), llvm::AMDGPU::isInlinableLiteralBF16(), llvm::AMDGPU::isInlinableLiteralFP16(), llvm::AMDGPU::isInlinableLiteralV2BF16(), llvm::AMDGPU::isInlinableLiteralV2F16(), llvm::AMDGPU::isInlinableLiteralV2I16(), llvm::isInt(), isLegalAV64PseudoImm(), llvm::isUInt(), llvm_unreachable, llvm::MCOI::OPERAND_GENERIC_0, llvm::MCOI::OPERAND_GENERIC_1, llvm::MCOI::OPERAND_GENERIC_2, llvm::MCOI::OPERAND_GENERIC_3, llvm::MCOI::OPERAND_GENERIC_4, llvm::MCOI::OPERAND_GENERIC_5, llvm::MCOI::OPERAND_IMMEDIATE, llvm::AMDGPU::OPERAND_INLINE_C_AV64_PSEUDO, llvm::AMDGPU::OPERAND_INLINE_SPLIT_BARRIER_INT32, llvm::AMDGPU::OPERAND_INPUT_MODS, llvm::AMDGPU::OPERAND_KIMM16, llvm::AMDGPU::OPERAND_KIMM32, llvm::AMDGPU::OPERAND_KIMM64, llvm::MCOI::OPERAND_PCREL, llvm::AMDGPU::OPERAND_REG_IMM_BF16, llvm::AMDGPU::OPERAND_REG_IMM_FP16, llvm::AMDGPU::OPERAND_REG_IMM_FP32, llvm::AMDGPU::OPERAND_REG_IMM_FP64, llvm::AMDGPU::OPERAND_REG_IMM_INT16, llvm::AMDGPU::OPERAND_REG_IMM_INT32, llvm::AMDGPU::OPERAND_REG_IMM_INT64, llvm::AMDGPU::OPERAND_REG_IMM_NOINLINE_V2FP16, llvm::AMDGPU::OPERAND_REG_IMM_V2BF16, llvm::AMDGPU::OPERAND_REG_IMM_V2FP16, llvm::AMDGPU::OPERAND_REG_IMM_V2FP32, llvm::AMDGPU::OPERAND_REG_IMM_V2INT16, llvm::AMDGPU::OPERAND_REG_IMM_V2INT32, llvm::AMDGPU::OPERAND_REG_INLINE_AC_FP32, llvm::AMDGPU::OPERAND_REG_INLINE_AC_FP64, llvm::AMDGPU::OPERAND_REG_INLINE_AC_INT32, llvm::AMDGPU::OPERAND_REG_INLINE_C_BF16, llvm::AMDGPU::OPERAND_REG_INLINE_C_FP16, llvm::AMDGPU::OPERAND_REG_INLINE_C_FP32, llvm::AMDGPU::OPERAND_REG_INLINE_C_FP64, llvm::AMDGPU::OPERAND_REG_INLINE_C_INT16, llvm::AMDGPU::OPERAND_REG_INLINE_C_INT32, llvm::AMDGPU::OPERAND_REG_INLINE_C_INT64, llvm::AMDGPU::OPERAND_REG_INLINE_C_V2BF16, llvm::AMDGPU::OPERAND_REG_INLINE_C_V2FP16, llvm::AMDGPU::OPERAND_REG_INLINE_C_V2INT16, llvm::MCOI::OPERAND_REGISTER, and llvm::MCOI::OPERAND_UNKNOWN.
◆ isKillTerminator()
Definition at line 10024 of file SIInstrInfo.cpp.
◆ isLDSDIR() [1/2]
|
inlinestatic |
Definition at line 1000 of file SIInstrInfo.h.
References llvm::SIInstrFlags::LDSDIR, and MI.
◆ isLDSDIR() [2/2]
Definition at line 1004 of file SIInstrInfo.h.
References llvm::get(), and llvm::SIInstrFlags::LDSDIR.
◆ isLDSDMA() [1/2]
|
inlinestatic |
Definition at line 622 of file SIInstrInfo.h.
References isFLAT(), isMUBUF(), isVALU(), MI, and llvm::SIInstrFlags::TENSOR_CNT.
Referenced by areMemAccessesTriviallyDisjoint(), mayWriteLDSThroughDMA(), and shouldRunLdsBranchVmemWARHazardFixup().
◆ isLDSDMA() [2/2]
Definition at line 627 of file SIInstrInfo.h.
References llvm::get(), isFLAT(), isMUBUF(), isVALU(), and llvm::SIInstrFlags::TENSOR_CNT.
◆ isLegalAV64PseudoImm()
Check if this immediate value can be used for AV_MOV_B64_IMM_PSEUDO.
Definition at line 4836 of file SIInstrInfo.cpp.
References llvm::Hi_32(), llvm::AMDGPU::isInlinableLiteral32(), and llvm::Lo_32().
Referenced by isInlineConstant().
◆ isLegalFLATOffset()
| bool SIInstrInfo::isLegalFLATOffset | ( | int64_t | Offset, |
| unsigned | AddrSpace, | ||
| uint64_t | FlatVariant ) const |
Returns if Offset is legal for the subtarget as the offset to a FLAT encoded instruction with the given FlatVariant.
Definition at line 10165 of file SIInstrInfo.cpp.
References allowNegativeFlatOffset(), llvm::SIInstrFlags::FLAT, llvm::AMDGPUAS::FLAT_ADDRESS, llvm::SIInstrFlags::FlatScratch, llvm::AMDGPU::getNumFlatOffsetBits(), llvm::AMDGPUAS::GLOBAL_ADDRESS, llvm::isIntN(), N, and llvm::Offset.
Referenced by splitFlatOffset().
◆ isLegalGFX12PlusPackedMathFP32Operand()
| bool SIInstrInfo::isLegalGFX12PlusPackedMathFP32Operand | ( | const MachineRegisterInfo & | MRI, |
| const MachineInstr & | MI, | ||
| unsigned | SrcN, | ||
| const MachineOperand * | MO = nullptr ) const |
Check if MO would be a legal operand for gfx12+ packed math FP32 instructions.
Packed math FP32 instructions typically accept SGPRs or VGPRs as source operands. On gfx12+, if a source operand uses SGPRs, the HW can only read the first SGPR and use it for both the low and high operations. SrcN can be 0, 1, or 2, representing src0, src1, and src2, respectively. If MO is nullptr, the operand corresponding to SrcN will be used.
Definition at line 6380 of file SIInstrInfo.cpp.
References AbstractManglingParser< Derived, Alloc >::NumOps, assert(), llvm::MachineOperand::getReg(), llvm::MachineOperand::isReg(), MI, MRI, llvm::SISrcMods::OP_SEL_0, and llvm::SISrcMods::OP_SEL_1.
Referenced by isLegalRegOperand(), legalizeOperandsVOP3(), and verifyInstruction().
◆ isLegalMUBUFImmOffset()
Definition at line 10045 of file SIInstrInfo.cpp.
References getMaxMUBUFImmOffset().
◆ isLegalRegOperand() [1/2]
| bool SIInstrInfo::isLegalRegOperand | ( | const MachineInstr & | MI, |
| unsigned | OpIdx, | ||
| const MachineOperand & | MO ) const |
Definition at line 6299 of file SIInstrInfo.cpp.
References llvm::enumerate(), getNamedOperand(), llvm::MachineOperand::getReg(), llvm::AMDGPU::getRegBitWidth(), I, isDS(), llvm::AMDGPU::isGFX12Plus(), isLegalGFX12PlusPackedMathFP32Operand(), isLegalRegOperand(), isMIMG(), llvm::AMDGPU::isPackedFP32Inst(), llvm::MachineOperand::isReg(), isSALU(), MI, MRI, Opc, and OpIdx.
◆ isLegalRegOperand() [2/2]
| bool SIInstrInfo::isLegalRegOperand | ( | const MachineRegisterInfo & | MRI, |
| const MCOperandInfo & | OpInfo, | ||
| const MachineOperand & | MO ) const |
Check if MO (a register operand) is a legal register for the given operand description or operand index.
The operand index version provide more legality checks
Definition at line 6274 of file SIInstrInfo.cpp.
References llvm::TargetRegisterClass::contains(), llvm::MachineInstr::getMF(), llvm::MachineOperand::getParent(), llvm::MachineOperand::getReg(), llvm::MachineOperand::getSubReg(), llvm::MachineOperand::isReg(), and MRI.
Referenced by isLegalRegOperand(), isLegalToSwap(), isLegalVSrcOperand(), isOperandLegal(), and legalizeOperandsVOP2().
◆ isLegalToSwap()
|
protected |
Definition at line 2776 of file SIInstrInfo.cpp.
References isImmOperandLegal(), isInlineConstant(), isLegalRegOperand(), llvm::MachineOperand::isReg(), isVALU(), MI, Opc, llvm::MCOI::OPERAND_UNKNOWN, llvm::MCInstrDesc::operands(), llvm::MCOperandInfo::OperandType, and llvm::MCOperandInfo::RegClass.
Referenced by commuteInstructionImpl().
◆ isLegalVSrcOperand()
| bool SIInstrInfo::isLegalVSrcOperand | ( | const MachineRegisterInfo & | MRI, |
| const MCOperandInfo & | OpInfo, | ||
| const MachineOperand & | MO ) const |
Check if MO would be a valid operand for the given operand definition OpInfo.
Note this does not attempt to validate constant bus restrictions (e.g. literal constant usage).
Definition at line 6369 of file SIInstrInfo.cpp.
References assert(), llvm::MachineOperand::isFI(), llvm::MachineOperand::isGlobal(), llvm::MachineOperand::isImm(), isLegalRegOperand(), llvm::MachineOperand::isReg(), llvm::MachineOperand::isTargetIndex(), and MRI.
◆ isLiteralOperandLegal()
| bool SIInstrInfo::isLiteralOperandLegal | ( | const MCInstrDesc & | InstDesc, |
| const MCOperandInfo & | OpInfo ) const |
Definition at line 4797 of file SIInstrInfo.cpp.
References llvm::AMDGPU::isSISrcOperand(), isVOP3(), and llvm::MCOI::OPERAND_IMMEDIATE.
Referenced by isImmOperandLegal(), and isImmOperandLegal().
◆ isLoadFromStackSlot()
|
override |
Definition at line 9708 of file SIInstrInfo.cpp.
References isMUBUF(), isSGPRSpill(), isSGPRStackAccess(), isStackAccess(), isVGPRSpill(), MI, and Register.
◆ isLowLatencyInstruction()
| bool SIInstrInfo::isLowLatencyInstruction | ( | const MachineInstr & | MI | ) | const |
Definition at line 9676 of file SIInstrInfo.cpp.
◆ isMAI() [1/3]
|
inlinestatic |
◆ isMAI() [2/3]
|
inlinestatic |
Definition at line 944 of file SIInstrInfo.h.
References llvm::SIInstrFlags::IsMAI.
Referenced by llvm::GCNHazardRecognizer::getHazardType(), isImmOperandLegal(), isMFMA(), isMFMA(), isXDL(), llvm::GCNHazardRecognizer::PreEmitNoopsCommon(), and pseudoToMCOpcode().
◆ isMAI() [3/3]
Definition at line 950 of file SIInstrInfo.h.
References llvm::get(), and isMAI().
Referenced by isMAI().
◆ isMFMA() [1/2]
|
inlinestatic |
Definition at line 952 of file SIInstrInfo.h.
Referenced by isMFMAorWMMA(), isMFMAorWMMA(), isNeverCoissue(), and llvm::GCNHazardRecognizer::ShouldPreferAnother().
◆ isMFMA() [2/2]
Definition at line 957 of file SIInstrInfo.h.
References isMAI().
◆ isMFMAorWMMA() [1/2]
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inlinestatic |
Definition at line 974 of file SIInstrInfo.h.
References isMFMA(), isSWMMAC(), isWMMA(), and MI.
◆ isMFMAorWMMA() [2/2]
Definition at line 978 of file SIInstrInfo.h.
References isMFMA(), isSWMMAC(), and isWMMA().
◆ isMIMG() [1/2]
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inlinestatic |
Definition at line 642 of file SIInstrInfo.h.
References MI, and llvm::SIInstrFlags::MIMG.
Referenced by getInstSizeInBytes(), getMemOperandsWithOffsetWidth(), isHighLatencyDef(), isImage(), isImage(), isLegalRegOperand(), legalizeOperands(), and verifyInstruction().
◆ isMIMG() [2/2]
Definition at line 646 of file SIInstrInfo.h.
References llvm::get(), and llvm::SIInstrFlags::MIMG.
◆ isMTBUF() [1/2]
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inlinestatic |
Definition at line 592 of file SIInstrInfo.h.
References MI, and llvm::SIInstrFlags::MTBUF.
Referenced by areLoadsFromSameBasePtr(), areMemAccessesTriviallyDisjoint(), getMemOperandsWithOffsetWidth(), isBUF(), isHighLatencyDef(), isVMEM(), isVMEM(), and legalizeOperands().
◆ isMTBUF() [2/2]
Definition at line 596 of file SIInstrInfo.h.
References llvm::get(), and llvm::SIInstrFlags::MTBUF.
◆ isMUBUF() [1/2]
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inlinestatic |
Definition at line 584 of file SIInstrInfo.h.
References MI, and llvm::SIInstrFlags::MUBUF.
Referenced by areLoadsFromSameBasePtr(), areMemAccessesTriviallyDisjoint(), llvm::SIRegisterInfo::getFrameIndexInstrOffset(), getMemOperandsWithOffsetWidth(), llvm::SIRegisterInfo::getScratchInstrOffset(), isBUF(), llvm::SIRegisterInfo::isFrameOffsetLegal(), isHighLatencyDef(), isLDSDMA(), isLDSDMA(), isLdsDma(), isLoadFromStackSlot(), isStoreToStackSlot(), isVMEM(), isVMEM(), legalizeOperands(), and llvm::SIRegisterInfo::needsFrameBaseReg().
◆ isMUBUF() [2/2]
Definition at line 588 of file SIInstrInfo.h.
References llvm::get(), and llvm::SIInstrFlags::MUBUF.
◆ isNeverCoissue()
| bool SIInstrInfo::isNeverCoissue | ( | MachineInstr & | MI | ) | const |
◆ isNeverUniform()
|
inlinestatic |
Definition at line 1092 of file SIInstrInfo.h.
References llvm::SIInstrFlags::IsNeverUniform, and MI.
Referenced by getInstructionUniformity().
◆ isOperandLegal()
| bool SIInstrInfo::isOperandLegal | ( | const MachineInstr & | MI, |
| unsigned | OpIdx, | ||
| const MachineOperand * | MO = nullptr ) const |
Check if MO is a legal operand if it was the OpIdx Operand for MI.
Definition at line 6413 of file SIInstrInfo.cpp.
References assert(), llvm::MachineOperand::getImm(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), llvm::MCInstrDesc::getSize(), llvm::MachineOperand::getSubReg(), llvm::detail::DenseSetImpl< ValueT, MapTy, ValueInfoT >::insert(), isF16PseudoScalarTrans(), llvm::MachineOperand::isFI(), llvm::MachineOperand::isGlobal(), llvm::MachineOperand::isIdenticalTo(), llvm::MachineOperand::isImm(), isImmOperandLegal(), llvm::AMDGPU::isInlinableLiteral64(), isInlineConstant(), isLegalRegOperand(), llvm::MachineOperand::isReg(), isSALU(), llvm::AMDGPU::isSISrcOperand(), llvm::MachineOperand::isTargetIndex(), llvm::AMDGPU::isValid32BitLiteral(), isVALU(), isVOP3(), MI, MRI, llvm::AMDGPU::OPERAND_REG_IMM_FP64, llvm::AMDGPU::OPERAND_REG_IMM_INT64, llvm::AMDGPU::OPERAND_REG_IMM_V2FP32, llvm::AMDGPU::OPERAND_REG_IMM_V2INT32, llvm::MCOI::OPERAND_UNKNOWN, llvm::MCInstrDesc::operands(), OpIdx, regUsesConstantBus(), and usesConstantBus().
◆ isPacked() [1/2]
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inlinestatic |
Definition at line 536 of file SIInstrInfo.h.
References llvm::SIInstrFlags::IsPacked, and MI.
◆ isPacked() [2/2]
Definition at line 540 of file SIInstrInfo.h.
References llvm::get(), and llvm::SIInstrFlags::IsPacked.
◆ isProgramStateSALU()
|
inlinestatic |
Definition at line 466 of file SIInstrInfo.h.
References MI.
◆ isReMaterializableImpl()
|
override |
Definition at line 128 of file SIInstrInfo.cpp.
References canRemat(), llvm::TargetInstrInfo::isReMaterializableImpl(), and MI.
◆ isSafeToSink()
|
override |
Definition at line 199 of file SIInstrInfo.cpp.
References llvm::GenericCycle< ContextT >::contains(), llvm::GenericCycleInfo< ContextT >::getCycle(), llvm::GenericCycle< ContextT >::getExitingBlocks(), llvm::MachineInstr::getParent(), llvm::GenericCycle< ContextT >::getParentCycle(), hasDivergentBranch(), MI, and MRI.
◆ isSALU() [1/2]
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inlinestatic |
Definition at line 458 of file SIInstrInfo.h.
References MI, and llvm::SIInstrFlags::SALU.
Referenced by canRemat(), getInstSizeInBytes(), isLegalRegOperand(), isOperandLegal(), isSGPRSpill(), isSGPRSpill(), mayReadEXEC(), shouldReadExec(), and verifyInstruction().
◆ isSALU() [2/2]
Definition at line 462 of file SIInstrInfo.h.
References llvm::get(), and llvm::SIInstrFlags::SALU.
◆ isSBarrierSCCWrite()
Definition at line 833 of file SIInstrInfo.h.
◆ isScalarStore() [1/2]
|
inlinestatic |
- Returns
- true if this is an s_store_dword* instruction. This is more specific than isSMEM && mayStore.
Definition at line 1040 of file SIInstrInfo.h.
References MI, and llvm::SIInstrFlags::SCALAR_STORE.
◆ isScalarStore() [2/2]
Definition at line 1044 of file SIInstrInfo.h.
References llvm::get(), and llvm::SIInstrFlags::SCALAR_STORE.
◆ isScalarUnit()
|
inlinestatic |
Definition at line 1016 of file SIInstrInfo.h.
References MI, llvm::SIInstrFlags::SALU, and llvm::SIInstrFlags::SMRD.
◆ isSchedulingBoundary()
|
override |
Definition at line 4447 of file SIInstrInfo.cpp.
References changesVGPRIndexingMode(), MBB, and MI.
◆ isSDWA() [1/2]
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inlinestatic |
Definition at line 568 of file SIInstrInfo.h.
References MI, and llvm::SIInstrFlags::SDWA.
Referenced by canRemat(), getDstSelForwardingOperand(), and verifyInstruction().
◆ isSDWA() [2/2]
Definition at line 572 of file SIInstrInfo.h.
References llvm::get(), and llvm::SIInstrFlags::SDWA.
◆ isSegmentSpecificFLAT() [1/2]
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inlinestatic |
Definition at line 680 of file SIInstrInfo.h.
References llvm::SIInstrFlags::FlatGlobal, llvm::SIInstrFlags::FlatScratch, and MI.
Referenced by areMemAccessesTriviallyDisjoint(), legalizeOperandsFLAT(), and moveFlatAddrToVGPR().
◆ isSegmentSpecificFLAT() [2/2]
Definition at line 685 of file SIInstrInfo.h.
References llvm::SIInstrFlags::FlatGlobal, llvm::SIInstrFlags::FlatScratch, and llvm::get().
◆ isSGPRSpill() [1/2]
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inlinestatic |
Definition at line 878 of file SIInstrInfo.h.
References isSALU(), isSpill(), and MI.
Referenced by canAddToBBProlog(), isLoadFromStackSlot(), and isStoreToStackSlot().
◆ isSGPRSpill() [2/2]
Definition at line 884 of file SIInstrInfo.h.
◆ isSGPRStackAccess()
| Register SIInstrInfo::isSGPRStackAccess | ( | const MachineInstr & | MI, |
| int & | FrameIndex ) const |
Definition at line 9700 of file SIInstrInfo.cpp.
References assert(), llvm::MachineOperand::getIndex(), getNamedOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::isFI(), and MI.
Referenced by isLoadFromStackSlot(), and isStoreToStackSlot().
◆ isSMRD() [1/2]
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inlinestatic |
Definition at line 604 of file SIInstrInfo.h.
References MI, and llvm::SIInstrFlags::SMRD.
Referenced by areLoadsFromSameBasePtr(), areMemAccessesTriviallyDisjoint(), breaksSMEMSoftClause(), canRemat(), llvm::GCNHazardRecognizer::getHazardType(), getMemOperandsWithOffsetWidth(), hasUnwantedEffectsWhenEXECEmpty(), isBufferSMRD(), isLowLatencyInstruction(), isSMEMClauseInst(), legalizeOperands(), llvm::GCNHazardRecognizer::PreEmitNoopsCommon(), shouldReadExec(), and verifyInstruction().
◆ isSMRD() [2/2]
Definition at line 608 of file SIInstrInfo.h.
References llvm::get(), and llvm::SIInstrFlags::SMRD.
◆ isSOP1() [1/2]
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inlinestatic |
Definition at line 496 of file SIInstrInfo.h.
References MI, and llvm::SIInstrFlags::SOP1.
◆ isSOP1() [2/2]
Definition at line 500 of file SIInstrInfo.h.
References llvm::get(), and llvm::SIInstrFlags::SOP1.
◆ isSOP2() [1/2]
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inlinestatic |
Definition at line 504 of file SIInstrInfo.h.
References MI, and llvm::SIInstrFlags::SOP2.
Referenced by verifyInstruction().
◆ isSOP2() [2/2]
Definition at line 508 of file SIInstrInfo.h.
References llvm::get(), and llvm::SIInstrFlags::SOP2.
◆ isSOPC() [1/2]
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inlinestatic |
Definition at line 512 of file SIInstrInfo.h.
References MI, and llvm::SIInstrFlags::SOPC.
Referenced by verifyInstruction().
◆ isSOPC() [2/2]
Definition at line 516 of file SIInstrInfo.h.
References llvm::get(), and llvm::SIInstrFlags::SOPC.
◆ isSOPK() [1/2]
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inlinestatic |
Definition at line 520 of file SIInstrInfo.h.
References MI, and llvm::SIInstrFlags::SOPK.
Referenced by isBranchOffsetInRange(), and verifyInstruction().
◆ isSOPK() [2/2]
Definition at line 524 of file SIInstrInfo.h.
References llvm::get(), and llvm::SIInstrFlags::SOPK.
◆ isSOPP() [1/2]
|
inlinestatic |
Definition at line 528 of file SIInstrInfo.h.
References MI, and llvm::SIInstrFlags::SOPP.
Referenced by isBranchOffsetInRange().
◆ isSOPP() [2/2]
Definition at line 532 of file SIInstrInfo.h.
References llvm::get(), and llvm::SIInstrFlags::SOPP.
◆ isSpill() [1/3]
|
inlinestatic |
Definition at line 898 of file SIInstrInfo.h.
Referenced by isSpill().
◆ isSpill() [2/3]
|
inlinestatic |
Definition at line 894 of file SIInstrInfo.h.
References llvm::SIInstrFlags::Spill.
◆ isSpill() [3/3]
Definition at line 890 of file SIInstrInfo.h.
References llvm::get(), and llvm::SIInstrFlags::Spill.
Referenced by isSGPRSpill(), isSGPRSpill(), isVGPRSpill(), and isVGPRSpill().
◆ isStackAccess()
| Register SIInstrInfo::isStackAccess | ( | const MachineInstr & | MI, |
| int & | FrameIndex ) const |
Definition at line 9687 of file SIInstrInfo.cpp.
References assert(), llvm::MachineOperand::getIndex(), getNamedOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::isFI(), MI, llvm::AMDGPUAS::PRIVATE_ADDRESS, and Register.
Referenced by isLoadFromStackSlot(), and isStoreToStackSlot().
◆ isStoreToStackSlot()
|
override |
Definition at line 9722 of file SIInstrInfo.cpp.
References isMUBUF(), isSGPRSpill(), isSGPRStackAccess(), isStackAccess(), isVGPRSpill(), MI, and Register.
◆ isSWMMAC() [1/2]
|
inlinestatic |
Definition at line 982 of file SIInstrInfo.h.
References llvm::SIInstrFlags::IsSWMMAC, and MI.
Referenced by isCoexecutableVALUInst(), isMFMAorWMMA(), isMFMAorWMMA(), IsWMMAHazardInstInCategory(), and isXDLWMMA().
◆ isSWMMAC() [2/2]
Definition at line 986 of file SIInstrInfo.h.
References llvm::get(), and llvm::SIInstrFlags::IsSWMMAC.
◆ isTRANS() [1/2]
|
inlinestatic |
Definition at line 920 of file SIInstrInfo.h.
References MI, and llvm::SIInstrFlags::TRANS.
Referenced by isCoexecutableVALUInst(), and isNeverCoissue().
◆ isTRANS() [2/2]
Definition at line 924 of file SIInstrInfo.h.
References llvm::get(), and llvm::SIInstrFlags::TRANS.
◆ isVALU() [1/2]
|
inlinestatic |
Definition at line 472 of file SIInstrInfo.h.
References MI, and llvm::SIInstrFlags::VALU.
Referenced by getDstSelForwardingOperand(), llvm::GCNHazardRecognizer::getHazardType(), getInstSizeInBytes(), isCoexecutableVALUInst(), isIgnorableUse(), isLDSDMA(), isLDSDMA(), isLdsDma(), isLegalToSwap(), isNeverCoissue(), isOperandLegal(), isVGPRSpill(), isVGPRSpill(), llvm::GCNHazardRecognizer::PreEmitNoopsCommon(), shouldReadExec(), and verifyInstruction().
◆ isVALU() [2/2]
Definition at line 476 of file SIInstrInfo.h.
References llvm::get(), and llvm::SIInstrFlags::VALU.
◆ isVGPRCopy()
|
inline |
Definition at line 1198 of file SIInstrInfo.h.
References assert(), llvm::MachineFunction::getRegInfo(), MI, and MRI.
◆ isVGPRSpill() [1/2]
|
inlinestatic |
Definition at line 866 of file SIInstrInfo.h.
References isSpill(), isVALU(), and MI.
Referenced by isLoadFromStackSlot(), isStoreToStackSlot(), and verifyInstruction().
◆ isVGPRSpill() [2/2]
Definition at line 872 of file SIInstrInfo.h.
◆ isVIMAGE() [1/2]
|
inlinestatic |
Definition at line 650 of file SIInstrInfo.h.
References MI, and llvm::SIInstrFlags::VIMAGE.
Referenced by isImage(), isImage(), and legalizeOperands().
◆ isVIMAGE() [2/2]
Definition at line 654 of file SIInstrInfo.h.
References llvm::get(), and llvm::SIInstrFlags::VIMAGE.
◆ isVINTERP() [1/2]
|
inlinestatic |
Definition at line 1008 of file SIInstrInfo.h.
References MI, and llvm::SIInstrFlags::VINTERP.
◆ isVINTERP() [2/2]
Definition at line 1012 of file SIInstrInfo.h.
References llvm::get(), and llvm::SIInstrFlags::VINTERP.
◆ isVINTRP() [1/2]
|
inlinestatic |
Definition at line 936 of file SIInstrInfo.h.
References MI, and llvm::SIInstrFlags::VINTRP.
◆ isVINTRP() [2/2]
Definition at line 940 of file SIInstrInfo.h.
References llvm::get(), and llvm::SIInstrFlags::VINTRP.
◆ isVMEM() [1/2]
|
inlinestatic |
Definition at line 488 of file SIInstrInfo.h.
References isFLAT(), isImage(), isMTBUF(), isMUBUF(), and MI.
Referenced by breaksVMEMSoftClause(), llvm::GCNHazardRecognizer::getHazardType(), isVMEMClauseInst(), isVMEMLoad(), llvm::GCNHazardRecognizer::PreEmitNoopsCommon(), and shouldRunLdsBranchVmemWARHazardFixup().
◆ isVMEM() [2/2]
Definition at line 492 of file SIInstrInfo.h.
◆ isVOP1() [1/2]
|
inlinestatic |
Definition at line 544 of file SIInstrInfo.h.
References MI, and llvm::SIInstrFlags::VOP1.
Referenced by canRemat().
◆ isVOP1() [2/2]
Definition at line 548 of file SIInstrInfo.h.
References llvm::get(), and llvm::SIInstrFlags::VOP1.
◆ isVOP2() [1/2]
|
inlinestatic |
Definition at line 552 of file SIInstrInfo.h.
References MI, and llvm::SIInstrFlags::VOP2.
Referenced by canRemat(), legalizeOperands(), and verifyInstruction().
◆ isVOP2() [2/2]
Definition at line 556 of file SIInstrInfo.h.
References llvm::get(), and llvm::SIInstrFlags::VOP2.
◆ isVOP3() [1/3]
|
inlinestatic |
◆ isVOP3() [2/3]
|
inlinestatic |
Definition at line 560 of file SIInstrInfo.h.
References llvm::SIInstrFlags::VOP3.
Referenced by canRemat(), llvm::SIRegisterInfo::eliminateFrameIndex(), isLiteralOperandLegal(), isOperandLegal(), legalizeOperands(), moveToVALUImpl(), and verifyInstruction().
◆ isVOP3() [3/3]
Definition at line 566 of file SIInstrInfo.h.
References llvm::get(), and isVOP3().
Referenced by isVOP3().
◆ isVOP3P() [1/2]
|
inlinestatic |
Definition at line 928 of file SIInstrInfo.h.
References MI, and llvm::SIInstrFlags::VOP3P.
◆ isVOP3P() [2/2]
Definition at line 932 of file SIInstrInfo.h.
References llvm::get(), and llvm::SIInstrFlags::VOP3P.
◆ isVOPC() [1/2]
|
inlinestatic |
Definition at line 576 of file SIInstrInfo.h.
References MI, and llvm::SIInstrFlags::VOPC.
Referenced by legalizeOperands(), and verifyInstruction().
◆ isVOPC() [2/2]
Definition at line 580 of file SIInstrInfo.h.
References llvm::get(), and llvm::SIInstrFlags::VOPC.
◆ isVSAMPLE() [1/2]
|
inlinestatic |
Definition at line 658 of file SIInstrInfo.h.
References MI, and llvm::SIInstrFlags::VSAMPLE.
Referenced by isImage(), isImage(), legalizeOperands(), and verifyInstruction().
◆ isVSAMPLE() [2/2]
Definition at line 662 of file SIInstrInfo.h.
References llvm::get(), and llvm::SIInstrFlags::VSAMPLE.
◆ isWaitcnt()
Definition at line 1175 of file SIInstrInfo.h.
References getNonSoftWaitcntOpcode().
◆ isWave32()
| bool llvm::SIInstrInfo::isWave32 | ( | ) | const |
Definition at line 10571 of file SIInstrInfo.cpp.
◆ isWMMA() [1/2]
|
inlinestatic |
Definition at line 966 of file SIInstrInfo.h.
References llvm::SIInstrFlags::IsWMMA, and MI.
Referenced by isCoexecutableVALUInst(), isMFMAorWMMA(), isMFMAorWMMA(), IsWMMAHazardInstInCategory(), and isXDLWMMA().
◆ isWMMA() [2/2]
Definition at line 970 of file SIInstrInfo.h.
References llvm::get(), and llvm::SIInstrFlags::IsWMMA.
◆ isWQM() [1/2]
|
inlinestatic |
Definition at line 845 of file SIInstrInfo.h.
References MI, and llvm::SIInstrFlags::WQM.
◆ isWQM() [2/2]
Definition at line 849 of file SIInstrInfo.h.
References llvm::get(), and llvm::SIInstrFlags::WQM.
◆ isWWMRegSpillOpcode()
Definition at line 900 of file SIInstrInfo.h.
Referenced by canAddToBBProlog().
◆ isXDL()
| bool SIInstrInfo::isXDL | ( | const MachineInstr & | MI | ) | const |
Definition at line 11232 of file SIInstrInfo.cpp.
References llvm::AMDGPU::getMAIIsGFX940XDL(), isDGEMM(), isDOT(), llvm::AMDGPU::isGFX12Plus(), isMAI(), isXDLWMMA(), and MI.
◆ isXDLWMMA()
| bool SIInstrInfo::isXDLWMMA | ( | const MachineInstr & | MI | ) | const |
Definition at line 11222 of file SIInstrInfo.cpp.
References llvm::AMDGPU::getWMMAIsXDL(), llvm::AMDGPU::isGFX1250(), isSWMMAC(), isWMMA(), and MI.
Referenced by isXDL().
◆ legalizeGenericOperand()
| void SIInstrInfo::legalizeGenericOperand | ( | MachineBasicBlock & | InsertMBB, |
| MachineBasicBlock::iterator | I, | ||
| const TargetRegisterClass * | DstRC, | ||
| MachineOperand & | Op, | ||
| MachineRegisterInfo & | MRI, | ||
| const DebugLoc & | DL ) const |
Definition at line 6975 of file SIInstrInfo.cpp.
References llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), DL, foldImmediate(), llvm::get(), I, llvm::RegState::Implicit, and MRI.
Referenced by legalizeOperands().
◆ legalizeOperands()
| MachineBasicBlock * SIInstrInfo::legalizeOperands | ( | MachineInstr & | MI, |
| MachineDominatorTree * | MDT = nullptr ) const |
Legalize all operands in this instruction.
This function may create new instructions and control-flow around MI. If present, MDT is updated.
- Returns
- A new basic block that contains
MIif new blocks were created.
Definition at line 7309 of file SIInstrInfo.cpp.
References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addDef(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), llvm::MachineOperand::ChangeToRegister(), llvm::MachineInstrBuilder::cloneMemRefs(), llvm::RegState::Dead, DL, extractRsrcPtr(), llvm::get(), llvm::AMDGPU::getAddr64Inst(), llvm::Function::getCallingConv(), llvm::MachineInstr::getDebugLoc(), llvm::MachineBasicBlock::getFirstTerminator(), llvm::MachineFunction::getFunction(), llvm::AMDGPU::getIfAddr64Inst(), getNamedImmOperand(), getNamedOperand(), getOpRegClass(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), I, isFLAT(), llvm::AMDGPU::isGraphics(), isImage(), isMIMG(), isMTBUF(), isMUBUF(), llvm::MachineOperand::isReg(), isSMRD(), isVIMAGE(), llvm::Register::isVirtual(), isVOP2(), isVOP3(), isVOPC(), isVSAMPLE(), llvm::RegState::Kill, legalizeGenericOperand(), legalizeOperandsFLAT(), legalizeOperandsSMRD(), legalizeOperandsVOP2(), legalizeOperandsVOP3(), loadMBUFScalarOperandsFromVGPR(), MBB, MI, MRI, llvm::Offset, readlaneVGPRToSGPR(), llvm::MachineOperand::setReg(), and llvm::AMDGPUSubtarget::VOLCANIC_ISLANDS.
Referenced by foldImmediate(), and moveToVALUImpl().
◆ legalizeOperandsFLAT()
| void SIInstrInfo::legalizeOperandsFLAT | ( | MachineRegisterInfo & | MRI, |
| MachineInstr & | MI ) const |
Definition at line 6954 of file SIInstrInfo.cpp.
References getNamedOperand(), llvm::MachineOperand::getOperandNo(), llvm::MachineOperand::getReg(), getRegClass(), isSegmentSpecificFLAT(), MI, moveFlatAddrToVGPR(), MRI, readlaneVGPRToSGPR(), and llvm::MachineOperand::setReg().
Referenced by legalizeOperands().
◆ legalizeOperandsSMRD()
| void SIInstrInfo::legalizeOperandsSMRD | ( | MachineRegisterInfo & | MRI, |
| MachineInstr & | MI ) const |
Definition at line 6854 of file SIInstrInfo.cpp.
References getNamedOperand(), llvm::MachineOperand::getReg(), MI, MRI, readlaneVGPRToSGPR(), and llvm::MachineOperand::setReg().
Referenced by legalizeOperands().
◆ legalizeOperandsVALUt16() [1/2]
| void SIInstrInfo::legalizeOperandsVALUt16 | ( | MachineInstr & | Inst, |
| MachineRegisterInfo & | MRI ) const |
Fix operands in Inst to fix 16bit SALU to VALU lowering.
Definition at line 7763 of file SIInstrInfo.cpp.
References legalizeOperandsVALUt16(), MI, MRI, and OpIdx.
Referenced by legalizeOperandsVALUt16(), and moveToVALUImpl().
◆ legalizeOperandsVALUt16() [2/2]
| void SIInstrInfo::legalizeOperandsVALUt16 | ( | MachineInstr & | Inst, |
| unsigned | OpIdx, | ||
| MachineRegisterInfo & | MRI ) const |
Definition at line 7725 of file SIInstrInfo.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), DL, llvm::get(), MBB, MI, MRI, and OpIdx.
◆ legalizeOperandsVOP2()
| void SIInstrInfo::legalizeOperandsVOP2 | ( | MachineRegisterInfo & | MRI, |
| MachineInstr & | MI ) const |
Legalize operands in MI by either commuting it or inserting a copy of src1.
Definition at line 6596 of file SIInstrInfo.cpp.
References llvm::MachineInstrBuilder::add(), llvm::BuildMI(), llvm::MachineOperand::ChangeToImmediate(), llvm::MachineOperand::ChangeToRegister(), commuteOpcode(), DL, findImplicitSGPRRead(), fixImplicitOperands(), llvm::get(), llvm::MachineOperand::getImm(), llvm::MachineOperand::getReg(), llvm::MachineOperand::getSubReg(), llvm::MachineOperand::isImm(), llvm::MachineOperand::isKill(), isLegalRegOperand(), llvm::MachineOperand::isReg(), legalizeOpWithMove(), llvm_unreachable, MI, MRI, Opc, llvm::MCInstrDesc::operands(), and llvm::MachineOperand::setSubReg().
Referenced by legalizeOperands().
◆ legalizeOperandsVOP3()
| void SIInstrInfo::legalizeOperandsVOP3 | ( | MachineRegisterInfo & | MRI, |
| MachineInstr & | MI ) const |
Fix operands in MI to satisfy constant bus requirements.
Definition at line 6707 of file SIInstrInfo.cpp.
References llvm::MachineInstrBuilder::add(), llvm::BuildMI(), llvm::MachineOperand::ChangeToRegister(), llvm::detail::DenseSetImpl< ValueT, MapTy, ValueInfoT >::count(), DL, llvm::get(), llvm::MachineOperand::getReg(), I, llvm::detail::DenseSetImpl< ValueT, MapTy, ValueInfoT >::insert(), llvm::AMDGPU::isGFX12Plus(), isInlineConstant(), isLegalGFX12PlusPackedMathFP32Operand(), llvm::AMDGPU::isPackedFP32Inst(), llvm::MachineOperand::isReg(), legalizeOpWithMove(), MI, MRI, and Opc.
Referenced by legalizeOperands().
◆ legalizeOpWithMove()
| void SIInstrInfo::legalizeOpWithMove | ( | MachineInstr & | MI, |
| unsigned | OpIdx ) const |
Legalize the OpIndex operand of this instruction by inserting a MOV.
For example: ADD_I32_e32 VGPR0, 15 to MOV VGPR1, 15 ADD_I32_e32 VGPR0, VGPR1
If the operand being legalized is a register, then a COPY will be used instead of MOV.
Definition at line 6208 of file SIInstrInfo.cpp.
References llvm::MachineInstrBuilder::add(), llvm::BuildMI(), llvm::MachineOperand::ChangeToRegister(), DL, llvm::get(), I, llvm::MachineOperand::isReg(), MBB, MI, MRI, OpIdx, and Size.
Referenced by legalizeOperandsVOP2(), and legalizeOperandsVOP3().
◆ loadRegFromStackSlot()
|
override |
Definition at line 1887 of file SIInstrInfo.cpp.
References llvm::MachineInstrBuilder::addFrameIndex(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMemOperand(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), DL, llvm::get(), llvm::MachinePointerInfo::getFixedStack(), llvm::MachineFunction::getFrameInfo(), llvm::MachineFunction::getInfo(), llvm::MachineFunction::getMachineMemOperand(), llvm::MachineFunction::getRegInfo(), getSGPRSpillRestoreOpcode(), llvm::SIMachineFunctionInfo::getStackPtrOffsetReg(), getVectorRegSpillRestoreOpcode(), llvm::RegState::Implicit, llvm::Register::isVirtual(), MBB, MI, llvm::MachineMemOperand::MOLoad, MRI, llvm::SIMachineFunctionInfo::setHasSpilledSGPRs(), llvm::TargetStackID::SGPRSpill, and SubReg.
◆ mayAccessFlatAddressSpace()
| bool SIInstrInfo::mayAccessFlatAddressSpace | ( | const MachineInstr & | MI | ) | const |
Definition at line 9841 of file SIInstrInfo.cpp.
References llvm::AMDGPUAS::FLAT_ADDRESS, isFLAT(), and MI.
◆ mayAccessLDSThroughFlat()
| bool SIInstrInfo::mayAccessLDSThroughFlat | ( | const MachineInstr & | MI | ) | const |
- Returns
- true for FLAT instructions that can access LDS.
Definition at line 4542 of file SIInstrInfo.cpp.
References assert(), llvm::AMDGPUAS::FLAT_ADDRESS, isFLAT(), llvm::AMDGPUAS::LOCAL_ADDRESS, MI, and usesLGKM_CNT().
◆ mayAccessScratch()
| bool SIInstrInfo::mayAccessScratch | ( | const MachineInstr & | MI | ) | const |
- Returns
- true for SCRATCH_ instructions, or FLAT/BUF instructions unless the MMOs do not include scratch. Conservatively correct; will return true if
MIcannot be proven to not hit scratch.
Definition at line 4485 of file SIInstrInfo.cpp.
References llvm::any_of(), isBUF(), isFLAT(), isFLATGlobal(), isFLATScratch(), MI, and llvm::AMDGPUAS::PRIVATE_ADDRESS.
◆ mayAccessVMEMThroughFlat()
| bool SIInstrInfo::mayAccessVMEMThroughFlat | ( | const MachineInstr & | MI | ) | const |
- Returns
- true for FLAT instructions that can access VMEM.
Definition at line 4515 of file SIInstrInfo.cpp.
References assert(), isFLAT(), llvm::AMDGPUAS::LOCAL_ADDRESS, MI, llvm::AMDGPUAS::REGION_ADDRESS, and usesVM_CNT().
◆ mayReadEXEC()
| bool SIInstrInfo::mayReadEXEC | ( | const MachineRegisterInfo & | MRI, |
| const MachineInstr & | MI ) const |
Returns true if the instruction could potentially depend on the value of exec.
If false, exec dependencies may safely be ignored.
Definition at line 4621 of file SIInstrInfo.cpp.
References isSALU(), llvm::isTargetSpecificOpcode(), MI, and MRI.
◆ mayWriteLDSThroughDMA()
|
inlinestatic |
Definition at line 825 of file SIInstrInfo.h.
References isLDSDMA(), MI, and Opc.
◆ modifiesModeRegister()
|
static |
Return true if the instruction modifies the mode register.q.
Definition at line 4568 of file SIInstrInfo.cpp.
References llvm::is_contained(), and MI.
Referenced by hasUnwantedEffectsWhenEXECEmpty().
◆ moveFlatAddrToVGPR()
| bool SIInstrInfo::moveFlatAddrToVGPR | ( | MachineInstr & | Inst | ) | const |
Change SADDR form of a FLAT Inst to its VADDR form if saddr operand was moved to VGPR.
- Returns
- true if succeeded.
Definition at line 6873 of file SIInstrInfo.cpp.
References assert(), llvm::MachineInstr::eraseFromParent(), llvm::get(), llvm::AMDGPU::getFlatScratchInstSVfromSS(), llvm::AMDGPU::getGlobalVaddrOp(), llvm::MachineOperand::getImm(), llvm::MachineInstr::getMF(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), isFLAT(), llvm::MachineOperand::isImm(), llvm::MachineInstr::isMoveImmediate(), isSegmentSpecificFLAT(), MRI, Opc, llvm::MachineInstr::removeOperand(), llvm::MachineInstr::setDesc(), llvm::MachineInstr::tieOperands(), and llvm::MachineInstr::untieRegOperand().
Referenced by legalizeOperandsFLAT().
◆ moveToVALU()
| void SIInstrInfo::moveToVALU | ( | SIInstrWorklist & | Worklist, |
| MachineDominatorTree * | MDT ) const |
Replace the instructions opcode with the equivalent VALU opcode.
This function will also move the users of MachineInstruntions in the WorkList to the VALU if necessary. If present, MDT is updated.
Definition at line 7769 of file SIInstrInfo.cpp.
References assert(), llvm::SIInstrWorklist::empty(), llvm::SIInstrWorklist::erase_top(), llvm::SIInstrWorklist::getDeferredList(), llvm::SIInstrWorklist::isDeferred(), moveToVALUImpl(), and llvm::SIInstrWorklist::top().
◆ moveToVALUImpl()
| void SIInstrInfo::moveToVALUImpl | ( | SIInstrWorklist & | Worklist, |
| MachineDominatorTree * | MDT, | ||
| MachineInstr & | Inst ) const |
Definition at line 7790 of file SIInstrInfo.cpp.
References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::AMDGPU::LaneMaskConstants::AndOpc, assert(), llvm::BitWidth, llvm::BuildMI(), Changed, llvm::RegState::Define, DL, llvm::MachineInstr::eraseFromParent(), llvm::AMDGPU::LaneMaskConstants::ExecReg, llvm::MachineInstr::explicit_operands(), llvm::MachineInstr::findRegisterDefOperandIdx(), fixImplicitOperands(), llvm::AMDGPU::LaneMaskConstants::get(), llvm::get(), llvm::MachineInstr::getDebugLoc(), llvm::MachineInstr::getFlags(), llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), getOpRegClass(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), getVALUOp(), llvm::AMDGPUSubtarget::GFX12, llvm::AMDGPU::hasNamedOperand(), llvm::MachineInstr::implicit_operands(), llvm::MachineInstr::isCopy(), llvm::MachineOperand::isImm(), llvm::Register::isPhysical(), llvm::Register::isVirtual(), isVOP3(), legalizeOperands(), legalizeOperandsVALUt16(), llvm_unreachable, llvm::make_early_inc_range(), MBB, MRI, llvm::Offset, Opc, llvm::MachineInstr::removeOperand(), llvm::MachineInstrBuilder::setMIFlags(), llvm::MachineOperand::setReg(), llvm::MachineOperand::setSubReg(), Size, and llvm::AMDGPU::LaneMaskConstants::VccReg.
Referenced by moveToVALU().
◆ mutateAndCleanupImplicit()
| void SIInstrInfo::mutateAndCleanupImplicit | ( | MachineInstr & | MI, |
| const MCInstrDesc & | NewDesc ) const |
Definition at line 3501 of file SIInstrInfo.cpp.
References AbstractManglingParser< Derived, Alloc >::NumOps, I, and MI.
◆ optimizeCompareInstr()
|
override |
Definition at line 10982 of file SIInstrInfo.cpp.
References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addImm(), assert(), llvm::BuildMI(), llvm::countr_zero(), foldableSelect(), llvm::get(), getFoldableImm(), llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::getSubReg(), llvm::has_single_bit(), llvm::MachineOperand::isImm(), llvm::Register::isPhysical(), llvm::isPowerOf2_64(), llvm::MachineOperand::isReg(), llvm::maxUIntN(), MBB, MRI, Select, and setsSCCifResultIsNonZero().
◆ physRegUsesConstantBus()
| bool SIInstrInfo::physRegUsesConstantBus | ( | const MachineOperand & | Reg | ) | const |
Definition at line 4993 of file SIInstrInfo.cpp.
References llvm::MachineOperand::getReg(), and llvm::MachineOperand::isImplicit().
Referenced by regUsesConstantBus(), and usesConstantBus().
◆ pseudoToMCOpcode()
| int SIInstrInfo::pseudoToMCOpcode | ( | int | Opcode | ) | const |
Return a target-specific opcode if Opcode is a pseudo instruction.
Return -1 if the target-specific opcode for the pseudo instruction does not exist. If Opcode is not a pseudo instruction, this is identity.
Definition at line 10302 of file SIInstrInfo.cpp.
References assert(), llvm::SIInstrFlags::D16Buf, llvm::get(), llvm::AMDGPU::getMCOpcode(), llvm::AMDGPU::getMFMAEarlyClobberOp(), getNonSoftWaitcntOpcode(), llvm::AMDGPUSubtarget::GFX10, llvm::SIEncodingFamily::GFX12, llvm::SIEncodingFamily::GFX80, llvm::AMDGPUSubtarget::GFX9, llvm::SIEncodingFamily::GFX9, llvm::SIEncodingFamily::GFX90A, llvm::SIEncodingFamily::GFX940, isAsmOnlyOpcode(), isMAI(), isRenamedInGFX9(), llvm::SIEncodingFamily::SDWA, llvm::SIInstrFlags::SDWA, llvm::SIEncodingFamily::SDWA10, llvm::SIEncodingFamily::SDWA9, and subtargetEncodingFamily().
Referenced by commuteOpcode(), foldImmediate(), getMCOpcodeFromPseudo(), and hasVALU32BitEncoding().
◆ readlaneVGPRToSGPR()
| Register SIInstrInfo::readlaneVGPRToSGPR | ( | Register | SrcReg, |
| MachineInstr & | UseMI, | ||
| MachineRegisterInfo & | MRI, | ||
| const TargetRegisterClass * | DstRC = nullptr ) const |
Copy a value from a VGPR (SrcReg) to SGPR.
The desired register class for the dst register (DstRC) can be optionally supplied. This function can only be used when it is know that the value in SrcReg is same across all threads in the wave.
- Returns
- The SGPR register that
SrcRegwas copied to.
Definition at line 6808 of file SIInstrInfo.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::get(), MRI, llvm::SmallVectorTemplateBase< T, bool >::push_back(), and UseMI.
Referenced by legalizeOperands(), legalizeOperandsFLAT(), and legalizeOperandsSMRD().
◆ regUsesConstantBus()
| bool SIInstrInfo::regUsesConstantBus | ( | const MachineOperand & | Reg, |
| const MachineRegisterInfo & | MRI ) const |
Definition at line 5011 of file SIInstrInfo.cpp.
References llvm::MachineOperand::getReg(), llvm::Register::isVirtual(), MRI, and physRegUsesConstantBus().
Referenced by isOperandLegal().
◆ reMaterialize()
|
override |
Definition at line 2556 of file SIInstrInfo.cpp.
References assert(), llvm::get(), llvm::MachineOperand::getImm(), llvm::MachineFunction::getMachineMemOperand(), getNamedOperand(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), getRegClass(), llvm::MachineFunction::getRegInfo(), llvm::MachineOperand::getSubReg(), I, MBB, llvm::MachineInstr::memoperands(), MI, MRI, llvm::Offset, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::TargetInstrInfo::reMaterialize(), llvm::MachineOperand::setImm(), llvm::MachineOperand::setReg(), and llvm::MachineOperand::setSubReg().
◆ removeBranch()
|
override |
Definition at line 3195 of file SIInstrInfo.cpp.
References llvm::Count, getInstSizeInBytes(), llvm::make_early_inc_range(), MBB, and MI.
◆ removeModOperands()
| void SIInstrInfo::removeModOperands | ( | MachineInstr & | MI | ) | const |
Definition at line 3492 of file SIInstrInfo.cpp.
References MI, ModifierOpNames, Opc, and llvm::reverse().
Referenced by foldImmediate().
◆ restoreExec()
| void SIInstrInfo::restoreExec | ( | MachineFunction & | MF, |
| MachineBasicBlock & | MBB, | ||
| MachineBasicBlock::iterator | MBBI, | ||
| const DebugLoc & | DL, | ||
| Register | Reg, | ||
| SlotIndexes * | Indexes = nullptr ) const |
Definition at line 6166 of file SIInstrInfo.cpp.
References llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), DL, llvm::AMDGPU::LaneMaskConstants::ExecReg, llvm::AMDGPU::LaneMaskConstants::get(), llvm::get(), llvm::SlotIndexes::insertMachineInstrInMaps(), llvm::RegState::Kill, MBB, MBBI, and llvm::AMDGPU::LaneMaskConstants::MovOpc.
◆ reverseBranchCondition()
|
override |
Definition at line 3273 of file SIInstrInfo.cpp.
References Cond, and llvm::getImm().
◆ setsSCCifResultIsNonZero()
|
inlinestatic |
◆ shouldClusterMemOps()
|
override |
Definition at line 562 of file SIInstrInfo.cpp.
References llvm::DefaultMemoryClusterDWordsLimit, llvm::ArrayRef< T >::empty(), llvm::ArrayRef< T >::front(), llvm::MachineFunction::getInfo(), llvm::SIMachineFunctionInfo::getMaxMemoryClusterDWords(), llvm::MachineInstr::getMF(), and memOpsHaveSameBasePtr().
◆ shouldScheduleLoadsNear()
|
override |
Definition at line 614 of file SIInstrInfo.cpp.
References assert().
◆ sopkIsZext()
Definition at line 1030 of file SIInstrInfo.h.
Referenced by verifyInstruction().
◆ splitFlatOffset()
| std::pair< int64_t, int64_t > SIInstrInfo::splitFlatOffset | ( | int64_t | COffsetVal, |
| unsigned | AddrSpace, | ||
| uint64_t | FlatVariant ) const |
Split COffsetVal into {immediate offset field, remainder offset} values.
Definition at line 10189 of file SIInstrInfo.cpp.
References allowNegativeFlatOffset(), assert(), D(), llvm::SIInstrFlags::FlatScratch, llvm::AMDGPU::getNumFlatOffsetBits(), isLegalFLATOffset(), and llvm::maskTrailingOnes().
◆ splitMUBUFOffset()
| bool SIInstrInfo::splitMUBUFOffset | ( | uint32_t | Imm, |
| uint32_t & | SOffset, | ||
| uint32_t & | ImmOffset, | ||
| Align | Alignment = Align(4) ) const |
Definition at line 10089 of file SIInstrInfo.cpp.
References llvm::alignDown(), getMaxMUBUFImmOffset(), High, llvm::Low, llvm::AMDGPUSubtarget::SEA_ISLANDS, and llvm::Align::value().
◆ storeRegToStackSlot()
|
override |
Definition at line 1695 of file SIInstrInfo.cpp.
References llvm::MachineInstrBuilder::addFrameIndex(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMemOperand(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), DL, llvm::get(), llvm::MachinePointerInfo::getFixedStack(), llvm::MachineFunction::getFrameInfo(), llvm::MachineFunction::getInfo(), llvm::getKillRegState(), llvm::MachineFunction::getMachineMemOperand(), llvm::MachineFunction::getRegInfo(), getSGPRSpillSaveOpcode(), llvm::SIMachineFunctionInfo::getStackPtrOffsetReg(), getVectorRegSpillSaveOpcode(), llvm::RegState::Implicit, llvm::Register::isVirtual(), MBB, MI, llvm::MachineMemOperand::MOStore, MRI, llvm::SIMachineFunctionInfo::setHasSpilledSGPRs(), llvm::SIMachineFunctionInfo::setHasSpilledVGPRs(), and llvm::TargetStackID::SGPRSpill.
◆ swapSourceModifiers()
|
protected |
Definition at line 2714 of file SIInstrInfo.cpp.
References assert(), llvm::MachineOperand::getImm(), getNamedOperand(), MI, and llvm::MachineOperand::setImm().
Referenced by commuteInstructionImpl().
◆ usesConstantBus() [1/2]
|
inline |
Definition at line 1331 of file SIInstrInfo.h.
References MI, MRI, OpIdx, and usesConstantBus().
◆ usesConstantBus() [2/2]
| bool SIInstrInfo::usesConstantBus | ( | const MachineRegisterInfo & | MRI, |
| const MachineOperand & | MO, | ||
| const MCOperandInfo & | OpInfo ) const |
Returns true if this operand uses the constant bus.
Definition at line 5018 of file SIInstrInfo.cpp.
References llvm::MachineOperand::getReg(), isInlineConstant(), llvm::MachineOperand::isReg(), llvm::Register::isVirtual(), MRI, and physRegUsesConstantBus().
Referenced by isOperandLegal(), usesConstantBus(), and verifyInstruction().
◆ usesFPDPRounding() [1/2]
|
inlinestatic |
Definition at line 1076 of file SIInstrInfo.h.
References llvm::SIInstrFlags::FPDPRounding, and MI.
◆ usesFPDPRounding() [2/2]
Definition at line 1080 of file SIInstrInfo.h.
References llvm::SIInstrFlags::FPDPRounding, and llvm::get().
◆ usesLGKM_CNT()
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inlinestatic |
Definition at line 1024 of file SIInstrInfo.h.
References llvm::SIInstrFlags::LGKM_CNT, and MI.
Referenced by mayAccessLDSThroughFlat().
◆ usesVM_CNT()
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inlinestatic |
Definition at line 1020 of file SIInstrInfo.h.
References MI, and llvm::SIInstrFlags::VM_CNT.
Referenced by mayAccessVMEMThroughFlat().
◆ verifyInstruction()
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override |
Definition at line 5102 of file SIInstrInfo.cpp.
References llvm::SISrcMods::ABS, llvm::all_of(), assert(), compareMachineOp(), llvm::TargetRegisterClass::contains(), llvm::Data, llvm::dbgs(), llvm::divideCeil(), llvm::AMDGPU::SDWA::DWORD, findImplicitSGPRRead(), llvm::get(), llvm::AMDGPU::getAddrSizeMIMGOp(), llvm::AMDGPU::getBasicFromSDWAOp(), llvm::getImm(), llvm::MachineOperand::getImm(), llvm::AMDGPU::getMIMGBaseOpcodeInfo(), llvm::AMDGPU::getMIMGDimInfoByEncoding(), llvm::AMDGPU::getMIMGInfo(), getNamedOperand(), getOpRegClass(), getOpSize(), llvm::MachineOperand::getReg(), llvm::SrcOp::getReg(), llvm::MachineFunction::getRegInfo(), llvm::MachineOperand::getSubReg(), llvm::AMDGPUSubtarget::GFX10, I, llvm::is_contained(), llvm::AMDGPU::isDPALU_DPP(), isDS(), llvm::MachineOperand::isFI(), isFLAT(), llvm::MachineOperand::isFPImm(), isGather4(), llvm::AMDGPU::isGFX12Plus(), llvm::MachineOperand::isIdenticalTo(), isImage(), llvm::MachineOperand::isImm(), llvm::MachineOperand::isImplicit(), isInlineConstant(), llvm::isInt(), llvm::AMDGPU::isLegalDPALU_DPPControl(), isLegalGFX12PlusPackedMathFP32Operand(), isMIMG(), llvm::AMDGPU::isPackedFP32Inst(), llvm::Register::isPhysical(), llvm::MachineOperand::isReg(), isRegOrFI(), isSALU(), isSDWA(), isSMRD(), isSOP2(), isSOPC(), isSOPK(), isSubRegOf(), llvm::isUInt(), llvm::MachineOperand::isUse(), isVALU(), isVGPRSpill(), llvm::Register::isVirtual(), isVOP2(), isVOP3(), isVOPC(), isVSAMPLE(), LLVM_DEBUG, MI, llvm::InlineAsm::MIOp_FirstOperand, MRI, llvm::SISrcMods::NEG, llvm::Offset, llvm::MCOI::OPERAND_IMMEDIATE, llvm::AMDGPU::OPERAND_INLINE_C_AV64_PSEUDO, llvm::AMDGPU::OPERAND_INLINE_SPLIT_BARRIER_INT32, llvm::AMDGPU::OPERAND_INPUT_MODS, llvm::AMDGPU::OPERAND_KIMM16, llvm::AMDGPU::OPERAND_KIMM32, llvm::AMDGPU::OPERAND_KIMM64, llvm::MCOI::OPERAND_MEMORY, llvm::MCOI::OPERAND_PCREL, llvm::AMDGPU::OPERAND_REG_IMM_BF16, llvm::AMDGPU::OPERAND_REG_IMM_FP16, llvm::AMDGPU::OPERAND_REG_IMM_FP32, llvm::AMDGPU::OPERAND_REG_IMM_FP64, llvm::AMDGPU::OPERAND_REG_IMM_INT16, llvm::AMDGPU::OPERAND_REG_IMM_INT32, llvm::AMDGPU::OPERAND_REG_IMM_INT64, llvm::AMDGPU::OPERAND_REG_IMM_NOINLINE_V2FP16, llvm::AMDGPU::OPERAND_REG_IMM_V2BF16, llvm::AMDGPU::OPERAND_REG_IMM_V2FP16, llvm::AMDGPU::OPERAND_REG_IMM_V2FP32, llvm::AMDGPU::OPERAND_REG_IMM_V2INT16, llvm::AMDGPU::OPERAND_REG_IMM_V2INT32, llvm::AMDGPU::OPERAND_REG_INLINE_AC_FP32, llvm::AMDGPU::OPERAND_REG_INLINE_AC_FP64, llvm::AMDGPU::OPERAND_REG_INLINE_AC_INT32, llvm::AMDGPU::OPERAND_REG_INLINE_C_BF16, llvm::AMDGPU::OPERAND_REG_INLINE_C_FP16, llvm::AMDGPU::OPERAND_REG_INLINE_C_FP32, llvm::AMDGPU::OPERAND_REG_INLINE_C_FP64, llvm::AMDGPU::OPERAND_REG_INLINE_C_INT16, llvm::AMDGPU::OPERAND_REG_INLINE_C_INT32, llvm::AMDGPU::OPERAND_REG_INLINE_C_INT64, llvm::AMDGPU::OPERAND_REG_INLINE_C_V2BF16, llvm::AMDGPU::OPERAND_REG_INLINE_C_V2FP16, llvm::AMDGPU::OPERAND_REG_INLINE_C_V2INT16, llvm::MCOI::OPERAND_REGISTER, llvm::AMDGPU::OPERAND_SDWA_VOPC_DST, llvm::MCOI::OPERAND_UNKNOWN, OpIdx, llvm::popcount(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::AMDGPU::CPol::SCAL, llvm::SISrcMods::SEXT, shouldReadExec(), sopkIsZext(), llvm::AMDGPU::supportsScaleOffset(), llvm::AMDGPU::SDWA::UNUSED_PRESERVE, usesConstantBus(), and llvm::AMDGPUSubtarget::VOLCANIC_ISLANDS.
Referenced by llvm::AMDGPUAsmPrinter::emitInstruction().
The documentation for this class was generated from the following files:
- lib/Target/AMDGPU/SIInstrInfo.h
- lib/Target/AMDGPU/SIInstrInfo.cpp
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