47#define DEBUG_TYPE "reg-scavenging"
49STATISTIC(NumScavengedRegs,
"Number of frame index regs scavenged");
64 for (ScavengedInfo &SI : Scavenged) {
87 for (ScavengedInfo &
I : Scavenged) {
88 if (
I.Restore == &
MI) {
97 return includeReserved;
127static std::pair<MCPhysReg, MachineBasicBlock::iterator>
132 bool FoundTo =
false;
141 assert(
From->getParent() == To->getParent() &&
142 "Target instruction is in other than current basic block, use "
143 "enterBasicBlockEnd first");
153 if (!
MRI.isReserved(Reg) && Used.available(Reg) &&
155 return std::make_pair(Reg,
MBB.
end());
165 Used.accumulate(*std::next(
From));
175 if (Survivor == 0 || !Used.available(Survivor)) {
178 if (!
MRI.isReserved(Reg) && Used.available(Reg)) {
183 if (AvilableReg == 0)
185 Survivor = AvilableReg;
187 if (--InstrCountDown == 0)
192 bool FoundVReg =
false;
194 if (MO.isReg() && MO.getReg().isVirtual()) {
207 "iterating backwards");
210 return std::make_pair(Survivor, Pos);
215 while (!
MI.getOperand(i).isFI()) {
217 assert(i <
MI.getNumOperands() &&
"Instr doesn't have FrameIndex operand!");
222RegScavenger::ScavengedInfo &
233 unsigned SI = Scavenged.
size(), Diff = std::numeric_limits<unsigned>::max();
235 for (
unsigned I = 0;
I < Scavenged.
size(); ++
I) {
236 if (Scavenged[
I].Reg != 0)
239 int FI = Scavenged[
I].FrameIndex;
240 if (FI < FIB || FI >= FIE)
244 if (NeedSize > S || NeedAlign >
A)
252 unsigned D = (S - NeedSize) + (
A.value() - NeedAlign.
value());
259 if (SI == Scavenged.
size()) {
266 Scavenged[
SI].Reg =
Reg;
272 int FI = Scavenged[
SI].FrameIndex;
273 if (FI < FIB || FI >= FIE) {
275 TRI->
getName(Reg) +
" from class " +
277 ": Cannot scavenge register without an emergency "
293 return Scavenged[
SI];
298 bool RestoreAfter,
int SPAdj,
311 if (Reg != 0 && SpillBefore ==
MBB.
end()) {
320 assert(Reg != 0 &&
"No register left to scavenge!");
323 RestoreAfter ? std::next(MBBI) : MBBI;
324 if (ReloadBefore !=
MBB.
end())
326 ScavengedInfo &Scavenged = spill(Reg, RC, SPAdj, SpillBefore, ReloadBefore);
327 Scavenged.Restore = &*std::prev(SpillBefore);
330 <<
" until " << *SpillBefore);
349 if (CommonMBB ==
nullptr)
351 assert(
MBB == CommonMBB &&
"All defs+uses must be in the same basic block");
354 if (!
MI.readsRegister(VReg, &
TRI)) {
355 assert((!RealDef || RealDef == &
MI) &&
356 "Can have at most one definition which is not a redefinition");
361 assert(RealDef !=
nullptr &&
"Must have at least 1 Def");
372 return !MO.getParent()->readsRegister(VReg, &TRI);
375 "Must have one definition that does not redefine vreg");
383 ReserveAfter, SPAdj);
384 MRI.replaceRegWith(VReg, SReg);
398 unsigned InitialNumVirtRegs =
MRI.getNumVirtRegs();
399 bool NextInstructionReadsVReg =
false;
406 if (NextInstructionReadsVReg) {
416 if (!Reg.isVirtual() ||
423 N->addRegisterKilled(SReg, &
TRI,
false);
429 NextInstructionReadsVReg =
false;
436 if (!Reg.isVirtual() ||
442 assert(!MO.isInternalRead() &&
"Cannot assign inside bundles");
443 assert((!MO.isUndef() || MO.isDef()) &&
"Cannot handle undef uses");
445 NextInstructionReadsVReg =
true;
449 I->addRegisterDead(SReg, &
TRI,
false);
455 if (!MO.isReg() || !MO.getReg().isVirtual())
457 assert(!MO.isInternalRead() &&
"Cannot assign inside bundles");
458 assert((!MO.isUndef() || MO.isDef()) &&
"Cannot handle undef uses");
459 assert(!MO.readsReg() &&
"Vreg use in first instruction not allowed");
463 return MRI.getNumVirtRegs() != InitialNumVirtRegs;
472 if (
MRI.getNumVirtRegs() == 0) {
484 LLVM_DEBUG(
dbgs() <<
"Warning: Required two scavenging passes for block "
528char ScavengerTest::ID;
531 "Scavenge virtual registers inside basic blocks",
false,
false)
unsigned const MachineRegisterInfo * MRI
MachineInstrBuilder & UseMI
MachineInstrBuilder MachineInstrBuilder & DefMI
This file implements the BitVector class.
BlockVerifier::State From
static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")
static GCRegistry::Add< StatepointGC > D("statepoint-example", "an example strategy for statepoint")
static cl::opt< unsigned > InstrLimit("dfa-instr-limit", cl::Hidden, cl::init(0), cl::desc("If present, stops packetizing after N instructions"))
unsigned const TargetRegisterInfo * TRI
uint64_t IntrinsicInst * II
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
static Register scavengeVReg(MachineRegisterInfo &MRI, RegScavenger &RS, Register VReg, bool ReserveAfter)
Allocate a register for the virtual register VReg.
static unsigned getFrameIndexOperandNum(MachineInstr &MI)
static bool scavengeFrameVirtualRegsInBlock(MachineRegisterInfo &MRI, RegScavenger &RS, MachineBasicBlock &MBB)
Allocate (scavenge) vregs inside a single basic block.
static std::pair< MCPhysReg, MachineBasicBlock::iterator > findSurvivorBackwards(const MachineRegisterInfo &MRI, MachineBasicBlock::iterator From, MachineBasicBlock::iterator To, const LiveRegUnits &LiveOut, ArrayRef< MCPhysReg > AllocationOrder, bool RestoreAfter)
Given the bitvector Available of free register units at position From.
This file declares the machine register scavenger class.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file defines the SmallVector class.
This file defines the 'Statistic' class, which is designed to be an easy way to expose various metric...
#define STATISTIC(VARNAME, DESC)
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
A set of register units used to track register liveness.
void addRegMasked(MCPhysReg Reg, LaneBitmask Mask)
Adds register units covered by physical register Reg that are part of the lanemask Mask.
bool available(MCPhysReg Reg) const
Returns true if no part of physical register Reg is live.
void init(const TargetRegisterInfo &TRI)
Initialize and clear the set.
void stepBackward(const MachineInstr &MI)
Updates liveness when stepping backwards over the instruction MI.
void addLiveOuts(const MachineBasicBlock &MBB)
Adds registers living out of block MBB.
void addLiveIns(const MachineBasicBlock &MBB)
Adds registers living into block MBB.
void removeReg(MCPhysReg Reg)
Removes all register units covered by physical register Reg.
const char * getName(MCRegister RegNo) const
Return the human-readable symbolic target-specific name for the specified physical register.
unsigned getNumRegs() const
Return the number of registers this target has (useful for sizing arrays holding per register informa...
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
StringRef getName() const
Return the name of the corresponding LLVM basic block, or an empty string.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Align getObjectAlign(int ObjectIdx) const
Return the alignment of the specified stack object.
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
int getObjectIndexEnd() const
Return one past the maximum frame object index.
int getObjectIndexBegin() const
Return the minimum frame object index.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
MachineFunctionProperties & set(Property P)
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
const MachineFunctionProperties & getProperties() const
Get the function properties.
Representation of each machine instruction.
iterator_range< mop_iterator > operands()
MachineOperand class - Representation of each machine instruction operand.
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
reg_begin/reg_end - Provide iteration support to walk over all definitions and uses of a register wit...
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
void enterBasicBlockEnd(MachineBasicBlock &MBB)
Start tracking liveness from the end of basic block MBB.
bool isRegUsed(Register Reg, bool includeReserved=true) const
Return if a specific register is currently used.
Register FindUnusedReg(const TargetRegisterClass *RC) const
Find an unused register of the specified register class.
void setRegUsed(Register Reg, LaneBitmask LaneMask=LaneBitmask::getAll())
Tell the scavenger a register is used.
void backward()
Update internal register state and move MBB iterator backwards.
void enterBasicBlock(MachineBasicBlock &MBB)
Start tracking liveness from the begin of basic block MBB.
Register scavengeRegisterBackwards(const TargetRegisterClass &RC, MachineBasicBlock::iterator To, bool RestoreAfter, int SPAdj, bool AllowSpill=true)
Make a register of the specific register class available from the current position backwards to the p...
BitVector getRegsAvailable(const TargetRegisterClass *RC)
Return all available registers in the register class in Mask.
Wrapper class representing virtual and physical registers.
static unsigned virtReg2Index(Register Reg)
Convert a virtual register number to a 0-based index.
void push_back(const T &Elt)
Information about stack frame layout on the target.
virtual void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS=nullptr) const
This method determines which of the registers reported by TargetRegisterInfo::getCalleeSavedRegs() sh...
virtual void processFunctionBeforeFrameFinalized(MachineFunction &MF, RegScavenger *RS=nullptr) const
processFunctionBeforeFrameFinalized - This method is called immediately before the specified function...
virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const
Load the specified register of the given register class from the specified stack frame index.
virtual void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const
Store the specified register of the given register class to the specified stack frame index.
ArrayRef< MCPhysReg > getRawAllocationOrder(const MachineFunction &MF) const
Returns the preferred order for allocating registers from this register class in MF.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Align getSpillAlign(const TargetRegisterClass &RC) const
Return the minimum required alignment in bytes for a spill slot for a register of this class.
virtual bool eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const =0
This method must be overriden to eliminate abstract frame indices from instructions which may use the...
virtual bool saveScavengerRegister(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, MachineBasicBlock::iterator &UseMI, const TargetRegisterClass *RC, Register Reg) const
Spill the register so it can be used by the register scavenger.
unsigned getSpillSize(const TargetRegisterClass &RC) const
Return the size in bytes of the stack slot allocated to hold a spilled copy of a register from class ...
const char * getRegClassName(const TargetRegisterClass *Class) const
Returns the name of the register class.
TargetSubtargetInfo - Generic base class for all target subtargets.
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
virtual const TargetFrameLowering * getFrameLowering() const
virtual const TargetInstrInfo * getInstrInfo() const
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Reg
All possible values of the reg field in the ModR/M byte.
This is an optimization pass for GlobalISel generic memory operations.
void scavengeFrameVirtualRegs(MachineFunction &MF, RegScavenger &RS)
Replaces all frame index virtual registers with physical registers.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
auto find_if(R &&Range, UnaryPredicate P)
Provide wrappers to std::find_if which take ranges instead of having to pass begin/end explicitly.
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
This struct is a compact representation of a valid (non-zero power of two) alignment.
uint64_t value() const
This is a hole in the type system and should not be abused.