14#ifndef LLVM_CODEGEN_LIVEREGUNITS_H
15#define LLVM_CODEGEN_LIVEREGUNITS_H
27class MachineBasicBlock;
57 if (!
Reg.isPhysical())
63 if (!
TRI->isConstantPhysReg(
Reg))
66 assert(O->isUse() &&
"Reg operand not a def and not a use");
96 if ((UnitMask & Mask).any())
97 Units.
set((*Unit).first);
118 if (Units.
test(Unit))
149 Units.
reset(RegUnits);
164inline iterator_range<
168 return MOP.isRegMask() ||
169 (MOP.isReg() && !MOP.isDebug() && MOP.getReg().isPhysical());
This file implements the BitVector class.
A common definition of LaneBitmask for use in TableGen and CodeGen.
unsigned const TargetRegisterInfo * TRI
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool test(unsigned Idx) const
void resize(unsigned N, bool t=false)
resize - Grow or shrink the bitvector.
bool none() const
none - Returns true if none of the bits are set.
ConstMIBundleOperands - Iterate over all operands in a const bundle of machine instructions.
A set of register units used to track register liveness.
static void accumulateUsedDefed(const MachineInstr &MI, LiveRegUnits &ModifiedRegUnits, LiveRegUnits &UsedRegUnits, const TargetRegisterInfo *TRI)
For a machine instruction MI, adds all register units used in UsedRegUnits and defined or clobbered i...
LiveRegUnits(const TargetRegisterInfo &TRI)
Constructs and initialize an empty LiveRegUnits set.
const BitVector & getBitVector() const
Return the internal bitvector representation of the set.
void addRegMasked(MCPhysReg Reg, LaneBitmask Mask)
Adds register units covered by physical register Reg that are part of the lanemask Mask.
bool available(MCPhysReg Reg) const
Returns true if no part of physical register Reg is live.
void addRegsInMask(const uint32_t *RegMask)
Adds register units not preserved by the regmask RegMask.
void init(const TargetRegisterInfo &TRI)
Initialize and clear the set.
LiveRegUnits()=default
Constructs a new empty LiveRegUnits set.
void stepBackward(const MachineInstr &MI)
Updates liveness when stepping backwards over the instruction MI.
void addReg(MCPhysReg Reg)
Adds register units covered by physical register Reg.
void addLiveOuts(const MachineBasicBlock &MBB)
Adds registers living out of block MBB.
void addUnits(const BitVector &RegUnits)
Adds all register units marked in the bitvector RegUnits.
bool empty() const
Returns true if the set is empty.
void addLiveIns(const MachineBasicBlock &MBB)
Adds registers living into block MBB.
void removeUnits(const BitVector &RegUnits)
Removes all register units marked in the bitvector RegUnits.
void removeRegsNotPreserved(const uint32_t *RegMask)
Removes register units not preserved by the regmask RegMask.
void removeReg(MCPhysReg Reg)
Removes all register units covered by physical register Reg.
void clear()
Clears the set.
void accumulate(const MachineInstr &MI)
Adds all register units used, defined or clobbered in MI.
MCRegUnitMaskIterator enumerates a list of register units and their associated lane masks for Reg.
Representation of each machine instruction.
MachineOperand class - Representation of each machine instruction operand.
Wrapper class representing virtual and physical registers.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This is an optimization pass for GlobalISel generic memory operations.
iterator_range< filter_iterator< ConstMIBundleOperands, bool(*)(const MachineOperand &)> > phys_regs_and_masks(const MachineInstr &MI)
Returns an iterator range over all physical register and mask operands for MI and bundled instruction...
iterator_range< filter_iterator< detail::IterOfRange< RangeT >, PredicateT > > make_filter_range(RangeT &&Range, PredicateT Pred)
Convenience function that takes a range of elements and a predicate, and return a new filter_iterator...
iterator_range< ConstMIBundleOperands > const_mi_bundle_ops(const MachineInstr &MI)
filter_iterator_impl< WrappedIteratorT, PredicateT, typename detail::fwd_or_bidi_tag< WrappedIteratorT >::type > filter_iterator
Defines filter_iterator to a suitable specialization of filter_iterator_impl, based on the underlying...