LLVM 20.0.0git
MachineIRBuilder.h
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1//===-- llvm/CodeGen/GlobalISel/MachineIRBuilder.h - MIBuilder --*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8/// \file
9/// This file declares the MachineIRBuilder class.
10/// This is a helper class to build MachineInstr.
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_CODEGEN_GLOBALISEL_MACHINEIRBUILDER_H
14#define LLVM_CODEGEN_GLOBALISEL_MACHINEIRBUILDER_H
15
22#include "llvm/IR/DebugLoc.h"
23#include "llvm/IR/Module.h"
24
25namespace llvm {
26
27// Forward declarations.
28class APInt;
29class BlockAddress;
30class Constant;
31class ConstantFP;
32class ConstantInt;
33class DataLayout;
34class GISelCSEInfo;
35class GlobalValue;
36class TargetRegisterClass;
37class MachineFunction;
38class MachineInstr;
39class TargetInstrInfo;
40class GISelChangeObserver;
41
42/// Class which stores all the state required in a MachineIRBuilder.
43/// Since MachineIRBuilders will only store state in this object, it allows
44/// to transfer BuilderState between different kinds of MachineIRBuilders.
46 /// MachineFunction under construction.
47 MachineFunction *MF = nullptr;
48 /// Information used to access the description of the opcodes.
49 const TargetInstrInfo *TII = nullptr;
50 /// Information used to verify types are consistent and to create virtual registers.
52 /// Debug location to be set to any instruction we create.
54 /// PC sections metadata to be set to any instruction we create.
55 MDNode *PCSections = nullptr;
56 /// MMRA Metadata to be set on any instruction we create.
57 MDNode *MMRA = nullptr;
58
59 /// \name Fields describing the insertion point.
60 /// @{
63 /// @}
64
66
68};
69
70class DstOp {
71 union {
76 };
77
78public:
80 DstOp(unsigned R) : Reg(R), Ty(DstType::Ty_Reg) {}
81 DstOp(Register R) : Reg(R), Ty(DstType::Ty_Reg) {}
83 DstOp(const LLT T) : LLTTy(T), Ty(DstType::Ty_LLT) {}
84 DstOp(const TargetRegisterClass *TRC) : RC(TRC), Ty(DstType::Ty_RC) {}
88 : Attrs({RCOrRB, Ty}), Ty(DstType::Ty_VRegAttrs) {}
89
91 switch (Ty) {
92 case DstType::Ty_Reg:
93 MIB.addDef(Reg);
94 break;
95 case DstType::Ty_LLT:
96 MIB.addDef(MRI.createGenericVirtualRegister(LLTTy));
97 break;
98 case DstType::Ty_RC:
99 MIB.addDef(MRI.createVirtualRegister(RC));
100 break;
102 MIB.addDef(MRI.createVirtualRegister(Attrs));
103 break;
104 }
105 }
106
108 switch (Ty) {
109 case DstType::Ty_RC:
110 return LLT{};
111 case DstType::Ty_LLT:
112 return LLTTy;
113 case DstType::Ty_Reg:
114 return MRI.getType(Reg);
116 return Attrs.Ty;
117 }
118 llvm_unreachable("Unrecognised DstOp::DstType enum");
119 }
120
121 Register getReg() const {
122 assert(Ty == DstType::Ty_Reg && "Not a register");
123 return Reg;
124 }
125
127 assert(Ty == DstType::Ty_RC && "Not a RC Operand");
128 return RC;
129 }
130
132 assert(Ty == DstType::Ty_VRegAttrs && "Not a VRegAttrs Operand");
133 return Attrs;
134 }
135
136 DstType getDstOpKind() const { return Ty; }
137
138private:
139 DstType Ty;
140};
141
142class SrcOp {
143 union {
147 int64_t Imm;
148 };
149
150public:
152 SrcOp(Register R) : Reg(R), Ty(SrcType::Ty_Reg) {}
154 SrcOp(const MachineInstrBuilder &MIB) : SrcMIB(MIB), Ty(SrcType::Ty_MIB) {}
156 /// Use of registers held in unsigned integer variables (or more rarely signed
157 /// integers) is no longer permitted to avoid ambiguity with upcoming support
158 /// for immediates.
159 SrcOp(unsigned) = delete;
160 SrcOp(int) = delete;
161 SrcOp(uint64_t V) : Imm(V), Ty(SrcType::Ty_Imm) {}
162 SrcOp(int64_t V) : Imm(V), Ty(SrcType::Ty_Imm) {}
163
165 switch (Ty) {
167 MIB.addPredicate(Pred);
168 break;
169 case SrcType::Ty_Reg:
170 MIB.addUse(Reg);
171 break;
172 case SrcType::Ty_MIB:
173 MIB.addUse(SrcMIB->getOperand(0).getReg());
174 break;
175 case SrcType::Ty_Imm:
176 MIB.addImm(Imm);
177 break;
178 }
179 }
180
182 switch (Ty) {
184 case SrcType::Ty_Imm:
185 llvm_unreachable("Not a register operand");
186 case SrcType::Ty_Reg:
187 return MRI.getType(Reg);
188 case SrcType::Ty_MIB:
189 return MRI.getType(SrcMIB->getOperand(0).getReg());
190 }
191 llvm_unreachable("Unrecognised SrcOp::SrcType enum");
192 }
193
194 Register getReg() const {
195 switch (Ty) {
197 case SrcType::Ty_Imm:
198 llvm_unreachable("Not a register operand");
199 case SrcType::Ty_Reg:
200 return Reg;
201 case SrcType::Ty_MIB:
202 return SrcMIB->getOperand(0).getReg();
203 }
204 llvm_unreachable("Unrecognised SrcOp::SrcType enum");
205 }
206
208 switch (Ty) {
210 return Pred;
211 default:
212 llvm_unreachable("Not a register operand");
213 }
214 }
215
216 int64_t getImm() const {
217 switch (Ty) {
218 case SrcType::Ty_Imm:
219 return Imm;
220 default:
221 llvm_unreachable("Not an immediate");
222 }
223 }
224
225 SrcType getSrcOpKind() const { return Ty; }
226
227private:
228 SrcType Ty;
229};
230
231/// Helper class to build MachineInstr.
232/// It keeps internally the insertion point and debug location for all
233/// the new instructions we want to create.
234/// This information can be modified via the related setters.
236
238
239 unsigned getOpcodeForMerge(const DstOp &DstOp, ArrayRef<SrcOp> SrcOps) const;
240
241protected:
242 void validateTruncExt(const LLT Dst, const LLT Src, bool IsExtend);
243
244 void validateUnaryOp(const LLT Res, const LLT Op0);
245 void validateBinaryOp(const LLT Res, const LLT Op0, const LLT Op1);
246 void validateShiftOp(const LLT Res, const LLT Op0, const LLT Op1);
247
248 void validateSelectOp(const LLT ResTy, const LLT TstTy, const LLT Op0Ty,
249 const LLT Op1Ty);
250
251 void recordInsertion(MachineInstr *InsertedInstr) const {
252 if (State.Observer)
253 State.Observer->createdInstr(*InsertedInstr);
254 }
255
256public:
257 /// Some constructors for easy use.
258 MachineIRBuilder() = default;
260
262 setMF(*MBB.getParent());
263 setInsertPt(MBB, InsPt);
264 }
265
267 MachineIRBuilder(*MI.getParent(), MI.getIterator()) {
268 setInstr(MI);
269 setDebugLoc(MI.getDebugLoc());
270 }
271
274 setChangeObserver(Observer);
275 }
276
277 virtual ~MachineIRBuilder() = default;
278
279 MachineIRBuilder(const MachineIRBuilderState &BState) : State(BState) {}
280
282 assert(State.TII && "TargetInstrInfo is not set");
283 return *State.TII;
284 }
285
286 /// Getter for the function we currently build.
288 assert(State.MF && "MachineFunction is not set");
289 return *State.MF;
290 }
291
292 const MachineFunction &getMF() const {
293 assert(State.MF && "MachineFunction is not set");
294 return *State.MF;
295 }
296
297 const DataLayout &getDataLayout() const {
298 return getMF().getFunction().getDataLayout();
299 }
300
302 return getMF().getFunction().getContext();
303 }
304
305 /// Getter for DebugLoc
306 const DebugLoc &getDL() { return State.DL; }
307
308 /// Getter for MRI
309 MachineRegisterInfo *getMRI() { return State.MRI; }
310 const MachineRegisterInfo *getMRI() const { return State.MRI; }
311
312 /// Getter for the State
313 MachineIRBuilderState &getState() { return State; }
314
315 /// Setter for the State
316 void setState(const MachineIRBuilderState &NewState) { State = NewState; }
317
318 /// Getter for the basic block we currently build.
319 const MachineBasicBlock &getMBB() const {
320 assert(State.MBB && "MachineBasicBlock is not set");
321 return *State.MBB;
322 }
323
325 return const_cast<MachineBasicBlock &>(
326 const_cast<const MachineIRBuilder *>(this)->getMBB());
327 }
328
329 GISelCSEInfo *getCSEInfo() { return State.CSEInfo; }
330 const GISelCSEInfo *getCSEInfo() const { return State.CSEInfo; }
331
332 /// Current insertion point for new instructions.
334
335 /// Set the insertion point before the specified position.
336 /// \pre MBB must be in getMF().
337 /// \pre II must be a valid iterator in MBB.
339 assert(MBB.getParent() == &getMF() &&
340 "Basic block is in a different function");
341 State.MBB = &MBB;
342 State.II = II;
343 }
344
345 /// @}
346
348
349 /// \name Setters for the insertion point.
350 /// @{
351 /// Set the MachineFunction where to build instructions.
352 void setMF(MachineFunction &MF);
353
354 /// Set the insertion point to the end of \p MBB.
355 /// \pre \p MBB must be contained by getMF().
357 State.MBB = &MBB;
358 State.II = MBB.end();
359 assert(&getMF() == MBB.getParent() &&
360 "Basic block is in a different function");
361 }
362
363 /// Set the insertion point to before MI.
364 /// \pre MI must be in getMF().
366 assert(MI.getParent() && "Instruction is not part of a basic block");
367 setMBB(*MI.getParent());
368 State.II = MI.getIterator();
369 setPCSections(MI.getPCSections());
370 setMMRAMetadata(MI.getMMRAMetadata());
371 }
372 /// @}
373
374 /// Set the insertion point to before MI, and set the debug loc to MI's loc.
375 /// \pre MI must be in getMF().
377 setInstr(MI);
378 setDebugLoc(MI.getDebugLoc());
379 }
380
382 State.Observer = &Observer;
383 }
384
386
387 void stopObservingChanges() { State.Observer = nullptr; }
388
389 bool isObservingChanges() const { return State.Observer != nullptr; }
390 /// @}
391
392 /// Set the debug location to \p DL for all the next build instructions.
393 void setDebugLoc(const DebugLoc &DL) { this->State.DL = DL; }
394
395 /// Get the current instruction's debug location.
396 const DebugLoc &getDebugLoc() { return State.DL; }
397
398 /// Set the PC sections metadata to \p MD for all the next build instructions.
399 void setPCSections(MDNode *MD) { State.PCSections = MD; }
400
401 /// Get the current instruction's PC sections metadata.
402 MDNode *getPCSections() { return State.PCSections; }
403
404 /// Set the PC sections metadata to \p MD for all the next build instructions.
405 void setMMRAMetadata(MDNode *MMRA) { State.MMRA = MMRA; }
406
407 /// Get the current instruction's MMRA metadata.
408 MDNode *getMMRAMetadata() { return State.MMRA; }
409
410 /// Build and insert <empty> = \p Opcode <empty>.
411 /// The insertion point is the one set by the last call of either
412 /// setBasicBlock or setMI.
413 ///
414 /// \pre setBasicBlock or setMI must have been called.
415 ///
416 /// \return a MachineInstrBuilder for the newly created instruction.
418 return insertInstr(buildInstrNoInsert(Opcode));
419 }
420
421 /// Build but don't insert <empty> = \p Opcode <empty>.
422 ///
423 /// \pre setMF, setBasicBlock or setMI must have been called.
424 ///
425 /// \return a MachineInstrBuilder for the newly created instruction.
427
428 /// Insert an existing instruction at the insertion point.
430
431 /// Build and insert a DBG_VALUE instruction expressing the fact that the
432 /// associated \p Variable lives in \p Reg (suitably modified by \p Expr).
434 const MDNode *Expr);
435
436 /// Build and insert a DBG_VALUE instruction expressing the fact that the
437 /// associated \p Variable lives in memory at \p Reg (suitably modified by \p
438 /// Expr).
440 const MDNode *Variable,
441 const MDNode *Expr);
442
443 /// Build and insert a DBG_VALUE instruction expressing the fact that the
444 /// associated \p Variable lives in the stack slot specified by \p FI
445 /// (suitably modified by \p Expr).
446 MachineInstrBuilder buildFIDbgValue(int FI, const MDNode *Variable,
447 const MDNode *Expr);
448
449 /// Build and insert a DBG_VALUE instructions specifying that \p Variable is
450 /// given by \p C (suitably modified by \p Expr).
452 const MDNode *Variable,
453 const MDNode *Expr);
454
455 /// Build and insert a DBG_LABEL instructions specifying that \p Label is
456 /// given. Convert "llvm.dbg.label Label" to "DBG_LABEL Label".
458
459 /// Build and insert \p Res = G_DYN_STACKALLOC \p Size, \p Align
460 ///
461 /// G_DYN_STACKALLOC does a dynamic stack allocation and writes the address of
462 /// the allocated memory into \p Res.
463 /// \pre setBasicBlock or setMI must have been called.
464 /// \pre \p Res must be a generic virtual register with pointer type.
465 ///
466 /// \return a MachineInstrBuilder for the newly created instruction.
468 Align Alignment);
469
470 /// Build and insert \p Res = G_FRAME_INDEX \p Idx
471 ///
472 /// G_FRAME_INDEX materializes the address of an alloca value or other
473 /// stack-based object.
474 ///
475 /// \pre setBasicBlock or setMI must have been called.
476 /// \pre \p Res must be a generic virtual register with pointer type.
477 ///
478 /// \return a MachineInstrBuilder for the newly created instruction.
480
481 /// Build and insert \p Res = G_GLOBAL_VALUE \p GV
482 ///
483 /// G_GLOBAL_VALUE materializes the address of the specified global
484 /// into \p Res.
485 ///
486 /// \pre setBasicBlock or setMI must have been called.
487 /// \pre \p Res must be a generic virtual register with pointer type
488 /// in the same address space as \p GV.
489 ///
490 /// \return a MachineInstrBuilder for the newly created instruction.
492
493 /// Build and insert \p Res = G_CONSTANT_POOL \p Idx
494 ///
495 /// G_CONSTANT_POOL materializes the address of an object in the constant
496 /// pool.
497 ///
498 /// \pre setBasicBlock or setMI must have been called.
499 /// \pre \p Res must be a generic virtual register with pointer type.
500 ///
501 /// \return a MachineInstrBuilder for the newly created instruction.
502 MachineInstrBuilder buildConstantPool(const DstOp &Res, unsigned Idx);
503
504 /// Build and insert \p Res = G_PTR_ADD \p Op0, \p Op1
505 ///
506 /// G_PTR_ADD adds \p Op1 addressible units to the pointer specified by \p Op0,
507 /// storing the resulting pointer in \p Res. Addressible units are typically
508 /// bytes but this can vary between targets.
509 ///
510 /// \pre setBasicBlock or setMI must have been called.
511 /// \pre \p Res and \p Op0 must be generic virtual registers with pointer
512 /// type.
513 /// \pre \p Op1 must be a generic virtual register with scalar type.
514 ///
515 /// \return a MachineInstrBuilder for the newly created instruction.
516 MachineInstrBuilder buildPtrAdd(const DstOp &Res, const SrcOp &Op0,
517 const SrcOp &Op1,
518 std::optional<unsigned> Flags = std::nullopt);
519
520 /// Materialize and insert \p Res = G_PTR_ADD \p Op0, (G_CONSTANT \p Value)
521 ///
522 /// G_PTR_ADD adds \p Value bytes to the pointer specified by \p Op0,
523 /// storing the resulting pointer in \p Res. If \p Value is zero then no
524 /// G_PTR_ADD or G_CONSTANT will be created and \pre Op0 will be assigned to
525 /// \p Res.
526 ///
527 /// \pre setBasicBlock or setMI must have been called.
528 /// \pre \p Op0 must be a generic virtual register with pointer type.
529 /// \pre \p ValueTy must be a scalar type.
530 /// \pre \p Res must be 0. This is to detect confusion between
531 /// materializePtrAdd() and buildPtrAdd().
532 /// \post \p Res will either be a new generic virtual register of the same
533 /// type as \p Op0 or \p Op0 itself.
534 ///
535 /// \return a MachineInstrBuilder for the newly created instruction.
536 std::optional<MachineInstrBuilder> materializePtrAdd(Register &Res,
537 Register Op0,
538 const LLT ValueTy,
540
541 /// Build and insert \p Res = G_PTRMASK \p Op0, \p Op1
543 const SrcOp &Op1) {
544 return buildInstr(TargetOpcode::G_PTRMASK, {Res}, {Op0, Op1});
545 }
546
547 /// Build and insert \p Res = G_PTRMASK \p Op0, \p G_CONSTANT (1 << NumBits) - 1
548 ///
549 /// This clears the low bits of a pointer operand without destroying its
550 /// pointer properties. This has the effect of rounding the address *down* to
551 /// a specified alignment in bits.
552 ///
553 /// \pre setBasicBlock or setMI must have been called.
554 /// \pre \p Res and \p Op0 must be generic virtual registers with pointer
555 /// type.
556 /// \pre \p NumBits must be an integer representing the number of low bits to
557 /// be cleared in \p Op0.
558 ///
559 /// \return a MachineInstrBuilder for the newly created instruction.
560 MachineInstrBuilder buildMaskLowPtrBits(const DstOp &Res, const SrcOp &Op0,
561 uint32_t NumBits);
562
563 /// Build and insert
564 /// a, b, ..., x = G_UNMERGE_VALUES \p Op0
565 /// \p Res = G_BUILD_VECTOR a, b, ..., x, undef, ..., undef
566 ///
567 /// Pad \p Op0 with undef elements to match number of elements in \p Res.
568 ///
569 /// \pre setBasicBlock or setMI must have been called.
570 /// \pre \p Res and \p Op0 must be generic virtual registers with vector type,
571 /// same vector element type and Op0 must have fewer elements then Res.
572 ///
573 /// \return a MachineInstrBuilder for the newly created build vector instr.
575 const SrcOp &Op0);
576
577 /// Build and insert
578 /// a, b, ..., x, y, z = G_UNMERGE_VALUES \p Op0
579 /// \p Res = G_BUILD_VECTOR a, b, ..., x
580 ///
581 /// Delete trailing elements in \p Op0 to match number of elements in \p Res.
582 ///
583 /// \pre setBasicBlock or setMI must have been called.
584 /// \pre \p Res and \p Op0 must be generic virtual registers with vector type,
585 /// same vector element type and Op0 must have more elements then Res.
586 ///
587 /// \return a MachineInstrBuilder for the newly created build vector instr.
589 const SrcOp &Op0);
590
591 /// Build and insert \p Res, \p CarryOut = G_UADDO \p Op0, \p Op1
592 ///
593 /// G_UADDO sets \p Res to \p Op0 + \p Op1 (truncated to the bit width) and
594 /// sets \p CarryOut to 1 if the result overflowed in unsigned arithmetic.
595 ///
596 /// \pre setBasicBlock or setMI must have been called.
597 /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers with the
598 /// same scalar type.
599 ////\pre \p CarryOut must be generic virtual register with scalar type
600 ///(typically s1)
601 ///
602 /// \return The newly created instruction.
603 MachineInstrBuilder buildUAddo(const DstOp &Res, const DstOp &CarryOut,
604 const SrcOp &Op0, const SrcOp &Op1) {
605 return buildInstr(TargetOpcode::G_UADDO, {Res, CarryOut}, {Op0, Op1});
606 }
607
608 /// Build and insert \p Res, \p CarryOut = G_USUBO \p Op0, \p Op1
609 MachineInstrBuilder buildUSubo(const DstOp &Res, const DstOp &CarryOut,
610 const SrcOp &Op0, const SrcOp &Op1) {
611 return buildInstr(TargetOpcode::G_USUBO, {Res, CarryOut}, {Op0, Op1});
612 }
613
614 /// Build and insert \p Res, \p CarryOut = G_SADDO \p Op0, \p Op1
615 MachineInstrBuilder buildSAddo(const DstOp &Res, const DstOp &CarryOut,
616 const SrcOp &Op0, const SrcOp &Op1) {
617 return buildInstr(TargetOpcode::G_SADDO, {Res, CarryOut}, {Op0, Op1});
618 }
619
620 /// Build and insert \p Res, \p CarryOut = G_SUBO \p Op0, \p Op1
621 MachineInstrBuilder buildSSubo(const DstOp &Res, const DstOp &CarryOut,
622 const SrcOp &Op0, const SrcOp &Op1) {
623 return buildInstr(TargetOpcode::G_SSUBO, {Res, CarryOut}, {Op0, Op1});
624 }
625
626 /// Build and insert \p Res, \p CarryOut = G_UADDE \p Op0,
627 /// \p Op1, \p CarryIn
628 ///
629 /// G_UADDE sets \p Res to \p Op0 + \p Op1 + \p CarryIn (truncated to the bit
630 /// width) and sets \p CarryOut to 1 if the result overflowed in unsigned
631 /// arithmetic.
632 ///
633 /// \pre setBasicBlock or setMI must have been called.
634 /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
635 /// with the same scalar type.
636 /// \pre \p CarryOut and \p CarryIn must be generic virtual
637 /// registers with the same scalar type (typically s1)
638 ///
639 /// \return The newly created instruction.
640 MachineInstrBuilder buildUAdde(const DstOp &Res, const DstOp &CarryOut,
641 const SrcOp &Op0, const SrcOp &Op1,
642 const SrcOp &CarryIn) {
643 return buildInstr(TargetOpcode::G_UADDE, {Res, CarryOut},
644 {Op0, Op1, CarryIn});
645 }
646
647 /// Build and insert \p Res, \p CarryOut = G_USUBE \p Op0, \p Op1, \p CarryInp
648 MachineInstrBuilder buildUSube(const DstOp &Res, const DstOp &CarryOut,
649 const SrcOp &Op0, const SrcOp &Op1,
650 const SrcOp &CarryIn) {
651 return buildInstr(TargetOpcode::G_USUBE, {Res, CarryOut},
652 {Op0, Op1, CarryIn});
653 }
654
655 /// Build and insert \p Res, \p CarryOut = G_SADDE \p Op0, \p Op1, \p CarryInp
656 MachineInstrBuilder buildSAdde(const DstOp &Res, const DstOp &CarryOut,
657 const SrcOp &Op0, const SrcOp &Op1,
658 const SrcOp &CarryIn) {
659 return buildInstr(TargetOpcode::G_SADDE, {Res, CarryOut},
660 {Op0, Op1, CarryIn});
661 }
662
663 /// Build and insert \p Res, \p CarryOut = G_SSUBE \p Op0, \p Op1, \p CarryInp
664 MachineInstrBuilder buildSSube(const DstOp &Res, const DstOp &CarryOut,
665 const SrcOp &Op0, const SrcOp &Op1,
666 const SrcOp &CarryIn) {
667 return buildInstr(TargetOpcode::G_SSUBE, {Res, CarryOut},
668 {Op0, Op1, CarryIn});
669 }
670
671 /// Build and insert \p Res = G_ANYEXT \p Op0
672 ///
673 /// G_ANYEXT produces a register of the specified width, with bits 0 to
674 /// sizeof(\p Ty) * 8 set to \p Op. The remaining bits are unspecified
675 /// (i.e. this is neither zero nor sign-extension). For a vector register,
676 /// each element is extended individually.
677 ///
678 /// \pre setBasicBlock or setMI must have been called.
679 /// \pre \p Res must be a generic virtual register with scalar or vector type.
680 /// \pre \p Op must be a generic virtual register with scalar or vector type.
681 /// \pre \p Op must be smaller than \p Res
682 ///
683 /// \return The newly created instruction.
684
685 MachineInstrBuilder buildAnyExt(const DstOp &Res, const SrcOp &Op);
686
687 /// Build and insert \p Res = G_SEXT \p Op
688 ///
689 /// G_SEXT produces a register of the specified width, with bits 0 to
690 /// sizeof(\p Ty) * 8 set to \p Op. The remaining bits are duplicated from the
691 /// high bit of \p Op (i.e. 2s-complement sign extended).
692 ///
693 /// \pre setBasicBlock or setMI must have been called.
694 /// \pre \p Res must be a generic virtual register with scalar or vector type.
695 /// \pre \p Op must be a generic virtual register with scalar or vector type.
696 /// \pre \p Op must be smaller than \p Res
697 ///
698 /// \return The newly created instruction.
699 MachineInstrBuilder buildSExt(const DstOp &Res, const SrcOp &Op);
700
701 /// Build and insert \p Res = G_SEXT_INREG \p Op, ImmOp
702 MachineInstrBuilder buildSExtInReg(const DstOp &Res, const SrcOp &Op, int64_t ImmOp) {
703 return buildInstr(TargetOpcode::G_SEXT_INREG, {Res}, {Op, SrcOp(ImmOp)});
704 }
705
706 /// Build and insert \p Res = G_FPEXT \p Op
708 std::optional<unsigned> Flags = std::nullopt) {
709 return buildInstr(TargetOpcode::G_FPEXT, {Res}, {Op}, Flags);
710 }
711
712 /// Build and insert a G_PTRTOINT instruction.
714 return buildInstr(TargetOpcode::G_PTRTOINT, {Dst}, {Src});
715 }
716
717 /// Build and insert a G_INTTOPTR instruction.
719 return buildInstr(TargetOpcode::G_INTTOPTR, {Dst}, {Src});
720 }
721
722 /// Build and insert \p Dst = G_BITCAST \p Src
723 MachineInstrBuilder buildBitcast(const DstOp &Dst, const SrcOp &Src) {
724 return buildInstr(TargetOpcode::G_BITCAST, {Dst}, {Src});
725 }
726
727 /// Build and insert \p Dst = G_ADDRSPACE_CAST \p Src
729 return buildInstr(TargetOpcode::G_ADDRSPACE_CAST, {Dst}, {Src});
730 }
731
732 /// \return The opcode of the extension the target wants to use for boolean
733 /// values.
734 unsigned getBoolExtOp(bool IsVec, bool IsFP) const;
735
736 // Build and insert \p Res = G_ANYEXT \p Op, \p Res = G_SEXT \p Op, or \p Res
737 // = G_ZEXT \p Op depending on how the target wants to extend boolean values.
738 MachineInstrBuilder buildBoolExt(const DstOp &Res, const SrcOp &Op,
739 bool IsFP);
740
741 // Build and insert \p Res = G_SEXT_INREG \p Op, 1 or \p Res = G_AND \p Op, 1,
742 // or COPY depending on how the target wants to extend boolean values, using
743 // the original register size.
745 bool IsVector,
746 bool IsFP);
747
748 /// Build and insert \p Res = G_ZEXT \p Op
749 ///
750 /// G_ZEXT produces a register of the specified width, with bits 0 to
751 /// sizeof(\p Ty) * 8 set to \p Op. The remaining bits are 0. For a vector
752 /// register, each element is extended individually.
753 ///
754 /// \pre setBasicBlock or setMI must have been called.
755 /// \pre \p Res must be a generic virtual register with scalar or vector type.
756 /// \pre \p Op must be a generic virtual register with scalar or vector type.
757 /// \pre \p Op must be smaller than \p Res
758 ///
759 /// \return The newly created instruction.
760 MachineInstrBuilder buildZExt(const DstOp &Res, const SrcOp &Op,
761 std::optional<unsigned> Flags = std::nullopt);
762
763 /// Build and insert \p Res = G_SEXT \p Op, \p Res = G_TRUNC \p Op, or
764 /// \p Res = COPY \p Op depending on the differing sizes of \p Res and \p Op.
765 /// ///
766 /// \pre setBasicBlock or setMI must have been called.
767 /// \pre \p Res must be a generic virtual register with scalar or vector type.
768 /// \pre \p Op must be a generic virtual register with scalar or vector type.
769 ///
770 /// \return The newly created instruction.
772
773 /// Build and insert \p Res = G_ZEXT \p Op, \p Res = G_TRUNC \p Op, or
774 /// \p Res = COPY \p Op depending on the differing sizes of \p Res and \p Op.
775 /// ///
776 /// \pre setBasicBlock or setMI must have been called.
777 /// \pre \p Res must be a generic virtual register with scalar or vector type.
778 /// \pre \p Op must be a generic virtual register with scalar or vector type.
779 ///
780 /// \return The newly created instruction.
782
783 // Build and insert \p Res = G_ANYEXT \p Op, \p Res = G_TRUNC \p Op, or
784 /// \p Res = COPY \p Op depending on the differing sizes of \p Res and \p Op.
785 /// ///
786 /// \pre setBasicBlock or setMI must have been called.
787 /// \pre \p Res must be a generic virtual register with scalar or vector type.
788 /// \pre \p Op must be a generic virtual register with scalar or vector type.
789 ///
790 /// \return The newly created instruction.
792
793 /// Build and insert \p Res = \p ExtOpc, \p Res = G_TRUNC \p
794 /// Op, or \p Res = COPY \p Op depending on the differing sizes of \p Res and
795 /// \p Op.
796 /// ///
797 /// \pre setBasicBlock or setMI must have been called.
798 /// \pre \p Res must be a generic virtual register with scalar or vector type.
799 /// \pre \p Op must be a generic virtual register with scalar or vector type.
800 ///
801 /// \return The newly created instruction.
802 MachineInstrBuilder buildExtOrTrunc(unsigned ExtOpc, const DstOp &Res,
803 const SrcOp &Op);
804
805 /// Build and inserts \p Res = \p G_AND \p Op, \p LowBitsSet(ImmOp)
806 /// Since there is no G_ZEXT_INREG like G_SEXT_INREG, the instruction is
807 /// emulated using G_AND.
809 int64_t ImmOp);
810
811 /// Build and insert an appropriate cast between two registers of equal size.
812 MachineInstrBuilder buildCast(const DstOp &Dst, const SrcOp &Src);
813
814 /// Build and insert G_BR \p Dest
815 ///
816 /// G_BR is an unconditional branch to \p Dest.
817 ///
818 /// \pre setBasicBlock or setMI must have been called.
819 ///
820 /// \return a MachineInstrBuilder for the newly created instruction.
822
823 /// Build and insert G_BRCOND \p Tst, \p Dest
824 ///
825 /// G_BRCOND is a conditional branch to \p Dest.
826 ///
827 /// \pre setBasicBlock or setMI must have been called.
828 /// \pre \p Tst must be a generic virtual register with scalar
829 /// type. At the beginning of legalization, this will be a single
830 /// bit (s1). Targets with interesting flags registers may change
831 /// this. For a wider type, whether the branch is taken must only
832 /// depend on bit 0 (for now).
833 ///
834 /// \return The newly created instruction.
836
837 /// Build and insert G_BRINDIRECT \p Tgt
838 ///
839 /// G_BRINDIRECT is an indirect branch to \p Tgt.
840 ///
841 /// \pre setBasicBlock or setMI must have been called.
842 /// \pre \p Tgt must be a generic virtual register with pointer type.
843 ///
844 /// \return a MachineInstrBuilder for the newly created instruction.
846
847 /// Build and insert G_BRJT \p TablePtr, \p JTI, \p IndexReg
848 ///
849 /// G_BRJT is a jump table branch using a table base pointer \p TablePtr,
850 /// jump table index \p JTI and index \p IndexReg
851 ///
852 /// \pre setBasicBlock or setMI must have been called.
853 /// \pre \p TablePtr must be a generic virtual register with pointer type.
854 /// \pre \p JTI must be a jump table index.
855 /// \pre \p IndexReg must be a generic virtual register with pointer type.
856 ///
857 /// \return a MachineInstrBuilder for the newly created instruction.
858 MachineInstrBuilder buildBrJT(Register TablePtr, unsigned JTI,
859 Register IndexReg);
860
861 /// Build and insert \p Res = G_CONSTANT \p Val
862 ///
863 /// G_CONSTANT is an integer constant with the specified size and value. \p
864 /// Val will be extended or truncated to the size of \p Reg.
865 ///
866 /// \pre setBasicBlock or setMI must have been called.
867 /// \pre \p Res must be a generic virtual register with scalar or pointer
868 /// type.
869 ///
870 /// \return The newly created instruction.
871 virtual MachineInstrBuilder buildConstant(const DstOp &Res,
872 const ConstantInt &Val);
873
874 /// Build and insert \p Res = G_CONSTANT \p Val
875 ///
876 /// G_CONSTANT is an integer constant with the specified size and value.
877 ///
878 /// \pre setBasicBlock or setMI must have been called.
879 /// \pre \p Res must be a generic virtual register with scalar type.
880 ///
881 /// \return The newly created instruction.
882 MachineInstrBuilder buildConstant(const DstOp &Res, int64_t Val);
883 MachineInstrBuilder buildConstant(const DstOp &Res, const APInt &Val);
884
885 /// Build and insert \p Res = G_FCONSTANT \p Val
886 ///
887 /// G_FCONSTANT is a floating-point constant with the specified size and
888 /// value.
889 ///
890 /// \pre setBasicBlock or setMI must have been called.
891 /// \pre \p Res must be a generic virtual register with scalar type.
892 ///
893 /// \return The newly created instruction.
894 virtual MachineInstrBuilder buildFConstant(const DstOp &Res,
895 const ConstantFP &Val);
896
897 MachineInstrBuilder buildFConstant(const DstOp &Res, double Val);
898 MachineInstrBuilder buildFConstant(const DstOp &Res, const APFloat &Val);
899
900 /// Build and insert G_PTRAUTH_GLOBAL_VALUE
901 ///
902 /// \return a MachineInstrBuilder for the newly created instruction.
904 const ConstantPtrAuth *CPA,
905 Register Addr, Register AddrDisc);
906
907 /// Build and insert \p Res = COPY Op
908 ///
909 /// Register-to-register COPY sets \p Res to \p Op.
910 ///
911 /// \pre setBasicBlock or setMI must have been called.
912 ///
913 /// \return a MachineInstrBuilder for the newly created instruction.
914 MachineInstrBuilder buildCopy(const DstOp &Res, const SrcOp &Op);
915
916
917 /// Build and insert G_ASSERT_SEXT, G_ASSERT_ZEXT, or G_ASSERT_ALIGN
918 ///
919 /// \return a MachineInstrBuilder for the newly created instruction.
921 const SrcOp &Op, unsigned Val) {
922 return buildInstr(Opc, Res, Op).addImm(Val);
923 }
924
925 /// Build and insert \p Res = G_ASSERT_ZEXT Op, Size
926 ///
927 /// \return a MachineInstrBuilder for the newly created instruction.
929 unsigned Size) {
930 return buildAssertInstr(TargetOpcode::G_ASSERT_ZEXT, Res, Op, Size);
931 }
932
933 /// Build and insert \p Res = G_ASSERT_SEXT Op, Size
934 ///
935 /// \return a MachineInstrBuilder for the newly created instruction.
937 unsigned Size) {
938 return buildAssertInstr(TargetOpcode::G_ASSERT_SEXT, Res, Op, Size);
939 }
940
941 /// Build and insert \p Res = G_ASSERT_ALIGN Op, AlignVal
942 ///
943 /// \return a MachineInstrBuilder for the newly created instruction.
945 Align AlignVal) {
946 return buildAssertInstr(TargetOpcode::G_ASSERT_ALIGN, Res, Op,
947 AlignVal.value());
948 }
949
950 /// Build and insert `Res = G_LOAD Addr, MMO`.
951 ///
952 /// Loads the value stored at \p Addr. Puts the result in \p Res.
953 ///
954 /// \pre setBasicBlock or setMI must have been called.
955 /// \pre \p Res must be a generic virtual register.
956 /// \pre \p Addr must be a generic virtual register with pointer type.
957 ///
958 /// \return a MachineInstrBuilder for the newly created instruction.
960 MachineMemOperand &MMO) {
961 return buildLoadInstr(TargetOpcode::G_LOAD, Res, Addr, MMO);
962 }
963
964 /// Build and insert a G_LOAD instruction, while constructing the
965 /// MachineMemOperand.
967 buildLoad(const DstOp &Res, const SrcOp &Addr, MachinePointerInfo PtrInfo,
968 Align Alignment,
970 const AAMDNodes &AAInfo = AAMDNodes());
971
972 /// Build and insert `Res = <opcode> Addr, MMO`.
973 ///
974 /// Loads the value stored at \p Addr. Puts the result in \p Res.
975 ///
976 /// \pre setBasicBlock or setMI must have been called.
977 /// \pre \p Res must be a generic virtual register.
978 /// \pre \p Addr must be a generic virtual register with pointer type.
979 ///
980 /// \return a MachineInstrBuilder for the newly created instruction.
981 MachineInstrBuilder buildLoadInstr(unsigned Opcode, const DstOp &Res,
982 const SrcOp &Addr, MachineMemOperand &MMO);
983
984 /// Helper to create a load from a constant offset given a base address. Load
985 /// the type of \p Dst from \p Offset from the given base address and memory
986 /// operand.
988 const SrcOp &BasePtr,
989 MachineMemOperand &BaseMMO,
990 int64_t Offset);
991
992 /// Build and insert `G_STORE Val, Addr, MMO`.
993 ///
994 /// Stores the value \p Val to \p Addr.
995 ///
996 /// \pre setBasicBlock or setMI must have been called.
997 /// \pre \p Val must be a generic virtual register.
998 /// \pre \p Addr must be a generic virtual register with pointer type.
999 ///
1000 /// \return a MachineInstrBuilder for the newly created instruction.
1001 MachineInstrBuilder buildStore(const SrcOp &Val, const SrcOp &Addr,
1002 MachineMemOperand &MMO);
1003
1004 /// Build and insert a G_STORE instruction, while constructing the
1005 /// MachineMemOperand.
1007 buildStore(const SrcOp &Val, const SrcOp &Addr, MachinePointerInfo PtrInfo,
1008 Align Alignment,
1010 const AAMDNodes &AAInfo = AAMDNodes());
1011
1012 /// Build and insert `Res0, ... = G_EXTRACT Src, Idx0`.
1013 ///
1014 /// \pre setBasicBlock or setMI must have been called.
1015 /// \pre \p Res and \p Src must be generic virtual registers.
1016 ///
1017 /// \return a MachineInstrBuilder for the newly created instruction.
1018 MachineInstrBuilder buildExtract(const DstOp &Res, const SrcOp &Src, uint64_t Index);
1019
1020 /// Build and insert \p Res = IMPLICIT_DEF.
1022
1023 /// Build and insert \p Res = G_MERGE_VALUES \p Op0, ...
1024 ///
1025 /// G_MERGE_VALUES combines the input elements contiguously into a larger
1026 /// register. It should only be used when the destination register is not a
1027 /// vector.
1028 ///
1029 /// \pre setBasicBlock or setMI must have been called.
1030 /// \pre The entire register \p Res (and no more) must be covered by the input
1031 /// registers.
1032 /// \pre The type of all \p Ops registers must be identical.
1033 ///
1034 /// \return a MachineInstrBuilder for the newly created instruction.
1036 ArrayRef<Register> Ops);
1037
1038 /// Build and insert \p Res = G_MERGE_VALUES \p Op0, ...
1039 /// or \p Res = G_BUILD_VECTOR \p Op0, ...
1040 /// or \p Res = G_CONCAT_VECTORS \p Op0, ...
1041 ///
1042 /// G_MERGE_VALUES combines the input elements contiguously into a larger
1043 /// register. It is used when the destination register is not a vector.
1044 /// G_BUILD_VECTOR combines scalar inputs into a vector register.
1045 /// G_CONCAT_VECTORS combines vector inputs into a vector register.
1046 ///
1047 /// \pre setBasicBlock or setMI must have been called.
1048 /// \pre The entire register \p Res (and no more) must be covered by the input
1049 /// registers.
1050 /// \pre The type of all \p Ops registers must be identical.
1051 ///
1052 /// \return a MachineInstrBuilder for the newly created instruction. The
1053 /// opcode of the new instruction will depend on the types of both
1054 /// the destination and the sources.
1056 ArrayRef<Register> Ops);
1058 std::initializer_list<SrcOp> Ops);
1059
1060 /// Build and insert \p Res0, ... = G_UNMERGE_VALUES \p Op
1061 ///
1062 /// G_UNMERGE_VALUES splits contiguous bits of the input into multiple
1063 ///
1064 /// \pre setBasicBlock or setMI must have been called.
1065 /// \pre The entire register \p Res (and no more) must be covered by the input
1066 /// registers.
1067 /// \pre The type of all \p Res registers must be identical.
1068 ///
1069 /// \return a MachineInstrBuilder for the newly created instruction.
1072
1073 /// Build and insert an unmerge of \p Res sized pieces to cover \p Op
1075
1076 /// Build and insert an unmerge of pieces with \p Attrs register attributes to
1077 /// cover \p Op
1079 const SrcOp &Op);
1080
1081 /// Build and insert \p Res = G_BUILD_VECTOR \p Op0, ...
1082 ///
1083 /// G_BUILD_VECTOR creates a vector value from multiple scalar registers.
1084 /// \pre setBasicBlock or setMI must have been called.
1085 /// \pre The entire register \p Res (and no more) must be covered by the
1086 /// input scalar registers.
1087 /// \pre The type of all \p Ops registers must be identical.
1088 ///
1089 /// \return a MachineInstrBuilder for the newly created instruction.
1091 ArrayRef<Register> Ops);
1092
1093 /// Build and insert \p Res = G_BUILD_VECTOR \p Op0, ... where each OpN is
1094 /// built with G_CONSTANT.
1096 ArrayRef<APInt> Ops);
1097
1098 /// Build and insert \p Res = G_BUILD_VECTOR with \p Src replicated to fill
1099 /// the number of elements
1100 MachineInstrBuilder buildSplatBuildVector(const DstOp &Res, const SrcOp &Src);
1101
1102 /// Build and insert \p Res = G_BUILD_VECTOR_TRUNC \p Op0, ...
1103 ///
1104 /// G_BUILD_VECTOR_TRUNC creates a vector value from multiple scalar registers
1105 /// which have types larger than the destination vector element type, and
1106 /// truncates the values to fit.
1107 ///
1108 /// If the operands given are already the same size as the vector elt type,
1109 /// then this method will instead create a G_BUILD_VECTOR instruction.
1110 ///
1111 /// \pre setBasicBlock or setMI must have been called.
1112 /// \pre The type of all \p Ops registers must be identical.
1113 ///
1114 /// \return a MachineInstrBuilder for the newly created instruction.
1116 ArrayRef<Register> Ops);
1117
1118 /// Build and insert a vector splat of a scalar \p Src using a
1119 /// G_INSERT_VECTOR_ELT and G_SHUFFLE_VECTOR idiom.
1120 ///
1121 /// \pre setBasicBlock or setMI must have been called.
1122 /// \pre \p Src must have the same type as the element type of \p Dst
1123 ///
1124 /// \return a MachineInstrBuilder for the newly created instruction.
1125 MachineInstrBuilder buildShuffleSplat(const DstOp &Res, const SrcOp &Src);
1126
1127 /// Build and insert \p Res = G_SHUFFLE_VECTOR \p Src1, \p Src2, \p Mask
1128 ///
1129 /// \pre setBasicBlock or setMI must have been called.
1130 ///
1131 /// \return a MachineInstrBuilder for the newly created instruction.
1132 MachineInstrBuilder buildShuffleVector(const DstOp &Res, const SrcOp &Src1,
1133 const SrcOp &Src2, ArrayRef<int> Mask);
1134
1135 /// Build and insert \p Res = G_SPLAT_VECTOR \p Val
1136 ///
1137 /// \pre setBasicBlock or setMI must have been called.
1138 /// \pre \p Res must be a generic virtual register with vector type.
1139 /// \pre \p Val must be a generic virtual register with scalar type.
1140 ///
1141 /// \return a MachineInstrBuilder for the newly created instruction.
1142 MachineInstrBuilder buildSplatVector(const DstOp &Res, const SrcOp &Val);
1143
1144 /// Build and insert \p Res = G_CONCAT_VECTORS \p Op0, ...
1145 ///
1146 /// G_CONCAT_VECTORS creates a vector from the concatenation of 2 or more
1147 /// vectors.
1148 ///
1149 /// \pre setBasicBlock or setMI must have been called.
1150 /// \pre The entire register \p Res (and no more) must be covered by the input
1151 /// registers.
1152 /// \pre The type of all source operands must be identical.
1153 ///
1154 /// \return a MachineInstrBuilder for the newly created instruction.
1156 ArrayRef<Register> Ops);
1157
1158 /// Build and insert `Res = G_INSERT_SUBVECTOR Src0, Src1, Idx`.
1159 ///
1160 /// \pre setBasicBlock or setMI must have been called.
1161 /// \pre \p Res, \p Src0, and \p Src1 must be generic virtual registers with
1162 /// vector type.
1163 ///
1164 /// \return a MachineInstrBuilder for the newly created instruction.
1165 MachineInstrBuilder buildInsertSubvector(const DstOp &Res, const SrcOp &Src0,
1166 const SrcOp &Src1, unsigned Index);
1167
1168 /// Build and insert `Res = G_EXTRACT_SUBVECTOR Src, Idx0`.
1169 ///
1170 /// \pre setBasicBlock or setMI must have been called.
1171 /// \pre \p Res and \p Src must be generic virtual registers with vector type.
1172 ///
1173 /// \return a MachineInstrBuilder for the newly created instruction.
1175 unsigned Index);
1176
1177 MachineInstrBuilder buildInsert(const DstOp &Res, const SrcOp &Src,
1178 const SrcOp &Op, unsigned Index);
1179
1180 /// Build and insert \p Res = G_STEP_VECTOR \p Step
1181 ///
1182 /// G_STEP_VECTOR returns a scalable vector of linear sequence of step \p Step
1183 /// into \p Res.
1184 ///
1185 /// \pre setBasicBlock or setMI must have been called.
1186 /// \pre \p Res must be a generic virtual register with scalable vector type.
1187 ///
1188 /// \return a MachineInstrBuilder for the newly created instruction.
1189 MachineInstrBuilder buildStepVector(const DstOp &Res, unsigned Step);
1190
1191 /// Build and insert \p Res = G_VSCALE \p MinElts
1192 ///
1193 /// G_VSCALE puts the value of the runtime vscale multiplied by \p MinElts
1194 /// into \p Res.
1195 ///
1196 /// \pre setBasicBlock or setMI must have been called.
1197 /// \pre \p Res must be a generic virtual register with scalar type.
1198 ///
1199 /// \return a MachineInstrBuilder for the newly created instruction.
1200 MachineInstrBuilder buildVScale(const DstOp &Res, unsigned MinElts);
1201
1202 /// Build and insert \p Res = G_VSCALE \p MinElts
1203 ///
1204 /// G_VSCALE puts the value of the runtime vscale multiplied by \p MinElts
1205 /// into \p Res.
1206 ///
1207 /// \pre setBasicBlock or setMI must have been called.
1208 /// \pre \p Res must be a generic virtual register with scalar type.
1209 ///
1210 /// \return a MachineInstrBuilder for the newly created instruction.
1211 MachineInstrBuilder buildVScale(const DstOp &Res, const ConstantInt &MinElts);
1212
1213 /// Build and insert \p Res = G_VSCALE \p MinElts
1214 ///
1215 /// G_VSCALE puts the value of the runtime vscale multiplied by \p MinElts
1216 /// into \p Res.
1217 ///
1218 /// \pre setBasicBlock or setMI must have been called.
1219 /// \pre \p Res must be a generic virtual register with scalar type.
1220 ///
1221 /// \return a MachineInstrBuilder for the newly created instruction.
1222 MachineInstrBuilder buildVScale(const DstOp &Res, const APInt &MinElts);
1223
1224 /// Build and insert a G_INTRINSIC instruction.
1225 ///
1226 /// There are four different opcodes based on combinations of whether the
1227 /// intrinsic has side effects and whether it is convergent. These properties
1228 /// can be specified as explicit parameters, or else they are retrieved from
1229 /// the MCID for the intrinsic.
1230 ///
1231 /// The parameter \p Res provides the Registers or MOs that will be defined by
1232 /// this instruction.
1233 ///
1234 /// \pre setBasicBlock or setMI must have been called.
1235 ///
1236 /// \return a MachineInstrBuilder for the newly created instruction.
1238 bool HasSideEffects, bool isConvergent);
1241 bool HasSideEffects, bool isConvergent);
1243
1244 /// Build and insert \p Res = G_FPTRUNC \p Op
1245 ///
1246 /// G_FPTRUNC converts a floating-point value into one with a smaller type.
1247 ///
1248 /// \pre setBasicBlock or setMI must have been called.
1249 /// \pre \p Res must be a generic virtual register with scalar or vector type.
1250 /// \pre \p Op must be a generic virtual register with scalar or vector type.
1251 /// \pre \p Res must be smaller than \p Op
1252 ///
1253 /// \return The newly created instruction.
1255 buildFPTrunc(const DstOp &Res, const SrcOp &Op,
1256 std::optional<unsigned> Flags = std::nullopt);
1257
1258 /// Build and insert \p Res = G_TRUNC \p Op
1259 ///
1260 /// G_TRUNC extracts the low bits of a type. For a vector type each element is
1261 /// truncated independently before being packed into the destination.
1262 ///
1263 /// \pre setBasicBlock or setMI must have been called.
1264 /// \pre \p Res must be a generic virtual register with scalar or vector type.
1265 /// \pre \p Op must be a generic virtual register with scalar or vector type.
1266 /// \pre \p Res must be smaller than \p Op
1267 ///
1268 /// \return The newly created instruction.
1269 MachineInstrBuilder buildTrunc(const DstOp &Res, const SrcOp &Op,
1270 std::optional<unsigned> Flags = std::nullopt);
1271
1272 /// Build and insert a \p Res = G_ICMP \p Pred, \p Op0, \p Op1
1273 ///
1274 /// \pre setBasicBlock or setMI must have been called.
1275
1276 /// \pre \p Res must be a generic virtual register with scalar or
1277 /// vector type. Typically this starts as s1 or <N x s1>.
1278 /// \pre \p Op0 and Op1 must be generic virtual registers with the
1279 /// same number of elements as \p Res. If \p Res is a scalar,
1280 /// \p Op0 must be either a scalar or pointer.
1281 /// \pre \p Pred must be an integer predicate.
1282 ///
1283 /// \return a MachineInstrBuilder for the newly created instruction.
1285 const SrcOp &Op0, const SrcOp &Op1,
1286 std::optional<unsigned> Flags = std::nullopt);
1287
1288 /// Build and insert a \p Res = G_FCMP \p Pred\p Op0, \p Op1
1289 ///
1290 /// \pre setBasicBlock or setMI must have been called.
1291
1292 /// \pre \p Res must be a generic virtual register with scalar or
1293 /// vector type. Typically this starts as s1 or <N x s1>.
1294 /// \pre \p Op0 and Op1 must be generic virtual registers with the
1295 /// same number of elements as \p Res (or scalar, if \p Res is
1296 /// scalar).
1297 /// \pre \p Pred must be a floating-point predicate.
1298 ///
1299 /// \return a MachineInstrBuilder for the newly created instruction.
1301 const SrcOp &Op0, const SrcOp &Op1,
1302 std::optional<unsigned> Flags = std::nullopt);
1303
1304 /// Build and insert a \p Res = G_SCMP \p Op0, \p Op1
1305 ///
1306 /// \pre setBasicBlock or setMI must have been called.
1307
1308 /// \pre \p Res must be a generic virtual register with scalar or
1309 /// vector type. Typically this starts as s2 or <N x s2>.
1310 /// \pre \p Op0 and Op1 must be generic virtual registers with the
1311 /// same number of elements as \p Res. If \p Res is a scalar,
1312 /// \p Op0 must be a scalar.
1313 ///
1314 /// \return a MachineInstrBuilder for the newly created instruction.
1315 MachineInstrBuilder buildSCmp(const DstOp &Res, const SrcOp &Op0,
1316 const SrcOp &Op1);
1317
1318 /// Build and insert a \p Res = G_UCMP \p Op0, \p Op1
1319 ///
1320 /// \pre setBasicBlock or setMI must have been called.
1321
1322 /// \pre \p Res must be a generic virtual register with scalar or
1323 /// vector type. Typically this starts as s2 or <N x s2>.
1324 /// \pre \p Op0 and Op1 must be generic virtual registers with the
1325 /// same number of elements as \p Res. If \p Res is a scalar,
1326 /// \p Op0 must be a scalar.
1327 ///
1328 /// \return a MachineInstrBuilder for the newly created instruction.
1329 MachineInstrBuilder buildUCmp(const DstOp &Res, const SrcOp &Op0,
1330 const SrcOp &Op1);
1331
1332 /// Build and insert a \p Res = G_IS_FPCLASS \p Src, \p Mask
1334 unsigned Mask) {
1335 return buildInstr(TargetOpcode::G_IS_FPCLASS, {Res},
1336 {Src, SrcOp(static_cast<int64_t>(Mask))});
1337 }
1338
1339 /// Build and insert a \p Res = G_SELECT \p Tst, \p Op0, \p Op1
1340 ///
1341 /// \pre setBasicBlock or setMI must have been called.
1342 /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
1343 /// with the same type.
1344 /// \pre \p Tst must be a generic virtual register with scalar, pointer or
1345 /// vector type. If vector then it must have the same number of
1346 /// elements as the other parameters.
1347 ///
1348 /// \return a MachineInstrBuilder for the newly created instruction.
1349 MachineInstrBuilder buildSelect(const DstOp &Res, const SrcOp &Tst,
1350 const SrcOp &Op0, const SrcOp &Op1,
1351 std::optional<unsigned> Flags = std::nullopt);
1352
1353 /// Build and insert \p Res = G_INSERT_VECTOR_ELT \p Val,
1354 /// \p Elt, \p Idx
1355 ///
1356 /// \pre setBasicBlock or setMI must have been called.
1357 /// \pre \p Res and \p Val must be a generic virtual register
1358 // with the same vector type.
1359 /// \pre \p Elt and \p Idx must be a generic virtual register
1360 /// with scalar type.
1361 ///
1362 /// \return The newly created instruction.
1364 const SrcOp &Val,
1365 const SrcOp &Elt,
1366 const SrcOp &Idx);
1367
1368 /// Build and insert \p Res = G_EXTRACT_VECTOR_ELT \p Val, \p Idx
1369 ///
1370 /// \pre setBasicBlock or setMI must have been called.
1371 /// \pre \p Res must be a generic virtual register with scalar type.
1372 /// \pre \p Val must be a generic virtual register with vector type.
1373 ///
1374 /// \return The newly created instruction.
1376 const SrcOp &Val,
1377 const int Idx) {
1378 auto TLI = getMF().getSubtarget().getTargetLowering();
1379 unsigned VecIdxWidth = TLI->getVectorIdxTy(getDataLayout()).getSizeInBits();
1381 Res, Val, buildConstant(LLT::scalar(VecIdxWidth), Idx));
1382 }
1383
1384 /// Build and insert \p Res = G_EXTRACT_VECTOR_ELT \p Val, \p Idx
1385 ///
1386 /// \pre setBasicBlock or setMI must have been called.
1387 /// \pre \p Res must be a generic virtual register with scalar type.
1388 /// \pre \p Val must be a generic virtual register with vector type.
1389 /// \pre \p Idx must be a generic virtual register with scalar type.
1390 ///
1391 /// \return The newly created instruction.
1393 const SrcOp &Val,
1394 const SrcOp &Idx);
1395
1396 /// Build and insert `OldValRes<def>, SuccessRes<def> =
1397 /// G_ATOMIC_CMPXCHG_WITH_SUCCESS Addr, CmpVal, NewVal, MMO`.
1398 ///
1399 /// Atomically replace the value at \p Addr with \p NewVal if it is currently
1400 /// \p CmpVal otherwise leaves it unchanged. Puts the original value from \p
1401 /// Addr in \p Res, along with an s1 indicating whether it was replaced.
1402 ///
1403 /// \pre setBasicBlock or setMI must have been called.
1404 /// \pre \p OldValRes must be a generic virtual register of scalar type.
1405 /// \pre \p SuccessRes must be a generic virtual register of scalar type. It
1406 /// will be assigned 0 on failure and 1 on success.
1407 /// \pre \p Addr must be a generic virtual register with pointer type.
1408 /// \pre \p OldValRes, \p CmpVal, and \p NewVal must be generic virtual
1409 /// registers of the same type.
1410 ///
1411 /// \return a MachineInstrBuilder for the newly created instruction.
1413 buildAtomicCmpXchgWithSuccess(const DstOp &OldValRes, const DstOp &SuccessRes,
1414 const SrcOp &Addr, const SrcOp &CmpVal,
1415 const SrcOp &NewVal, MachineMemOperand &MMO);
1416
1417 /// Build and insert `OldValRes<def> = G_ATOMIC_CMPXCHG Addr, CmpVal, NewVal,
1418 /// MMO`.
1419 ///
1420 /// Atomically replace the value at \p Addr with \p NewVal if it is currently
1421 /// \p CmpVal otherwise leaves it unchanged. Puts the original value from \p
1422 /// Addr in \p Res.
1423 ///
1424 /// \pre setBasicBlock or setMI must have been called.
1425 /// \pre \p OldValRes must be a generic virtual register of scalar type.
1426 /// \pre \p Addr must be a generic virtual register with pointer type.
1427 /// \pre \p OldValRes, \p CmpVal, and \p NewVal must be generic virtual
1428 /// registers of the same type.
1429 ///
1430 /// \return a MachineInstrBuilder for the newly created instruction.
1432 const SrcOp &Addr, const SrcOp &CmpVal,
1433 const SrcOp &NewVal,
1434 MachineMemOperand &MMO);
1435
1436 /// Build and insert `OldValRes<def> = G_ATOMICRMW_<Opcode> Addr, Val, MMO`.
1437 ///
1438 /// Atomically read-modify-update the value at \p Addr with \p Val. Puts the
1439 /// original value from \p Addr in \p OldValRes. The modification is
1440 /// determined by the opcode.
1441 ///
1442 /// \pre setBasicBlock or setMI must have been called.
1443 /// \pre \p OldValRes must be a generic virtual register.
1444 /// \pre \p Addr must be a generic virtual register with pointer type.
1445 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1446 /// same type.
1447 ///
1448 /// \return a MachineInstrBuilder for the newly created instruction.
1449 MachineInstrBuilder buildAtomicRMW(unsigned Opcode, const DstOp &OldValRes,
1450 const SrcOp &Addr, const SrcOp &Val,
1451 MachineMemOperand &MMO);
1452
1453 /// Build and insert `OldValRes<def> = G_ATOMICRMW_XCHG Addr, Val, MMO`.
1454 ///
1455 /// Atomically replace the value at \p Addr with \p Val. Puts the original
1456 /// value from \p Addr in \p OldValRes.
1457 ///
1458 /// \pre setBasicBlock or setMI must have been called.
1459 /// \pre \p OldValRes must be a generic virtual register.
1460 /// \pre \p Addr must be a generic virtual register with pointer type.
1461 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1462 /// same type.
1463 ///
1464 /// \return a MachineInstrBuilder for the newly created instruction.
1466 Register Val, MachineMemOperand &MMO);
1467
1468 /// Build and insert `OldValRes<def> = G_ATOMICRMW_ADD Addr, Val, MMO`.
1469 ///
1470 /// Atomically replace the value at \p Addr with the addition of \p Val and
1471 /// the original value. Puts the original value from \p Addr in \p OldValRes.
1472 ///
1473 /// \pre setBasicBlock or setMI must have been called.
1474 /// \pre \p OldValRes must be a generic virtual register.
1475 /// \pre \p Addr must be a generic virtual register with pointer type.
1476 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1477 /// same type.
1478 ///
1479 /// \return a MachineInstrBuilder for the newly created instruction.
1481 Register Val, MachineMemOperand &MMO);
1482
1483 /// Build and insert `OldValRes<def> = G_ATOMICRMW_SUB Addr, Val, MMO`.
1484 ///
1485 /// Atomically replace the value at \p Addr with the subtraction of \p Val and
1486 /// the original value. Puts the original value from \p Addr in \p OldValRes.
1487 ///
1488 /// \pre setBasicBlock or setMI must have been called.
1489 /// \pre \p OldValRes must be a generic virtual register.
1490 /// \pre \p Addr must be a generic virtual register with pointer type.
1491 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1492 /// same type.
1493 ///
1494 /// \return a MachineInstrBuilder for the newly created instruction.
1496 Register Val, MachineMemOperand &MMO);
1497
1498 /// Build and insert `OldValRes<def> = G_ATOMICRMW_AND Addr, Val, MMO`.
1499 ///
1500 /// Atomically replace the value at \p Addr with the bitwise and of \p Val and
1501 /// the original value. Puts the original value from \p Addr in \p OldValRes.
1502 ///
1503 /// \pre setBasicBlock or setMI must have been called.
1504 /// \pre \p OldValRes must be a generic virtual register.
1505 /// \pre \p Addr must be a generic virtual register with pointer type.
1506 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1507 /// same type.
1508 ///
1509 /// \return a MachineInstrBuilder for the newly created instruction.
1511 Register Val, MachineMemOperand &MMO);
1512
1513 /// Build and insert `OldValRes<def> = G_ATOMICRMW_NAND Addr, Val, MMO`.
1514 ///
1515 /// Atomically replace the value at \p Addr with the bitwise nand of \p Val
1516 /// and the original value. Puts the original value from \p Addr in \p
1517 /// OldValRes.
1518 ///
1519 /// \pre setBasicBlock or setMI must have been called.
1520 /// \pre \p OldValRes must be a generic virtual register.
1521 /// \pre \p Addr must be a generic virtual register with pointer type.
1522 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1523 /// same type.
1524 ///
1525 /// \return a MachineInstrBuilder for the newly created instruction.
1527 Register Val, MachineMemOperand &MMO);
1528
1529 /// Build and insert `OldValRes<def> = G_ATOMICRMW_OR Addr, Val, MMO`.
1530 ///
1531 /// Atomically replace the value at \p Addr with the bitwise or of \p Val and
1532 /// the original value. Puts the original value from \p Addr in \p OldValRes.
1533 ///
1534 /// \pre setBasicBlock or setMI must have been called.
1535 /// \pre \p OldValRes must be a generic virtual register.
1536 /// \pre \p Addr must be a generic virtual register with pointer type.
1537 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1538 /// same type.
1539 ///
1540 /// \return a MachineInstrBuilder for the newly created instruction.
1542 Register Val, MachineMemOperand &MMO);
1543
1544 /// Build and insert `OldValRes<def> = G_ATOMICRMW_XOR Addr, Val, MMO`.
1545 ///
1546 /// Atomically replace the value at \p Addr with the bitwise xor of \p Val and
1547 /// the original value. Puts the original value from \p Addr in \p OldValRes.
1548 ///
1549 /// \pre setBasicBlock or setMI must have been called.
1550 /// \pre \p OldValRes must be a generic virtual register.
1551 /// \pre \p Addr must be a generic virtual register with pointer type.
1552 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1553 /// same type.
1554 ///
1555 /// \return a MachineInstrBuilder for the newly created instruction.
1557 Register Val, MachineMemOperand &MMO);
1558
1559 /// Build and insert `OldValRes<def> = G_ATOMICRMW_MAX Addr, Val, MMO`.
1560 ///
1561 /// Atomically replace the value at \p Addr with the signed maximum of \p
1562 /// Val and the original value. Puts the original value from \p Addr in \p
1563 /// OldValRes.
1564 ///
1565 /// \pre setBasicBlock or setMI must have been called.
1566 /// \pre \p OldValRes must be a generic virtual register.
1567 /// \pre \p Addr must be a generic virtual register with pointer type.
1568 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1569 /// same type.
1570 ///
1571 /// \return a MachineInstrBuilder for the newly created instruction.
1573 Register Val, MachineMemOperand &MMO);
1574
1575 /// Build and insert `OldValRes<def> = G_ATOMICRMW_MIN Addr, Val, MMO`.
1576 ///
1577 /// Atomically replace the value at \p Addr with the signed minimum of \p
1578 /// Val and the original value. Puts the original value from \p Addr in \p
1579 /// OldValRes.
1580 ///
1581 /// \pre setBasicBlock or setMI must have been called.
1582 /// \pre \p OldValRes must be a generic virtual register.
1583 /// \pre \p Addr must be a generic virtual register with pointer type.
1584 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1585 /// same type.
1586 ///
1587 /// \return a MachineInstrBuilder for the newly created instruction.
1589 Register Val, MachineMemOperand &MMO);
1590
1591 /// Build and insert `OldValRes<def> = G_ATOMICRMW_UMAX Addr, Val, MMO`.
1592 ///
1593 /// Atomically replace the value at \p Addr with the unsigned maximum of \p
1594 /// Val and the original value. Puts the original value from \p Addr in \p
1595 /// OldValRes.
1596 ///
1597 /// \pre setBasicBlock or setMI must have been called.
1598 /// \pre \p OldValRes must be a generic virtual register.
1599 /// \pre \p Addr must be a generic virtual register with pointer type.
1600 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1601 /// same type.
1602 ///
1603 /// \return a MachineInstrBuilder for the newly created instruction.
1605 Register Val, MachineMemOperand &MMO);
1606
1607 /// Build and insert `OldValRes<def> = G_ATOMICRMW_UMIN Addr, Val, MMO`.
1608 ///
1609 /// Atomically replace the value at \p Addr with the unsigned minimum of \p
1610 /// Val and the original value. Puts the original value from \p Addr in \p
1611 /// OldValRes.
1612 ///
1613 /// \pre setBasicBlock or setMI must have been called.
1614 /// \pre \p OldValRes must be a generic virtual register.
1615 /// \pre \p Addr must be a generic virtual register with pointer type.
1616 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1617 /// same type.
1618 ///
1619 /// \return a MachineInstrBuilder for the newly created instruction.
1621 Register Val, MachineMemOperand &MMO);
1622
1623 /// Build and insert `OldValRes<def> = G_ATOMICRMW_FADD Addr, Val, MMO`.
1625 const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val,
1626 MachineMemOperand &MMO);
1627
1628 /// Build and insert `OldValRes<def> = G_ATOMICRMW_FSUB Addr, Val, MMO`.
1630 const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val,
1631 MachineMemOperand &MMO);
1632
1633 /// Build and insert `OldValRes<def> = G_ATOMICRMW_FMAX Addr, Val, MMO`.
1634 ///
1635 /// Atomically replace the value at \p Addr with the floating point maximum of
1636 /// \p Val and the original value. Puts the original value from \p Addr in \p
1637 /// OldValRes.
1638 ///
1639 /// \pre setBasicBlock or setMI must have been called.
1640 /// \pre \p OldValRes must be a generic virtual register.
1641 /// \pre \p Addr must be a generic virtual register with pointer type.
1642 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1643 /// same type.
1644 ///
1645 /// \return a MachineInstrBuilder for the newly created instruction.
1647 const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val,
1648 MachineMemOperand &MMO);
1649
1650 /// Build and insert `OldValRes<def> = G_ATOMICRMW_FMIN Addr, Val, MMO`.
1651 ///
1652 /// Atomically replace the value at \p Addr with the floating point minimum of
1653 /// \p Val and the original value. Puts the original value from \p Addr in \p
1654 /// OldValRes.
1655 ///
1656 /// \pre setBasicBlock or setMI must have been called.
1657 /// \pre \p OldValRes must be a generic virtual register.
1658 /// \pre \p Addr must be a generic virtual register with pointer type.
1659 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1660 /// same type.
1661 ///
1662 /// \return a MachineInstrBuilder for the newly created instruction.
1664 const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val,
1665 MachineMemOperand &MMO);
1666
1667 /// Build and insert `OldValRes<def> = G_ATOMICRMW_USUB_COND Addr, Val, MMO`.
1668 ///
1669 /// Atomically replace the value at \p Addr with the original value minus \p
1670 /// Val if the original value is greater than or equal to \p Val, or leaves it
1671 /// unchanged otherwise. Puts the original value from \p Addr in \p OldValRes.
1672 ///
1673 /// \pre setBasicBlock or setMI must have been called.
1674 /// \pre \p OldValRes must be a generic virtual register.
1675 /// \pre \p Addr must be a generic virtual register with pointer type.
1676 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1677 /// same type.
1678 ///
1679 /// \return a MachineInstrBuilder for the newly created instruction.
1681 const SrcOp &Addr,
1682 const SrcOp &Val,
1683 MachineMemOperand &MMO);
1684
1685 /// Build and insert `OldValRes<def> = G_ATOMICRMW_USUB_SAT Addr, Val, MMO`.
1686 ///
1687 /// Atomically replace the value at \p Addr with the original value minus \p
1688 /// Val, with clamping to zero if the unsigned subtraction would overflow.
1689 /// Puts the original value from \p Addr in \p OldValRes.
1690 ///
1691 /// \pre setBasicBlock or setMI must have been called.
1692 /// \pre \p OldValRes must be a generic virtual register.
1693 /// \pre \p Addr must be a generic virtual register with pointer type.
1694 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1695 /// same type.
1696 ///
1697 /// \return a MachineInstrBuilder for the newly created instruction.
1699 const SrcOp &Addr, const SrcOp &Val,
1700 MachineMemOperand &MMO);
1701
1702 /// Build and insert `G_FENCE Ordering, Scope`.
1703 MachineInstrBuilder buildFence(unsigned Ordering, unsigned Scope);
1704
1705 /// Build and insert G_PREFETCH \p Addr, \p RW, \p Locality, \p CacheType
1706 MachineInstrBuilder buildPrefetch(const SrcOp &Addr, unsigned RW,
1707 unsigned Locality, unsigned CacheType,
1708 MachineMemOperand &MMO);
1709
1710 /// Build and insert \p Dst = G_FREEZE \p Src
1711 MachineInstrBuilder buildFreeze(const DstOp &Dst, const SrcOp &Src) {
1712 return buildInstr(TargetOpcode::G_FREEZE, {Dst}, {Src});
1713 }
1714
1715 /// Build and insert \p Res = G_BLOCK_ADDR \p BA
1716 ///
1717 /// G_BLOCK_ADDR computes the address of a basic block.
1718 ///
1719 /// \pre setBasicBlock or setMI must have been called.
1720 /// \pre \p Res must be a generic virtual register of a pointer type.
1721 ///
1722 /// \return The newly created instruction.
1724
1725 /// Build and insert \p Res = G_ADD \p Op0, \p Op1
1726 ///
1727 /// G_ADD sets \p Res to the sum of integer parameters \p Op0 and \p Op1,
1728 /// truncated to their width.
1729 ///
1730 /// \pre setBasicBlock or setMI must have been called.
1731 /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
1732 /// with the same (scalar or vector) type).
1733 ///
1734 /// \return a MachineInstrBuilder for the newly created instruction.
1735
1736 MachineInstrBuilder buildAdd(const DstOp &Dst, const SrcOp &Src0,
1737 const SrcOp &Src1,
1738 std::optional<unsigned> Flags = std::nullopt) {
1739 return buildInstr(TargetOpcode::G_ADD, {Dst}, {Src0, Src1}, Flags);
1740 }
1741
1742 /// Build and insert \p Res = G_SUB \p Op0, \p Op1
1743 ///
1744 /// G_SUB sets \p Res to the difference of integer parameters \p Op0 and
1745 /// \p Op1, truncated to their width.
1746 ///
1747 /// \pre setBasicBlock or setMI must have been called.
1748 /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
1749 /// with the same (scalar or vector) type).
1750 ///
1751 /// \return a MachineInstrBuilder for the newly created instruction.
1752
1753 MachineInstrBuilder buildSub(const DstOp &Dst, const SrcOp &Src0,
1754 const SrcOp &Src1,
1755 std::optional<unsigned> Flags = std::nullopt) {
1756 return buildInstr(TargetOpcode::G_SUB, {Dst}, {Src0, Src1}, Flags);
1757 }
1758
1759 /// Build and insert \p Res = G_MUL \p Op0, \p Op1
1760 ///
1761 /// G_MUL sets \p Res to the product of integer parameters \p Op0 and \p Op1,
1762 /// truncated to their width.
1763 ///
1764 /// \pre setBasicBlock or setMI must have been called.
1765 /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
1766 /// with the same (scalar or vector) type).
1767 ///
1768 /// \return a MachineInstrBuilder for the newly created instruction.
1769 MachineInstrBuilder buildMul(const DstOp &Dst, const SrcOp &Src0,
1770 const SrcOp &Src1,
1771 std::optional<unsigned> Flags = std::nullopt) {
1772 return buildInstr(TargetOpcode::G_MUL, {Dst}, {Src0, Src1}, Flags);
1773 }
1774
1775 /// Build and insert \p Res = G_ABDS \p Op0, \p Op1
1776 ///
1777 /// G_ABDS return the signed absolute difference of \p Op0 and \p Op1.
1778 ///
1779 /// \pre setBasicBlock or setMI must have been called.
1780 /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
1781 /// with the same (scalar or vector) type).
1782 ///
1783 /// \return a MachineInstrBuilder for the newly created instruction.
1784 MachineInstrBuilder buildAbds(const DstOp &Dst, const SrcOp &Src0,
1785 const SrcOp &Src1) {
1786 return buildInstr(TargetOpcode::G_ABDS, {Dst}, {Src0, Src1});
1787 }
1788
1789 /// Build and insert \p Res = G_ABDU \p Op0, \p Op1
1790 ///
1791 /// G_ABDU return the unsigned absolute difference of \p Op0 and \p Op1.
1792 ///
1793 /// \pre setBasicBlock or setMI must have been called.
1794 /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
1795 /// with the same (scalar or vector) type).
1796 ///
1797 /// \return a MachineInstrBuilder for the newly created instruction.
1798 MachineInstrBuilder buildAbdu(const DstOp &Dst, const SrcOp &Src0,
1799 const SrcOp &Src1) {
1800 return buildInstr(TargetOpcode::G_ABDU, {Dst}, {Src0, Src1});
1801 }
1802
1804 const SrcOp &Src1,
1805 std::optional<unsigned> Flags = std::nullopt) {
1806 return buildInstr(TargetOpcode::G_UMULH, {Dst}, {Src0, Src1}, Flags);
1807 }
1808
1810 const SrcOp &Src1,
1811 std::optional<unsigned> Flags = std::nullopt) {
1812 return buildInstr(TargetOpcode::G_SMULH, {Dst}, {Src0, Src1}, Flags);
1813 }
1814
1815 /// Build and insert \p Res = G_UREM \p Op0, \p Op1
1816 MachineInstrBuilder buildURem(const DstOp &Dst, const SrcOp &Src0,
1817 const SrcOp &Src1,
1818 std::optional<unsigned> Flags = std::nullopt) {
1819 return buildInstr(TargetOpcode::G_UREM, {Dst}, {Src0, Src1}, Flags);
1820 }
1821
1822 MachineInstrBuilder buildFMul(const DstOp &Dst, const SrcOp &Src0,
1823 const SrcOp &Src1,
1824 std::optional<unsigned> Flags = std::nullopt) {
1825 return buildInstr(TargetOpcode::G_FMUL, {Dst}, {Src0, Src1}, Flags);
1826 }
1827
1829 buildFMinNum(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1,
1830 std::optional<unsigned> Flags = std::nullopt) {
1831 return buildInstr(TargetOpcode::G_FMINNUM, {Dst}, {Src0, Src1}, Flags);
1832 }
1833
1835 buildFMaxNum(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1,
1836 std::optional<unsigned> Flags = std::nullopt) {
1837 return buildInstr(TargetOpcode::G_FMAXNUM, {Dst}, {Src0, Src1}, Flags);
1838 }
1839
1841 buildFMinNumIEEE(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1,
1842 std::optional<unsigned> Flags = std::nullopt) {
1843 return buildInstr(TargetOpcode::G_FMINNUM_IEEE, {Dst}, {Src0, Src1}, Flags);
1844 }
1845
1847 buildFMaxNumIEEE(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1,
1848 std::optional<unsigned> Flags = std::nullopt) {
1849 return buildInstr(TargetOpcode::G_FMAXNUM_IEEE, {Dst}, {Src0, Src1}, Flags);
1850 }
1851
1852 MachineInstrBuilder buildShl(const DstOp &Dst, const SrcOp &Src0,
1853 const SrcOp &Src1,
1854 std::optional<unsigned> Flags = std::nullopt) {
1855 return buildInstr(TargetOpcode::G_SHL, {Dst}, {Src0, Src1}, Flags);
1856 }
1857
1858 MachineInstrBuilder buildLShr(const DstOp &Dst, const SrcOp &Src0,
1859 const SrcOp &Src1,
1860 std::optional<unsigned> Flags = std::nullopt) {
1861 return buildInstr(TargetOpcode::G_LSHR, {Dst}, {Src0, Src1}, Flags);
1862 }
1863
1864 MachineInstrBuilder buildAShr(const DstOp &Dst, const SrcOp &Src0,
1865 const SrcOp &Src1,
1866 std::optional<unsigned> Flags = std::nullopt) {
1867 return buildInstr(TargetOpcode::G_ASHR, {Dst}, {Src0, Src1}, Flags);
1868 }
1869
1870 /// Build and insert \p Res = G_AND \p Op0, \p Op1
1871 ///
1872 /// G_AND sets \p Res to the bitwise and of integer parameters \p Op0 and \p
1873 /// Op1.
1874 ///
1875 /// \pre setBasicBlock or setMI must have been called.
1876 /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
1877 /// with the same (scalar or vector) type).
1878 ///
1879 /// \return a MachineInstrBuilder for the newly created instruction.
1880
1881 MachineInstrBuilder buildAnd(const DstOp &Dst, const SrcOp &Src0,
1882 const SrcOp &Src1) {
1883 return buildInstr(TargetOpcode::G_AND, {Dst}, {Src0, Src1});
1884 }
1885
1886 /// Build and insert \p Res = G_OR \p Op0, \p Op1
1887 ///
1888 /// G_OR sets \p Res to the bitwise or of integer parameters \p Op0 and \p
1889 /// Op1.
1890 ///
1891 /// \pre setBasicBlock or setMI must have been called.
1892 /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
1893 /// with the same (scalar or vector) type).
1894 ///
1895 /// \return a MachineInstrBuilder for the newly created instruction.
1896 MachineInstrBuilder buildOr(const DstOp &Dst, const SrcOp &Src0,
1897 const SrcOp &Src1,
1898 std::optional<unsigned> Flags = std::nullopt) {
1899 return buildInstr(TargetOpcode::G_OR, {Dst}, {Src0, Src1}, Flags);
1900 }
1901
1902 /// Build and insert \p Res = G_XOR \p Op0, \p Op1
1903 MachineInstrBuilder buildXor(const DstOp &Dst, const SrcOp &Src0,
1904 const SrcOp &Src1) {
1905 return buildInstr(TargetOpcode::G_XOR, {Dst}, {Src0, Src1});
1906 }
1907
1908 /// Build and insert a bitwise not,
1909 /// \p NegOne = G_CONSTANT -1
1910 /// \p Res = G_OR \p Op0, NegOne
1911 MachineInstrBuilder buildNot(const DstOp &Dst, const SrcOp &Src0) {
1912 auto NegOne = buildConstant(Dst.getLLTTy(*getMRI()), -1);
1913 return buildInstr(TargetOpcode::G_XOR, {Dst}, {Src0, NegOne});
1914 }
1915
1916 /// Build and insert integer negation
1917 /// \p Zero = G_CONSTANT 0
1918 /// \p Res = G_SUB Zero, \p Op0
1919 MachineInstrBuilder buildNeg(const DstOp &Dst, const SrcOp &Src0) {
1920 auto Zero = buildConstant(Dst.getLLTTy(*getMRI()), 0);
1921 return buildInstr(TargetOpcode::G_SUB, {Dst}, {Zero, Src0});
1922 }
1923
1924 /// Build and insert \p Res = G_CTPOP \p Op0, \p Src0
1925 MachineInstrBuilder buildCTPOP(const DstOp &Dst, const SrcOp &Src0) {
1926 return buildInstr(TargetOpcode::G_CTPOP, {Dst}, {Src0});
1927 }
1928
1929 /// Build and insert \p Res = G_CTLZ \p Op0, \p Src0
1930 MachineInstrBuilder buildCTLZ(const DstOp &Dst, const SrcOp &Src0) {
1931 return buildInstr(TargetOpcode::G_CTLZ, {Dst}, {Src0});
1932 }
1933
1934 /// Build and insert \p Res = G_CTLZ_ZERO_UNDEF \p Op0, \p Src0
1936 return buildInstr(TargetOpcode::G_CTLZ_ZERO_UNDEF, {Dst}, {Src0});
1937 }
1938
1939 /// Build and insert \p Res = G_CTTZ \p Op0, \p Src0
1940 MachineInstrBuilder buildCTTZ(const DstOp &Dst, const SrcOp &Src0) {
1941 return buildInstr(TargetOpcode::G_CTTZ, {Dst}, {Src0});
1942 }
1943
1944 /// Build and insert \p Res = G_CTTZ_ZERO_UNDEF \p Op0, \p Src0
1946 return buildInstr(TargetOpcode::G_CTTZ_ZERO_UNDEF, {Dst}, {Src0});
1947 }
1948
1949 /// Build and insert \p Dst = G_BSWAP \p Src0
1950 MachineInstrBuilder buildBSwap(const DstOp &Dst, const SrcOp &Src0) {
1951 return buildInstr(TargetOpcode::G_BSWAP, {Dst}, {Src0});
1952 }
1953
1954 /// Build and insert \p Res = G_FADD \p Op0, \p Op1
1955 MachineInstrBuilder buildFAdd(const DstOp &Dst, const SrcOp &Src0,
1956 const SrcOp &Src1,
1957 std::optional<unsigned> Flags = std::nullopt) {
1958 return buildInstr(TargetOpcode::G_FADD, {Dst}, {Src0, Src1}, Flags);
1959 }
1960
1961 /// Build and insert \p Res = G_STRICT_FADD \p Op0, \p Op1
1963 buildStrictFAdd(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1,
1964 std::optional<unsigned> Flags = std::nullopt) {
1965 return buildInstr(TargetOpcode::G_STRICT_FADD, {Dst}, {Src0, Src1}, Flags);
1966 }
1967
1968 /// Build and insert \p Res = G_FSUB \p Op0, \p Op1
1969 MachineInstrBuilder buildFSub(const DstOp &Dst, const SrcOp &Src0,
1970 const SrcOp &Src1,
1971 std::optional<unsigned> Flags = std::nullopt) {
1972 return buildInstr(TargetOpcode::G_FSUB, {Dst}, {Src0, Src1}, Flags);
1973 }
1974
1975 /// Build and insert \p Res = G_FDIV \p Op0, \p Op1
1976 MachineInstrBuilder buildFDiv(const DstOp &Dst, const SrcOp &Src0,
1977 const SrcOp &Src1,
1978 std::optional<unsigned> Flags = std::nullopt) {
1979 return buildInstr(TargetOpcode::G_FDIV, {Dst}, {Src0, Src1}, Flags);
1980 }
1981
1982 /// Build and insert \p Res = G_FMA \p Op0, \p Op1, \p Op2
1983 MachineInstrBuilder buildFMA(const DstOp &Dst, const SrcOp &Src0,
1984 const SrcOp &Src1, const SrcOp &Src2,
1985 std::optional<unsigned> Flags = std::nullopt) {
1986 return buildInstr(TargetOpcode::G_FMA, {Dst}, {Src0, Src1, Src2}, Flags);
1987 }
1988
1989 /// Build and insert \p Res = G_FMAD \p Op0, \p Op1, \p Op2
1990 MachineInstrBuilder buildFMAD(const DstOp &Dst, const SrcOp &Src0,
1991 const SrcOp &Src1, const SrcOp &Src2,
1992 std::optional<unsigned> Flags = std::nullopt) {
1993 return buildInstr(TargetOpcode::G_FMAD, {Dst}, {Src0, Src1, Src2}, Flags);
1994 }
1995
1996 /// Build and insert \p Res = G_FNEG \p Op0
1997 MachineInstrBuilder buildFNeg(const DstOp &Dst, const SrcOp &Src0,
1998 std::optional<unsigned> Flags = std::nullopt) {
1999 return buildInstr(TargetOpcode::G_FNEG, {Dst}, {Src0}, Flags);
2000 }
2001
2002 /// Build and insert \p Res = G_FABS \p Op0
2003 MachineInstrBuilder buildFAbs(const DstOp &Dst, const SrcOp &Src0,
2004 std::optional<unsigned> Flags = std::nullopt) {
2005 return buildInstr(TargetOpcode::G_FABS, {Dst}, {Src0}, Flags);
2006 }
2007
2008 /// Build and insert \p Dst = G_FCANONICALIZE \p Src0
2010 buildFCanonicalize(const DstOp &Dst, const SrcOp &Src0,
2011 std::optional<unsigned> Flags = std::nullopt) {
2012 return buildInstr(TargetOpcode::G_FCANONICALIZE, {Dst}, {Src0}, Flags);
2013 }
2014
2015 /// Build and insert \p Dst = G_INTRINSIC_TRUNC \p Src0
2017 buildIntrinsicTrunc(const DstOp &Dst, const SrcOp &Src0,
2018 std::optional<unsigned> Flags = std::nullopt) {
2019 return buildInstr(TargetOpcode::G_INTRINSIC_TRUNC, {Dst}, {Src0}, Flags);
2020 }
2021
2022 /// Build and insert \p Res = GFFLOOR \p Op0, \p Op1
2024 buildFFloor(const DstOp &Dst, const SrcOp &Src0,
2025 std::optional<unsigned> Flags = std::nullopt) {
2026 return buildInstr(TargetOpcode::G_FFLOOR, {Dst}, {Src0}, Flags);
2027 }
2028
2029 /// Build and insert \p Dst = G_FLOG \p Src
2031 std::optional<unsigned> Flags = std::nullopt) {
2032 return buildInstr(TargetOpcode::G_FLOG, {Dst}, {Src}, Flags);
2033 }
2034
2035 /// Build and insert \p Dst = G_FLOG2 \p Src
2037 std::optional<unsigned> Flags = std::nullopt) {
2038 return buildInstr(TargetOpcode::G_FLOG2, {Dst}, {Src}, Flags);
2039 }
2040
2041 /// Build and insert \p Dst = G_FEXP2 \p Src
2043 std::optional<unsigned> Flags = std::nullopt) {
2044 return buildInstr(TargetOpcode::G_FEXP2, {Dst}, {Src}, Flags);
2045 }
2046
2047 /// Build and insert \p Dst = G_FPOW \p Src0, \p Src1
2048 MachineInstrBuilder buildFPow(const DstOp &Dst, const SrcOp &Src0,
2049 const SrcOp &Src1,
2050 std::optional<unsigned> Flags = std::nullopt) {
2051 return buildInstr(TargetOpcode::G_FPOW, {Dst}, {Src0, Src1}, Flags);
2052 }
2053
2054 /// Build and insert \p Dst = G_FLDEXP \p Src0, \p Src1
2056 buildFLdexp(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1,
2057 std::optional<unsigned> Flags = std::nullopt) {
2058 return buildInstr(TargetOpcode::G_FLDEXP, {Dst}, {Src0, Src1}, Flags);
2059 }
2060
2061 /// Build and insert \p Fract, \p Exp = G_FFREXP \p Src
2063 buildFFrexp(const DstOp &Fract, const DstOp &Exp, const SrcOp &Src,
2064 std::optional<unsigned> Flags = std::nullopt) {
2065 return buildInstr(TargetOpcode::G_FFREXP, {Fract, Exp}, {Src}, Flags);
2066 }
2067
2068 /// Build and insert \p Sin, \p Cos = G_FSINCOS \p Src
2070 buildFSincos(const DstOp &Sin, const DstOp &Cos, const SrcOp &Src,
2071 std::optional<unsigned> Flags = std::nullopt) {
2072 return buildInstr(TargetOpcode::G_FSINCOS, {Sin, Cos}, {Src}, Flags);
2073 }
2074
2075 /// Build and insert \p Res = G_FCOPYSIGN \p Op0, \p Op1
2077 const SrcOp &Src1) {
2078 return buildInstr(TargetOpcode::G_FCOPYSIGN, {Dst}, {Src0, Src1});
2079 }
2080
2081 /// Build and insert \p Res = G_UITOFP \p Src0
2082 MachineInstrBuilder buildUITOFP(const DstOp &Dst, const SrcOp &Src0) {
2083 return buildInstr(TargetOpcode::G_UITOFP, {Dst}, {Src0});
2084 }
2085
2086 /// Build and insert \p Res = G_SITOFP \p Src0
2087 MachineInstrBuilder buildSITOFP(const DstOp &Dst, const SrcOp &Src0) {
2088 return buildInstr(TargetOpcode::G_SITOFP, {Dst}, {Src0});
2089 }
2090
2091 /// Build and insert \p Res = G_FPTOUI \p Src0
2092 MachineInstrBuilder buildFPTOUI(const DstOp &Dst, const SrcOp &Src0) {
2093 return buildInstr(TargetOpcode::G_FPTOUI, {Dst}, {Src0});
2094 }
2095
2096 /// Build and insert \p Res = G_FPTOSI \p Src0
2097 MachineInstrBuilder buildFPTOSI(const DstOp &Dst, const SrcOp &Src0) {
2098 return buildInstr(TargetOpcode::G_FPTOSI, {Dst}, {Src0});
2099 }
2100
2101 /// Build and insert \p Res = G_FPTOUI_SAT \p Src0
2103 return buildInstr(TargetOpcode::G_FPTOUI_SAT, {Dst}, {Src0});
2104 }
2105
2106 /// Build and insert \p Res = G_FPTOSI_SAT \p Src0
2108 return buildInstr(TargetOpcode::G_FPTOSI_SAT, {Dst}, {Src0});
2109 }
2110
2111 /// Build and insert \p Dst = G_INTRINSIC_ROUNDEVEN \p Src0, \p Src1
2113 buildIntrinsicRoundeven(const DstOp &Dst, const SrcOp &Src0,
2114 std::optional<unsigned> Flags = std::nullopt) {
2115 return buildInstr(TargetOpcode::G_INTRINSIC_ROUNDEVEN, {Dst}, {Src0},
2116 Flags);
2117 }
2118
2119 /// Build and insert \p Res = G_SMIN \p Op0, \p Op1
2120 MachineInstrBuilder buildSMin(const DstOp &Dst, const SrcOp &Src0,
2121 const SrcOp &Src1) {
2122 return buildInstr(TargetOpcode::G_SMIN, {Dst}, {Src0, Src1});
2123 }
2124
2125 /// Build and insert \p Res = G_SMAX \p Op0, \p Op1
2126 MachineInstrBuilder buildSMax(const DstOp &Dst, const SrcOp &Src0,
2127 const SrcOp &Src1) {
2128 return buildInstr(TargetOpcode::G_SMAX, {Dst}, {Src0, Src1});
2129 }
2130
2131 /// Build and insert \p Res = G_UMIN \p Op0, \p Op1
2132 MachineInstrBuilder buildUMin(const DstOp &Dst, const SrcOp &Src0,
2133 const SrcOp &Src1) {
2134 return buildInstr(TargetOpcode::G_UMIN, {Dst}, {Src0, Src1});
2135 }
2136
2137 /// Build and insert \p Res = G_UMAX \p Op0, \p Op1
2138 MachineInstrBuilder buildUMax(const DstOp &Dst, const SrcOp &Src0,
2139 const SrcOp &Src1) {
2140 return buildInstr(TargetOpcode::G_UMAX, {Dst}, {Src0, Src1});
2141 }
2142
2143 /// Build and insert \p Dst = G_ABS \p Src
2144 MachineInstrBuilder buildAbs(const DstOp &Dst, const SrcOp &Src) {
2145 return buildInstr(TargetOpcode::G_ABS, {Dst}, {Src});
2146 }
2147
2148 /// Build and insert \p Res = G_JUMP_TABLE \p JTI
2149 ///
2150 /// G_JUMP_TABLE sets \p Res to the address of the jump table specified by
2151 /// the jump table index \p JTI.
2152 ///
2153 /// \return a MachineInstrBuilder for the newly created instruction.
2154 MachineInstrBuilder buildJumpTable(const LLT PtrTy, unsigned JTI);
2155
2156 /// Build and insert \p Res = G_VECREDUCE_SEQ_FADD \p ScalarIn, \p VecIn
2157 ///
2158 /// \p ScalarIn is the scalar accumulator input to start the sequential
2159 /// reduction operation of \p VecIn.
2161 const SrcOp &ScalarIn,
2162 const SrcOp &VecIn) {
2163 return buildInstr(TargetOpcode::G_VECREDUCE_SEQ_FADD, {Dst},
2164 {ScalarIn, {VecIn}});
2165 }
2166
2167 /// Build and insert \p Res = G_VECREDUCE_SEQ_FMUL \p ScalarIn, \p VecIn
2168 ///
2169 /// \p ScalarIn is the scalar accumulator input to start the sequential
2170 /// reduction operation of \p VecIn.
2172 const SrcOp &ScalarIn,
2173 const SrcOp &VecIn) {
2174 return buildInstr(TargetOpcode::G_VECREDUCE_SEQ_FMUL, {Dst},
2175 {ScalarIn, {VecIn}});
2176 }
2177
2178 /// Build and insert \p Res = G_VECREDUCE_FADD \p Src
2179 ///
2180 /// \p ScalarIn is the scalar accumulator input to the reduction operation of
2181 /// \p VecIn.
2183 const SrcOp &ScalarIn,
2184 const SrcOp &VecIn) {
2185 return buildInstr(TargetOpcode::G_VECREDUCE_FADD, {Dst}, {ScalarIn, VecIn});
2186 }
2187
2188 /// Build and insert \p Res = G_VECREDUCE_FMUL \p Src
2189 ///
2190 /// \p ScalarIn is the scalar accumulator input to the reduction operation of
2191 /// \p VecIn.
2193 const SrcOp &ScalarIn,
2194 const SrcOp &VecIn) {
2195 return buildInstr(TargetOpcode::G_VECREDUCE_FMUL, {Dst}, {ScalarIn, VecIn});
2196 }
2197
2198 /// Build and insert \p Res = G_VECREDUCE_FMAX \p Src
2200 return buildInstr(TargetOpcode::G_VECREDUCE_FMAX, {Dst}, {Src});
2201 }
2202
2203 /// Build and insert \p Res = G_VECREDUCE_FMIN \p Src
2205 return buildInstr(TargetOpcode::G_VECREDUCE_FMIN, {Dst}, {Src});
2206 }
2207
2208 /// Build and insert \p Res = G_VECREDUCE_FMAXIMUM \p Src
2210 const SrcOp &Src) {
2211 return buildInstr(TargetOpcode::G_VECREDUCE_FMAXIMUM, {Dst}, {Src});
2212 }
2213
2214 /// Build and insert \p Res = G_VECREDUCE_FMINIMUM \p Src
2216 const SrcOp &Src) {
2217 return buildInstr(TargetOpcode::G_VECREDUCE_FMINIMUM, {Dst}, {Src});
2218 }
2219
2220 /// Build and insert \p Res = G_VECREDUCE_ADD \p Src
2222 return buildInstr(TargetOpcode::G_VECREDUCE_ADD, {Dst}, {Src});
2223 }
2224
2225 /// Build and insert \p Res = G_VECREDUCE_MUL \p Src
2227 return buildInstr(TargetOpcode::G_VECREDUCE_MUL, {Dst}, {Src});
2228 }
2229
2230 /// Build and insert \p Res = G_VECREDUCE_AND \p Src
2232 return buildInstr(TargetOpcode::G_VECREDUCE_AND, {Dst}, {Src});
2233 }
2234
2235 /// Build and insert \p Res = G_VECREDUCE_OR \p Src
2237 return buildInstr(TargetOpcode::G_VECREDUCE_OR, {Dst}, {Src});
2238 }
2239
2240 /// Build and insert \p Res = G_VECREDUCE_XOR \p Src
2242 return buildInstr(TargetOpcode::G_VECREDUCE_XOR, {Dst}, {Src});
2243 }
2244
2245 /// Build and insert \p Res = G_VECREDUCE_SMAX \p Src
2247 return buildInstr(TargetOpcode::G_VECREDUCE_SMAX, {Dst}, {Src});
2248 }
2249
2250 /// Build and insert \p Res = G_VECREDUCE_SMIN \p Src
2252 return buildInstr(TargetOpcode::G_VECREDUCE_SMIN, {Dst}, {Src});
2253 }
2254
2255 /// Build and insert \p Res = G_VECREDUCE_UMAX \p Src
2257 return buildInstr(TargetOpcode::G_VECREDUCE_UMAX, {Dst}, {Src});
2258 }
2259
2260 /// Build and insert \p Res = G_VECREDUCE_UMIN \p Src
2262 return buildInstr(TargetOpcode::G_VECREDUCE_UMIN, {Dst}, {Src});
2263 }
2264
2265 /// Build and insert G_MEMCPY or G_MEMMOVE
2266 MachineInstrBuilder buildMemTransferInst(unsigned Opcode, const SrcOp &DstPtr,
2267 const SrcOp &SrcPtr,
2268 const SrcOp &Size,
2269 MachineMemOperand &DstMMO,
2270 MachineMemOperand &SrcMMO) {
2271 auto MIB = buildInstr(
2272 Opcode, {}, {DstPtr, SrcPtr, Size, SrcOp(INT64_C(0) /*isTailCall*/)});
2273 MIB.addMemOperand(&DstMMO);
2274 MIB.addMemOperand(&SrcMMO);
2275 return MIB;
2276 }
2277
2278 MachineInstrBuilder buildMemCpy(const SrcOp &DstPtr, const SrcOp &SrcPtr,
2279 const SrcOp &Size, MachineMemOperand &DstMMO,
2280 MachineMemOperand &SrcMMO) {
2281 return buildMemTransferInst(TargetOpcode::G_MEMCPY, DstPtr, SrcPtr, Size,
2282 DstMMO, SrcMMO);
2283 }
2284
2285 /// Build and insert G_TRAP or G_DEBUGTRAP
2287 return buildInstr(Debug ? TargetOpcode::G_DEBUGTRAP : TargetOpcode::G_TRAP);
2288 }
2289
2290 /// Build and insert \p Dst = G_SBFX \p Src, \p LSB, \p Width.
2292 const SrcOp &LSB, const SrcOp &Width) {
2293 return buildInstr(TargetOpcode::G_SBFX, {Dst}, {Src, LSB, Width});
2294 }
2295
2296 /// Build and insert \p Dst = G_UBFX \p Src, \p LSB, \p Width.
2298 const SrcOp &LSB, const SrcOp &Width) {
2299 return buildInstr(TargetOpcode::G_UBFX, {Dst}, {Src, LSB, Width});
2300 }
2301
2302 /// Build and insert \p Dst = G_ROTR \p Src, \p Amt
2304 const SrcOp &Amt) {
2305 return buildInstr(TargetOpcode::G_ROTR, {Dst}, {Src, Amt});
2306 }
2307
2308 /// Build and insert \p Dst = G_ROTL \p Src, \p Amt
2310 const SrcOp &Amt) {
2311 return buildInstr(TargetOpcode::G_ROTL, {Dst}, {Src, Amt});
2312 }
2313
2314 /// Build and insert \p Dst = G_BITREVERSE \p Src
2316 return buildInstr(TargetOpcode::G_BITREVERSE, {Dst}, {Src});
2317 }
2318
2319 /// Build and insert \p Dst = G_GET_FPENV
2321 return buildInstr(TargetOpcode::G_GET_FPENV, {Dst}, {});
2322 }
2323
2324 /// Build and insert G_SET_FPENV \p Src
2326 return buildInstr(TargetOpcode::G_SET_FPENV, {}, {Src});
2327 }
2328
2329 /// Build and insert G_RESET_FPENV
2331 return buildInstr(TargetOpcode::G_RESET_FPENV, {}, {});
2332 }
2333
2334 /// Build and insert \p Dst = G_GET_FPMODE
2336 return buildInstr(TargetOpcode::G_GET_FPMODE, {Dst}, {});
2337 }
2338
2339 /// Build and insert G_SET_FPMODE \p Src
2341 return buildInstr(TargetOpcode::G_SET_FPMODE, {}, {Src});
2342 }
2343
2344 /// Build and insert G_RESET_FPMODE
2346 return buildInstr(TargetOpcode::G_RESET_FPMODE, {}, {});
2347 }
2348
2349 virtual MachineInstrBuilder
2350 buildInstr(unsigned Opc, ArrayRef<DstOp> DstOps, ArrayRef<SrcOp> SrcOps,
2351 std::optional<unsigned> Flags = std::nullopt);
2352};
2353
2354} // End namespace llvm.
2355#endif // LLVM_CODEGEN_GLOBALISEL_MACHINEIRBUILDER_H
unsigned const MachineRegisterInfo * MRI
MachineBasicBlock & MBB
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
static const Function * getParent(const Value *V)
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
static ManagedStatic< cl::opt< bool, true >, CreateDebug > Debug
Definition: Debug.cpp:108
uint64_t Addr
uint32_t Index
uint64_t Size
This contains common code to allow clients to notify changes to machine instr.
IRTranslator LLVM IR MI
Module.h This file contains the declarations for the Module class.
unsigned Reg
uint64_t IntrinsicInst * II
#define P(N)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file describes how to lower LLVM code to machine code.
Class for arbitrary precision integers.
Definition: APInt.h:78
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
The address of a basic block.
Definition: Constants.h:893
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:673
ConstantFP - Floating Point Values [float, double].
Definition: Constants.h:271
This is the shared class of boolean and integer constants.
Definition: Constants.h:83
A signed pointer, in the ptrauth sense.
Definition: Constants.h:1021
This is an important base class in LLVM.
Definition: Constant.h:42
This class represents an Operation in the Expression.
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:63
A debug info location.
Definition: DebugLoc.h:33
DstOp(const LLT T)
DstOp(unsigned R)
DstOp(Register R)
void addDefToMIB(MachineRegisterInfo &MRI, MachineInstrBuilder &MIB) const
LLT getLLTTy(const MachineRegisterInfo &MRI) const
MachineRegisterInfo::VRegAttrs Attrs
DstOp(MachineRegisterInfo::VRegAttrs Attrs)
DstOp(const MachineOperand &Op)
MachineRegisterInfo::VRegAttrs getVRegAttrs() const
DstType getDstOpKind() const
const TargetRegisterClass * RC
const TargetRegisterClass * getRegClass() const
DstOp(const TargetRegisterClass *TRC)
DstOp(RegClassOrRegBank RCOrRB, LLT Ty)
Register getReg() const
const DataLayout & getDataLayout() const
Get the data layout of the module this function belongs to.
Definition: Function.cpp:373
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function.
Definition: Function.cpp:369
The CSE Analysis object.
Definition: CSEInfo.h:70
Abstract class that contains various methods for clients to notify about changes.
virtual void createdInstr(MachineInstr &MI)=0
An instruction has been created and inserted into the function.
static constexpr LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
Definition: LowLevelType.h:42
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:67
Metadata node.
Definition: Metadata.h:1073
TypeSize getSizeInBits() const
Returns the size of the specified MVT in bits.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Function & getFunction()
Return the LLVM function that this machine code represents.
Helper class to build MachineInstr.
MachineInstrBuilder buildFPTOUI_SAT(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_FPTOUI_SAT Src0.
MachineInstrBuilder buildLoadFromOffset(const DstOp &Dst, const SrcOp &BasePtr, MachineMemOperand &BaseMMO, int64_t Offset)
Helper to create a load from a constant offset given a base address.
MachineInstrBuilder buildAtomicRMWFMin(const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_FMIN Addr, Val, MMO.
MachineInstrBuilder buildFSub(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt)
Build and insert Res = G_FSUB Op0, Op1.
MachineInstrBuilder buildFPTOSI(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_FPTOSI Src0.
GISelChangeObserver * getObserver()
MachineInstrBuilder buildFMul(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt)
MachineInstrBuilder buildBoolExtInReg(const DstOp &Res, const SrcOp &Op, bool IsVector, bool IsFP)
MachineInstrBuilder insertInstr(MachineInstrBuilder MIB)
Insert an existing instruction at the insertion point.
MachineInstrBuilder buildFLdexp(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt)
Build and insert Dst = G_FLDEXP Src0, Src1.
MachineInstrBuilder buildFreeze(const DstOp &Dst, const SrcOp &Src)
Build and insert Dst = G_FREEZE Src.
MachineInstrBuilder buildAtomicRMWXor(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_XOR Addr, Val, MMO.
MachineInstrBuilder buildGlobalValue(const DstOp &Res, const GlobalValue *GV)
Build and insert Res = G_GLOBAL_VALUE GV.
MachineInstrBuilder buildBr(MachineBasicBlock &Dest)
Build and insert G_BR Dest.
void setInsertPt(MachineBasicBlock &MBB, MachineBasicBlock::iterator II)
Set the insertion point before the specified position.
const MachineFunction & getMF() const
std::optional< MachineInstrBuilder > materializePtrAdd(Register &Res, Register Op0, const LLT ValueTy, uint64_t Value)
Materialize and insert Res = G_PTR_ADD Op0, (G_CONSTANT Value)
LLVMContext & getContext() const
MachineInstrBuilder buildAdd(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt)
Build and insert Res = G_ADD Op0, Op1.
MachineInstrBuilder buildUndef(const DstOp &Res)
Build and insert Res = IMPLICIT_DEF.
MachineInstrBuilder buildResetFPMode()
Build and insert G_RESET_FPMODE.
MachineInstrBuilder buildFPExt(const DstOp &Res, const SrcOp &Op, std::optional< unsigned > Flags=std::nullopt)
Build and insert Res = G_FPEXT Op.
MachineInstrBuilder buildNot(const DstOp &Dst, const SrcOp &Src0)
Build and insert a bitwise not, NegOne = G_CONSTANT -1 Res = G_OR Op0, NegOne.
MachineInstrBuilder buildFPTOSI_SAT(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_FPTOSI_SAT Src0.
MachineInstrBuilder buildVecReduceSeqFAdd(const DstOp &Dst, const SrcOp &ScalarIn, const SrcOp &VecIn)
Build and insert Res = G_VECREDUCE_SEQ_FADD ScalarIn, VecIn.
MachineInstrBuilder buildAtomicRMWUSubSat(const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_USUB_SAT Addr, Val, MMO.
MachineInstrBuilder buildRotateRight(const DstOp &Dst, const SrcOp &Src, const SrcOp &Amt)
Build and insert Dst = G_ROTR Src, Amt.
MachineInstrBuilder buildUCmp(const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1)
Build and insert a Res = G_UCMP Op0, Op1.
MachineInstrBuilder buildCTTZ(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_CTTZ Op0, Src0.
virtual ~MachineIRBuilder()=default
MachineInstrBuilder buildVecReduceOr(const DstOp &Dst, const SrcOp &Src)
Build and insert Res = G_VECREDUCE_OR Src.
MachineInstrBuilder buildFLog2(const DstOp &Dst, const SrcOp &Src, std::optional< unsigned > Flags=std::nullopt)
Build and insert Dst = G_FLOG2 Src.
MachineInstrBuilder buildAShr(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt)
MachineInstrBuilder buildConstantPool(const DstOp &Res, unsigned Idx)
Build and insert Res = G_CONSTANT_POOL Idx.
MachineInstrBuilder buildJumpTable(const LLT PtrTy, unsigned JTI)
Build and insert Res = G_JUMP_TABLE JTI.
MachineInstrBuilder buildBoolExt(const DstOp &Res, const SrcOp &Op, bool IsFP)
MachineInstrBuilder buildUnmerge(ArrayRef< LLT > Res, const SrcOp &Op)
Build and insert Res0, ... = G_UNMERGE_VALUES Op.
MachineInstrBuilder buildFAbs(const DstOp &Dst, const SrcOp &Src0, std::optional< unsigned > Flags=std::nullopt)
Build and insert Res = G_FABS Op0.
MachineInstrBuilder buildSCmp(const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1)
Build and insert a Res = G_SCMP Op0, Op1.
MachineInstrBuilder buildFence(unsigned Ordering, unsigned Scope)
Build and insert G_FENCE Ordering, Scope.
MachineInstrBuilder buildFMinNumIEEE(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt)
MachineInstrBuilder buildSelect(const DstOp &Res, const SrcOp &Tst, const SrcOp &Op0, const SrcOp &Op1, std::optional< unsigned > Flags=std::nullopt)
Build and insert a Res = G_SELECT Tst, Op0, Op1.
MachineInstrBuilder buildFMA(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, const SrcOp &Src2, std::optional< unsigned > Flags=std::nullopt)
Build and insert Res = G_FMA Op0, Op1, Op2.
MachineInstrBuilder buildGetFPMode(const DstOp &Dst)
Build and insert Dst = G_GET_FPMODE.
MachineInstrBuilder buildAtomicRMWAnd(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_AND Addr, Val, MMO.
MachineInstrBuilder buildZExtInReg(const DstOp &Res, const SrcOp &Op, int64_t ImmOp)
Build and inserts Res = G_AND Op, LowBitsSet(ImmOp) Since there is no G_ZEXT_INREG like G_SEXT_INREG,...
MachineInstrBuilder buildSMulH(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt)
GISelCSEInfo * getCSEInfo()
MachineInstrBuilder buildAtomicRMWMin(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_MIN Addr, Val, MMO.
MachineInstrBuilder buildVecReduceFMax(const DstOp &Dst, const SrcOp &Src)
Build and insert Res = G_VECREDUCE_FMAX Src.
MachineInstrBuilder buildExtract(const DstOp &Res, const SrcOp &Src, uint64_t Index)
Build and insert Res0, ... = G_EXTRACT Src, Idx0.
MachineInstrBuilder buildMul(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt)
Build and insert Res = G_MUL Op0, Op1.
MachineInstrBuilder buildInsertSubvector(const DstOp &Res, const SrcOp &Src0, const SrcOp &Src1, unsigned Index)
Build and insert Res = G_INSERT_SUBVECTOR Src0, Src1, Idx.
MachineInstrBuilder buildAnd(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_AND Op0, Op1.
MachineInstrBuilder buildCast(const DstOp &Dst, const SrcOp &Src)
Build and insert an appropriate cast between two registers of equal size.
const TargetInstrInfo & getTII()
MachineInstrBuilder buildAtomicRMWFAdd(const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_FADD Addr, Val, MMO.
MachineInstrBuilder buildSAdde(const DstOp &Res, const DstOp &CarryOut, const SrcOp &Op0, const SrcOp &Op1, const SrcOp &CarryIn)
Build and insert Res, CarryOut = G_SADDE Op0, Op1, CarryInp.
MachineInstrBuilder buildAtomicRMWNand(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_NAND Addr, Val, MMO.
MachineInstrBuilder buildICmp(CmpInst::Predicate Pred, const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1, std::optional< unsigned > Flags=std::nullopt)
Build and insert a Res = G_ICMP Pred, Op0, Op1.
MachineInstrBuilder buildURem(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt)
Build and insert Res = G_UREM Op0, Op1.
MachineInstrBuilder buildSAddo(const DstOp &Res, const DstOp &CarryOut, const SrcOp &Op0, const SrcOp &Op1)
Build and insert Res, CarryOut = G_SADDO Op0, Op1.
MachineInstrBuilder buildFPTOUI(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_FPTOUI Src0.
MachineInstrBuilder buildLShr(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt)
MachineInstrBuilder buildFPow(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt)
Build and insert Dst = G_FPOW Src0, Src1.
MachineInstrBuilder buildAnyExtOrTrunc(const DstOp &Res, const SrcOp &Op)
Res = COPY Op depending on the differing sizes of Res and Op.
MachineInstrBuilder buildSExt(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_SEXT Op.
MachineInstrBuilder buildIntrinsicTrunc(const DstOp &Dst, const SrcOp &Src0, std::optional< unsigned > Flags=std::nullopt)
Build and insert Dst = G_INTRINSIC_TRUNC Src0.
MachineBasicBlock::iterator getInsertPt()
Current insertion point for new instructions.
MachineInstrBuilder buildSExtOrTrunc(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_SEXT Op, Res = G_TRUNC Op, or Res = COPY Op depending on the differing sizes...
MachineInstrBuilder buildShuffleSplat(const DstOp &Res, const SrcOp &Src)
Build and insert a vector splat of a scalar Src using a G_INSERT_VECTOR_ELT and G_SHUFFLE_VECTOR idio...
MachineInstrBuilder buildZExt(const DstOp &Res, const SrcOp &Op, std::optional< unsigned > Flags=std::nullopt)
Build and insert Res = G_ZEXT Op.
MachineInstrBuilder buildConcatVectors(const DstOp &Res, ArrayRef< Register > Ops)
Build and insert Res = G_CONCAT_VECTORS Op0, ...
MachineInstrBuilder buildAtomicRMW(unsigned Opcode, const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_<Opcode> Addr, Val, MMO.
MachineInstrBuilder buildVecReduceSeqFMul(const DstOp &Dst, const SrcOp &ScalarIn, const SrcOp &VecIn)
Build and insert Res = G_VECREDUCE_SEQ_FMUL ScalarIn, VecIn.
MachineInstrBuilder buildAtomicRMWUSubCond(const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_USUB_COND Addr, Val, MMO.
MachineInstrBuilder buildSub(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt)
Build and insert Res = G_SUB Op0, Op1.
MachineInstrBuilder buildIntrinsic(Intrinsic::ID ID, ArrayRef< Register > Res, bool HasSideEffects, bool isConvergent)
Build and insert a G_INTRINSIC instruction.
void setInstr(MachineInstr &MI)
Set the insertion point to before MI.
MDNode * getPCSections()
Get the current instruction's PC sections metadata.
MachineInstrBuilder buildBSwap(const DstOp &Dst, const SrcOp &Src0)
Build and insert Dst = G_BSWAP Src0.
MachineInstrBuilder buildVecReduceFMul(const DstOp &Dst, const SrcOp &ScalarIn, const SrcOp &VecIn)
Build and insert Res = G_VECREDUCE_FMUL Src.
MachineInstrBuilder buildCTLZ_ZERO_UNDEF(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_CTLZ_ZERO_UNDEF Op0, Src0.
MachineInstrBuilder buildVScale(const DstOp &Res, unsigned MinElts)
Build and insert Res = G_VSCALE MinElts.
MachineInstrBuilder buildAddrSpaceCast(const DstOp &Dst, const SrcOp &Src)
Build and insert Dst = G_ADDRSPACE_CAST Src.
MachineInstrBuilder buildSplatBuildVector(const DstOp &Res, const SrcOp &Src)
Build and insert Res = G_BUILD_VECTOR with Src replicated to fill the number of elements.
MachineInstrBuilder buildFExp2(const DstOp &Dst, const SrcOp &Src, std::optional< unsigned > Flags=std::nullopt)
Build and insert Dst = G_FEXP2 Src.
MachineInstrBuilder buildSetFPMode(const SrcOp &Src)
Build and insert G_SET_FPMODE Src.
MachineInstrBuilder buildIntToPtr(const DstOp &Dst, const SrcOp &Src)
Build and insert a G_INTTOPTR instruction.
MachineInstrBuilder buildIndirectDbgValue(Register Reg, const MDNode *Variable, const MDNode *Expr)
Build and insert a DBG_VALUE instruction expressing the fact that the associated Variable lives in me...
unsigned getBoolExtOp(bool IsVec, bool IsFP) const
MachineInstrBuilder buildUSubo(const DstOp &Res, const DstOp &CarryOut, const SrcOp &Op0, const SrcOp &Op1)
Build and insert Res, CarryOut = G_USUBO Op0, Op1.
MachineInstrBuilder buildVecReduceFAdd(const DstOp &Dst, const SrcOp &ScalarIn, const SrcOp &VecIn)
Build and insert Res = G_VECREDUCE_FADD Src.
MachineInstrBuilder buildAtomicRMWUmax(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_UMAX Addr, Val, MMO.
MachineInstrBuilder buildBuildVector(const DstOp &Res, ArrayRef< Register > Ops)
Build and insert Res = G_BUILD_VECTOR Op0, ...
MachineIRBuilder(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsPt)
MachineInstrBuilder buildAbdu(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_ABDU Op0, Op1.
MachineInstrBuilder buildVecReduceFMinimum(const DstOp &Dst, const SrcOp &Src)
Build and insert Res = G_VECREDUCE_FMINIMUM Src.
MachineInstrBuilder buildNeg(const DstOp &Dst, const SrcOp &Src0)
Build and insert integer negation Zero = G_CONSTANT 0 Res = G_SUB Zero, Op0.
MachineInstrBuilder buildVecReduceSMin(const DstOp &Dst, const SrcOp &Src)
Build and insert Res = G_VECREDUCE_SMIN Src.
MachineInstrBuilder buildCTLZ(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_CTLZ Op0, Src0.
MachineInstrBuilder buildSMax(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_SMAX Op0, Op1.
MachineInstrBuilder buildConstDbgValue(const Constant &C, const MDNode *Variable, const MDNode *Expr)
Build and insert a DBG_VALUE instructions specifying that Variable is given by C (suitably modified b...
MachineInstrBuilder buildAssertZExt(const DstOp &Res, const SrcOp &Op, unsigned Size)
Build and insert Res = G_ASSERT_ZEXT Op, Size.
void recordInsertion(MachineInstr *InsertedInstr) const
MachineInstrBuilder buildUMulH(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt)
MachineInstrBuilder buildStrictFAdd(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt)
Build and insert Res = G_STRICT_FADD Op0, Op1.
MachineInstrBuilder buildBrCond(const SrcOp &Tst, MachineBasicBlock &Dest)
Build and insert G_BRCOND Tst, Dest.
MachineInstrBuilder buildVecReduceXor(const DstOp &Dst, const SrcOp &Src)
Build and insert Res = G_VECREDUCE_XOR Src.
MachineInstrBuilder buildVecReduceFMin(const DstOp &Dst, const SrcOp &Src)
Build and insert Res = G_VECREDUCE_FMIN Src.
MachineInstrBuilder buildFDiv(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt)
Build and insert Res = G_FDIV Op0, Op1.
MachineInstrBuilder buildMergeLikeInstr(const DstOp &Res, ArrayRef< Register > Ops)
Build and insert Res = G_MERGE_VALUES Op0, ... or Res = G_BUILD_VECTOR Op0, ... or Res = G_CONCAT_VEC...
const GISelCSEInfo * getCSEInfo() const
MachineInstrBuilder buildExtractVectorElement(const DstOp &Res, const SrcOp &Val, const SrcOp &Idx)
Build and insert Res = G_EXTRACT_VECTOR_ELT Val, Idx.
MachineInstrBuilder buildLoad(const DstOp &Res, const SrcOp &Addr, MachineMemOperand &MMO)
Build and insert Res = G_LOAD Addr, MMO.
MachineInstrBuilder buildPtrAdd(const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1, std::optional< unsigned > Flags=std::nullopt)
Build and insert Res = G_PTR_ADD Op0, Op1.
MachineInstrBuilder buildZExtOrTrunc(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_ZEXT Op, Res = G_TRUNC Op, or Res = COPY Op depending on the differing sizes...
MachineInstrBuilder buildBuildVectorTrunc(const DstOp &Res, ArrayRef< Register > Ops)
Build and insert Res = G_BUILD_VECTOR_TRUNC Op0, ...
MachineBasicBlock & getMBB()
MachineIRBuilder(MachineInstr &MI)
MachineInstrBuilder buildExtractVectorElementConstant(const DstOp &Res, const SrcOp &Val, const int Idx)
Build and insert Res = G_EXTRACT_VECTOR_ELT Val, Idx.
MachineInstrBuilder buildCTTZ_ZERO_UNDEF(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_CTTZ_ZERO_UNDEF Op0, Src0.
virtual MachineInstrBuilder buildFConstant(const DstOp &Res, const ConstantFP &Val)
Build and insert Res = G_FCONSTANT Val.
MachineInstrBuilder buildBitReverse(const DstOp &Dst, const SrcOp &Src)
Build and insert Dst = G_BITREVERSE Src.
MachineInstrBuilder buildShl(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt)
MachineInstrBuilder buildUITOFP(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_UITOFP Src0.
MachineInstrBuilder buildStore(const SrcOp &Val, const SrcOp &Addr, MachineMemOperand &MMO)
Build and insert G_STORE Val, Addr, MMO.
MachineInstrBuilder buildInstr(unsigned Opcode)
Build and insert <empty> = Opcode <empty>.
MachineInstrBuilder buildSITOFP(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_SITOFP Src0.
MachineIRBuilder(MachineInstr &MI, GISelChangeObserver &Observer)
MachineInstrBuilder buildFMAD(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, const SrcOp &Src2, std::optional< unsigned > Flags=std::nullopt)
Build and insert Res = G_FMAD Op0, Op1, Op2.
MachineInstrBuilder buildPadVectorWithUndefElements(const DstOp &Res, const SrcOp &Op0)
Build and insert a, b, ..., x = G_UNMERGE_VALUES Op0 Res = G_BUILD_VECTOR a, b, .....
MachineInstrBuilder buildAbds(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_ABDS Op0, Op1.
MachineInstrBuilder buildFLog(const DstOp &Dst, const SrcOp &Src, std::optional< unsigned > Flags=std::nullopt)
Build and insert Dst = G_FLOG Src.
void validateSelectOp(const LLT ResTy, const LLT TstTy, const LLT Op0Ty, const LLT Op1Ty)
MachineInstrBuilder buildFrameIndex(const DstOp &Res, int Idx)
Build and insert Res = G_FRAME_INDEX Idx.
MachineInstrBuilder buildVecReduceUMax(const DstOp &Dst, const SrcOp &Src)
Build and insert Res = G_VECREDUCE_UMAX Src.
MachineInstrBuilder buildDirectDbgValue(Register Reg, const MDNode *Variable, const MDNode *Expr)
Build and insert a DBG_VALUE instruction expressing the fact that the associated Variable lives in Re...
const DebugLoc & getDL()
Getter for DebugLoc.
MachineInstrBuilder buildUbfx(const DstOp &Dst, const SrcOp &Src, const SrcOp &LSB, const SrcOp &Width)
Build and insert Dst = G_UBFX Src, LSB, Width.
const MachineRegisterInfo * getMRI() const
MachineInstrBuilder buildCTPOP(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_CTPOP Op0, Src0.
MachineInstrBuilder buildAbs(const DstOp &Dst, const SrcOp &Src)
Build and insert Dst = G_ABS Src.
MachineInstrBuilder buildBuildVectorConstant(const DstOp &Res, ArrayRef< APInt > Ops)
Build and insert Res = G_BUILD_VECTOR Op0, ... where each OpN is built with G_CONSTANT.
MachineInstrBuilder buildAtomicRMWUmin(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_UMIN Addr, Val, MMO.
void validateBinaryOp(const LLT Res, const LLT Op0, const LLT Op1)
MachineInstrBuilder buildVecReduceAnd(const DstOp &Dst, const SrcOp &Src)
Build and insert Res = G_VECREDUCE_AND Src.
MachineInstrBuilder buildVecReduceFMaximum(const DstOp &Dst, const SrcOp &Src)
Build and insert Res = G_VECREDUCE_FMAXIMUM Src.
void validateShiftOp(const LLT Res, const LLT Op0, const LLT Op1)
MachineFunction & getMF()
Getter for the function we currently build.
MachineIRBuilder(MachineFunction &MF)
MachineIRBuilder(const MachineIRBuilderState &BState)
MachineInstrBuilder buildMemCpy(const SrcOp &DstPtr, const SrcOp &SrcPtr, const SrcOp &Size, MachineMemOperand &DstMMO, MachineMemOperand &SrcMMO)
MachineInstrBuilder buildAssertAlign(const DstOp &Res, const SrcOp &Op, Align AlignVal)
Build and insert Res = G_ASSERT_ALIGN Op, AlignVal.
MachineInstrBuilder buildSbfx(const DstOp &Dst, const SrcOp &Src, const SrcOp &LSB, const SrcOp &Width)
Build and insert Dst = G_SBFX Src, LSB, Width.
MachineInstrBuilder buildFMaxNum(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt)
MachineInstrBuilder buildSMin(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_SMIN Op0, Op1.
MachineInstrBuilder buildFMinNum(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt)
MachineInstrBuilder buildDbgLabel(const MDNode *Label)
Build and insert a DBG_LABEL instructions specifying that Label is given.
MachineInstrBuilder buildBrJT(Register TablePtr, unsigned JTI, Register IndexReg)
Build and insert G_BRJT TablePtr, JTI, IndexReg.
MachineInstrBuilder buildInsert(const DstOp &Res, const SrcOp &Src, const SrcOp &Op, unsigned Index)
MachineInstrBuilder buildDynStackAlloc(const DstOp &Res, const SrcOp &Size, Align Alignment)
Build and insert Res = G_DYN_STACKALLOC Size, Align.
MachineInstrBuilder buildVecReduceUMin(const DstOp &Dst, const SrcOp &Src)
Build and insert Res = G_VECREDUCE_UMIN Src.
MachineInstrBuilder buildFIDbgValue(int FI, const MDNode *Variable, const MDNode *Expr)
Build and insert a DBG_VALUE instruction expressing the fact that the associated Variable lives in th...
void setInstrAndDebugLoc(MachineInstr &MI)
Set the insertion point to before MI, and set the debug loc to MI's loc.
void setMMRAMetadata(MDNode *MMRA)
Set the PC sections metadata to MD for all the next build instructions.
MachineInstrBuilder buildSSube(const DstOp &Res, const DstOp &CarryOut, const SrcOp &Op0, const SrcOp &Op1, const SrcOp &CarryIn)
Build and insert Res, CarryOut = G_SSUBE Op0, Op1, CarryInp.
MachineInstrBuilder buildIntrinsicRoundeven(const DstOp &Dst, const SrcOp &Src0, std::optional< unsigned > Flags=std::nullopt)
Build and insert Dst = G_INTRINSIC_ROUNDEVEN Src0, Src1.
MachineInstrBuilder buildResetFPEnv()
Build and insert G_RESET_FPENV.
void setPCSections(MDNode *MD)
Set the PC sections metadata to MD for all the next build instructions.
MachineInstrBuilder buildExtOrTrunc(unsigned ExtOpc, const DstOp &Res, const SrcOp &Op)
Build and insert Res = ExtOpc, Res = G_TRUNC Op, or Res = COPY Op depending on the differing sizes of...
MachineInstrBuilder buildVecReduceAdd(const DstOp &Dst, const SrcOp &Src)
Build and insert Res = G_VECREDUCE_ADD Src.
MachineInstrBuilder buildAtomicRMWSub(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_SUB Addr, Val, MMO.
MachineInstrBuilder buildIsFPClass(const DstOp &Res, const SrcOp &Src, unsigned Mask)
Build and insert a Res = G_IS_FPCLASS Src, Mask.
MachineInstrBuilder buildMergeValues(const DstOp &Res, ArrayRef< Register > Ops)
Build and insert Res = G_MERGE_VALUES Op0, ...
MachineInstrBuilder buildTrunc(const DstOp &Res, const SrcOp &Op, std::optional< unsigned > Flags=std::nullopt)
Build and insert Res = G_TRUNC Op.
MachineInstrBuilder buildUAdde(const DstOp &Res, const DstOp &CarryOut, const SrcOp &Op0, const SrcOp &Op1, const SrcOp &CarryIn)
Build and insert Res, CarryOut = G_UADDE Op0, Op1, CarryIn.
MachineInstrBuilder buildAtomicRMWFMax(const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_FMAX Addr, Val, MMO.
void setDebugLoc(const DebugLoc &DL)
Set the debug location to DL for all the next build instructions.
MachineInstrBuilder buildGetFPEnv(const DstOp &Dst)
Build and insert Dst = G_GET_FPENV.
MachineInstrBuilder buildFCopysign(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_FCOPYSIGN Op0, Op1.
MachineInstrBuilder buildSSubo(const DstOp &Res, const DstOp &CarryOut, const SrcOp &Op0, const SrcOp &Op1)
Build and insert Res, CarryOut = G_SUBO Op0, Op1.
MachineInstrBuilder buildAtomicRMWOr(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_OR Addr, Val, MMO.
bool isObservingChanges() const
MachineInstrBuilder buildUSube(const DstOp &Res, const DstOp &CarryOut, const SrcOp &Op0, const SrcOp &Op1, const SrcOp &CarryIn)
Build and insert Res, CarryOut = G_USUBE Op0, Op1, CarryInp.
const MachineBasicBlock & getMBB() const
Getter for the basic block we currently build.
MachineInstrBuilder buildFNeg(const DstOp &Dst, const SrcOp &Src0, std::optional< unsigned > Flags=std::nullopt)
Build and insert Res = G_FNEG Op0.
MachineInstrBuilder buildInsertVectorElement(const DstOp &Res, const SrcOp &Val, const SrcOp &Elt, const SrcOp &Idx)
Build and insert Res = G_INSERT_VECTOR_ELT Val, Elt, Idx.
MachineInstrBuilder buildAnyExt(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_ANYEXT Op0.
MachineInstrBuilder buildAtomicCmpXchgWithSuccess(const DstOp &OldValRes, const DstOp &SuccessRes, const SrcOp &Addr, const SrcOp &CmpVal, const SrcOp &NewVal, MachineMemOperand &MMO)
Build and insert OldValRes<def>, SuccessRes<def> = G_ATOMIC_CMPXCHG_WITH_SUCCESS Addr,...
void setMBB(MachineBasicBlock &MBB)
Set the insertion point to the end of MBB.
MachineInstrBuilder buildBitcast(const DstOp &Dst, const SrcOp &Src)
Build and insert Dst = G_BITCAST Src.
const DebugLoc & getDebugLoc()
Get the current instruction's debug location.
MachineInstrBuilder buildUAddo(const DstOp &Res, const DstOp &CarryOut, const SrcOp &Op0, const SrcOp &Op1)
Build and insert Res, CarryOut = G_UADDO Op0, Op1.
void setCSEInfo(GISelCSEInfo *Info)
MachineInstrBuilder buildFMaxNumIEEE(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt)
MachineInstrBuilder buildTrap(bool Debug=false)
Build and insert G_TRAP or G_DEBUGTRAP.
MachineInstrBuilder buildFFloor(const DstOp &Dst, const SrcOp &Src0, std::optional< unsigned > Flags=std::nullopt)
Build and insert Res = GFFLOOR Op0, Op1.
MachineInstrBuilder buildFFrexp(const DstOp &Fract, const DstOp &Exp, const SrcOp &Src, std::optional< unsigned > Flags=std::nullopt)
Build and insert Fract, Exp = G_FFREXP Src.
MachineIRBuilder()=default
Some constructors for easy use.
MachineInstrBuilder buildDeleteTrailingVectorElements(const DstOp &Res, const SrcOp &Op0)
Build and insert a, b, ..., x, y, z = G_UNMERGE_VALUES Op0 Res = G_BUILD_VECTOR a,...
MachineRegisterInfo * getMRI()
Getter for MRI.
MachineInstrBuilder buildAtomicRMWAdd(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_ADD Addr, Val, MMO.
MachineInstrBuilder buildFPTrunc(const DstOp &Res, const SrcOp &Op, std::optional< unsigned > Flags=std::nullopt)
Build and insert Res = G_FPTRUNC Op.
MachineInstrBuilder buildOr(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt)
Build and insert Res = G_OR Op0, Op1.
MachineInstrBuilder buildFSincos(const DstOp &Sin, const DstOp &Cos, const SrcOp &Src, std::optional< unsigned > Flags=std::nullopt)
Build and insert Sin, Cos = G_FSINCOS Src.
MachineInstrBuilder buildAtomicCmpXchg(const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &CmpVal, const SrcOp &NewVal, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMIC_CMPXCHG Addr, CmpVal, NewVal, MMO.
MachineIRBuilderState & getState()
Getter for the State.
MachineInstrBuilder buildShuffleVector(const DstOp &Res, const SrcOp &Src1, const SrcOp &Src2, ArrayRef< int > Mask)
Build and insert Res = G_SHUFFLE_VECTOR Src1, Src2, Mask.
MachineInstrBuilder buildAssertInstr(unsigned Opc, const DstOp &Res, const SrcOp &Op, unsigned Val)
Build and insert G_ASSERT_SEXT, G_ASSERT_ZEXT, or G_ASSERT_ALIGN.
void validateTruncExt(const LLT Dst, const LLT Src, bool IsExtend)
MachineInstrBuilder buildInstrNoInsert(unsigned Opcode)
Build but don't insert <empty> = Opcode <empty>.
MachineInstrBuilder buildPtrMask(const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1)
Build and insert Res = G_PTRMASK Op0, Op1.
MachineInstrBuilder buildCopy(const DstOp &Res, const SrcOp &Op)
Build and insert Res = COPY Op.
MachineInstrBuilder buildVecReduceSMax(const DstOp &Dst, const SrcOp &Src)
Build and insert Res = G_VECREDUCE_SMAX Src.
MachineInstrBuilder buildMemTransferInst(unsigned Opcode, const SrcOp &DstPtr, const SrcOp &SrcPtr, const SrcOp &Size, MachineMemOperand &DstMMO, MachineMemOperand &SrcMMO)
Build and insert G_MEMCPY or G_MEMMOVE.
void validateUnaryOp(const LLT Res, const LLT Op0)
MachineInstrBuilder buildBlockAddress(Register Res, const BlockAddress *BA)
Build and insert Res = G_BLOCK_ADDR BA.
MDNode * getMMRAMetadata()
Get the current instruction's MMRA metadata.
MachineInstrBuilder buildAtomicRMWMax(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_MAX Addr, Val, MMO.
MachineInstrBuilder buildPrefetch(const SrcOp &Addr, unsigned RW, unsigned Locality, unsigned CacheType, MachineMemOperand &MMO)
Build and insert G_PREFETCH Addr, RW, Locality, CacheType.
MachineInstrBuilder buildExtractSubvector(const DstOp &Res, const SrcOp &Src, unsigned Index)
Build and insert Res = G_EXTRACT_SUBVECTOR Src, Idx0.
const DataLayout & getDataLayout() const
MachineInstrBuilder buildBrIndirect(Register Tgt)
Build and insert G_BRINDIRECT Tgt.
MachineInstrBuilder buildSplatVector(const DstOp &Res, const SrcOp &Val)
Build and insert Res = G_SPLAT_VECTOR Val.
MachineInstrBuilder buildLoadInstr(unsigned Opcode, const DstOp &Res, const SrcOp &Addr, MachineMemOperand &MMO)
Build and insert Res = <opcode> Addr, MMO.
void setMF(MachineFunction &MF)
MachineInstrBuilder buildStepVector(const DstOp &Res, unsigned Step)
Build and insert Res = G_STEP_VECTOR Step.
MachineInstrBuilder buildAtomicRMWFSub(const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_FSUB Addr, Val, MMO.
MachineInstrBuilder buildAssertSExt(const DstOp &Res, const SrcOp &Op, unsigned Size)
Build and insert Res = G_ASSERT_SEXT Op, Size.
MachineInstrBuilder buildXor(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_XOR Op0, Op1.
MachineInstrBuilder buildAtomicRMWXchg(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_XCHG Addr, Val, MMO.
void setState(const MachineIRBuilderState &NewState)
Setter for the State.
void setChangeObserver(GISelChangeObserver &Observer)
MachineInstrBuilder buildMaskLowPtrBits(const DstOp &Res, const SrcOp &Op0, uint32_t NumBits)
Build and insert Res = G_PTRMASK Op0, G_CONSTANT (1 << NumBits) - 1.
virtual MachineInstrBuilder buildConstant(const DstOp &Res, const ConstantInt &Val)
Build and insert Res = G_CONSTANT Val.
MachineInstrBuilder buildVecReduceMul(const DstOp &Dst, const SrcOp &Src)
Build and insert Res = G_VECREDUCE_MUL Src.
MachineInstrBuilder buildUMin(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_UMIN Op0, Op1.
MachineInstrBuilder buildUMax(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_UMAX Op0, Op1.
MachineInstrBuilder buildFCmp(CmpInst::Predicate Pred, const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1, std::optional< unsigned > Flags=std::nullopt)
Build and insert a Res = G_FCMP PredOp0, Op1.
MachineInstrBuilder buildFAdd(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt)
Build and insert Res = G_FADD Op0, Op1.
MachineInstrBuilder buildSetFPEnv(const SrcOp &Src)
Build and insert G_SET_FPENV Src.
MachineInstrBuilder buildPtrToInt(const DstOp &Dst, const SrcOp &Src)
Build and insert a G_PTRTOINT instruction.
MachineInstrBuilder buildFCanonicalize(const DstOp &Dst, const SrcOp &Src0, std::optional< unsigned > Flags=std::nullopt)
Build and insert Dst = G_FCANONICALIZE Src0.
MachineInstrBuilder buildSExtInReg(const DstOp &Res, const SrcOp &Op, int64_t ImmOp)
Build and insert Res = G_SEXT_INREG Op, ImmOp.
MachineInstrBuilder buildRotateLeft(const DstOp &Dst, const SrcOp &Src, const SrcOp &Amt)
Build and insert Dst = G_ROTL Src, Amt.
MachineInstrBuilder buildConstantPtrAuth(const DstOp &Res, const ConstantPtrAuth *CPA, Register Addr, Register AddrDisc)
Build and insert G_PTRAUTH_GLOBAL_VALUE.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & addPredicate(CmpInst::Predicate Pred) const
const MachineInstrBuilder & addUse(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register use operand.
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
const MachineInstrBuilder & addDef(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register definition operand.
Representation of each machine instruction.
Definition: MachineInstr.h:71
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:587
A description of a memory reference used in the backend.
Flags
Flags values. These may be or'd together.
MachineOperand class - Representation of each machine instruction operand.
Register getReg() const
getReg - Returns the register number.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
SrcOp(const MachineInstrBuilder &MIB)
SrcOp(int64_t V)
SrcOp(const CmpInst::Predicate P)
SrcOp(uint64_t V)
SrcOp(int)=delete
MachineInstrBuilder SrcMIB
CmpInst::Predicate getPredicate() const
SrcType getSrcOpKind() const
CmpInst::Predicate Pred
int64_t getImm() const
LLT getLLTTy(const MachineRegisterInfo &MRI) const
SrcOp(const MachineOperand &Op)
void addSrcToMIB(MachineInstrBuilder &MIB) const
SrcOp(unsigned)=delete
Use of registers held in unsigned integer variables (or more rarely signed integers) is no longer per...
Register getReg() const
SrcOp(Register R)
TargetInstrInfo - Interface to description of machine instruction set.
virtual MVT getVectorIdxTy(const DataLayout &DL) const
Returns the type to be used for the index operand of: ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT...
virtual const TargetLowering * getTargetLowering() const
LLVM Value Representation.
Definition: Value.h:74
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ C
The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
@ ConstantFP
Definition: ISDOpcodes.h:77
@ BlockAddress
Definition: ISDOpcodes.h:84
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Offset
Definition: DWP.cpp:480
DWARFExpression::Operation Op
A collection of metadata nodes that might be associated with a memory access used by the alias-analys...
Definition: Metadata.h:764
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
uint64_t value() const
This is a hole in the type system and should not be abused.
Definition: Alignment.h:85
Class which stores all the state required in a MachineIRBuilder.
MachineFunction * MF
MachineFunction under construction.
MDNode * MMRA
MMRA Metadata to be set on any instruction we create.
DebugLoc DL
Debug location to be set to any instruction we create.
const TargetInstrInfo * TII
Information used to access the description of the opcodes.
MDNode * PCSections
PC sections metadata to be set to any instruction we create.
MachineBasicBlock::iterator II
MachineRegisterInfo * MRI
Information used to verify types are consistent and to create virtual registers.
GISelChangeObserver * Observer
This class contains a discriminated union of information about pointers in memory operands,...
All attributes(register class or bank and low-level type) a virtual register can have.