AMDGPUInstructionSelector.cpp File Reference

This file implements the targeting of the InstructionSelector class for AMDGPU. More...

#include "AMDGPUInstructionSelector.h"
#include "AMDGPU.h"
#include "AMDGPUGlobalISelUtils.h"
#include "AMDGPUInstrInfo.h"
#include "AMDGPURegisterBankInfo.h"
#include "AMDGPUTargetMachine.h"
#include "SIMachineFunctionInfo.h"
#include "Utils/AMDGPUBaseInfo.h"
#include "llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h"
#include "llvm/CodeGen/GlobalISel/GISelKnownBits.h"
#include "llvm/CodeGen/GlobalISel/GenericMachineInstrs.h"
#include "llvm/CodeGen/GlobalISel/MIPatternMatch.h"
#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/IR/DiagnosticInfo.h"
#include "llvm/IR/IntrinsicsAMDGPU.h"
#include <optional>
#include "AMDGPUGenGlobalISel.inc"

Go to the source code of this file.

Macros
#define	DEBUG_TYPE   "amdgpu-isel"
#define	GET_GLOBALISEL_IMPL
#define	AMDGPUSubtarget   GCNSubtarget
#define	GET_GLOBALISEL_PREDICATES_INIT
#define	GET_GLOBALISEL_TEMPORARIES_INIT

Functions
static Register	getWaveAddress (const MachineInstr *Def)
static unsigned	getLogicalBitOpcode (unsigned Opc, bool Is64)
static int	getV_CMPOpcode (CmpInst::Predicate P, unsigned Size, const GCNSubtarget &ST)
static bool	isLaneMaskFromSameBlock (Register Reg, MachineRegisterInfo &MRI, MachineBasicBlock *MBB)
static unsigned	gwsIntrinToOpcode (unsigned IntrID)
static bool	parseTexFail (uint64_t TexFailCtrl, bool &TFE, bool &LWE, bool &IsTexFail)
static bool	shouldUseAndMask (unsigned Size, unsigned &Mask)
static Register	stripCopy (Register Reg, MachineRegisterInfo &MRI)
static Register	stripBitCast (Register Reg, MachineRegisterInfo &MRI)
static bool	isExtractHiElt (MachineRegisterInfo &MRI, Register In, Register &Out)
static bool	isConstant (const MachineInstr &MI)
static bool	isVCmpResult (Register Reg, MachineRegisterInfo &MRI)
static std::pair< Register, unsigned >	computeIndirectRegIndex (MachineRegisterInfo &MRI, const SIRegisterInfo &TRI, const TargetRegisterClass *SuperRC, Register IdxReg, unsigned EltSize, GISelKnownBits &KnownBits)
	Return the register to use for the index value, and the subregister to use for the indirectly accessed register.
static Register	matchZeroExtendFromS32 (MachineRegisterInfo &MRI, Register Reg)
	Match a zero extend from a 32-bit value to 64-bits.
static std::pair< unsigned, uint8_t >	BitOp3_Op (Register R, SmallVectorImpl< Register > &Src, const MachineRegisterInfo &MRI)
static Register	buildRegSequence (SmallVectorImpl< Register > &Elts, MachineInstr *InsertPt, MachineRegisterInfo &MRI)
static void	selectWMMAModsNegAbs (unsigned ModOpcode, unsigned &Mods, SmallVectorImpl< Register > &Elts, Register &Src, MachineInstr *InsertPt, MachineRegisterInfo &MRI)
static bool	isNoUnsignedWrap (MachineInstr *Addr)
static void	addZeroImm (MachineInstrBuilder &MIB)
static Register	buildRSRC (MachineIRBuilder &B, MachineRegisterInfo &MRI, uint32_t FormatLo, uint32_t FormatHi, Register BasePtr)
	Return a resource descriptor for use with an arbitrary 64-bit pointer.
static Register	buildAddr64RSrc (MachineIRBuilder &B, MachineRegisterInfo &MRI, const SIInstrInfo &TII, Register BasePtr)
static Register	buildOffsetSrc (MachineIRBuilder &B, MachineRegisterInfo &MRI, const SIInstrInfo &TII, Register BasePtr)
static std::optional< uint64_t >	getConstantZext32Val (Register Reg, const MachineRegisterInfo &MRI)
	Get an immediate that must be 32-bits, and treated as zero extended.
unsigned	getNamedBarrierOp (bool HasInlineConst, Intrinsic::ID IntrID)

Detailed Description

This file implements the targeting of the InstructionSelector class for AMDGPU.

Todo:

This should be generated by TableGen.

Definition in file AMDGPUInstructionSelector.cpp.

Macro Definition Documentation

AMDGPUSubtarget

#define AMDGPUSubtarget   GCNSubtarget

Definition at line 38 of file AMDGPUInstructionSelector.cpp.

DEBUG_TYPE

#define DEBUG_TYPE   "amdgpu-isel"

Definition at line 32 of file AMDGPUInstructionSelector.cpp.

GET_GLOBALISEL_IMPL

#define GET_GLOBALISEL_IMPL

Definition at line 37 of file AMDGPUInstructionSelector.cpp.

GET_GLOBALISEL_PREDICATES_INIT

#define GET_GLOBALISEL_PREDICATES_INIT

GET_GLOBALISEL_TEMPORARIES_INIT

#define GET_GLOBALISEL_TEMPORARIES_INIT

Function Documentation

addZeroImm()

static void addZeroImm ( MachineInstrBuilder &  MIB )

static

Definition at line 5368 of file AMDGPUInstructionSelector.cpp.

References llvm::MachineInstrBuilder::addImm().

BitOp3_Op()

static std::pair< unsigned, uint8_t > BitOp3_Op ( Register  R, SmallVectorImpl< Register > &  Src, const MachineRegisterInfo &  MRI  )

static

Definition at line 3648 of file AMDGPUInstructionSelector.cpp.

References BitOp3_Op(), llvm::getSrcRegIgnoringCopies(), I, LHS, llvm::MIPatternMatch::m_AllOnesInt(), llvm::PatternMatch::m_Not(), llvm::MIPatternMatch::m_Reg(), llvm::PatternMatch::m_ZeroInt(), MI, llvm::MIPatternMatch::mi_match(), MRI, and RHS.

Referenced by BitOp3_Op().

buildAddr64RSrc()

static Register buildAddr64RSrc ( MachineIRBuilder &  B, MachineRegisterInfo &  MRI, const SIInstrInfo &  TII, Register  BasePtr  )

static

Definition at line 5417 of file AMDGPUInstructionSelector.cpp.

References B, buildRSRC(), llvm::Hi_32(), MRI, and TII.

buildOffsetSrc()

static Register buildOffsetSrc ( MachineIRBuilder &  B, MachineRegisterInfo &  MRI, const SIInstrInfo &  TII, Register  BasePtr  )

static

Definition at line 5426 of file AMDGPUInstructionSelector.cpp.

References B, buildRSRC(), llvm::Hi_32(), MRI, and TII.

buildRegSequence()

static Register buildRegSequence ( SmallVectorImpl< Register > &  Elts, MachineInstr *  InsertPt, MachineRegisterInfo &  MRI  )

static

Definition at line 4279 of file AMDGPUInstructionSelector.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), B, llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::SIRegisterInfo::getSubRegFromChannel(), llvm_unreachable, MRI, and llvm::SmallVectorBase< Size_T >::size().

Referenced by selectWMMAModsNegAbs().

buildRSRC()

static Register buildRSRC ( MachineIRBuilder &  B, MachineRegisterInfo &  MRI, uint32_t  FormatLo, uint32_t  FormatHi, Register  BasePtr  )

static

Return a resource descriptor for use with an arbitrary 64-bit pointer.

If BasePtr is not valid, a null base pointer will be used.

Definition at line 5374 of file AMDGPUInstructionSelector.cpp.

References B, and MRI.

Referenced by buildAddr64RSrc(), and buildOffsetSrc().

computeIndirectRegIndex()

static std::pair< Register, unsigned > computeIndirectRegIndex ( MachineRegisterInfo &  MRI, const SIRegisterInfo &  TRI, const TargetRegisterClass *  SuperRC, Register  IdxReg, unsigned  EltSize, GISelKnownBits &  KnownBits  )

static

Return the register to use for the index value, and the subregister to use for the indirectly accessed register.

Definition at line 3083 of file AMDGPUInstructionSelector.cpp.

References assert(), llvm::AMDGPU::getBaseWithConstantOffset(), MRI, llvm::Offset, llvm::ArrayRef< T >::size(), and TRI.

getConstantZext32Val()

static std::optional< uint64_t > getConstantZext32Val ( Register  Reg, const MachineRegisterInfo &  MRI  )

static

Get an immediate that must be 32-bits, and treated as zero extended.

Definition at line 5646 of file AMDGPUInstructionSelector.cpp.

References llvm::getIConstantVRegSExtVal(), llvm::Lo_32(), and MRI.

getLogicalBitOpcode()

static unsigned getLogicalBitOpcode ( unsigned  Opc, bool  Is64  )

static

Definition at line 292 of file AMDGPUInstructionSelector.cpp.

References llvm_unreachable.

getNamedBarrierOp()

unsigned getNamedBarrierOp	(	bool	HasInlineConst,
		Intrinsic::ID	IntrID
	)

Definition at line 5834 of file AMDGPUInstructionSelector.cpp.

References llvm_unreachable.

getV_CMPOpcode()

static int getV_CMPOpcode ( CmpInst::Predicate  P, unsigned  Size, const GCNSubtarget &  ST  )

static

Definition at line 1116 of file AMDGPUInstructionSelector.cpp.

References llvm::CmpInst::FCMP_FALSE, llvm::CmpInst::FCMP_OEQ, llvm::CmpInst::FCMP_OGE, llvm::CmpInst::FCMP_OGT, llvm::CmpInst::FCMP_OLE, llvm::CmpInst::FCMP_OLT, llvm::CmpInst::FCMP_ONE, llvm::CmpInst::FCMP_ORD, llvm::CmpInst::FCMP_TRUE, llvm::CmpInst::FCMP_UEQ, llvm::CmpInst::FCMP_UGE, llvm::CmpInst::FCMP_UGT, llvm::CmpInst::FCMP_ULE, llvm::CmpInst::FCMP_ULT, llvm::CmpInst::FCMP_UNE, llvm::CmpInst::FCMP_UNO, llvm::CmpInst::ICMP_EQ, llvm::CmpInst::ICMP_NE, llvm::CmpInst::ICMP_SGE, llvm::CmpInst::ICMP_SGT, llvm::CmpInst::ICMP_SLE, llvm::CmpInst::ICMP_SLT, llvm::CmpInst::ICMP_UGE, llvm::CmpInst::ICMP_UGT, llvm::CmpInst::ICMP_ULE, llvm::CmpInst::ICMP_ULT, llvm_unreachable, P, Select, and Size.

getWaveAddress()

static Register getWaveAddress ( const MachineInstr *  Def )

static

Definition at line 70 of file AMDGPUInstructionSelector.cpp.

gwsIntrinToOpcode()

static unsigned gwsIntrinToOpcode ( unsigned  IntrID )

static

Definition at line 1730 of file AMDGPUInstructionSelector.cpp.

References llvm_unreachable.

isConstant()

static bool isConstant ( const MachineInstr &  MI )

static

Definition at line 2780 of file AMDGPUInstructionSelector.cpp.

References MI.

Referenced by arePointersCompatible(), llvm::buildModuleSummaryIndex(), llvm::MDBuilder::createTBAANode(), llvm::HexagonInstrInfo::expandPostRAPseudo(), llvm::slpvectorizer::BoUpSLP::findReusedOrderedScalars(), getMemcpyLoadsAndStores(), isSimpleVIDSequence(), and tryFoldHelper().

isExtractHiElt()

static bool isExtractHiElt ( MachineRegisterInfo &  MRI, Register  In, Register &  Out  )

static

Definition at line 2622 of file AMDGPUInstructionSelector.cpp.

References assert(), llvm::LLT::fixed_vector(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::getShuffleMask(), llvm::MIPatternMatch::m_GLShr(), llvm::MIPatternMatch::m_GTrunc(), llvm::MIPatternMatch::m_Reg(), llvm::MIPatternMatch::m_SpecificICst(), llvm::MIPatternMatch::mi_match(), MRI, stripBitCast(), and stripCopy().

Referenced by buildRegSequence16().

isLaneMaskFromSameBlock()

static bool isLaneMaskFromSameBlock ( Register  Reg, MachineRegisterInfo &  MRI, MachineBasicBlock *  MBB  )

static

Definition at line 1466 of file AMDGPUInstructionSelector.cpp.

References llvm::RegisterBank::getID(), isLaneMaskFromSameBlock(), LHS, llvm::MIPatternMatch::m_GAnd(), llvm::MIPatternMatch::m_Reg(), MBB, MI, llvm::MIPatternMatch::mi_match(), MRI, and RHS.

Referenced by isLaneMaskFromSameBlock().

isNoUnsignedWrap()

static bool isNoUnsignedWrap ( MachineInstr *  Addr )

static

Definition at line 5092 of file AMDGPUInstructionSelector.cpp.

References Addr, and llvm::MachineInstr::NoUWrap.

isVCmpResult()

static bool isVCmpResult ( Register  Reg, MachineRegisterInfo &  MRI  )

static

Definition at line 2877 of file AMDGPUInstructionSelector.cpp.

References isVCmpResult(), MI, and MRI.

Referenced by isVCmpResult().

matchZeroExtendFromS32()

static Register matchZeroExtendFromS32 ( MachineRegisterInfo &  MRI, Register  Reg  )

static

Match a zero extend from a 32-bit value to 64-bits.

Definition at line 3374 of file AMDGPUInstructionSelector.cpp.

References assert(), llvm::getDefIgnoringCopies(), llvm::MIPatternMatch::m_GZExt(), llvm::MIPatternMatch::m_Reg(), llvm::PatternMatch::m_ZeroInt(), llvm::MIPatternMatch::mi_match(), MRI, and llvm::LLT::scalar().

parseTexFail()

static bool parseTexFail ( uint64_t  TexFailCtrl, bool &  TFE, bool &  LWE, bool &  IsTexFail  )

static

Definition at line 1913 of file AMDGPUInstructionSelector.cpp.

selectWMMAModsNegAbs()

static void selectWMMAModsNegAbs ( unsigned  ModOpcode, unsigned &  Mods, SmallVectorImpl< Register > &  Elts, Register &  Src, MachineInstr *  InsertPt, MachineRegisterInfo &  MRI  )

static

Definition at line 4307 of file AMDGPUInstructionSelector.cpp.

References assert(), buildRegSequence(), llvm::MIPatternMatch::m_GFabs(), llvm::MIPatternMatch::m_Reg(), llvm::MIPatternMatch::mi_match(), MRI, llvm::SISrcMods::NEG, llvm::SISrcMods::NEG_HI, llvm::SmallVectorTemplateBase< T, bool >::push_back(), and llvm::SmallVectorBase< Size_T >::size().

shouldUseAndMask()

static bool shouldUseAndMask ( unsigned  Size, unsigned &  Mask  )

static

Returns

true if a bitmask for Size bits will be an inline immediate.

Definition at line 2441 of file AMDGPUInstructionSelector.cpp.

References Size.

stripBitCast()

static Register stripBitCast ( Register  Reg, MachineRegisterInfo &  MRI  )

static

Definition at line 2615 of file AMDGPUInstructionSelector.cpp.

References llvm::MIPatternMatch::m_GBitcast(), llvm::MIPatternMatch::m_Reg(), llvm::MIPatternMatch::mi_match(), and MRI.

Referenced by isExtractHiElt().

stripCopy()

static Register stripCopy ( Register  Reg, MachineRegisterInfo &  MRI  )

static

Definition at line 2611 of file AMDGPUInstructionSelector.cpp.

References llvm::getDefSrcRegIgnoringCopies(), and MRI.

Referenced by isExtractHiElt().