13#ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRUCTIONSELECTOR_H
14#define LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRUCTIONSELECTOR_H
21#define GET_GLOBALISEL_PREDICATE_BITSET
22#define AMDGPUSubtarget GCNSubtarget
23#include "AMDGPUGenGlobalISel.inc"
24#undef GET_GLOBALISEL_PREDICATE_BITSET
31struct ImageDimIntrinsicInfo;
34class AMDGPURegisterBankInfo;
35class AMDGPUTargetMachine;
36class BlockFrequencyInfo;
37class ProfileSummaryInfo;
40class MachineIRBuilder;
42class MachineRegisterInfo;
46class TargetRegisterClass;
86 unsigned SubIdx)
const;
88 bool constrainCopyLikeIntrin(
MachineInstr &
MI,
unsigned NewOpc)
const;
123 bool selectDSAppendConsume(
MachineInstr &
MI,
bool IsAppend)
const;
129 bool selectG_INTRINSIC_W_SIDE_EFFECTS(
MachineInstr &
I)
const;
154 std::pair<Register, unsigned> selectVOP3ModsImpl(
MachineOperand &Root,
155 bool IsCanonicalizing =
true,
156 bool AllowAbs =
true,
157 bool OpSel =
false)
const;
161 bool ForceVGPR =
false)
const;
184 std::pair<Register, unsigned>
186 bool IsDOT =
false)
const;
232 std::pair<Register, int> selectFlatOffsetImpl(
MachineOperand &Root,
258 bool isDSOffset2Legal(
Register Base, int64_t Offset0, int64_t Offset1,
259 unsigned Size)
const;
264 std::pair<Register, unsigned>
275 std::pair<Register, unsigned> selectDSReadWrite2Impl(
MachineOperand &Root,
276 unsigned size)
const;
280 std::pair<Register, int64_t>
281 getPtrBaseWithConstantOffset(
Register Root,
287 struct MUBUFAddressData {
292 bool shouldUseAddr64(MUBUFAddressData AddrData)
const;
294 void splitIllegalMUBUFOffset(MachineIRBuilder &
B,
295 Register &SOffset, int64_t &ImmOffset)
const;
297 MUBUFAddressData parseMUBUFAddress(Register Src)
const;
299 bool selectMUBUFAddr64Impl(MachineOperand &Root, Register &VAddr,
300 Register &RSrcReg, Register &SOffset,
303 bool selectMUBUFOffsetImpl(MachineOperand &Root, Register &RSrcReg,
304 Register &SOffset, int64_t &
Offset)
const;
307 selectBUFSOffset(MachineOperand &Root)
const;
310 selectMUBUFAddr64(MachineOperand &Root)
const;
313 selectMUBUFOffset(MachineOperand &Root)
const;
319 std::pair<Register, unsigned> selectVOP3PMadMixModsImpl(MachineOperand &Root,
320 bool &Matched)
const;
324 void renderTruncImm32(MachineInstrBuilder &MIB,
const MachineInstr &
MI,
325 int OpIdx = -1)
const;
327 void renderTruncTImm(MachineInstrBuilder &MIB,
const MachineInstr &
MI,
330 void renderOpSelTImm(MachineInstrBuilder &MIB,
const MachineInstr &
MI,
333 void renderNegateImm(MachineInstrBuilder &MIB,
const MachineInstr &
MI,
336 void renderBitcastImm(MachineInstrBuilder &MIB,
const MachineInstr &
MI,
339 void renderPopcntImm(MachineInstrBuilder &MIB,
const MachineInstr &
MI,
341 void renderExtractCPol(MachineInstrBuilder &MIB,
const MachineInstr &
MI,
343 void renderExtractSWZ(MachineInstrBuilder &MIB,
const MachineInstr &
MI,
345 void renderExtractCpolSetGLC(MachineInstrBuilder &MIB,
const MachineInstr &
MI,
348 void renderFrameIndex(MachineInstrBuilder &MIB,
const MachineInstr &
MI,
351 void renderFPPow2ToExponent(MachineInstrBuilder &MIB,
const MachineInstr &
MI,
354 bool isInlineImmediate(
const APInt &Imm)
const;
355 bool isInlineImmediate(
const APFloat &Imm)
const;
359 bool isUnneededShiftMask(
const MachineInstr &
MI,
unsigned ShAmtBits)
const;
361 const SIInstrInfo &TII;
362 const SIRegisterInfo &TRI;
363 const AMDGPURegisterBankInfo &RBI;
364 const AMDGPUTargetMachine &
TM;
365 const GCNSubtarget &STI;
366 bool EnableLateStructurizeCFG;
367#define GET_GLOBALISEL_PREDICATES_DECL
368#define AMDGPUSubtarget GCNSubtarget
369#include "AMDGPUGenGlobalISel.inc"
370#undef GET_GLOBALISEL_PREDICATES_DECL
371#undef AMDGPUSubtarget
373#define GET_GLOBALISEL_TEMPORARIES_DECL
374#include "AMDGPUGenGlobalISel.inc"
375#undef GET_GLOBALISEL_TEMPORARIES_DECL
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
const char LLVMTargetMachineRef TM
static const char * getName()
bool select(MachineInstr &I) override
Select the (possibly generic) instruction I to only use target-specific opcodes.
void setupMF(MachineFunction &MF, GISelKnownBits *KB, CodeGenCoverage *CoverageInfo, ProfileSummaryInfo *PSI, BlockFrequencyInfo *BFI) override
Setup per-MF executor state.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
BlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate IR basic block frequen...
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
std::optional< SmallVector< std::function< void(MachineInstrBuilder &)>, 4 > > ComplexRendererFns
CodeGenCoverage * CoverageInfo
Representation of each machine instruction.
MachineOperand class - Representation of each machine instruction operand.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Analysis providing profile information.
This class implements the register bank concept.
Wrapper class representing virtual and physical registers.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This is an optimization pass for GlobalISel generic memory operations.