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AMDGPUInstructionSelector.h
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1//===- AMDGPUInstructionSelector --------------------------------*- C++ -*-==//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8/// \file
9/// This file declares the targeting of the InstructionSelector class for
10/// AMDGPU.
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRUCTIONSELECTOR_H
14#define LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRUCTIONSELECTOR_H
15
16#include "SIDefines.h"
17#include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
18#include "llvm/IR/InstrTypes.h"
19
20namespace {
21#define GET_GLOBALISEL_PREDICATE_BITSET
22#define AMDGPUSubtarget GCNSubtarget
23#include "AMDGPUGenGlobalISel.inc"
24#undef GET_GLOBALISEL_PREDICATE_BITSET
25#undef AMDGPUSubtarget
26}
27
28namespace llvm {
29
30namespace AMDGPU {
31struct ImageDimIntrinsicInfo;
32}
33
34class AMDGPURegisterBankInfo;
35class AMDGPUTargetMachine;
36class BlockFrequencyInfo;
37class ProfileSummaryInfo;
38class GCNSubtarget;
39class MachineInstr;
40class MachineIRBuilder;
41class MachineOperand;
42class MachineRegisterInfo;
43class RegisterBank;
44class SIInstrInfo;
45class SIRegisterInfo;
46class TargetRegisterClass;
47
48class AMDGPUInstructionSelector final : public InstructionSelector {
49private:
50 MachineRegisterInfo *MRI;
51 const GCNSubtarget *Subtarget;
52
53public:
54 AMDGPUInstructionSelector(const GCNSubtarget &STI,
55 const AMDGPURegisterBankInfo &RBI,
56 const AMDGPUTargetMachine &TM);
57
58 bool select(MachineInstr &I) override;
59 static const char *getName();
60
61 void setupMF(MachineFunction &MF, GISelKnownBits *KB,
62 CodeGenCoverage *CoverageInfo, ProfileSummaryInfo *PSI,
63 BlockFrequencyInfo *BFI) override;
64
65private:
66 struct GEPInfo {
67 SmallVector<unsigned, 2> SgprParts;
68 SmallVector<unsigned, 2> VgprParts;
69 int64_t Imm = 0;
70 };
71
72 bool isSGPR(Register Reg) const;
73
74 bool isInstrUniform(const MachineInstr &MI) const;
75 bool isVCC(Register Reg, const MachineRegisterInfo &MRI) const;
76
77 const RegisterBank *getArtifactRegBank(
78 Register Reg, const MachineRegisterInfo &MRI,
79 const TargetRegisterInfo &TRI) const;
80
81 /// tblgen-erated 'select' implementation.
82 bool selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const;
83
84 MachineOperand getSubOperand64(MachineOperand &MO,
85 const TargetRegisterClass &SubRC,
86 unsigned SubIdx) const;
87
88 bool constrainCopyLikeIntrin(MachineInstr &MI, unsigned NewOpc) const;
89 bool selectCOPY(MachineInstr &I) const;
90 bool selectPHI(MachineInstr &I) const;
91 bool selectG_TRUNC(MachineInstr &I) const;
92 bool selectG_SZA_EXT(MachineInstr &I) const;
93 bool selectG_FPEXT(MachineInstr &I) const;
94 bool selectG_FNEG(MachineInstr &I) const;
95 bool selectG_FABS(MachineInstr &I) const;
96 bool selectG_AND_OR_XOR(MachineInstr &I) const;
97 bool selectG_ADD_SUB(MachineInstr &I) const;
98 bool selectG_UADDO_USUBO_UADDE_USUBE(MachineInstr &I) const;
99 bool selectG_AMDGPU_MAD_64_32(MachineInstr &I) const;
100 bool selectG_EXTRACT(MachineInstr &I) const;
101 bool selectG_FMA_FMAD(MachineInstr &I) const;
102 bool selectG_MERGE_VALUES(MachineInstr &I) const;
103 bool selectG_UNMERGE_VALUES(MachineInstr &I) const;
104 bool selectG_BUILD_VECTOR(MachineInstr &I) const;
105 bool selectG_IMPLICIT_DEF(MachineInstr &I) const;
106 bool selectG_INSERT(MachineInstr &I) const;
107 bool selectG_SBFX_UBFX(MachineInstr &I) const;
108
109 bool selectInterpP1F16(MachineInstr &MI) const;
110 bool selectWritelane(MachineInstr &MI) const;
111 bool selectDivScale(MachineInstr &MI) const;
112 bool selectIntrinsicCmp(MachineInstr &MI) const;
113 bool selectBallot(MachineInstr &I) const;
114 bool selectRelocConstant(MachineInstr &I) const;
115 bool selectGroupStaticSize(MachineInstr &I) const;
116 bool selectReturnAddress(MachineInstr &I) const;
117 bool selectG_INTRINSIC(MachineInstr &I) const;
118
119 bool selectEndCfIntrinsic(MachineInstr &MI) const;
120 bool selectDSOrderedIntrinsic(MachineInstr &MI, Intrinsic::ID IID) const;
121 bool selectDSGWSIntrinsic(MachineInstr &MI, Intrinsic::ID IID) const;
122 bool selectDSAppendConsume(MachineInstr &MI, bool IsAppend) const;
123 bool selectSBarrier(MachineInstr &MI) const;
124 bool selectDSBvhStackIntrinsic(MachineInstr &MI) const;
125
126 bool selectImageIntrinsic(MachineInstr &MI,
127 const AMDGPU::ImageDimIntrinsicInfo *Intr) const;
128 bool selectG_INTRINSIC_W_SIDE_EFFECTS(MachineInstr &I) const;
129 int getS_CMPOpcode(CmpInst::Predicate P, unsigned Size) const;
130 bool selectG_ICMP_or_FCMP(MachineInstr &I) const;
131 bool hasVgprParts(ArrayRef<GEPInfo> AddrInfo) const;
132 void getAddrModeInfo(const MachineInstr &Load, const MachineRegisterInfo &MRI,
133 SmallVectorImpl<GEPInfo> &AddrInfo) const;
134
135 void initM0(MachineInstr &I) const;
136 bool selectG_LOAD_STORE_ATOMICRMW(MachineInstr &I) const;
137 bool selectG_SELECT(MachineInstr &I) const;
138 bool selectG_BRCOND(MachineInstr &I) const;
139 bool selectG_GLOBAL_VALUE(MachineInstr &I) const;
140 bool selectG_PTRMASK(MachineInstr &I) const;
141 bool selectG_EXTRACT_VECTOR_ELT(MachineInstr &I) const;
142 bool selectG_INSERT_VECTOR_ELT(MachineInstr &I) const;
143 bool selectBufferLoadLds(MachineInstr &MI) const;
144 bool selectGlobalLoadLds(MachineInstr &MI) const;
145 bool selectBVHIntrinsic(MachineInstr &I) const;
146 bool selectSMFMACIntrin(MachineInstr &I) const;
147 bool selectWaveAddress(MachineInstr &I) const;
148 bool selectStackRestore(MachineInstr &MI) const;
149 bool selectNamedBarrierInst(MachineInstr &I, Intrinsic::ID IID) const;
150 bool selectSBarrierSignalIsfirst(MachineInstr &I, Intrinsic::ID IID) const;
151 bool selectSBarrierLeave(MachineInstr &I) const;
152
153 std::pair<Register, unsigned> selectVOP3ModsImpl(Register Src,
154 bool IsCanonicalizing = true,
155 bool AllowAbs = true,
156 bool OpSel = false) const;
157
158 Register copyToVGPRIfSrcFolded(Register Src, unsigned Mods,
159 MachineOperand Root, MachineInstr *InsertPt,
160 bool ForceVGPR = false) const;
161
162 InstructionSelector::ComplexRendererFns
163 selectVCSRC(MachineOperand &Root) const;
164
165 InstructionSelector::ComplexRendererFns
166 selectVSRC0(MachineOperand &Root) const;
167
168 InstructionSelector::ComplexRendererFns
169 selectVOP3Mods0(MachineOperand &Root) const;
170 InstructionSelector::ComplexRendererFns
171 selectVOP3BMods0(MachineOperand &Root) const;
172 InstructionSelector::ComplexRendererFns
173 selectVOP3OMods(MachineOperand &Root) const;
174 InstructionSelector::ComplexRendererFns
175 selectVOP3Mods(MachineOperand &Root) const;
176 InstructionSelector::ComplexRendererFns
177 selectVOP3ModsNonCanonicalizing(MachineOperand &Root) const;
178 InstructionSelector::ComplexRendererFns
179 selectVOP3BMods(MachineOperand &Root) const;
180
181 ComplexRendererFns selectVOP3NoMods(MachineOperand &Root) const;
182
183 std::pair<Register, unsigned>
184 selectVOP3PModsImpl(Register Src, const MachineRegisterInfo &MRI,
185 bool IsDOT = false) const;
186
187 InstructionSelector::ComplexRendererFns
188 selectVOP3PMods(MachineOperand &Root) const;
189
190 InstructionSelector::ComplexRendererFns
191 selectVOP3PModsDOT(MachineOperand &Root) const;
192
193 InstructionSelector::ComplexRendererFns
194 selectVOP3PModsNeg(MachineOperand &Root) const;
195
196 InstructionSelector::ComplexRendererFns
197 selectWMMAOpSelVOP3PMods(MachineOperand &Root) const;
198
199 InstructionSelector::ComplexRendererFns
200 selectWMMAModsF32NegAbs(MachineOperand &Root) const;
201 InstructionSelector::ComplexRendererFns
202 selectWMMAModsF16Neg(MachineOperand &Root) const;
203 InstructionSelector::ComplexRendererFns
204 selectWMMAModsF16NegAbs(MachineOperand &Root) const;
205 InstructionSelector::ComplexRendererFns
206 selectWMMAVISrc(MachineOperand &Root) const;
207 InstructionSelector::ComplexRendererFns
208 selectSWMMACIndex8(MachineOperand &Root) const;
209 InstructionSelector::ComplexRendererFns
210 selectSWMMACIndex16(MachineOperand &Root) const;
211
212 InstructionSelector::ComplexRendererFns
213 selectVOP3OpSelMods(MachineOperand &Root) const;
214
215 InstructionSelector::ComplexRendererFns
216 selectVINTERPMods(MachineOperand &Root) const;
217 InstructionSelector::ComplexRendererFns
218 selectVINTERPModsHi(MachineOperand &Root) const;
219
220 bool selectSmrdOffset(MachineOperand &Root, Register &Base, Register *SOffset,
221 int64_t *Offset) const;
222 InstructionSelector::ComplexRendererFns
223 selectSmrdImm(MachineOperand &Root) const;
224 InstructionSelector::ComplexRendererFns
225 selectSmrdImm32(MachineOperand &Root) const;
226 InstructionSelector::ComplexRendererFns
227 selectSmrdSgpr(MachineOperand &Root) const;
228 InstructionSelector::ComplexRendererFns
229 selectSmrdSgprImm(MachineOperand &Root) const;
230
231 std::pair<Register, int> selectFlatOffsetImpl(MachineOperand &Root,
232 uint64_t FlatVariant) const;
233
234 InstructionSelector::ComplexRendererFns
235 selectFlatOffset(MachineOperand &Root) const;
236 InstructionSelector::ComplexRendererFns
237 selectGlobalOffset(MachineOperand &Root) const;
238 InstructionSelector::ComplexRendererFns
239 selectScratchOffset(MachineOperand &Root) const;
240
241 InstructionSelector::ComplexRendererFns
242 selectGlobalSAddr(MachineOperand &Root) const;
243
244 InstructionSelector::ComplexRendererFns
245 selectScratchSAddr(MachineOperand &Root) const;
246 bool checkFlatScratchSVSSwizzleBug(Register VAddr, Register SAddr,
247 uint64_t ImmOffset) const;
248 InstructionSelector::ComplexRendererFns
249 selectScratchSVAddr(MachineOperand &Root) const;
250
251 InstructionSelector::ComplexRendererFns
252 selectMUBUFScratchOffen(MachineOperand &Root) const;
253 InstructionSelector::ComplexRendererFns
254 selectMUBUFScratchOffset(MachineOperand &Root) const;
255
256 bool isDSOffsetLegal(Register Base, int64_t Offset) const;
257 bool isDSOffset2Legal(Register Base, int64_t Offset0, int64_t Offset1,
258 unsigned Size) const;
259 bool isFlatScratchBaseLegal(Register Addr) const;
260 bool isFlatScratchBaseLegalSV(Register Addr) const;
261 bool isFlatScratchBaseLegalSVImm(Register Addr) const;
262
263 std::pair<Register, unsigned>
264 selectDS1Addr1OffsetImpl(MachineOperand &Root) const;
265 InstructionSelector::ComplexRendererFns
266 selectDS1Addr1Offset(MachineOperand &Root) const;
267
268 InstructionSelector::ComplexRendererFns
269 selectDS64Bit4ByteAligned(MachineOperand &Root) const;
270
271 InstructionSelector::ComplexRendererFns
272 selectDS128Bit8ByteAligned(MachineOperand &Root) const;
273
274 std::pair<Register, unsigned> selectDSReadWrite2Impl(MachineOperand &Root,
275 unsigned size) const;
276 InstructionSelector::ComplexRendererFns
277 selectDSReadWrite2(MachineOperand &Root, unsigned size) const;
278
279 std::pair<Register, int64_t>
280 getPtrBaseWithConstantOffset(Register Root,
281 const MachineRegisterInfo &MRI) const;
282
283 // Parse out a chain of up to two g_ptr_add instructions.
284 // g_ptr_add (n0, _)
285 // g_ptr_add (n0, (n1 = g_ptr_add n2, n3))
286 struct MUBUFAddressData {
287 Register N0, N2, N3;
288 int64_t Offset = 0;
289 };
290
291 bool shouldUseAddr64(MUBUFAddressData AddrData) const;
292
293 void splitIllegalMUBUFOffset(MachineIRBuilder &B,
294 Register &SOffset, int64_t &ImmOffset) const;
295
296 MUBUFAddressData parseMUBUFAddress(Register Src) const;
297
298 bool selectMUBUFAddr64Impl(MachineOperand &Root, Register &VAddr,
299 Register &RSrcReg, Register &SOffset,
300 int64_t &Offset) const;
301
302 bool selectMUBUFOffsetImpl(MachineOperand &Root, Register &RSrcReg,
303 Register &SOffset, int64_t &Offset) const;
304
305 InstructionSelector::ComplexRendererFns
306 selectBUFSOffset(MachineOperand &Root) const;
307
308 InstructionSelector::ComplexRendererFns
309 selectMUBUFAddr64(MachineOperand &Root) const;
310
311 InstructionSelector::ComplexRendererFns
312 selectMUBUFOffset(MachineOperand &Root) const;
313
314 ComplexRendererFns selectSMRDBufferImm(MachineOperand &Root) const;
315 ComplexRendererFns selectSMRDBufferImm32(MachineOperand &Root) const;
316 ComplexRendererFns selectSMRDBufferSgprImm(MachineOperand &Root) const;
317
318 std::pair<Register, unsigned> selectVOP3PMadMixModsImpl(MachineOperand &Root,
319 bool &Matched) const;
320 ComplexRendererFns selectVOP3PMadMixModsExt(MachineOperand &Root) const;
321 ComplexRendererFns selectVOP3PMadMixMods(MachineOperand &Root) const;
322
323 void renderTruncImm32(MachineInstrBuilder &MIB, const MachineInstr &MI,
324 int OpIdx = -1) const;
325
326 void renderTruncTImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
327 int OpIdx) const;
328
329 void renderOpSelTImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
330 int OpIdx) const;
331
332 void renderNegateImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
333 int OpIdx) const;
334
335 void renderBitcastFPImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
336 int OpIdx) const;
337
338 void renderBitcastFPImm32(MachineInstrBuilder &MIB, const MachineInstr &MI,
339 int OpIdx) const {
340 renderBitcastFPImm(MIB, MI, OpIdx);
341 }
342 void renderBitcastFPImm64(MachineInstrBuilder &MIB, const MachineInstr &MI,
343 int OpIdx) const {
344 renderBitcastFPImm(MIB, MI, OpIdx);
345 }
346
347 void renderPopcntImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
348 int OpIdx) const;
349 void renderExtractCPol(MachineInstrBuilder &MIB, const MachineInstr &MI,
350 int OpIdx) const;
351 void renderExtractSWZ(MachineInstrBuilder &MIB, const MachineInstr &MI,
352 int OpIdx) const;
353 void renderExtractCpolSetGLC(MachineInstrBuilder &MIB, const MachineInstr &MI,
354 int OpIdx) const;
355
356 void renderFrameIndex(MachineInstrBuilder &MIB, const MachineInstr &MI,
357 int OpIdx) const;
358
359 void renderFPPow2ToExponent(MachineInstrBuilder &MIB, const MachineInstr &MI,
360 int OpIdx) const;
361
362 bool isInlineImmediate(const APInt &Imm) const;
363 bool isInlineImmediate(const APFloat &Imm) const;
364
365 // Returns true if TargetOpcode::G_AND MachineInstr `MI`'s masking of the
366 // shift amount operand's `ShAmtBits` bits is unneeded.
367 bool isUnneededShiftMask(const MachineInstr &MI, unsigned ShAmtBits) const;
368
369 const SIInstrInfo &TII;
370 const SIRegisterInfo &TRI;
371 const AMDGPURegisterBankInfo &RBI;
372 const AMDGPUTargetMachine &TM;
373 const GCNSubtarget &STI;
374 bool EnableLateStructurizeCFG;
375#define GET_GLOBALISEL_PREDICATES_DECL
376#define AMDGPUSubtarget GCNSubtarget
377#include "AMDGPUGenGlobalISel.inc"
378#undef GET_GLOBALISEL_PREDICATES_DECL
379#undef AMDGPUSubtarget
380
381#define GET_GLOBALISEL_TEMPORARIES_DECL
382#include "AMDGPUGenGlobalISel.inc"
383#undef GET_GLOBALISEL_TEMPORARIES_DECL
384};
385
386} // End llvm namespace.
387#endif
Intr
unsigned Intr
Definition: AMDGPUBaseInfo.cpp:2906
B
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
Addr
uint64_t Addr
Definition: ELFObjHandler.cpp:79
Size
uint64_t Size
Definition: ELFObjHandler.cpp:81
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:113
I
#define I(x, y, z)
Definition: MD5.cpp:58
Reg
unsigned Reg
Definition: MachineSink.cpp:1927
P
#define P(N)
llvm::AMDGPUInstructionSelector::getName
static const char * getName()
llvm::AMDGPUInstructionSelector::select
bool select(MachineInstr &I) override
Select the (possibly generic) instruction I to only use target-specific opcodes.
Definition: AMDGPUInstructionSelector.cpp:3458
llvm::AMDGPUInstructionSelector::setupMF
void setupMF(MachineFunction &MF, GISelKnownBits *KB, CodeGenCoverage *CoverageInfo, ProfileSummaryInfo *PSI, BlockFrequencyInfo *BFI) override
Setup per-MF executor state.
Definition: AMDGPUInstructionSelector.cpp:60
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
llvm::BlockFrequencyInfo
BlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate IR basic block frequen...
Definition: BlockFrequencyInfo.h:37
llvm::CmpInst::Predicate
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:757
llvm::GIMatchTableExecutor::ComplexRendererFns
std::optional< SmallVector< std::function< void(MachineInstrBuilder &)>, 4 > > ComplexRendererFns
Definition: GIMatchTableExecutor.h:615
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:69
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:48
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:51
llvm::ProfileSummaryInfo
Analysis providing profile information.
Definition: ProfileSummaryInfo.h:41
llvm::RegisterBank
This class implements the register bank concept.
Definition: RegisterBank.h:28
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:586
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1209
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:238
uint64_t
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::Offset
@ Offset
Definition: DWP.cpp:480
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