LLVM 24.0.0git
AMDGPUInstructionSelector.h
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1//===- AMDGPUInstructionSelector --------------------------------*- C++ -*-==//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8/// \file
9/// This file declares the targeting of the InstructionSelector class for
10/// AMDGPU.
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRUCTIONSELECTOR_H
14#define LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRUCTIONSELECTOR_H
15
16#include "SIDefines.h"
17#include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
18#include "llvm/IR/InstrTypes.h"
19
20namespace {
21#define GET_GLOBALISEL_PREDICATE_BITSET
22#define AMDGPUSubtarget GCNSubtarget
23#include "AMDGPUGenGlobalISel.inc"
24#undef GET_GLOBALISEL_PREDICATE_BITSET
25#undef AMDGPUSubtarget
26}
27
28namespace llvm {
29
30namespace AMDGPU {
31struct ImageDimIntrinsicInfo;
32}
33
34class AMDGPURegisterBankInfo;
35class AMDGPUTargetMachine;
36class BlockFrequencyInfo;
37class ProfileSummaryInfo;
38class GCNSubtarget;
39class MachineInstr;
40class MachineIRBuilder;
41class MachineOperand;
42class MachineRegisterInfo;
43class RegisterBank;
44class SIInstrInfo;
45class SIRegisterInfo;
46class MCRegisterClass;
47using TargetRegisterClass = MCRegisterClass;
48
49class AMDGPUInstructionSelector final : public InstructionSelector {
50private:
51 MachineRegisterInfo *MRI;
52 const GCNSubtarget *Subtarget;
53
54public:
55 AMDGPUInstructionSelector(const GCNSubtarget &STI,
56 const AMDGPURegisterBankInfo &RBI);
57
58 bool select(MachineInstr &I) override;
59 static const char *getName();
60
61 void setupMF(MachineFunction &MF, GISelValueTracking *VT,
62 CodeGenCoverage *CoverageInfo, ProfileSummaryInfo *PSI,
63 BlockFrequencyInfo *BFI) override;
64
65private:
66 struct GEPInfo {
67 SmallVector<unsigned, 2> SgprParts;
68 SmallVector<unsigned, 2> VgprParts;
69 int64_t Imm = 0;
70 };
71
72 bool isSGPR(Register Reg) const;
73
74 bool isInstrUniform(const MachineInstr &MI) const;
75 bool isVCC(Register Reg, const MachineRegisterInfo &MRI) const;
76
77 const RegisterBank *getArtifactRegBank(
78 Register Reg, const MachineRegisterInfo &MRI,
79 const TargetRegisterInfo &TRI) const;
80
81 /// tblgen-erated 'select' implementation.
82 bool selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const;
83
84 MachineOperand getSubOperand64(MachineOperand &MO,
85 const TargetRegisterClass &SubRC,
86 unsigned SubIdx) const;
87
88 bool constrainCopyLikeIntrin(MachineInstr &MI, unsigned NewOpc) const;
89 bool selectCOPY(MachineInstr &I) const;
90 bool selectCOPY_SCC_VCC(MachineInstr &I) const;
91 bool selectCOPY_VCC_SCC(MachineInstr &I) const;
92 bool selectReadAnyLane(MachineInstr &I) const;
93 bool selectPHI(MachineInstr &I) const;
94 bool selectG_TRUNC(MachineInstr &I) const;
95 bool selectG_SZA_EXT(MachineInstr &I) const;
96 bool selectG_FPEXT(MachineInstr &I) const;
97 bool selectG_FNEG(MachineInstr &I) const;
98 bool selectG_FABS(MachineInstr &I) const;
99 bool selectG_AND_OR_XOR(MachineInstr &I) const;
100 bool selectG_ADD_SUB(MachineInstr &I) const;
101 bool selectG_UADDO_USUBO_UADDE_USUBE(MachineInstr &I) const;
102 bool selectG_AMDGPU_MAD_64_32(MachineInstr &I) const;
103 bool selectG_EXTRACT(MachineInstr &I) const;
104 bool selectS16MergeToS32(MachineInstr &MI) const;
105 bool selectS16MergeToWide(MachineInstr &MI) const;
106 bool selectG_MERGE_VALUES(MachineInstr &I) const;
107 bool selectG_UNMERGE_VALUES(MachineInstr &I) const;
108 bool selectG_BUILD_VECTOR(MachineInstr &I) const;
109 bool selectG_IMPLICIT_DEF(MachineInstr &I) const;
110 bool selectG_INSERT(MachineInstr &I) const;
111 bool selectG_SBFX_UBFX(MachineInstr &I) const;
112
113 bool selectInterpP1F16(MachineInstr &MI) const;
114 bool selectWritelane(MachineInstr &MI) const;
115 bool selectDivScale(MachineInstr &MI) const;
116 bool selectBallot(MachineInstr &I) const;
117 bool selectRelocConstant(MachineInstr &I) const;
118 bool selectGroupStaticSize(MachineInstr &I) const;
119 bool selectReturnAddress(MachineInstr &I) const;
120 bool selectG_INTRINSIC(MachineInstr &I) const;
121
122 bool selectEndCfIntrinsic(MachineInstr &MI) const;
123 bool selectDSOrderedIntrinsic(MachineInstr &MI, Intrinsic::ID IID) const;
124 bool selectDSGWSIntrinsic(MachineInstr &MI, Intrinsic::ID IID) const;
125 bool selectDSAppendConsume(MachineInstr &MI, bool IsAppend) const;
126 bool selectInitWholeWave(MachineInstr &MI) const;
127 bool selectDSBvhStackIntrinsic(MachineInstr &MI) const;
128
129 bool selectImageIntrinsic(MachineInstr &MI,
130 const AMDGPU::ImageDimIntrinsicInfo *Intr) const;
131 bool selectG_INTRINSIC_W_SIDE_EFFECTS(MachineInstr &I) const;
132 int getS_CMPOpcode(CmpInst::Predicate P, unsigned Size) const;
133 bool selectG_ICMP_or_FCMP(MachineInstr &I) const;
134 bool hasVgprParts(ArrayRef<GEPInfo> AddrInfo) const;
135 void getAddrModeInfo(const MachineInstr &Load, const MachineRegisterInfo &MRI,
136 SmallVectorImpl<GEPInfo> &AddrInfo) const;
137
138 void initM0(MachineInstr &I) const;
139 bool selectG_LOAD_STORE_ATOMICRMW(MachineInstr &I) const;
140 bool selectG_SELECT(MachineInstr &I) const;
141 bool selectG_BRCOND(MachineInstr &I) const;
142 bool selectG_GLOBAL_VALUE(MachineInstr &I) const;
143 bool selectG_PTRMASK(MachineInstr &I) const;
144 bool selectG_EXTRACT_VECTOR_ELT(MachineInstr &I) const;
145 bool selectG_INSERT_VECTOR_ELT(MachineInstr &I) const;
146 bool selectBufferLoadLds(MachineInstr &MI) const;
147 bool selectGlobalLoadLds(MachineInstr &MI) const;
148 bool selectTensorLoadStore(MachineInstr &MI, Intrinsic::ID IID) const;
149 bool selectBVHIntersectRayIntrinsic(MachineInstr &I) const;
150 bool selectSMFMACIntrin(MachineInstr &I) const;
151 bool selectPermlaneSwapIntrin(MachineInstr &I, Intrinsic::ID IntrID) const;
152 bool selectWaveAddress(MachineInstr &I) const;
153 bool selectBITOP3(MachineInstr &I) const;
154 bool selectWriteRegister(MachineInstr &MI) const;
155 bool selectStackRestore(MachineInstr &MI) const;
156 bool selectNamedBarrierInit(MachineInstr &I, Intrinsic::ID IID) const;
157 bool selectNamedBarrierInst(MachineInstr &I, Intrinsic::ID IID) const;
158 bool selectSBarrierSignalIsfirst(MachineInstr &I, Intrinsic::ID IID) const;
159 bool selectSGetBarrierState(MachineInstr &I, Intrinsic::ID IID) const;
160 bool selectWaveShuffleIntrin(MachineInstr &I) const;
161
162 std::pair<Register, unsigned> selectVOP3ModsImpl(Register Src,
163 bool IsCanonicalizing = true,
164 bool AllowAbs = true,
165 bool OpSel = false) const;
166 std::pair<Register, unsigned> selectVOP3PModsF32Impl(Register Src) const;
167
168 Register copyToVGPRIfSrcFolded(Register Src, unsigned Mods,
169 MachineOperand Root, MachineInstr *InsertPt,
170 bool ForceVGPR = false) const;
171
172 Register widenSrcIfVGPR16(Register Src, MachineInstr *InsertPt) const;
173
174 InstructionSelector::ComplexRendererFns
175 selectVCSRC(MachineOperand &Root) const;
176
177 InstructionSelector::ComplexRendererFns
178 selectVSRC0(MachineOperand &Root) const;
179
180 InstructionSelector::ComplexRendererFns
181 selectVOP3Mods0(MachineOperand &Root) const;
182 InstructionSelector::ComplexRendererFns
183 selectVOP3BMods0(MachineOperand &Root) const;
184 InstructionSelector::ComplexRendererFns
185 selectVOP3OMods(MachineOperand &Root) const;
186 InstructionSelector::ComplexRendererFns
187 selectVOP3Mods(MachineOperand &Root) const;
188 InstructionSelector::ComplexRendererFns
189 selectVOP3ModsNonCanonicalizing(MachineOperand &Root) const;
190 InstructionSelector::ComplexRendererFns
191 selectVOP3BMods(MachineOperand &Root) const;
192
193 ComplexRendererFns selectVOP3NoMods(MachineOperand &Root) const;
194
195 std::pair<Register, unsigned>
196 selectVOP3PModsImpl(Register RootReg, const MachineRegisterInfo &MRI,
197 bool IsDOT = false) const;
198 InstructionSelector::ComplexRendererFns
199 selectVOP3PRetHelper(MachineOperand &Root, bool IsDOT = false) const;
200
201 InstructionSelector::ComplexRendererFns
202 selectVOP3PMods(MachineOperand &Root) const;
203
204 InstructionSelector::ComplexRendererFns
205 selectVOP3PModsDOT(MachineOperand &Root) const;
206 InstructionSelector::ComplexRendererFns
207 selectVOP3PNoModsDOT(MachineOperand &Root) const;
208 InstructionSelector::ComplexRendererFns
209 selectVOP3PModsF32(MachineOperand &Root) const;
210 InstructionSelector::ComplexRendererFns
211 selectVOP3PNoModsF32(MachineOperand &Root) const;
212
213 InstructionSelector::ComplexRendererFns
214 selectWMMAOpSelVOP3PMods(MachineOperand &Root) const;
215
216 InstructionSelector::ComplexRendererFns
217 selectWMMAModsF32NegAbs(MachineOperand &Root) const;
218 InstructionSelector::ComplexRendererFns
219 selectWMMAModsF16Neg(MachineOperand &Root) const;
220 InstructionSelector::ComplexRendererFns
221 selectWMMAModsF16NegAbs(MachineOperand &Root) const;
222 InstructionSelector::ComplexRendererFns
223 selectWMMAVISrc(MachineOperand &Root) const;
224 InstructionSelector::ComplexRendererFns
225 selectSWMMACIndex8(MachineOperand &Root) const;
226 InstructionSelector::ComplexRendererFns
227 selectSWMMACIndex16(MachineOperand &Root) const;
228 InstructionSelector::ComplexRendererFns
229 selectSWMMACIndex32(MachineOperand &Root) const;
230
231 InstructionSelector::ComplexRendererFns
232 selectVOP3OpSelMods(MachineOperand &Root) const;
233
234 InstructionSelector::ComplexRendererFns
235 selectVINTERPMods(MachineOperand &Root) const;
236 InstructionSelector::ComplexRendererFns
237 selectVINTERPModsHi(MachineOperand &Root) const;
238
239 bool selectScaleOffset(MachineOperand &Root, Register &Offset,
240 bool IsSigned) const;
241 bool selectSmrdOffset(MachineOperand &Root, Register &Base, Register *SOffset,
242 int64_t *Offset, bool *ScaleOffset) const;
243 InstructionSelector::ComplexRendererFns
244 selectSmrdImm(MachineOperand &Root) const;
245 InstructionSelector::ComplexRendererFns
246 selectSmrdImm32(MachineOperand &Root) const;
247 InstructionSelector::ComplexRendererFns
248 selectSmrdSgpr(MachineOperand &Root) const;
249 InstructionSelector::ComplexRendererFns
250 selectSmrdSgprImm(MachineOperand &Root) const;
251
252 std::pair<Register, int>
253 selectFlatOffsetImpl(MachineOperand &Root,
254 AMDGPU::FlatAddrSpace FlatVariant) const;
255
256 InstructionSelector::ComplexRendererFns
257 selectFlatOffset(MachineOperand &Root) const;
258 InstructionSelector::ComplexRendererFns
259 selectGlobalOffset(MachineOperand &Root) const;
260 InstructionSelector::ComplexRendererFns
261 selectScratchOffset(MachineOperand &Root) const;
262
263 InstructionSelector::ComplexRendererFns
264 selectGlobalSAddr(MachineOperand &Root, unsigned CPolBits,
265 bool NeedIOffset = true) const;
266 InstructionSelector::ComplexRendererFns
267 selectGlobalSAddr(MachineOperand &Root) const;
268 InstructionSelector::ComplexRendererFns
269 selectGlobalSAddrCPol(MachineOperand &Root) const;
270 InstructionSelector::ComplexRendererFns
271 selectGlobalSAddrCPolM0(MachineOperand &Root) const;
272 InstructionSelector::ComplexRendererFns
273 selectGlobalSAddrGLC(MachineOperand &Root) const;
274 InstructionSelector::ComplexRendererFns
275 selectGlobalSAddrNoIOffset(MachineOperand &Root) const;
276 InstructionSelector::ComplexRendererFns
277 selectGlobalSAddrNoIOffsetM0(MachineOperand &Root) const;
278
279 InstructionSelector::ComplexRendererFns
280 selectScratchSAddr(MachineOperand &Root) const;
281 bool checkFlatScratchSVSSwizzleBug(Register VAddr, Register SAddr,
282 uint64_t ImmOffset) const;
283 InstructionSelector::ComplexRendererFns
284 selectScratchSVAddr(MachineOperand &Root) const;
285
286 InstructionSelector::ComplexRendererFns
287 selectMUBUFScratchOffen(MachineOperand &Root) const;
288 InstructionSelector::ComplexRendererFns
289 selectMUBUFScratchOffset(MachineOperand &Root) const;
290
291 bool isDSOffsetLegal(Register Base, int64_t Offset) const;
292 bool isDSOffset2Legal(Register Base, int64_t Offset0, int64_t Offset1,
293 unsigned Size) const;
294 bool isFlatScratchBaseLegal(Register Addr) const;
295 bool isFlatScratchBaseLegalSV(Register Addr) const;
296 bool isFlatScratchBaseLegalSVImm(Register Addr) const;
297
298 std::pair<Register, unsigned>
299 selectDS1Addr1OffsetImpl(MachineOperand &Root) const;
300 InstructionSelector::ComplexRendererFns
301 selectDS1Addr1Offset(MachineOperand &Root) const;
302
303 InstructionSelector::ComplexRendererFns
304 selectDS64Bit4ByteAligned(MachineOperand &Root) const;
305
306 InstructionSelector::ComplexRendererFns
307 selectDS128Bit8ByteAligned(MachineOperand &Root) const;
308
309 std::pair<Register, unsigned> selectDSReadWrite2Impl(MachineOperand &Root,
310 unsigned size) const;
311 InstructionSelector::ComplexRendererFns
312 selectDSReadWrite2(MachineOperand &Root, unsigned size) const;
313
314 std::tuple<Register, int64_t, bool>
315 getPtrBaseWithConstantOffset(Register Root,
316 const MachineRegisterInfo &MRI) const;
317
318 // Parse out a chain of up to two g_ptr_add instructions.
319 // g_ptr_add (n0, _)
320 // g_ptr_add (n0, (n1 = g_ptr_add n2, n3))
321 struct MUBUFAddressData {
322 Register N0, N2, N3;
323 int64_t Offset = 0;
324 };
325
326 bool shouldUseAddr64(MUBUFAddressData AddrData) const;
327
328 void splitIllegalMUBUFOffset(MachineIRBuilder &B,
329 Register &SOffset, int64_t &ImmOffset) const;
330
331 MUBUFAddressData parseMUBUFAddress(Register Src) const;
332
333 bool selectMUBUFAddr64Impl(MachineOperand &Root, Register &VAddr,
334 Register &RSrcReg, Register &SOffset,
335 int64_t &Offset) const;
336
337 bool selectMUBUFOffsetImpl(MachineOperand &Root, Register &RSrcReg,
338 Register &SOffset, int64_t &Offset) const;
339
340 InstructionSelector::ComplexRendererFns
341 selectBUFSOffset(MachineOperand &Root) const;
342
343 InstructionSelector::ComplexRendererFns
344 selectMUBUFAddr64(MachineOperand &Root) const;
345
346 InstructionSelector::ComplexRendererFns
347 selectMUBUFOffset(MachineOperand &Root) const;
348
349 ComplexRendererFns selectSMRDBufferImm(MachineOperand &Root) const;
350 ComplexRendererFns selectSMRDBufferImm32(MachineOperand &Root) const;
351 ComplexRendererFns selectSMRDBufferSgprImm(MachineOperand &Root) const;
352
353 std::pair<Register, unsigned> selectVOP3PMadMixModsImpl(MachineOperand &Root,
354 bool &Matched) const;
355 ComplexRendererFns selectVOP3PMadMixModsExt(MachineOperand &Root) const;
356 ComplexRendererFns selectVOP3PMadMixMods(MachineOperand &Root) const;
357 ComplexRendererFns selectVOP3PMadMixModsExtNeg(MachineOperand &Root) const;
358 ComplexRendererFns selectVOP3PMadMixModsNeg(MachineOperand &Root) const;
359
360 void renderTruncTImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
361 int OpIdx) const;
362 void renderZextBoolTImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
363 int OpIdx) const;
364
365 void renderOpSelTImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
366 int OpIdx) const;
367
368 void renderSrcAndDstSelToOpSelXForm_0_0(MachineInstrBuilder &MIB,
369 const MachineInstr &MI,
370 int OpIdx) const;
371
372 void renderSrcAndDstSelToOpSelXForm_0_1(MachineInstrBuilder &MIB,
373 const MachineInstr &MI,
374 int OpIdx) const;
375
376 void renderSrcAndDstSelToOpSelXForm_1_0(MachineInstrBuilder &MIB,
377 const MachineInstr &MI,
378 int OpIdx) const;
379
380 void renderSrcAndDstSelToOpSelXForm_1_1(MachineInstrBuilder &MIB,
381 const MachineInstr &MI,
382 int OpIdx) const;
383
384 void renderDstSelToOpSelXForm(MachineInstrBuilder &MIB,
385 const MachineInstr &MI, int OpIdx) const;
386
387 void renderSrcSelToOpSelXForm(MachineInstrBuilder &MIB,
388 const MachineInstr &MI, int OpIdx) const;
389
390 void renderSrcAndDstSelToOpSelXForm_2_0(MachineInstrBuilder &MIB,
391 const MachineInstr &MI,
392 int OpIdx) const;
393
394 void renderDstSelToOpSel3XFormXForm(MachineInstrBuilder &MIB,
395 const MachineInstr &MI, int OpIdx) const;
396
397 void renderNegateImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
398 int OpIdx) const;
399
400 void renderBitcastFPImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
401 int OpIdx) const;
402
403 void renderBitcastFPImm32(MachineInstrBuilder &MIB, const MachineInstr &MI,
404 int OpIdx) const {
405 renderBitcastFPImm(MIB, MI, OpIdx);
406 }
407 void renderBitcastFPImm64(MachineInstrBuilder &MIB, const MachineInstr &MI,
408 int OpIdx) const {
409 renderBitcastFPImm(MIB, MI, OpIdx);
410 }
411
412 void renderCountTrailingOnesImm(MachineInstrBuilder &MIB,
413 const MachineInstr &MI, int OpIdx) const;
414 void renderExtractCPol(MachineInstrBuilder &MIB, const MachineInstr &MI,
415 int OpIdx) const;
416 void renderExtractSWZ(MachineInstrBuilder &MIB, const MachineInstr &MI,
417 int OpIdx) const;
418 void renderExtractCpolSetGLC(MachineInstrBuilder &MIB, const MachineInstr &MI,
419 int OpIdx) const;
420
421 void renderFPPow2ToExponent(MachineInstrBuilder &MIB, const MachineInstr &MI,
422 int OpIdx) const;
423
424 void renderRoundMode(MachineInstrBuilder &MIB, const MachineInstr &MI,
425 int OpIdx) const;
426
427 void renderVOP3PModsNeg(MachineInstrBuilder &MIB, const MachineInstr &MI,
428 int OpIdx) const;
429 void renderVOP3PModsNegs(MachineInstrBuilder &MIB, const MachineInstr &MI,
430 int OpIdx) const;
431 void renderVOP3PModsNegAbs(MachineInstrBuilder &MIB, const MachineInstr &MI,
432 int OpIdx) const;
433
434 void renderPrefetchLoc(MachineInstrBuilder &MIB, const MachineInstr &MI,
435 int OpIdx) const;
436
437 void renderScaledMAIIntrinsicOperand(MachineInstrBuilder &MIB,
438 const MachineInstr &MI, int OpIdx) const;
439
440 bool isInlineImmediate(const APInt &Imm) const;
441 bool isInlineImmediate(const APFloat &Imm) const;
442
443 // Returns true if TargetOpcode::G_AND MachineInstr `MI`'s masking of the
444 // shift amount operand's `ShAmtBits` bits is unneeded.
445 bool isUnneededShiftMask(const MachineInstr &MI, unsigned ShAmtBits) const;
446
447 /// Match a zero extend from a 32-bit value to 64-bits.
448 Register matchZeroExtendFromS32(Register Reg) const;
449 /// Match a sign extend from a 32-bit value to 64-bits.
450 Register matchSignExtendFromS32(Register Reg) const;
451 /// Match a zero extend from a 32-bit value to 64-bits, or \p Reg itself if it
452 /// is 32-bit.
453 Register matchZeroExtendFromS32OrS32(Register Reg) const;
454 /// Match a sign extend from a 32-bit value to 64-bits, or \p Reg itself if it
455 /// is 32-bit.
456 Register matchSignExtendFromS32OrS32(Register Reg) const;
457 /// Match either sign or zero extend depending on the \p IsSigned from a
458 /// 32-bit value to 64-bits, or \p Reg itself if it is 32-bit.
459 Register matchExtendFromS32OrS32(Register Reg, bool IsSigned) const;
460 /// Match an any extend from a 32-bit value to 64-bit.
461 Register matchAnyExtendFromS32(Register Reg) const;
462
463 const SIInstrInfo &TII;
464 const SIRegisterInfo &TRI;
465 const AMDGPURegisterBankInfo &RBI;
466 const GCNSubtarget &STI;
467#define GET_GLOBALISEL_PREDICATES_DECL
468#define AMDGPUSubtarget GCNSubtarget
469#include "AMDGPUGenGlobalISel.inc"
470#undef GET_GLOBALISEL_PREDICATES_DECL
471#undef AMDGPUSubtarget
472
473#define GET_GLOBALISEL_TEMPORARIES_DECL
474#include "AMDGPUGenGlobalISel.inc"
475#undef GET_GLOBALISEL_TEMPORARIES_DECL
476};
477
478} // End llvm namespace.
479#endif
Imm
unsigned Imm
Definition AMDGPUDisassembler.cpp:539
uint64_t
unsigned uint64_t
Definition AMDGPUDisassembler.cpp:540
B
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
MI
IRTranslator LLVM IR MI
Definition IRTranslator.cpp:863
I
#define I(x, y, z)
Definition MD5.cpp:57
Reg
Register Reg
Definition MachineSink.cpp:2127
TRI
Register const TargetRegisterInfo * TRI
Definition MachineSink.cpp:2128
Register
Promote Memory to Register
Definition Mem2Reg.cpp:110
P
#define P(N)
llvm::AMDGPUInstructionSelector::AMDGPUInstructionSelector
AMDGPUInstructionSelector(const GCNSubtarget &STI, const AMDGPURegisterBankInfo &RBI)
Definition AMDGPUInstructionSelector.cpp:42
llvm::AMDGPUInstructionSelector::getName
static const char * getName()
llvm::AMDGPUInstructionSelector::select
bool select(MachineInstr &I) override
Select the (possibly generic) instruction I to only use target-specific opcodes.
Definition AMDGPUInstructionSelector.cpp:4553
llvm::AMDGPUInstructionSelector::setupMF
void setupMF(MachineFunction &MF, GISelValueTracking *VT, CodeGenCoverage *CoverageInfo, ProfileSummaryInfo *PSI, BlockFrequencyInfo *BFI) override
Setup per-MF executor state.
Definition AMDGPUInstructionSelector.cpp:56
llvm::ArrayRef
Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition ArrayRef.h:40
llvm::BlockFrequencyInfo
BlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate IR basic block frequen...
Definition BlockFrequencyInfo.h:38
llvm::CmpInst::Predicate
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition InstrTypes.h:740
llvm::GIMatchTableExecutor::ComplexRendererFns
std::optional< SmallVector< std::function< void(MachineInstrBuilder &)>, 4 > > ComplexRendererFns
Definition GIMatchTableExecutor.h:643
llvm::MCRegisterClass
MCRegisterClass - Base class of TargetRegisterClass.
Definition MCRegisterInfo.h:37
llvm::MachineIRBuilder
Helper class to build MachineInstr.
Definition MachineIRBuilder.h:238
llvm::MachineInstr
Representation of each machine instruction.
Definition MachineInstr.h:74
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition MachineOperand.h:49
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition MachineRegisterInfo.h:55
llvm::ProfileSummaryInfo
Analysis providing profile information.
Definition ProfileSummaryInfo.h:42
llvm::RegisterBank
This class implements the register bank concept.
Definition RegisterBank.h:30
llvm::Register
Wrapper class representing virtual and physical registers.
Definition Register.h:20
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition SmallVector.h:592
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition SmallVector.h:1252
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition TargetRegisterInfo.h:74
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition DefaultTargetInfo.h:21
llvm::Offset
@ Offset
Definition DWP.cpp:577
llvm::size
auto size(R &&Range, std::enable_if_t< std::is_base_of< std::random_access_iterator_tag, typename std::iterator_traits< decltype(Range.begin())>::iterator_category >::value, void > *=nullptr)
Get the size of a range.
Definition STLExtras.h:1685
llvm::VectorInstrContext::Load
@ Load
The value being inserted comes from a load (InsertElement only).
Definition TargetTransformInfo.h:200
llvm::TargetRegisterClass
MCRegisterClass TargetRegisterClass
Definition FastISel.h:58
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