LLVM 22.0.0git
GIMatchTableExecutor.h
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1//===- llvm/CodeGen/GlobalISel/GIMatchTableExecutor.h -----------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9/// \file This file declares the GIMatchTableExecutor API, the opcodes supported
10/// by the match table, and some associated data structures used by the
11/// executor's implementation (see `GIMatchTableExecutorImpl.h`).
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef LLVM_CODEGEN_GLOBALISEL_GIMATCHTABLEEXECUTOR_H
16#define LLVM_CODEGEN_GLOBALISEL_GIMATCHTABLEEXECUTOR_H
17
18#include "llvm/ADT/ArrayRef.h"
19#include "llvm/ADT/Bitset.h"
20#include "llvm/ADT/DenseMap.h"
26#include "llvm/IR/Function.h"
29#include <bitset>
30#include <cstddef>
31#include <cstdint>
32#include <functional>
33#include <initializer_list>
34#include <optional>
35#include <vector>
36
37namespace llvm {
38
39class BlockFrequencyInfo;
40class CodeGenCoverage;
41class MachineBasicBlock;
42class ProfileSummaryInfo;
43class APInt;
44class APFloat;
45class GISelValueTracking;
46class MachineInstr;
47class MachineIRBuilder;
48class MachineInstrBuilder;
49class MachineFunction;
50class MachineOperand;
51class MachineRegisterInfo;
52class RegisterBankInfo;
53class TargetInstrInfo;
54class TargetRegisterInfo;
55
56enum {
59};
60
61/// The MatchTable is encoded as an array of bytes.
62/// Thus, opcodes are expected to be <255.
63///
64/// Operands can be variable-sized, their size is always after their name
65/// in the docs, e.g. "Foo(4)" means that "Foo" takes 4 entries in the table,
66/// so 4 bytes. "Foo()"
67///
68/// As a general rule of thumb:
69/// - Instruction & Operand IDs are ULEB128
70/// - LLT IDs are 1 byte
71/// - Predicates and target opcodes, register and register class IDs are 2
72/// bytes.
73/// - Indexes into the table are 4 bytes.
74/// - Inline constants are 8 bytes
75///
76/// Design notes:
77/// - Inst/Op IDs have to be LEB128 because some targets generate
78/// extremely long patterns which need more than 255 temporaries.
79/// We could just use 2 bytes everytime, but then some targets like
80/// X86/AMDGPU that have no need for it will pay the price all the time.
81enum {
82 /// Begin a try-block to attempt a match and jump to OnFail if it is
83 /// unsuccessful.
84 /// - OnFail(4) - The MatchTable entry at which to resume if the match fails.
85 ///
86 /// FIXME: This ought to take an argument indicating the number of try-blocks
87 /// to exit on failure. It's usually one but the last match attempt of
88 /// a block will need more. The (implemented) alternative is to tack a
89 /// GIM_Reject on the end of each try-block which is simpler but
90 /// requires an extra opcode and iteration in the interpreter on each
91 /// failed match.
93
94 /// Switch over the opcode on the specified instruction
95 /// - InsnID(ULEB128) - Instruction ID
96 /// - LowerBound(2) - numerically minimum opcode supported
97 /// - UpperBound(2) - numerically maximum + 1 opcode supported
98 /// - Default(4) - failure jump target
99 /// - JumpTable(4)... - (UpperBound - LowerBound) (at least 2) jump targets
101
102 /// Switch over the LLT on the specified instruction operand
103 /// - InsnID(ULEB128) - Instruction ID
104 /// - OpIdx(ULEB128) - Operand index
105 /// - LowerBound(2) - numerically minimum Type ID supported
106 /// - UpperBound(2) - numerically maximum + 1 Type ID supported
107 /// - Default(4) - failure jump target
108 /// - JumpTable(4)... - (UpperBound - LowerBound) (at least 2) jump targets
110
111 /// Record the specified instruction.
112 /// The IgnoreCopies variant ignores COPY instructions.
113 /// - NewInsnID(ULEB128) - Instruction ID to define
114 /// - InsnID(ULEB128) - Instruction ID
115 /// - OpIdx(ULEB128) - Operand index
118
119 /// Check the feature bits
120 /// Feature(2) - Expected features
122
123 /// Check the opcode on the specified instruction
124 /// - InsnID(ULEB128) - Instruction ID
125 /// - Opc(2) - Expected opcode
127
128 /// Check the opcode on the specified instruction, checking 2 acceptable
129 /// alternatives.
130 /// - InsnID(ULEB128) - Instruction ID
131 /// - Opc(2) - Expected opcode
132 /// - Opc(2) - Alternative expected opcode
134
135 /// Check the instruction has the right number of operands
136 /// - InsnID(ULEB128) - Instruction ID
137 /// - Ops(ULEB128) - Expected number of operands
139
140 /// Check the instruction has a number of operands <= or >= than given number.
141 /// - InsnID(ULEB128) - Instruction ID
142 /// - Ops(ULEB128) - Number of operands
145
146 /// Check an immediate predicate on the specified instruction
147 /// - InsnID(ULEB128) - Instruction ID
148 /// - Pred(2) - The predicate to test
150 /// Check an immediate predicate on the specified instruction via an APInt.
151 /// - InsnID(ULEB128) - Instruction ID
152 /// - Pred(2) - The predicate to test
154 /// Check a floating point immediate predicate on the specified instruction.
155 /// - InsnID(ULEB128) - Instruction ID
156 /// - Pred(2) - The predicate to test
158 /// Check an immediate predicate on the specified instruction
159 /// - InsnID(ULEB128) - Instruction ID
160 /// - OpIdx(ULEB128) - Operand index
161 /// - Pred(2) - The predicate to test
163
164 /// Check a leaf predicate on the specified instruction.
165 /// - InsnID(ULEB128) - Instruction ID
166 /// - OpIdx(ULEB128) - Operand index
167 /// - Pred(2) - The predicate to test
169
170 /// Check a memory operation has the specified atomic ordering.
171 /// - InsnID(ULEB128) - Instruction ID
172 /// - Ordering(ULEB128) - The AtomicOrdering value
176
177 /// Check the size of the memory access for the given machine memory operand.
178 /// - InsnID(ULEB128) - Instruction ID
179 /// - MMOIdx(ULEB128) - MMO index
180 /// - Size(4) - The size in bytes of the memory access
182
183 /// Check the address space of the memory access for the given machine memory
184 /// operand.
185 /// - InsnID(ULEB128) - Instruction ID
186 /// - MMOIdx(ULEB128) - MMO index
187 /// - NumAddrSpace(1) - Number of valid address spaces
188 /// - AddrSpaceN(ULEB128) - An allowed space of the memory access
189 /// - AddrSpaceN+1 ...
191
192 /// Check the minimum alignment of the memory access for the given machine
193 /// memory operand.
194 /// - InsnID(ULEB128) - Instruction ID
195 /// - MMOIdx(ULEB128) - MMO index
196 /// - MinAlign(1) - Minimum acceptable alignment
198
199 /// Check the size of the memory access for the given machine memory operand
200 /// against the size of an operand.
201 /// - InsnID(ULEB128) - Instruction ID
202 /// - MMOIdx(ULEB128) - MMO index
203 /// - OpIdx(ULEB128) - The operand index to compare the MMO against
207
208 /// Check if this is a vector that can be treated as a vector splat
209 /// constant. This is valid for both G_BUILD_VECTOR as well as
210 /// G_BUILD_VECTOR_TRUNC. For AllOnes refers to individual bits, so a -1
211 /// element.
212 /// - InsnID(ULEB128) - Instruction ID
215
216 /// Check a trivial predicate which takes no arguments.
217 /// This can be used by executors to implement custom flags that don't fit in
218 /// target features.
219 /// - Pred(2) - Predicate ID to check.
221
222 /// Check a generic C++ instruction predicate
223 /// - InsnID(ULEB128) - Instruction ID
224 /// - PredicateID(2) - The ID of the predicate function to call
226
227 /// Check if there's no use of the first result.
228 /// - InsnID(ULEB128) - Instruction ID
230
231 /// Check if there's one use of the first result.
232 /// - InsnID(ULEB128) - Instruction ID
234
235 /// Check the type for the specified operand
236 /// - InsnID(ULEB128) - Instruction ID
237 /// - OpIdx(ULEB128) - Operand index
238 /// - Ty(1) - Expected type
240 /// GIM_CheckType but InsnID is omitted and defaults to zero.
242
243 /// Check the type of a pointer to any address space.
244 /// - InsnID(ULEB128) - Instruction ID
245 /// - OpIdx(ULEB128) - Operand index
246 /// - SizeInBits(ULEB128) - The size of the pointer value in bits.
248
249 /// Check the register bank for the specified operand
250 /// - InsnID(ULEB128) - Instruction ID
251 /// - OpIdx(ULEB128) - Operand index
252 /// - RC(2) - Expected register bank (specified as a register class)
254 /// GIM_CheckRegBankForClass but InsnID is omitted and defaults to zero.
256
257 /// Check the operand matches a complex predicate
258 /// - InsnID(ULEB128) - Instruction ID
259 /// - OpIdx(ULEB128) - Operand index
260 /// - RendererID(2) - The renderer to hold the result
261 /// - Pred(2) - Complex predicate ID
263
264 /// Check the operand is a specific integer
265 /// - InsnID(ULEB128) - Instruction ID
266 /// - OpIdx(ULEB128) - Operand index
267 /// - Val(8) Expected integer
269
270 /// Check the operand is a specific 8-bit signed integer
271 /// - InsnID(ULEB128) - Instruction ID
272 /// - OpIdx(ULEB128) - Operand index
273 /// - Val(1) Expected integer
275
276 /// Check the operand is a specific literal integer (i.e. MO.isImm() or
277 /// MO.isCImm() is true).
278 /// - InsnID(ULEB128) - Instruction ID
279 /// - OpIdx(ULEB128) - Operand index
280 /// - Val(8) - Expected integer
282
283 /// Check the operand is a specific intrinsic ID
284 /// - InsnID(ULEB128) - Instruction ID
285 /// - OpIdx(ULEB128) - Operand index
286 /// - IID(2) - Expected Intrinsic ID
288
289 /// Check the operand is a specific predicate
290 /// - InsnID(ULEB128) - Instruction ID
291 /// - OpIdx(ULEB128) - Operand index
292 /// - Pred(2) - Expected predicate
294
295 /// Check the specified operand is an MBB
296 /// - InsnID(ULEB128) - Instruction ID
297 /// - OpIdx(ULEB128) - Operand index
299
300 /// Check the specified operand is an Imm
301 /// - InsnID(ULEB128) - Instruction ID
302 /// - OpIdx(ULEB128) - Operand index
304
305 /// Checks if the matched instructions numbered [1, 1+N) can
306 /// be folded into the root (inst 0).
307 /// - Num(1)
309
310 /// Check the specified operands are identical.
311 /// The IgnoreCopies variant looks through COPY instructions before
312 /// comparing the operands.
313 /// The "All" variants check all operands starting from the index.
314 /// - InsnID(ULEB128) - Instruction ID
315 /// - OpIdx(ULEB128) - Operand index
316 /// - OtherInsnID(ULEB128) - Other instruction ID
317 /// - OtherOpIdx(ULEB128) - Other operand index
322
323 /// Check we can replace all uses of a register with another.
324 /// - OldInsnID(ULEB128)
325 /// - OldOpIdx(ULEB128)
326 /// - NewInsnID(ULEB128)
327 /// - NewOpIdx(ULEB128)
329
330 /// Check that a matched instruction has, or doesn't have a MIFlag.
331 ///
332 /// - InsnID(ULEB128) - Instruction to check.
333 /// - Flags(4) - (can be one or more flags OR'd together)
336
337 /// Predicates with 'let PredicateCodeUsesOperands = 1' need to examine some
338 /// named operands that will be recorded in RecordedOperands. Names of these
339 /// operands are referenced in predicate argument list. Emitter determines
340 /// StoreIdx(corresponds to the order in which names appear in argument list).
341 /// - InsnID(ULEB128) - Instruction ID
342 /// - OpIdx(ULEB128) - Operand index
343 /// - StoreIdx(ULEB128) - Store location in RecordedOperands.
345
346 /// Records an operand's register type into the set of temporary types.
347 /// - InsnID(ULEB128) - Instruction ID
348 /// - OpIdx(ULEB128) - Operand index
349 /// - TempTypeIdx(1) - Temp Type Index, always negative.
351
352 /// Fail the current try-block, or completely fail to match if there is no
353 /// current try-block.
355
356 //=== Renderers ===
357
358 /// Mutate an instruction
359 /// - NewInsnID(ULEB128) - Instruction ID to define
360 /// - OldInsnID(ULEB128) - Instruction ID to mutate
361 /// - NewOpcode(2) - The new opcode to use
363
364 /// Build a new instruction
365 /// - InsnID(ULEB128) - Instruction ID to define
366 /// - Opcode(2) - The new opcode to use
368 /// GIR_BuildMI but InsnID is omitted and defaults to zero.
370
371 /// Builds a constant and stores its result in a TempReg.
372 /// - TempRegID(ULEB128) - Temp Register to define.
373 /// - Imm(8) - The immediate to add
375
376 /// Copy an operand to the specified instruction
377 /// - NewInsnID(ULEB128) - Instruction ID to modify
378 /// - OldInsnID(ULEB128) - Instruction ID to copy from
379 /// - OpIdx(ULEB128) - The operand to copy
381 /// GIR_Copy but with both New/OldInsnIDs omitted and defaulting to zero.
383
384 /// Copies all operand starting from OpIdx in OldInsnID into the new
385 /// instruction NewInsnID.
386 /// - NewInsnID(ULEB128) - Instruction ID to modify
387 /// - OldInsnID(ULEB128) - Instruction ID to copy from
388 /// - OpIdx(ULEB128) - The first operand to copy
390
391 /// Copy an operand to the specified instruction or add a zero register if the
392 /// operand is a zero immediate.
393 /// - NewInsnID(ULEB128) - Instruction ID to modify
394 /// - OldInsnID(ULEB128) - Instruction ID to copy from
395 /// - OpIdx(ULEB128) - The operand to copy
396 /// - ZeroReg(2) - The zero register to use
398 /// Copy an operand to the specified instruction
399 /// - NewInsnID(ULEB128) - Instruction ID to modify
400 /// - OldInsnID(ULEB128) - Instruction ID to copy from
401 /// - OpIdx(ULEB128) - The operand to copy
402 /// - SubRegIdx(2) - The subregister to copy
404
405 /// Add an implicit register def to the specified instruction
406 /// - InsnID(ULEB128) - Instruction ID to modify
407 /// - RegNum(2) - The register to add
408 /// - Flags(2) - Register Flags
410 /// Add an implicit register use to the specified instruction
411 /// - InsnID(ULEB128) - Instruction ID to modify
412 /// - RegNum(2) - The register to add
414 /// Add an register to the specified instruction
415 /// - InsnID(ULEB128) - Instruction ID to modify
416 /// - RegNum(2) - The register to add
417 /// - Flags(2) - Register Flags
419
420 /// Adds an intrinsic ID to the specified instruction.
421 /// - InsnID(ULEB128) - Instruction ID to modify
422 /// - IID(2) - Intrinsic ID
424
425 /// Marks the implicit def of a register as dead.
426 /// - InsnID(ULEB128) - Instruction ID to modify
427 /// - OpIdx(ULEB128) - The implicit def operand index
428 ///
429 /// OpIdx starts at 0 for the first implicit def.
431
432 /// Set or unset a MIFlag on an instruction.
433 ///
434 /// - InsnID(ULEB128) - Instruction to modify.
435 /// - Flags(4) - (can be one or more flags OR'd together)
438
439 /// Copy the MIFlags of a matched instruction into an
440 /// output instruction. The flags are OR'd together.
441 ///
442 /// - InsnID(ULEB128) - Instruction to modify.
443 /// - OldInsnID(ULEB128) - Matched instruction to copy flags from.
445
446 /// Add a temporary register to the specified instruction
447 /// - InsnID(ULEB128) - Instruction ID to modify
448 /// - TempRegID(ULEB128) - The temporary register ID to add
449 /// - TempRegFlags(2) - The register flags to set
451
452 /// Add a temporary register to the specified instruction without
453 /// setting any flags.
454 /// - InsnID(ULEB128) - Instruction ID to modify
455 /// - TempRegID(ULEB128) - The temporary register ID to add
457
458 /// Add a temporary register to the specified instruction
459 /// - InsnID(ULEB128) - Instruction ID to modify
460 /// - TempRegID(ULEB128) - The temporary register ID to add
461 /// - TempRegFlags(2) - The register flags to set
462 /// - SubRegIndex(2) - The subregister index to set
464
465 /// Add an immediate to the specified instruction
466 /// - InsnID(ULEB128) - Instruction ID to modify
467 /// - Imm(8) - The immediate to add
469
470 /// Add signed 8 bit immediate to the specified instruction
471 /// - InsnID(ULEB128) - Instruction ID to modify
472 /// - Imm(1) - The immediate to add
474
475 /// Add an CImm to the specified instruction
476 /// - InsnID(ULEB128) - Instruction ID to modify
477 /// - Ty(1) - Type of the constant immediate.
478 /// - Imm(8) - The immediate to add
480
481 /// Render complex operands to the specified instruction
482 /// - InsnID(ULEB128) - Instruction ID to modify
483 /// - RendererID(2) - The renderer to call
485 /// Render sub-operands of complex operands to the specified instruction
486 /// - InsnID(ULEB128) - Instruction ID to modify
487 /// - RendererID(2) - The renderer to call
488 /// - RenderOpID(ULEB128) - The suboperand to render.
490 /// Render subregisters of suboperands of complex operands to the
491 /// specified instruction
492 /// - InsnID(ULEB128) - Instruction ID to modify
493 /// - RendererID(2) - The renderer to call
494 /// - RenderOpID(ULEB128) - The suboperand to render
495 /// - SubRegIdx(2) - The subregister to extract
497
498 /// Render operands to the specified instruction using a custom function
499 /// - InsnID(ULEB128) - Instruction ID to modify
500 /// - OldInsnID(ULEB128) - Instruction ID to get the matched operand from
501 /// - RendererFnID(2) - Custom renderer function to call
503
504 /// Calls a C++ function that concludes the current match.
505 /// The C++ function is free to return false and reject the match, or
506 /// return true and mutate the instruction(s) (or do nothing, even).
507 /// - FnID(2) - The function to call.
509
510 /// Render operands to the specified instruction using a custom function,
511 /// reading from a specific operand.
512 /// - InsnID(ULEB128) - Instruction ID to modify
513 /// - OldInsnID(ULEB128) - Instruction ID to get the matched operand from
514 /// - OpIdx(ULEB128) - Operand index in OldInsnID the render function should
515 /// read
516 /// from..
517 /// - RendererFnID(2) - Custom renderer function to call
519
520 /// Render a G_CONSTANT operator as a sign-extended immediate.
521 /// - NewInsnID(ULEB128) - Instruction ID to modify
522 /// - OldInsnID(ULEB128) - Instruction ID to copy from
523 /// The operand index is implicitly 1.
525
526 /// Render a G_FCONSTANT operator as a sign-extended immediate.
527 /// - NewInsnID(ULEB128) - Instruction ID to modify
528 /// - OldInsnID(ULEB128) - Instruction ID to copy from
529 /// The operand index is implicitly 1.
531
532 /// Constrain an instruction operand to a register class.
533 /// - InsnID(ULEB128) - Instruction ID to modify
534 /// - OpIdx(ULEB128) - Operand index
535 /// - RCEnum(2) - Register class enumeration value
537
538 /// Constrain an instructions operands according to the instruction
539 /// description.
540 /// - InsnID(ULEB128) - Instruction ID to modify
542 /// GIR_ConstrainSelectedInstOperands but InsnID is omitted and defaults to
543 /// zero.
545
546 /// Merge all memory operands into instruction.
547 /// - InsnID(ULEB128) - Instruction ID to modify
548 /// - NumInsnID(1) - Number of instruction IDs following this argument
549 /// - MergeInsnID(ULEB128)... - One or more Instruction ID to merge into the
550 /// result.
552
553 /// Erase from parent.
554 /// - InsnID(ULEB128) - Instruction ID to erase
556
557 /// Combines both a GIR_EraseFromParent 0 + GIR_Done
559
560 /// Create a new temporary register that's not constrained.
561 /// - TempRegID(ULEB128) - The temporary register ID to initialize.
562 /// - Ty(1) - Expected type
564
565 /// Replaces all references to a register from an instruction
566 /// with another register from another instruction.
567 /// - OldInsnID(ULEB128)
568 /// - OldOpIdx(ULEB128)
569 /// - NewInsnID(ULEB128)
570 /// - NewOpIdx(ULEB128)
572
573 /// Replaces all references to a register with a temporary register.
574 /// - OldInsnID(ULEB128)
575 /// - OldOpIdx(ULEB128)
576 /// - TempRegIdx(ULEB128)
578
579 /// A successful emission
581
582 /// Increment the rule coverage counter.
583 /// - RuleID(4) - The ID of the rule that was covered.
585
586 /// Keeping track of the number of the GI opcodes. Must be the last entry.
588};
589
590/// Provides the logic to execute GlobalISel match tables, which are used by the
591/// instruction selector and instruction combiners as their engine to match and
592/// apply MIR patterns.
594public:
595 virtual ~GIMatchTableExecutor() = default;
596
599 MachineFunction *MF = nullptr;
602 // For some predicates, we need to track the current MBB.
604
606
607 /// Setup per-MF executor state.
609 CodeGenCoverage *covinfo = nullptr,
610 ProfileSummaryInfo *psi = nullptr,
611 BlockFrequencyInfo *bfi = nullptr) {
612 CoverageInfo = covinfo;
613 VT = vt;
614 MF = &mf;
615 PSI = psi;
616 BFI = bfi;
617 CurMBB = nullptr;
619 }
620
621protected:
623 std::optional<SmallVector<std::function<void(MachineInstrBuilder &)>, 4>>;
626
628 std::vector<ComplexRendererFns::value_type> Renderers;
631 /// Named operands that predicate with 'let PredicateCodeUsesOperands = 1'
632 /// referenced in its argument list. Operands are inserted at index set by
633 /// emitter, it corresponds to the order in which names appear in argument
634 /// list. Currently such predicates don't have more then 3 arguments.
635 std::array<const MachineOperand *, 3> RecordedOperands;
636
637 /// Types extracted from an instruction's operand.
638 /// Whenever a type index is negative, we look here instead.
640
641 LLVM_ABI MatcherState(unsigned MaxRenderers);
642 };
643
645 const auto &F = MF->getFunction();
646 if (F.hasOptSize())
647 return true;
648 if (CurMBB)
649 if (auto *BB = CurMBB->getBasicBlock())
651 return false;
652 }
653
654public:
655 template <class PredicateBitset, class ComplexMatcherMemFn,
656 class CustomRendererFn>
657 struct ExecInfoTy {
658 ExecInfoTy(const LLT *TypeObjects, size_t NumTypeObjects,
659 const PredicateBitset *FeatureBitsets,
660 const ComplexMatcherMemFn *ComplexPredicates,
661 const CustomRendererFn *CustomRenderers)
665
666 for (size_t I = 0; I < NumTypeObjects; ++I)
668 }
670 const PredicateBitset *FeatureBitsets;
671 const ComplexMatcherMemFn *ComplexPredicates;
672 const CustomRendererFn *CustomRenderers;
673
675 };
676
677protected:
679
680 /// Execute a given matcher table and return true if the match was successful
681 /// and false otherwise.
682 template <class TgtExecutor, class PredicateBitset, class ComplexMatcherMemFn,
683 class CustomRendererFn>
684 bool executeMatchTable(TgtExecutor &Exec, MatcherState &State,
685 const ExecInfoTy<PredicateBitset, ComplexMatcherMemFn,
686 CustomRendererFn> &ExecInfo,
687 MachineIRBuilder &Builder, const uint8_t *MatchTable,
689 const TargetRegisterInfo &TRI,
690 const RegisterBankInfo &RBI,
691 const PredicateBitset &AvailableFeatures,
693
694 virtual const uint8_t *getMatchTable() const {
695 llvm_unreachable("Should have been overridden by tablegen if used");
696 }
697
698 virtual bool testImmPredicate_I64(unsigned, int64_t) const {
700 "Subclasses must override this with a tablegen-erated function");
701 }
702 virtual bool testImmPredicate_APInt(unsigned, const APInt &) const {
704 "Subclasses must override this with a tablegen-erated function");
705 }
706 virtual bool testImmPredicate_APFloat(unsigned, const APFloat &) const {
708 "Subclasses must override this with a tablegen-erated function");
709 }
710 virtual bool testMIPredicate_MI(unsigned, const MachineInstr &,
711 const MatcherState &State) const {
713 "Subclasses must override this with a tablegen-erated function");
714 }
715
716 virtual bool testMOPredicate_MO(unsigned, const MachineOperand &,
717 const MatcherState &State) const {
719 "Subclasses must override this with a tablegen-erated function");
720 }
721
722 virtual bool testSimplePredicate(unsigned) const {
723 llvm_unreachable("Subclass does not implement testSimplePredicate!");
724 }
725
726 virtual bool runCustomAction(unsigned, const MatcherState &State,
727 NewMIVector &OutMIs) const {
728 llvm_unreachable("Subclass does not implement runCustomAction!");
729 }
730
731 LLVM_ABI bool isOperandImmEqual(const MachineOperand &MO, int64_t Value,
733 bool Splat = false) const;
734
735 /// Return true if the specified operand is a G_PTR_ADD with a G_CONSTANT on
736 /// the right-hand side. GlobalISel's separation of pointer and integer types
737 /// means that we don't need to worry about G_OR with equivalent semantics.
739 const MachineRegisterInfo &MRI) const;
740
741 /// Return true if MI can obviously be folded into IntoMI.
742 /// MI and IntoMI do not need to be in the same basic blocks, but MI must
743 /// preceed IntoMI.
745 MachineInstr &IntoMI) const;
746
747 template <typename Ty> static Ty readBytesAs(const uint8_t *MatchTable) {
748 Ty Ret;
749 memcpy(&Ret, MatchTable, sizeof(Ret));
750 return Ret;
751 }
752
754 unsigned FirstVarOp) {
755 auto Operands = drop_begin(MI.operands(), FirstVarOp);
756 return {Operands.begin(), Operands.end()};
757 }
758
759public:
760 // Faster ULEB128 decoder tailored for the Match Table Executor.
761 //
762 // - Arguments are fixed to avoid mid-function checks.
763 // - Unchecked execution, assumes no error.
764 // - Fast common case handling (1 byte values).
767 uint64_t &CurrentIdx) {
768 uint64_t Value = MatchTable[CurrentIdx++];
769 if (LLVM_UNLIKELY(Value >= 128)) {
770 Value &= 0x7f;
771 unsigned Shift = 7;
772 do {
773 uint64_t Slice = MatchTable[CurrentIdx] & 0x7f;
774 Value += Slice << Shift;
775 Shift += 7;
776 } while (MatchTable[CurrentIdx++] >= 128);
777 }
778 return Value;
779 }
780};
781
782} // end namespace llvm
783
784#endif // LLVM_CODEGEN_GLOBALISEL_GIMATCHTABLEEXECUTOR_H
unsigned const MachineRegisterInfo * MRI
#define LLVM_UNLIKELY(EXPR)
Definition: Compiler.h:336
#define LLVM_ATTRIBUTE_ALWAYS_INLINE
LLVM_ATTRIBUTE_ALWAYS_INLINE - On compilers where we have a directive to do so, mark a method "always...
Definition: Compiler.h:356
#define LLVM_ATTRIBUTE_RESTRICT
LLVM_ATTRIBUTE_RESTRICT - Annotates a pointer to tell the compiler that it is not aliased in the curr...
Definition: Compiler.h:381
#define LLVM_ABI
Definition: Compiler.h:213
This file defines the DenseMap class.
const HexagonInstrInfo * TII
IRTranslator LLVM IR MI
Implement a low-level type suitable for MachineInstr level instruction selection.
#define F(x, y, z)
Definition: MD5.cpp:55
#define I(x, y, z)
Definition: MD5.cpp:58
mir Rename Register Operands
Register const TargetRegisterInfo * TRI
This file defines the SmallVector class.
Class for arbitrary precision integers.
Definition: APInt.h:78
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
BlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate IR basic block frequen...
Provides the logic to execute GlobalISel match tables, which are used by the instruction selector and...
virtual bool testSimplePredicate(unsigned) const
bool executeMatchTable(TgtExecutor &Exec, MatcherState &State, const ExecInfoTy< PredicateBitset, ComplexMatcherMemFn, CustomRendererFn > &ExecInfo, MachineIRBuilder &Builder, const uint8_t *MatchTable, const TargetInstrInfo &TII, MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI, const PredicateBitset &AvailableFeatures, CodeGenCoverage *CoverageInfo) const
Execute a given matcher table and return true if the match was successful and false otherwise.
virtual bool testImmPredicate_APFloat(unsigned, const APFloat &) const
virtual bool testMOPredicate_MO(unsigned, const MachineOperand &, const MatcherState &State) const
virtual const uint8_t * getMatchTable() const
virtual bool testImmPredicate_APInt(unsigned, const APInt &) const
virtual bool testMIPredicate_MI(unsigned, const MachineInstr &, const MatcherState &State) const
LLVM_ABI bool isBaseWithConstantOffset(const MachineOperand &Root, const MachineRegisterInfo &MRI) const
Return true if the specified operand is a G_PTR_ADD with a G_CONSTANT on the right-hand side.
virtual bool testImmPredicate_I64(unsigned, int64_t) const
static Ty readBytesAs(const uint8_t *MatchTable)
std::optional< SmallVector< std::function< void(MachineInstrBuilder &)>, 4 > > ComplexRendererFns
bool shouldOptForSize(const MachineFunction *MF) const
static LLVM_ATTRIBUTE_ALWAYS_INLINE uint64_t fastDecodeULEB128(const uint8_t *LLVM_ATTRIBUTE_RESTRICT MatchTable, uint64_t &CurrentIdx)
LLVM_ABI bool isOperandImmEqual(const MachineOperand &MO, int64_t Value, const MachineRegisterInfo &MRI, bool Splat=false) const
virtual ~GIMatchTableExecutor()=default
LLVM_ABI bool isObviouslySafeToFold(MachineInstr &MI, MachineInstr &IntoMI) const
Return true if MI can obviously be folded into IntoMI.
virtual void setupMF(MachineFunction &mf, GISelValueTracking *vt, CodeGenCoverage *covinfo=nullptr, ProfileSummaryInfo *psi=nullptr, BlockFrequencyInfo *bfi=nullptr)
Setup per-MF executor state.
virtual bool runCustomAction(unsigned, const MatcherState &State, NewMIVector &OutMIs) const
static ArrayRef< MachineOperand > getRemainingOperands(const MachineInstr &MI, unsigned FirstVarOp)
virtual void setupGeneratedPerFunctionState(MachineFunction &MF)=0
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
Function & getFunction()
Return the LLVM function that this machine code represents.
Helper class to build MachineInstr.
Representation of each machine instruction.
Definition: MachineInstr.h:72
MachineOperand class - Representation of each machine instruction operand.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Analysis providing profile information.
Holds all the information related to register banks.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1197
TargetInstrInfo - Interface to description of machine instruction set.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
LLVM Value Representation.
Definition: Value.h:75
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
auto drop_begin(T &&RangeOrContainer, size_t N=1)
Return a range covering RangeOrContainer with the first N elements excluded.
Definition: STLExtras.h:338
@ GICXXCustomAction_Invalid
LLVM_ABI bool shouldOptimizeForSize(const MachineFunction *MF, ProfileSummaryInfo *PSI, const MachineBlockFrequencyInfo *BFI, PGSOQueryType QueryType=PGSOQueryType::Other)
Returns true if machine function MF is suggested to be size-optimized based on the profile.
@ GIR_AddIntrinsicID
Adds an intrinsic ID to the specified instruction.
@ GIR_ComplexRenderer
Render complex operands to the specified instruction.
@ GIR_ReplaceRegWithTempReg
Replaces all references to a register with a temporary register.
@ GIR_ComplexSubOperandRenderer
Render sub-operands of complex operands to the specified instruction.
@ GIR_MakeTempReg
Create a new temporary register that's not constrained.
@ GIM_CheckMemorySizeEqualTo
Check the size of the memory access for the given machine memory operand.
@ GIM_RootCheckType
GIM_CheckType but InsnID is omitted and defaults to zero.
@ GIM_RootCheckRegBankForClass
GIM_CheckRegBankForClass but InsnID is omitted and defaults to zero.
@ GIR_Done
A successful emission.
@ GIM_RecordNamedOperand
Predicates with 'let PredicateCodeUsesOperands = 1' need to examine some named operands that will be ...
@ GIM_Try
Begin a try-block to attempt a match and jump to OnFail if it is unsuccessful.
@ GIR_RootConstrainSelectedInstOperands
GIR_ConstrainSelectedInstOperands but InsnID is omitted and defaults to zero.
@ GIM_CheckIsBuildVectorAllOnes
Check if this is a vector that can be treated as a vector splat constant.
@ GIM_CheckNumOperands
Check the instruction has the right number of operands.
@ GIR_AddCImm
Add an CImm to the specified instruction.
@ GIR_ConstrainOperandRC
Constrain an instruction operand to a register class.
@ GIM_CheckI64ImmPredicate
Check an immediate predicate on the specified instruction.
@ GIR_AddImplicitDef
Add an implicit register def to the specified instruction.
@ GIM_CheckAPIntImmPredicate
Check an immediate predicate on the specified instruction via an APInt.
@ GIM_CheckHasNoUse
Check if there's no use of the first result.
@ GIM_CheckPointerToAny
Check the type of a pointer to any address space.
@ GIM_CheckMemorySizeEqualToLLT
Check the size of the memory access for the given machine memory operand against the size of an opera...
@ GIM_CheckComplexPattern
Check the operand matches a complex predicate.
@ GIR_CopyConstantAsSImm
Render a G_CONSTANT operator as a sign-extended immediate.
@ GIR_EraseFromParent
Erase from parent.
@ GIM_SwitchType
Switch over the LLT on the specified instruction operand.
@ GIR_CopySubReg
Copy an operand to the specified instruction.
@ GIR_MutateOpcode
Mutate an instruction.
@ GIM_CheckIsBuildVectorAllZeros
@ GIM_CheckAtomicOrderingOrStrongerThan
@ GIR_AddRegister
Add an register to the specified instruction.
@ GIR_AddTempSubRegister
Add a temporary register to the specified instruction.
@ GIM_CheckIsSafeToFold
Checks if the matched instructions numbered [1, 1+N) can be folded into the root (inst 0).
@ GIM_CheckOpcode
Check the opcode on the specified instruction.
@ GIR_ReplaceReg
Replaces all references to a register from an instruction with another register from another instruct...
@ GIM_SwitchOpcode
Switch over the opcode on the specified instruction.
@ GIM_CheckAPFloatImmPredicate
Check a floating point immediate predicate on the specified instruction.
@ GIM_CheckAllSameOperandIgnoreCopies
@ GIM_Reject
Fail the current try-block, or completely fail to match if there is no current try-block.
@ GIR_AddSimpleTempRegister
Add a temporary register to the specified instruction without setting any flags.
@ GIR_AddTempRegister
Add a temporary register to the specified instruction.
@ GIR_Copy
Copy an operand to the specified instruction.
@ GIR_AddImm
Add an immediate to the specified instruction.
@ GIR_CopyFConstantAsFPImm
Render a G_FCONSTANT operator as a sign-extended immediate.
@ GIU_NumOpcodes
Keeping track of the number of the GI opcodes. Must be the last entry.
@ GIR_CopyRemaining
Copies all operand starting from OpIdx in OldInsnID into the new instruction NewInsnID.
@ GIM_MIFlags
Check that a matched instruction has, or doesn't have a MIFlag.
@ GIR_CopyOrAddZeroReg
Copy an operand to the specified instruction or add a zero register if the operand is a zero immediat...
@ GIM_CheckMemoryAlignment
Check the minimum alignment of the memory access for the given machine memory operand.
@ GIM_CheckIsSameOperand
Check the specified operands are identical.
@ GIR_AddImm8
Add signed 8 bit immediate to the specified instruction.
@ GIM_CheckIsSameOperandIgnoreCopies
@ GIM_CheckIsMBB
Check the specified operand is an MBB.
@ GIM_CheckNumOperandsLE
Check the instruction has a number of operands <= or >= than given number.
@ GIM_CheckMemorySizeGreaterThanLLT
@ GIM_CheckRegBankForClass
Check the register bank for the specified operand.
@ GIM_CheckNumOperandsGE
@ GIM_CheckLiteralInt
Check the operand is a specific literal integer (i.e.
@ GIM_CheckMemorySizeLessThanLLT
@ GIM_RecordRegType
Records an operand's register type into the set of temporary types.
@ GIM_CheckLeafOperandPredicate
Check a leaf predicate on the specified instruction.
@ GIM_CheckHasOneUse
Check if there's one use of the first result.
@ GIM_CheckAllSameOperand
@ GIR_EraseRootFromParent_Done
Combines both a GIR_EraseFromParent 0 + GIR_Done.
@ GIR_CopyMIFlags
Copy the MIFlags of a matched instruction into an output instruction.
@ GIR_DoneWithCustomAction
Calls a C++ function that concludes the current match.
@ GIR_BuildMI
Build a new instruction.
@ GIM_RecordInsn
Record the specified instruction.
@ GIM_CheckIsImm
Check the specified operand is an Imm.
@ GIR_BuildRootMI
GIR_BuildMI but InsnID is omitted and defaults to zero.
@ GIM_CheckFeatures
Check the feature bits Feature(2) - Expected features.
@ GIM_CheckCanReplaceReg
Check we can replace all uses of a register with another.
@ GIM_CheckMemoryAddressSpace
Check the address space of the memory access for the given machine memory operand.
@ GIR_CustomRenderer
Render operands to the specified instruction using a custom function.
@ GIM_CheckAtomicOrdering
Check a memory operation has the specified atomic ordering.
@ GIM_CheckType
Check the type for the specified operand.
@ GIM_CheckConstantInt8
Check the operand is a specific 8-bit signed integer.
@ GIM_CheckCmpPredicate
Check the operand is a specific predicate.
@ GIM_CheckOpcodeIsEither
Check the opcode on the specified instruction, checking 2 acceptable alternatives.
@ GIR_SetImplicitDefDead
Marks the implicit def of a register as dead.
@ GIR_BuildConstant
Builds a constant and stores its result in a TempReg.
@ GIR_AddImplicitUse
Add an implicit register use to the specified instruction.
@ GIR_Coverage
Increment the rule coverage counter.
@ GIR_MergeMemOperands
Merge all memory operands into instruction.
@ GIM_CheckImmOperandPredicate
Check an immediate predicate on the specified instruction.
@ GIM_CheckAtomicOrderingWeakerThan
@ GIR_SetMIFlags
Set or unset a MIFlag on an instruction.
@ GIM_CheckIntrinsicID
Check the operand is a specific intrinsic ID.
@ GIM_CheckConstantInt
Check the operand is a specific integer.
@ GIR_RootToRootCopy
GIR_Copy but with both New/OldInsnIDs omitted and defaulting to zero.
@ GIR_ComplexSubOperandSubRegRenderer
Render subregisters of suboperands of complex operands to the specified instruction.
@ GIM_RecordInsnIgnoreCopies
@ GIR_CustomOperandRenderer
Render operands to the specified instruction using a custom function, reading from a specific operand...
@ GIR_ConstrainSelectedInstOperands
Constrain an instructions operands according to the instruction description.
@ GIM_CheckCxxInsnPredicate
Check a generic C++ instruction predicate.
@ GIM_CheckSimplePredicate
Check a trivial predicate which takes no arguments.
ExecInfoTy(const LLT *TypeObjects, size_t NumTypeObjects, const PredicateBitset *FeatureBitsets, const ComplexMatcherMemFn *ComplexPredicates, const CustomRendererFn *CustomRenderers)
SmallDenseMap< LLT, unsigned, 64 > TypeIDMap
const ComplexMatcherMemFn * ComplexPredicates
std::array< const MachineOperand *, 3 > RecordedOperands
Named operands that predicate with 'let PredicateCodeUsesOperands = 1' referenced in its argument lis...
SmallVector< LLT, 4 > RecordedTypes
Types extracted from an instruction's operand.
DenseMap< unsigned, Register > TempRegisters
std::vector< ComplexRendererFns::value_type > Renderers