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| Register | llvm::constrainRegToClass (MachineRegisterInfo &MRI, const TargetInstrInfo &TII, const RegisterBankInfo &RBI, Register Reg, const TargetRegisterClass &RegClass) |
| | Try to constrain Reg to the specified register class.
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| Register | llvm::constrainOperandRegClass (const MachineFunction &MF, const TargetRegisterInfo &TRI, MachineRegisterInfo &MRI, const TargetInstrInfo &TII, const RegisterBankInfo &RBI, MachineInstr &InsertPt, const TargetRegisterClass &RegClass, MachineOperand &RegMO) |
| | Constrain the Register operand OpIdx, so that it is now constrained to the TargetRegisterClass passed as an argument (RegClass).
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| Register | llvm::constrainOperandRegClass (const MachineFunction &MF, const TargetRegisterInfo &TRI, MachineRegisterInfo &MRI, const TargetInstrInfo &TII, const RegisterBankInfo &RBI, MachineInstr &InsertPt, const MCInstrDesc &II, MachineOperand &RegMO, unsigned OpIdx) |
| | Try to constrain Reg so that it is usable by argument OpIdx of the provided MCInstrDesc II.
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| bool | llvm::constrainSelectedInstRegOperands (MachineInstr &I, const TargetInstrInfo &TII, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI) |
| | Mutate the newly-selected instruction I to constrain its (possibly generic) virtual register operands to the instruction's register class.
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| bool | llvm::canReplaceReg (Register DstReg, Register SrcReg, MachineRegisterInfo &MRI) |
| | Check if DstReg can be replaced with SrcReg depending on the register constraints.
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| bool | llvm::isTriviallyDead (const MachineInstr &MI, const MachineRegisterInfo &MRI) |
| | Check whether an instruction MI is dead: it only defines dead virtual registers, and doesn't have other side effects.
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| void | llvm::reportGISelFailure (MachineFunction &MF, const TargetPassConfig &TPC, MachineOptimizationRemarkEmitter &MORE, MachineOptimizationRemarkMissed &R) |
| | Report an ISel error as a missed optimization remark to the LLVMContext's diagnostic stream.
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| void | llvm::reportGISelFailure (MachineFunction &MF, const TargetPassConfig &TPC, MachineOptimizationRemarkEmitter &MORE, const char *PassName, StringRef Msg, const MachineInstr &MI) |
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| void | llvm::reportGISelWarning (MachineFunction &MF, const TargetPassConfig &TPC, MachineOptimizationRemarkEmitter &MORE, MachineOptimizationRemarkMissed &R) |
| | Report an ISel warning as a missed optimization remark to the LLVMContext's diagnostic stream.
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| std::optional< APInt > | llvm::getIConstantVRegVal (Register VReg, const MachineRegisterInfo &MRI) |
| | If VReg is defined by a G_CONSTANT, return the corresponding value.
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| std::optional< int64_t > | llvm::getIConstantVRegSExtVal (Register VReg, const MachineRegisterInfo &MRI) |
| | If VReg is defined by a G_CONSTANT fits in int64_t returns it.
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| const APInt & | llvm::getIConstantFromReg (Register VReg, const MachineRegisterInfo &MRI) |
| | VReg is defined by a G_CONSTANT, return the corresponding value.
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| std::optional< ValueAndVReg > | llvm::getIConstantVRegValWithLookThrough (Register VReg, const MachineRegisterInfo &MRI, bool LookThroughInstrs=true) |
| | If VReg is defined by a statically evaluable chain of instructions rooted on a G_CONSTANT returns its APInt value and def register.
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| std::optional< ValueAndVReg > | llvm::getAnyConstantVRegValWithLookThrough (Register VReg, const MachineRegisterInfo &MRI, bool LookThroughInstrs=true, bool LookThroughAnyExt=false) |
| | If VReg is defined by a statically evaluable chain of instructions rooted on a G_CONSTANT or G_FCONSTANT returns its value as APInt and def register.
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| std::optional< FPValueAndVReg > | llvm::getFConstantVRegValWithLookThrough (Register VReg, const MachineRegisterInfo &MRI, bool LookThroughInstrs=true) |
| | If VReg is defined by a statically evaluable chain of instructions rooted on a G_FCONSTANT returns its APFloat value and def register.
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| const ConstantFP * | llvm::getConstantFPVRegVal (Register VReg, const MachineRegisterInfo &MRI) |
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| MachineInstr * | llvm::getOpcodeDef (unsigned Opcode, Register Reg, const MachineRegisterInfo &MRI) |
| | See if Reg is defined by an single def instruction that is Opcode.
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| std::optional< DefinitionAndSourceRegister > | llvm::getDefSrcRegIgnoringCopies (Register Reg, const MachineRegisterInfo &MRI) |
| | Find the def instruction for Reg, and underlying value Register folding away any copies.
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| MachineInstr * | llvm::getDefIgnoringCopies (Register Reg, const MachineRegisterInfo &MRI) |
| | Find the def instruction for Reg, folding away any trivial copies.
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| Register | llvm::getSrcRegIgnoringCopies (Register Reg, const MachineRegisterInfo &MRI) |
| | Find the source register for Reg, folding away any trivial copies.
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| void | llvm::extractParts (Register Reg, LLT Ty, int NumParts, SmallVectorImpl< Register > &VRegs, MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI) |
| | Helper function to split a wide generic register into bitwise blocks with the given Type (which implies the number of blocks needed).
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| bool | llvm::extractParts (Register Reg, LLT RegTy, LLT MainTy, LLT &LeftoverTy, SmallVectorImpl< Register > &VRegs, SmallVectorImpl< Register > &LeftoverVRegs, MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI) |
| | Version which handles irregular splits.
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| void | llvm::extractVectorParts (Register Reg, unsigned NumElts, SmallVectorImpl< Register > &VRegs, MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI) |
| | Version which handles irregular sub-vector splits.
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| template<class T > |
| T * | llvm::getOpcodeDef (Register Reg, const MachineRegisterInfo &MRI) |
| | See if Reg is defined by an single def instruction of type T Also try to do trivial folding if it's a COPY with same types.
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| APFloat | llvm::getAPFloatFromSize (double Val, unsigned Size) |
| | Returns an APFloat from Val converted to the appropriate size.
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| void | llvm::getSelectionDAGFallbackAnalysisUsage (AnalysisUsage &AU) |
| | Modify analysis usage so it preserves passes required for the SelectionDAG fallback.
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| std::optional< APInt > | llvm::ConstantFoldBinOp (unsigned Opcode, const Register Op1, const Register Op2, const MachineRegisterInfo &MRI) |
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| std::optional< APFloat > | llvm::ConstantFoldFPBinOp (unsigned Opcode, const Register Op1, const Register Op2, const MachineRegisterInfo &MRI) |
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| SmallVector< APInt > | llvm::ConstantFoldVectorBinop (unsigned Opcode, const Register Op1, const Register Op2, const MachineRegisterInfo &MRI) |
| | Tries to constant fold a vector binop with sources Op1 and Op2.
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| std::optional< APInt > | llvm::ConstantFoldCastOp (unsigned Opcode, LLT DstTy, const Register Op0, const MachineRegisterInfo &MRI) |
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| std::optional< APInt > | llvm::ConstantFoldExtOp (unsigned Opcode, const Register Op1, uint64_t Imm, const MachineRegisterInfo &MRI) |
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| std::optional< APFloat > | llvm::ConstantFoldIntToFloat (unsigned Opcode, LLT DstTy, Register Src, const MachineRegisterInfo &MRI) |
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| std::optional< SmallVector< unsigned > > | llvm::ConstantFoldCountZeros (Register Src, const MachineRegisterInfo &MRI, std::function< unsigned(APInt)> CB) |
| | Tries to constant fold a counting-zero operation (G_CTLZ or G_CTTZ) on Src.
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| std::optional< SmallVector< APInt > > | llvm::ConstantFoldICmp (unsigned Pred, const Register Op1, const Register Op2, const MachineRegisterInfo &MRI) |
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| bool | llvm::isKnownToBeAPowerOfTwo (Register Val, const MachineRegisterInfo &MRI, GISelKnownBits *KnownBits=nullptr) |
| | Test if the given value is known to have exactly one bit set.
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| bool | llvm::isKnownNeverNaN (Register Val, const MachineRegisterInfo &MRI, bool SNaN=false) |
| | Returns true if Val can be assumed to never be a NaN.
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| bool | llvm::isKnownNeverSNaN (Register Val, const MachineRegisterInfo &MRI) |
| | Returns true if Val can be assumed to never be a signaling NaN.
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| Align | llvm::inferAlignFromPtrInfo (MachineFunction &MF, const MachinePointerInfo &MPO) |
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| Register | llvm::getFunctionLiveInPhysReg (MachineFunction &MF, const TargetInstrInfo &TII, MCRegister PhysReg, const TargetRegisterClass &RC, const DebugLoc &DL, LLT RegTy=LLT()) |
| | Return a virtual register corresponding to the incoming argument register PhysReg.
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| LLVM_READNONE LLT | llvm::getLCMType (LLT OrigTy, LLT TargetTy) |
| | Return the least common multiple type of OrigTy and TargetTy, by changing the number of vector elements or scalar bitwidth.
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| LLVM_READNONE LLT | llvm::getCoverTy (LLT OrigTy, LLT TargetTy) |
| | Return smallest type that covers both OrigTy and TargetTy and is multiple of TargetTy.
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| LLVM_READNONE LLT | llvm::getGCDType (LLT OrigTy, LLT TargetTy) |
| | Return a type where the total size is the greatest common divisor of OrigTy and TargetTy.
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| std::optional< int > | llvm::getSplatIndex (MachineInstr &MI) |
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| std::optional< APInt > | llvm::getIConstantSplatVal (const Register Reg, const MachineRegisterInfo &MRI) |
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| std::optional< APInt > | llvm::getIConstantSplatVal (const MachineInstr &MI, const MachineRegisterInfo &MRI) |
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| std::optional< int64_t > | llvm::getIConstantSplatSExtVal (const Register Reg, const MachineRegisterInfo &MRI) |
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| std::optional< int64_t > | llvm::getIConstantSplatSExtVal (const MachineInstr &MI, const MachineRegisterInfo &MRI) |
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| std::optional< FPValueAndVReg > | llvm::getFConstantSplat (Register VReg, const MachineRegisterInfo &MRI, bool AllowUndef=true) |
| | Returns a floating point scalar constant of a build vector splat if it exists.
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| bool | llvm::isBuildVectorConstantSplat (const Register Reg, const MachineRegisterInfo &MRI, int64_t SplatValue, bool AllowUndef) |
| | Return true if the specified register is defined by G_BUILD_VECTOR or G_BUILD_VECTOR_TRUNC where all of the elements are SplatValue or undef.
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| bool | llvm::isBuildVectorConstantSplat (const MachineInstr &MI, const MachineRegisterInfo &MRI, int64_t SplatValue, bool AllowUndef) |
| | Return true if the specified instruction is a G_BUILD_VECTOR or G_BUILD_VECTOR_TRUNC where all of the elements are SplatValue or undef.
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| bool | llvm::isBuildVectorAllZeros (const MachineInstr &MI, const MachineRegisterInfo &MRI, bool AllowUndef=false) |
| | Return true if the specified instruction is a G_BUILD_VECTOR or G_BUILD_VECTOR_TRUNC where all of the elements are 0 or undef.
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| bool | llvm::isBuildVectorAllOnes (const MachineInstr &MI, const MachineRegisterInfo &MRI, bool AllowUndef=false) |
| | Return true if the specified instruction is a G_BUILD_VECTOR or G_BUILD_VECTOR_TRUNC where all of the elements are ~0 or undef.
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| bool | llvm::isConstantOrConstantVector (const MachineInstr &MI, const MachineRegisterInfo &MRI, bool AllowFP=true, bool AllowOpaqueConstants=true) |
| | Return true if the specified instruction is known to be a constant, or a vector of constants.
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| bool | llvm::isNullOrNullSplat (const MachineInstr &MI, const MachineRegisterInfo &MRI, bool AllowUndefs=false) |
| | Return true if the value is a constant 0 integer or a splatted vector of a constant 0 integer (with no undefs if AllowUndefs is false).
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| bool | llvm::isAllOnesOrAllOnesSplat (const MachineInstr &MI, const MachineRegisterInfo &MRI, bool AllowUndefs=false) |
| | Return true if the value is a constant -1 integer or a splatted vector of a constant -1 integer (with no undefs if AllowUndefs is false).
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| std::optional< RegOrConstant > | llvm::getVectorSplat (const MachineInstr &MI, const MachineRegisterInfo &MRI) |
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| bool | llvm::isConstantOrConstantVector (MachineInstr &MI, const MachineRegisterInfo &MRI) |
| | Determines if MI defines a constant integer or a build vector of constant integers.
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| std::optional< APInt > | llvm::isConstantOrConstantSplatVector (MachineInstr &MI, const MachineRegisterInfo &MRI) |
| | Determines if MI defines a constant integer or a splat vector of constant integers.
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| bool | llvm::matchUnaryPredicate (const MachineRegisterInfo &MRI, Register Reg, std::function< bool(const Constant *ConstVal)> Match, bool AllowUndefs=false) |
| | Attempt to match a unary predicate against a scalar/splat constant or every element of a constant G_BUILD_VECTOR.
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| bool | llvm::isConstTrueVal (const TargetLowering &TLI, int64_t Val, bool IsVector, bool IsFP) |
| | Returns true if given the TargetLowering's boolean contents information, the value Val contains a true value.
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| bool | llvm::isConstFalseVal (const TargetLowering &TLI, int64_t Val, bool IsVector, bool IsFP) |
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| int64_t | llvm::getICmpTrueVal (const TargetLowering &TLI, bool IsVector, bool IsFP) |
| | Returns an integer representing true, as defined by the TargetBooleanContents.
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| void | llvm::saveUsesAndErase (MachineInstr &MI, MachineRegisterInfo &MRI, LostDebugLocObserver *LocObserver, SmallInstListTy &DeadInstChain) |
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| void | llvm::eraseInstrs (ArrayRef< MachineInstr * > DeadInstrs, MachineRegisterInfo &MRI, LostDebugLocObserver *LocObserver=nullptr) |
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| void | llvm::eraseInstr (MachineInstr &MI, MachineRegisterInfo &MRI, LostDebugLocObserver *LocObserver=nullptr) |
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| void | llvm::salvageDebugInfo (const MachineRegisterInfo &MRI, MachineInstr &MI) |
| | Assuming the instruction MI is going to be deleted, attempt to salvage debug users of MI by writing the effect of MI in a DIExpression.
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| bool | llvm::isPreISelGenericFloatingPointOpcode (unsigned Opc) |
| | Returns whether opcode Opc is a pre-isel generic floating-point opcode, having only floating-point operands.
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| bool | llvm::canCreateUndefOrPoison (Register Reg, const MachineRegisterInfo &MRI, bool ConsiderFlagsAndMetadata=true) |
| | Returns true if Reg can create undef or poison from non-undef & non-poison operands.
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| bool | llvm::canCreatePoison (Register Reg, const MachineRegisterInfo &MRI, bool ConsiderFlagsAndMetadata=true) |
| | Returns true if Reg can create poison from non-poison operands.
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| bool | llvm::isGuaranteedNotToBeUndefOrPoison (Register Reg, const MachineRegisterInfo &MRI, unsigned Depth=0) |
| | Returns true if Reg cannot be poison and undef.
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| bool | llvm::isGuaranteedNotToBePoison (Register Reg, const MachineRegisterInfo &MRI, unsigned Depth=0) |
| | Returns true if Reg cannot be poison, but may be undef.
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| bool | llvm::isGuaranteedNotToBeUndef (Register Reg, const MachineRegisterInfo &MRI, unsigned Depth=0) |
| | Returns true if Reg cannot be undef, but may be poison.
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| Type * | llvm::getTypeForLLT (LLT Ty, LLVMContext &C) |
| | Get the type back from LLT.
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