#include "AMDGPUBaseInfo.h"
#include "AMDGPU.h"
#include "AMDGPUAsmUtils.h"
#include "AMDKernelCodeT.h"
#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
#include "Utils/AMDKernelCodeTUtils.h"
#include "llvm/ADT/StringExtras.h"
#include "llvm/BinaryFormat/ELF.h"
#include "llvm/IR/Attributes.h"
#include "llvm/IR/Constants.h"
#include "llvm/IR/Function.h"
#include "llvm/IR/GlobalValue.h"
#include "llvm/IR/IntrinsicsAMDGPU.h"
#include "llvm/IR/IntrinsicsR600.h"
#include "llvm/IR/LLVMContext.h"
#include "llvm/MC/MCInstrInfo.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/MC/MCSubtargetInfo.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/TargetParser/TargetParser.h"
#include <optional>
#include "AMDGPUGenInstrInfo.inc"
#include "AMDGPUGenSearchableTables.inc"

Classes
struct	llvm::AMDGPU::MUBUFInfo

struct	llvm::AMDGPU::MTBUFInfo

struct	llvm::AMDGPU::SMInfo

struct	llvm::AMDGPU::VOPInfo

struct	llvm::AMDGPU::VOPC64DPPInfo

struct	llvm::AMDGPU::VOPCDPPAsmOnlyInfo

struct	llvm::AMDGPU::VOP3CDPPAsmOnlyInfo

struct	llvm::AMDGPU::VOPDComponentInfo

struct	llvm::AMDGPU::VOPDInfo

struct	llvm::AMDGPU::VOPTrue16Info

struct	llvm::AMDGPU::DPMACCInstructionInfo

struct	llvm::AMDGPU::FP4FP8DstByteSelInfo

struct	llvm::AMDGPU::Exp::ExpTgt

Namespaces
namespace	llvm
	This is an optimization pass for GlobalISel generic memory operations.

namespace	llvm::AMDGPU

namespace	llvm::AMDGPU::VOPD

namespace	llvm::AMDGPU::IsaInfo

namespace	llvm::AMDGPU::DepCtr

namespace	llvm::AMDGPU::Exp

namespace	llvm::AMDGPU::MTBUFFormat

namespace	llvm::AMDGPU::SendMsg

Macros
#define	GET_INSTRINFO_NAMED_OPS

#define	GET_INSTRMAP_INFO

#define	GET_MIMGBaseOpcodesTable_IMPL

#define	GET_MIMGDimInfoTable_IMPL

#define	GET_MIMGInfoTable_IMPL

#define	GET_MIMGLZMappingTable_IMPL

#define	GET_MIMGMIPMappingTable_IMPL

#define	GET_MIMGBiasMappingTable_IMPL

#define	GET_MIMGOffsetMappingTable_IMPL

#define	GET_MIMGG16MappingTable_IMPL

#define	GET_MAIInstInfoTable_IMPL

#define	GET_FP4FP8DstByteSelTable_DECL

#define	GET_FP4FP8DstByteSelTable_IMPL

#define	GET_MTBUFInfoTable_DECL

#define	GET_MTBUFInfoTable_IMPL

#define	GET_MUBUFInfoTable_DECL

#define	GET_MUBUFInfoTable_IMPL

#define	GET_SMInfoTable_DECL

#define	GET_SMInfoTable_IMPL

#define	GET_VOP1InfoTable_DECL

#define	GET_VOP1InfoTable_IMPL

#define	GET_VOP2InfoTable_DECL

#define	GET_VOP2InfoTable_IMPL

#define	GET_VOP3InfoTable_DECL

#define	GET_VOP3InfoTable_IMPL

#define	GET_VOPC64DPPTable_DECL

#define	GET_VOPC64DPPTable_IMPL

#define	GET_VOPC64DPP8Table_DECL

#define	GET_VOPC64DPP8Table_IMPL

#define	GET_VOPCAsmOnlyInfoTable_DECL

#define	GET_VOPCAsmOnlyInfoTable_IMPL

#define	GET_VOP3CAsmOnlyInfoTable_DECL

#define	GET_VOP3CAsmOnlyInfoTable_IMPL

#define	GET_VOPDComponentTable_DECL

#define	GET_VOPDComponentTable_IMPL

#define	GET_VOPDPairs_DECL

#define	GET_VOPDPairs_IMPL

#define	GET_VOPTrue16Table_DECL

#define	GET_VOPTrue16Table_IMPL

#define	GET_WMMAOpcode2AddrMappingTable_DECL

#define	GET_WMMAOpcode2AddrMappingTable_IMPL

#define	GET_WMMAOpcode3AddrMappingTable_DECL

#define	GET_WMMAOpcode3AddrMappingTable_IMPL

#define	GET_getMFMA_F8F6F4_WithSize_DECL

#define	GET_getMFMA_F8F6F4_WithSize_IMPL

#define	GET_isMFMA_F8F6F4Table_IMPL

#define	GET_isCvtScaleF32_F32F16ToF8F4Table_IMPL

#define	MAP_REG2REG

#define	CASE_CI_VI(node)

#define	CASE_VI_GFX9PLUS(node) case node: return isGFX9Plus(STI) ? node##_gfx9plus : node##_vi;

#define	CASE_GFXPRE11_GFX11PLUS(node) case node: return isGFX11Plus(STI) ? node##_gfx11plus : node##_gfxpre11;

#define	CASE_GFXPRE11_GFX11PLUS_TO(node, result) case node: return isGFX11Plus(STI) ? result##_gfx11plus : result##_gfxpre11;

#define	CASE_CI_VI(node) case node##_ci: case node##_vi: return node;

#define	CASE_VI_GFX9PLUS(node) case node##_vi: case node##_gfx9plus: return node;

#define	CASE_GFXPRE11_GFX11PLUS(node) case node##_gfx11plus: case node##_gfxpre11: return node;

#define	CASE_GFXPRE11_GFX11PLUS_TO(node, result)

#define	GET_SourcesOfDivergence_IMPL

#define	GET_UniformIntrinsics_IMPL

#define	GET_Gfx9BufferFormat_IMPL

#define	GET_Gfx10BufferFormat_IMPL

#define	GET_Gfx11PlusBufferFormat_IMPL

Functions
bool	llvm::AMDGPU::hasSMRDSignedImmOffset (const MCSubtargetInfo &ST)

bool	llvm::AMDGPU::isHsaAbi (const MCSubtargetInfo &STI)

unsigned	llvm::AMDGPU::getAMDHSACodeObjectVersion (const Module &M)

unsigned	llvm::AMDGPU::getDefaultAMDHSACodeObjectVersion ()

unsigned	llvm::AMDGPU::getAMDHSACodeObjectVersion (unsigned ABIVersion)

uint8_t	llvm::AMDGPU::getELFABIVersion (const Triple &T, unsigned CodeObjectVersion)

unsigned	llvm::AMDGPU::getMultigridSyncArgImplicitArgPosition (unsigned CodeObjectVersion)

unsigned	llvm::AMDGPU::getHostcallImplicitArgPosition (unsigned CodeObjectVersion)

unsigned	llvm::AMDGPU::getDefaultQueueImplicitArgPosition (unsigned CodeObjectVersion)

unsigned	llvm::AMDGPU::getCompletionActionImplicitArgPosition (unsigned CodeObjectVersion)

int	llvm::AMDGPU::getMIMGOpcode (unsigned BaseOpcode, unsigned MIMGEncoding, unsigned VDataDwords, unsigned VAddrDwords)

const MIMGBaseOpcodeInfo *	llvm::AMDGPU::getMIMGBaseOpcode (unsigned Opc)

int	llvm::AMDGPU::getMaskedMIMGOp (unsigned Opc, unsigned NewChannels)

unsigned	llvm::AMDGPU::getAddrSizeMIMGOp (const MIMGBaseOpcodeInfo BaseOpcode, const MIMGDimInfo Dim, bool IsA16, bool IsG16Supported)

int	llvm::AMDGPU::getMTBUFBaseOpcode (unsigned Opc)

int	llvm::AMDGPU::getMTBUFOpcode (unsigned BaseOpc, unsigned Elements)

int	llvm::AMDGPU::getMTBUFElements (unsigned Opc)

bool	llvm::AMDGPU::getMTBUFHasVAddr (unsigned Opc)

bool	llvm::AMDGPU::getMTBUFHasSrsrc (unsigned Opc)

bool	llvm::AMDGPU::getMTBUFHasSoffset (unsigned Opc)

int	llvm::AMDGPU::getMUBUFBaseOpcode (unsigned Opc)

int	llvm::AMDGPU::getMUBUFOpcode (unsigned BaseOpc, unsigned Elements)

int	llvm::AMDGPU::getMUBUFElements (unsigned Opc)

bool	llvm::AMDGPU::getMUBUFHasVAddr (unsigned Opc)

bool	llvm::AMDGPU::getMUBUFHasSrsrc (unsigned Opc)

bool	llvm::AMDGPU::getMUBUFHasSoffset (unsigned Opc)

bool	llvm::AMDGPU::getMUBUFIsBufferInv (unsigned Opc)

bool	llvm::AMDGPU::getMUBUFTfe (unsigned Opc)

bool	llvm::AMDGPU::getSMEMIsBuffer (unsigned Opc)

bool	llvm::AMDGPU::getVOP1IsSingle (unsigned Opc)

bool	llvm::AMDGPU::getVOP2IsSingle (unsigned Opc)

bool	llvm::AMDGPU::getVOP3IsSingle (unsigned Opc)

bool	llvm::AMDGPU::isVOPC64DPP (unsigned Opc)

bool	llvm::AMDGPU::isVOPCAsmOnly (unsigned Opc)

bool	llvm::AMDGPU::getMAIIsDGEMM (unsigned Opc)
	Returns true if MAI operation is a double precision GEMM.

bool	llvm::AMDGPU::getMAIIsGFX940XDL (unsigned Opc)

uint8_t	llvm::AMDGPU::mfmaScaleF8F6F4FormatToNumRegs (unsigned EncodingVal)

const MFMA_F8F6F4_Info *	llvm::AMDGPU::getMFMA_F8F6F4_WithFormatArgs (unsigned CBSZ, unsigned BLGP, unsigned F8F8Opcode)

unsigned	llvm::AMDGPU::getVOPDEncodingFamily (const MCSubtargetInfo &ST)

CanBeVOPD	llvm::AMDGPU::getCanBeVOPD (unsigned Opc)

unsigned	llvm::AMDGPU::getVOPDOpcode (unsigned Opc)

bool	llvm::AMDGPU::isVOPD (unsigned Opc)

bool	llvm::AMDGPU::isMAC (unsigned Opc)

bool	llvm::AMDGPU::isPermlane16 (unsigned Opc)

bool	llvm::AMDGPU::isCvt_F32_Fp8_Bf8_e64 (unsigned Opc)

bool	llvm::AMDGPU::isGenericAtomic (unsigned Opc)

bool	llvm::AMDGPU::isTrue16Inst (unsigned Opc)

FPType	llvm::AMDGPU::getFPDstSelType (unsigned Opc)

unsigned	llvm::AMDGPU::mapWMMA2AddrTo3AddrOpcode (unsigned Opc)

unsigned	llvm::AMDGPU::mapWMMA3AddrTo2AddrOpcode (unsigned Opc)

int	llvm::AMDGPU::getMCOpcode (uint16_t Opcode, unsigned Gen)

int	llvm::AMDGPU::getVOPDFull (unsigned OpX, unsigned OpY, unsigned EncodingFamily)

std::pair< unsigned, unsigned >	llvm::AMDGPU::getVOPDComponents (unsigned VOPDOpcode)

VOPD::InstInfo	llvm::AMDGPU::getVOPDInstInfo (const MCInstrDesc &OpX, const MCInstrDesc &OpY)

VOPD::InstInfo	llvm::AMDGPU::getVOPDInstInfo (unsigned VOPDOpcode, const MCInstrInfo *InstrInfo)

static TargetIDSetting	llvm::AMDGPU::IsaInfo::getTargetIDSettingFromFeatureString (StringRef FeatureString)

unsigned	llvm::AMDGPU::IsaInfo::getWavefrontSize (const MCSubtargetInfo *STI)

unsigned	llvm::AMDGPU::IsaInfo::getLocalMemorySize (const MCSubtargetInfo *STI)

unsigned	llvm::AMDGPU::IsaInfo::getAddressableLocalMemorySize (const MCSubtargetInfo *STI)

unsigned	llvm::AMDGPU::IsaInfo::getEUsPerCU (const MCSubtargetInfo *STI)

unsigned	llvm::AMDGPU::IsaInfo::getMaxWorkGroupsPerCU (const MCSubtargetInfo *STI, unsigned FlatWorkGroupSize)

unsigned	llvm::AMDGPU::IsaInfo::getMinWavesPerEU (const MCSubtargetInfo *STI)

unsigned	llvm::AMDGPU::IsaInfo::getMaxWavesPerEU (const MCSubtargetInfo *STI)

unsigned	llvm::AMDGPU::IsaInfo::getWavesPerEUForWorkGroup (const MCSubtargetInfo *STI, unsigned FlatWorkGroupSize)

unsigned	llvm::AMDGPU::IsaInfo::getMinFlatWorkGroupSize (const MCSubtargetInfo *STI)

unsigned	llvm::AMDGPU::IsaInfo::getMaxFlatWorkGroupSize (const MCSubtargetInfo *STI)

unsigned	llvm::AMDGPU::IsaInfo::getWavesPerWorkGroup (const MCSubtargetInfo *STI, unsigned FlatWorkGroupSize)

unsigned	llvm::AMDGPU::IsaInfo::getSGPRAllocGranule (const MCSubtargetInfo *STI)

unsigned	llvm::AMDGPU::IsaInfo::getSGPREncodingGranule (const MCSubtargetInfo *STI)

unsigned	llvm::AMDGPU::IsaInfo::getTotalNumSGPRs (const MCSubtargetInfo *STI)

unsigned	llvm::AMDGPU::IsaInfo::getAddressableNumSGPRs (const MCSubtargetInfo *STI)

unsigned	llvm::AMDGPU::IsaInfo::getMinNumSGPRs (const MCSubtargetInfo *STI, unsigned WavesPerEU)

unsigned	llvm::AMDGPU::IsaInfo::getMaxNumSGPRs (const MCSubtargetInfo *STI, unsigned WavesPerEU, bool Addressable)

unsigned	llvm::AMDGPU::IsaInfo::getNumExtraSGPRs (const MCSubtargetInfo *STI, bool VCCUsed, bool FlatScrUsed, bool XNACKUsed)

unsigned	llvm::AMDGPU::IsaInfo::getNumExtraSGPRs (const MCSubtargetInfo *STI, bool VCCUsed, bool FlatScrUsed)

static unsigned	llvm::AMDGPU::IsaInfo::getGranulatedNumRegisterBlocks (unsigned NumRegs, unsigned Granule)

unsigned	llvm::AMDGPU::IsaInfo::getNumSGPRBlocks (const MCSubtargetInfo *STI, unsigned NumSGPRs)

unsigned	llvm::AMDGPU::IsaInfo::getVGPRAllocGranule (const MCSubtargetInfo *STI, std::optional< bool > EnableWavefrontSize32)

unsigned	llvm::AMDGPU::IsaInfo::getVGPREncodingGranule (const MCSubtargetInfo *STI, std::optional< bool > EnableWavefrontSize32)

unsigned	llvm::AMDGPU::IsaInfo::getTotalNumVGPRs (const MCSubtargetInfo *STI)

unsigned	llvm::AMDGPU::IsaInfo::getAddressableNumArchVGPRs (const MCSubtargetInfo *STI)

unsigned	llvm::AMDGPU::IsaInfo::getAddressableNumVGPRs (const MCSubtargetInfo *STI)

unsigned	llvm::AMDGPU::IsaInfo::getNumWavesPerEUWithNumVGPRs (const MCSubtargetInfo *STI, unsigned NumVGPRs)

unsigned	llvm::AMDGPU::IsaInfo::getNumWavesPerEUWithNumVGPRs (unsigned NumVGPRs, unsigned Granule, unsigned MaxWaves, unsigned TotalNumVGPRs)

unsigned	llvm::AMDGPU::IsaInfo::getOccupancyWithNumSGPRs (unsigned SGPRs, unsigned MaxWaves, AMDGPUSubtarget::Generation Gen)

unsigned	llvm::AMDGPU::IsaInfo::getMinNumVGPRs (const MCSubtargetInfo *STI, unsigned WavesPerEU)

unsigned	llvm::AMDGPU::IsaInfo::getMaxNumVGPRs (const MCSubtargetInfo *STI, unsigned WavesPerEU)

unsigned	llvm::AMDGPU::IsaInfo::getEncodedNumVGPRBlocks (const MCSubtargetInfo *STI, unsigned NumVGPRs, std::optional< bool > EnableWavefrontSize32)

unsigned	llvm::AMDGPU::IsaInfo::getAllocatedNumVGPRBlocks (const MCSubtargetInfo *STI, unsigned NumVGPRs, std::optional< bool > EnableWavefrontSize32)

void	llvm::AMDGPU::initDefaultAMDKernelCodeT (AMDGPUMCKernelCodeT &KernelCode, const MCSubtargetInfo *STI)

bool	llvm::AMDGPU::isGroupSegment (const GlobalValue *GV)

bool	llvm::AMDGPU::isGlobalSegment (const GlobalValue *GV)

bool	llvm::AMDGPU::isReadOnlySegment (const GlobalValue *GV)

bool	llvm::AMDGPU::shouldEmitConstantsToTextSection (const Triple &TT)

std::pair< unsigned, unsigned >	llvm::AMDGPU::getIntegerPairAttribute (const Function &F, StringRef Name, std::pair< unsigned, unsigned > Default, bool OnlyFirstRequired)

std::optional< std::pair< unsigned, std::optional< unsigned > > >	llvm::AMDGPU::getIntegerPairAttribute (const Function &F, StringRef Name, bool OnlyFirstRequired)

SmallVector< unsigned >	llvm::AMDGPU::getIntegerVecAttribute (const Function &F, StringRef Name, unsigned Size, unsigned DefaultVal)

unsigned	llvm::AMDGPU::getVmcntBitMask (const IsaVersion &Version)

unsigned	llvm::AMDGPU::getLoadcntBitMask (const IsaVersion &Version)

unsigned	llvm::AMDGPU::getSamplecntBitMask (const IsaVersion &Version)

unsigned	llvm::AMDGPU::getBvhcntBitMask (const IsaVersion &Version)

unsigned	llvm::AMDGPU::getExpcntBitMask (const IsaVersion &Version)

unsigned	llvm::AMDGPU::getLgkmcntBitMask (const IsaVersion &Version)

unsigned	llvm::AMDGPU::getDscntBitMask (const IsaVersion &Version)

unsigned	llvm::AMDGPU::getKmcntBitMask (const IsaVersion &Version)

unsigned	llvm::AMDGPU::getStorecntBitMask (const IsaVersion &Version)

unsigned	llvm::AMDGPU::getWaitcntBitMask (const IsaVersion &Version)

unsigned	llvm::AMDGPU::decodeVmcnt (const IsaVersion &Version, unsigned Waitcnt)

unsigned	llvm::AMDGPU::decodeExpcnt (const IsaVersion &Version, unsigned Waitcnt)

unsigned	llvm::AMDGPU::decodeLgkmcnt (const IsaVersion &Version, unsigned Waitcnt)

void	llvm::AMDGPU::decodeWaitcnt (const IsaVersion &Version, unsigned Waitcnt, unsigned &Vmcnt, unsigned &Expcnt, unsigned &Lgkmcnt)
	Decodes Vmcnt, Expcnt and Lgkmcnt from given `Waitcnt` for given isa `Version`, and writes decoded values into `Vmcnt`, `Expcnt` and `Lgkmcnt` respectively.

Waitcnt	llvm::AMDGPU::decodeWaitcnt (const IsaVersion &Version, unsigned Encoded)

unsigned	llvm::AMDGPU::encodeVmcnt (const IsaVersion &Version, unsigned Waitcnt, unsigned Vmcnt)

unsigned	llvm::AMDGPU::encodeExpcnt (const IsaVersion &Version, unsigned Waitcnt, unsigned Expcnt)

unsigned	llvm::AMDGPU::encodeLgkmcnt (const IsaVersion &Version, unsigned Waitcnt, unsigned Lgkmcnt)

unsigned	llvm::AMDGPU::encodeWaitcnt (const IsaVersion &Version, unsigned Vmcnt, unsigned Expcnt, unsigned Lgkmcnt)
	Encodes `Vmcnt`, `Expcnt` and `Lgkmcnt` into Waitcnt for given isa `Version`.

unsigned	llvm::AMDGPU::encodeWaitcnt (const IsaVersion &Version, const Waitcnt &Decoded)

static unsigned	llvm::AMDGPU::getCombinedCountBitMask (const IsaVersion &Version, bool IsStore)

Waitcnt	llvm::AMDGPU::decodeLoadcntDscnt (const IsaVersion &Version, unsigned LoadcntDscnt)

Waitcnt	llvm::AMDGPU::decodeStorecntDscnt (const IsaVersion &Version, unsigned StorecntDscnt)

static unsigned	llvm::AMDGPU::encodeLoadcnt (const IsaVersion &Version, unsigned Waitcnt, unsigned Loadcnt)

static unsigned	llvm::AMDGPU::encodeStorecnt (const IsaVersion &Version, unsigned Waitcnt, unsigned Storecnt)

static unsigned	llvm::AMDGPU::encodeDscnt (const IsaVersion &Version, unsigned Waitcnt, unsigned Dscnt)

static unsigned	llvm::AMDGPU::encodeLoadcntDscnt (const IsaVersion &Version, unsigned Loadcnt, unsigned Dscnt)

unsigned	llvm::AMDGPU::encodeLoadcntDscnt (const IsaVersion &Version, const Waitcnt &Decoded)

static unsigned	llvm::AMDGPU::encodeStorecntDscnt (const IsaVersion &Version, unsigned Storecnt, unsigned Dscnt)

unsigned	llvm::AMDGPU::encodeStorecntDscnt (const IsaVersion &Version, const Waitcnt &Decoded)

static unsigned	llvm::AMDGPU::getDefaultCustomOperandEncoding (const CustomOperandVal *Opr, int Size, const MCSubtargetInfo &STI)

static bool	llvm::AMDGPU::isSymbolicCustomOperandEncoding (const CustomOperandVal *Opr, int Size, unsigned Code, bool &HasNonDefaultVal, const MCSubtargetInfo &STI)

static bool	llvm::AMDGPU::decodeCustomOperand (const CustomOperandVal *Opr, int Size, unsigned Code, int &Idx, StringRef &Name, unsigned &Val, bool &IsDefault, const MCSubtargetInfo &STI)

static int	llvm::AMDGPU::encodeCustomOperandVal (const CustomOperandVal &Op, int64_t InputVal)

static int	llvm::AMDGPU::encodeCustomOperand (const CustomOperandVal *Opr, int Size, const StringRef Name, int64_t InputVal, unsigned &UsedOprMask, const MCSubtargetInfo &STI)

int	llvm::AMDGPU::DepCtr::getDefaultDepCtrEncoding (const MCSubtargetInfo &STI)

bool	llvm::AMDGPU::DepCtr::isSymbolicDepCtrEncoding (unsigned Code, bool &HasNonDefaultVal, const MCSubtargetInfo &STI)

bool	llvm::AMDGPU::DepCtr::decodeDepCtr (unsigned Code, int &Id, StringRef &Name, unsigned &Val, bool &IsDefault, const MCSubtargetInfo &STI)

int	llvm::AMDGPU::DepCtr::encodeDepCtr (const StringRef Name, int64_t Val, unsigned &UsedOprMask, const MCSubtargetInfo &STI)

unsigned	llvm::AMDGPU::DepCtr::decodeFieldVmVsrc (unsigned Encoded)

unsigned	llvm::AMDGPU::DepCtr::decodeFieldVaVdst (unsigned Encoded)

unsigned	llvm::AMDGPU::DepCtr::decodeFieldSaSdst (unsigned Encoded)

unsigned	llvm::AMDGPU::DepCtr::encodeFieldVmVsrc (unsigned Encoded, unsigned VmVsrc)

unsigned	llvm::AMDGPU::DepCtr::encodeFieldVmVsrc (unsigned VmVsrc)

unsigned	llvm::AMDGPU::DepCtr::encodeFieldVaVdst (unsigned Encoded, unsigned VaVdst)

unsigned	llvm::AMDGPU::DepCtr::encodeFieldVaVdst (unsigned VaVdst)

unsigned	llvm::AMDGPU::DepCtr::encodeFieldSaSdst (unsigned Encoded, unsigned SaSdst)

unsigned	llvm::AMDGPU::DepCtr::encodeFieldSaSdst (unsigned SaSdst)

bool	llvm::AMDGPU::Exp::getTgtName (unsigned Id, StringRef &Name, int &Index)

unsigned	llvm::AMDGPU::Exp::getTgtId (const StringRef Name)

bool	llvm::AMDGPU::Exp::isSupportedTgtId (unsigned Id, const MCSubtargetInfo &STI)

int64_t	llvm::AMDGPU::MTBUFFormat::getDfmt (const StringRef Name)

StringRef	llvm::AMDGPU::MTBUFFormat::getDfmtName (unsigned Id)

static StringLiteral const *	llvm::AMDGPU::MTBUFFormat::getNfmtLookupTable (const MCSubtargetInfo &STI)

int64_t	llvm::AMDGPU::MTBUFFormat::getNfmt (const StringRef Name, const MCSubtargetInfo &STI)

StringRef	llvm::AMDGPU::MTBUFFormat::getNfmtName (unsigned Id, const MCSubtargetInfo &STI)

bool	llvm::AMDGPU::MTBUFFormat::isValidDfmtNfmt (unsigned Id, const MCSubtargetInfo &STI)

bool	llvm::AMDGPU::MTBUFFormat::isValidNfmt (unsigned Id, const MCSubtargetInfo &STI)

int64_t	llvm::AMDGPU::MTBUFFormat::encodeDfmtNfmt (unsigned Dfmt, unsigned Nfmt)

void	llvm::AMDGPU::MTBUFFormat::decodeDfmtNfmt (unsigned Format, unsigned &Dfmt, unsigned &Nfmt)

int64_t	llvm::AMDGPU::MTBUFFormat::getUnifiedFormat (const StringRef Name, const MCSubtargetInfo &STI)

StringRef	llvm::AMDGPU::MTBUFFormat::getUnifiedFormatName (unsigned Id, const MCSubtargetInfo &STI)

bool	llvm::AMDGPU::MTBUFFormat::isValidUnifiedFormat (unsigned Id, const MCSubtargetInfo &STI)

int64_t	llvm::AMDGPU::MTBUFFormat::convertDfmtNfmt2Ufmt (unsigned Dfmt, unsigned Nfmt, const MCSubtargetInfo &STI)

bool	llvm::AMDGPU::MTBUFFormat::isValidFormatEncoding (unsigned Val, const MCSubtargetInfo &STI)

unsigned	llvm::AMDGPU::MTBUFFormat::getDefaultFormatEncoding (const MCSubtargetInfo &STI)

static uint64_t	llvm::AMDGPU::SendMsg::getMsgIdMask (const MCSubtargetInfo &STI)

bool	llvm::AMDGPU::SendMsg::isValidMsgId (int64_t MsgId, const MCSubtargetInfo &STI)

bool	llvm::AMDGPU::SendMsg::isValidMsgOp (int64_t MsgId, int64_t OpId, const MCSubtargetInfo &STI, bool Strict)

bool	llvm::AMDGPU::SendMsg::isValidMsgStream (int64_t MsgId, int64_t OpId, int64_t StreamId, const MCSubtargetInfo &STI, bool Strict)

bool	llvm::AMDGPU::SendMsg::msgRequiresOp (int64_t MsgId, const MCSubtargetInfo &STI)

bool	llvm::AMDGPU::SendMsg::msgSupportsStream (int64_t MsgId, int64_t OpId, const MCSubtargetInfo &STI)

void	llvm::AMDGPU::SendMsg::decodeMsg (unsigned Val, uint16_t &MsgId, uint16_t &OpId, uint16_t &StreamId, const MCSubtargetInfo &STI)

uint64_t	llvm::AMDGPU::SendMsg::encodeMsg (uint64_t MsgId, uint64_t OpId, uint64_t StreamId)

unsigned	llvm::AMDGPU::getInitialPSInputAddr (const Function &F)

bool	llvm::AMDGPU::getHasColorExport (const Function &F)

bool	llvm::AMDGPU::getHasDepthExport (const Function &F)

bool	llvm::AMDGPU::isShader (CallingConv::ID cc)

bool	llvm::AMDGPU::isGraphics (CallingConv::ID cc)

bool	llvm::AMDGPU::isCompute (CallingConv::ID cc)

bool	llvm::AMDGPU::isEntryFunctionCC (CallingConv::ID CC)

bool	llvm::AMDGPU::isModuleEntryFunctionCC (CallingConv::ID CC)

bool	llvm::AMDGPU::isChainCC (CallingConv::ID CC)

bool	llvm::AMDGPU::isKernelCC (const Function *Func)

bool	llvm::AMDGPU::hasXNACK (const MCSubtargetInfo &STI)

bool	llvm::AMDGPU::hasSRAMECC (const MCSubtargetInfo &STI)

bool	llvm::AMDGPU::hasMIMG_R128 (const MCSubtargetInfo &STI)

bool	llvm::AMDGPU::hasA16 (const MCSubtargetInfo &STI)

bool	llvm::AMDGPU::hasG16 (const MCSubtargetInfo &STI)

bool	llvm::AMDGPU::hasPackedD16 (const MCSubtargetInfo &STI)

bool	llvm::AMDGPU::hasGDS (const MCSubtargetInfo &STI)

unsigned	llvm::AMDGPU::getNSAMaxSize (const MCSubtargetInfo &STI, bool HasSampler)

unsigned	llvm::AMDGPU::getMaxNumUserSGPRs (const MCSubtargetInfo &STI)

bool	llvm::AMDGPU::isSI (const MCSubtargetInfo &STI)

bool	llvm::AMDGPU::isCI (const MCSubtargetInfo &STI)

bool	llvm::AMDGPU::isVI (const MCSubtargetInfo &STI)

bool	llvm::AMDGPU::isGFX9 (const MCSubtargetInfo &STI)

bool	llvm::AMDGPU::isGFX9_GFX10 (const MCSubtargetInfo &STI)

bool	llvm::AMDGPU::isGFX9_GFX10_GFX11 (const MCSubtargetInfo &STI)

bool	llvm::AMDGPU::isGFX8_GFX9_GFX10 (const MCSubtargetInfo &STI)

bool	llvm::AMDGPU::isGFX8Plus (const MCSubtargetInfo &STI)

bool	llvm::AMDGPU::isGFX9Plus (const MCSubtargetInfo &STI)

bool	llvm::AMDGPU::isNotGFX9Plus (const MCSubtargetInfo &STI)

bool	llvm::AMDGPU::isGFX10 (const MCSubtargetInfo &STI)

bool	llvm::AMDGPU::isGFX10_GFX11 (const MCSubtargetInfo &STI)

bool	llvm::AMDGPU::isGFX10Plus (const MCSubtargetInfo &STI)

bool	llvm::AMDGPU::isGFX11 (const MCSubtargetInfo &STI)

bool	llvm::AMDGPU::isGFX11Plus (const MCSubtargetInfo &STI)

bool	llvm::AMDGPU::isGFX12 (const MCSubtargetInfo &STI)

bool	llvm::AMDGPU::isGFX12Plus (const MCSubtargetInfo &STI)

bool	llvm::AMDGPU::isNotGFX12Plus (const MCSubtargetInfo &STI)

bool	llvm::AMDGPU::isNotGFX11Plus (const MCSubtargetInfo &STI)

bool	llvm::AMDGPU::isNotGFX10Plus (const MCSubtargetInfo &STI)

bool	llvm::AMDGPU::isGFX10Before1030 (const MCSubtargetInfo &STI)

bool	llvm::AMDGPU::isGCN3Encoding (const MCSubtargetInfo &STI)

bool	llvm::AMDGPU::isGFX10_AEncoding (const MCSubtargetInfo &STI)

bool	llvm::AMDGPU::isGFX10_BEncoding (const MCSubtargetInfo &STI)

bool	llvm::AMDGPU::hasGFX10_3Insts (const MCSubtargetInfo &STI)

bool	llvm::AMDGPU::isGFX10_3_GFX11 (const MCSubtargetInfo &STI)

bool	llvm::AMDGPU::isGFX90A (const MCSubtargetInfo &STI)

bool	llvm::AMDGPU::isGFX940 (const MCSubtargetInfo &STI)

bool	llvm::AMDGPU::hasArchitectedFlatScratch (const MCSubtargetInfo &STI)

bool	llvm::AMDGPU::hasMAIInsts (const MCSubtargetInfo &STI)

bool	llvm::AMDGPU::hasVOPD (const MCSubtargetInfo &STI)

bool	llvm::AMDGPU::hasDPPSrc1SGPR (const MCSubtargetInfo &STI)

unsigned	llvm::AMDGPU::hasKernargPreload (const MCSubtargetInfo &STI)

int32_t	llvm::AMDGPU::getTotalNumVGPRs (bool has90AInsts, int32_t ArgNumAGPR, int32_t ArgNumVGPR)

bool	llvm::AMDGPU::isSGPR (MCRegister Reg, const MCRegisterInfo *TRI)
	Is Reg - scalar register.

bool	llvm::AMDGPU::isHi16Reg (MCRegister Reg, const MCRegisterInfo &MRI)

MCRegister	llvm::AMDGPU::getMCReg (MCRegister Reg, const MCSubtargetInfo &STI)
	If `Reg` is a pseudo reg, return the correct hardware register given `STI` otherwise return `Reg`.

MCRegister	llvm::AMDGPU::mc2PseudoReg (MCRegister Reg)
	Convert hardware register `Reg` to a pseudo register.

bool	llvm::AMDGPU::isInlineValue (unsigned Reg)

bool	llvm::AMDGPU::isSISrcOperand (const MCInstrDesc &Desc, unsigned OpNo)
	Is this an AMDGPU specific source operand? These include registers, inline constants, literals and mandatory literals (KImm).

bool	llvm::AMDGPU::isKImmOperand (const MCInstrDesc &Desc, unsigned OpNo)
	Is this a KImm operand?

bool	llvm::AMDGPU::isSISrcFPOperand (const MCInstrDesc &Desc, unsigned OpNo)
	Is this floating-point operand?

bool	llvm::AMDGPU::isSISrcInlinableOperand (const MCInstrDesc &Desc, unsigned OpNo)
	Does this operand support only inlinable literals?

unsigned	llvm::AMDGPU::getRegBitWidth (unsigned RCID)
	Get the size in bits of a register from the register class `RC`.

unsigned	llvm::AMDGPU::getRegBitWidth (const MCRegisterClass &RC)
	Get the size in bits of a register from the register class `RC`.

unsigned	llvm::AMDGPU::getRegOperandSize (const MCRegisterInfo *MRI, const MCInstrDesc &Desc, unsigned OpNo)
	Get size of register operand.

bool	llvm::AMDGPU::isInlinableLiteral64 (int64_t Literal, bool HasInv2Pi)
	Is this literal inlinable.

bool	llvm::AMDGPU::isInlinableLiteral32 (int32_t Literal, bool HasInv2Pi)

bool	llvm::AMDGPU::isInlinableLiteralBF16 (int16_t Literal, bool HasInv2Pi)

bool	llvm::AMDGPU::isInlinableLiteralI16 (int32_t Literal, bool HasInv2Pi)

bool	llvm::AMDGPU::isInlinableLiteralFP16 (int16_t Literal, bool HasInv2Pi)

std::optional< unsigned >	llvm::AMDGPU::getInlineEncodingV216 (bool IsFloat, uint32_t Literal)

std::optional< unsigned >	llvm::AMDGPU::getInlineEncodingV2I16 (uint32_t Literal)

std::optional< unsigned >	llvm::AMDGPU::getInlineEncodingV2BF16 (uint32_t Literal)

std::optional< unsigned >	llvm::AMDGPU::getInlineEncodingV2F16 (uint32_t Literal)

bool	llvm::AMDGPU::isInlinableLiteralV216 (uint32_t Literal, uint8_t OpType)

bool	llvm::AMDGPU::isInlinableLiteralV2I16 (uint32_t Literal)

bool	llvm::AMDGPU::isInlinableLiteralV2BF16 (uint32_t Literal)

bool	llvm::AMDGPU::isInlinableLiteralV2F16 (uint32_t Literal)

bool	llvm::AMDGPU::isValid32BitLiteral (uint64_t Val, bool IsFP64)

bool	llvm::AMDGPU::isArgPassedInSGPR (const Argument *A)

bool	llvm::AMDGPU::isArgPassedInSGPR (const CallBase *CB, unsigned ArgNo)

static bool	llvm::AMDGPU::hasSMEMByteOffset (const MCSubtargetInfo &ST)

bool	llvm::AMDGPU::isLegalSMRDEncodedUnsignedOffset (const MCSubtargetInfo &ST, int64_t EncodedOffset)

bool	llvm::AMDGPU::isLegalSMRDEncodedSignedOffset (const MCSubtargetInfo &ST, int64_t EncodedOffset, bool IsBuffer)

static bool	llvm::AMDGPU::isDwordAligned (uint64_t ByteOffset)

uint64_t	llvm::AMDGPU::convertSMRDOffsetUnits (const MCSubtargetInfo &ST, uint64_t ByteOffset)
	Convert `ByteOffset` to dwords if the subtarget uses dword SMRD immediate offsets.

std::optional< int64_t >	llvm::AMDGPU::getSMRDEncodedOffset (const MCSubtargetInfo &ST, int64_t ByteOffset, bool IsBuffer, bool HasSOffset)

std::optional< int64_t >	llvm::AMDGPU::getSMRDEncodedLiteralOffset32 (const MCSubtargetInfo &ST, int64_t ByteOffset)

unsigned	llvm::AMDGPU::getNumFlatOffsetBits (const MCSubtargetInfo &ST)
	For pre-GFX12 FLAT instructions the offset must be positive; MSB is ignored and forced to zero.

bool	llvm::AMDGPU::isIntrinsicSourceOfDivergence (unsigned IntrID)

bool	llvm::AMDGPU::isIntrinsicAlwaysUniform (unsigned IntrID)

const GcnBufferFormatInfo *	llvm::AMDGPU::getGcnBufferFormatInfo (uint8_t BitsPerComp, uint8_t NumComponents, uint8_t NumFormat, const MCSubtargetInfo &STI)

const GcnBufferFormatInfo *	llvm::AMDGPU::getGcnBufferFormatInfo (uint8_t Format, const MCSubtargetInfo &STI)

bool	llvm::AMDGPU::hasAny64BitVGPROperands (const MCInstrDesc &OpDesc)

bool	llvm::AMDGPU::isDPALU_DPP (const MCInstrDesc &OpDesc)

unsigned	llvm::AMDGPU::getLdsDwGranularity (const MCSubtargetInfo &ST)

raw_ostream &	llvm::operator<< (raw_ostream &OS, const AMDGPU::IsaInfo::TargetIDSetting S)

Variables
static llvm::cl::opt< unsigned >	DefaultAMDHSACodeObjectVersion ("amdhsa-code-object-version", llvm::cl::Hidden, llvm::cl::init(llvm::AMDGPU::AMDHSA_COV5), llvm::cl::desc("Set default AMDHSA Code Object Version (module flag " "or asm directive still take priority if present)"))

static constexpr ExpTgt	llvm::AMDGPU::Exp::ExpTgtInfo []

Macro Definition Documentation

◆ CASE_CI_VI [1/2]

#define CASE_CI_VI ( node )

Value:

assert(!isSI(STI)); \

case node: return isCI(STI) ? node##_ci : node##_vi;

assert

assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())

Definition at line 2360 of file AMDGPUBaseInfo.cpp.

◆ CASE_CI_VI [2/2]

#define CASE_CI_VI ( node ) case node##_ci: case node##_vi: return node;

Definition at line 2360 of file AMDGPUBaseInfo.cpp.

◆ CASE_GFXPRE11_GFX11PLUS [1/2]

#define CASE_GFXPRE11_GFX11PLUS ( node ) case node: return isGFX11Plus(STI) ? node##_gfx11plus : node##_gfxpre11;

Definition at line 2362 of file AMDGPUBaseInfo.cpp.

◆ CASE_GFXPRE11_GFX11PLUS [2/2]

#define CASE_GFXPRE11_GFX11PLUS ( node ) case node##_gfx11plus: case node##_gfxpre11: return node;

Definition at line 2362 of file AMDGPUBaseInfo.cpp.

◆ CASE_GFXPRE11_GFX11PLUS_TO [1/2]

#define CASE_GFXPRE11_GFX11PLUS_TO	(	node,
		result
	)	case node: return isGFX11Plus(STI) ? result##_gfx11plus : result##_gfxpre11;

Definition at line 2363 of file AMDGPUBaseInfo.cpp.

◆ CASE_GFXPRE11_GFX11PLUS_TO [2/2]

#define CASE_GFXPRE11_GFX11PLUS_TO	(	node,
		result
	)

Definition at line 2363 of file AMDGPUBaseInfo.cpp.

◆ CASE_VI_GFX9PLUS [1/2]

#define CASE_VI_GFX9PLUS ( node ) case node: return isGFX9Plus(STI) ? node##_gfx9plus : node##_vi;

Definition at line 2361 of file AMDGPUBaseInfo.cpp.

◆ CASE_VI_GFX9PLUS [2/2]

#define CASE_VI_GFX9PLUS ( node ) case node##_vi: case node##_gfx9plus: return node;

Definition at line 2361 of file AMDGPUBaseInfo.cpp.

◆ GET_FP4FP8DstByteSelTable_DECL

#define GET_FP4FP8DstByteSelTable_DECL

Definition at line 381 of file AMDGPUBaseInfo.cpp.

◆ GET_FP4FP8DstByteSelTable_IMPL

#define GET_FP4FP8DstByteSelTable_IMPL

Definition at line 382 of file AMDGPUBaseInfo.cpp.

◆ GET_getMFMA_F8F6F4_WithSize_DECL

#define GET_getMFMA_F8F6F4_WithSize_DECL

Definition at line 425 of file AMDGPUBaseInfo.cpp.

◆ GET_getMFMA_F8F6F4_WithSize_IMPL

#define GET_getMFMA_F8F6F4_WithSize_IMPL

Definition at line 426 of file AMDGPUBaseInfo.cpp.

◆ GET_Gfx10BufferFormat_IMPL

#define GET_Gfx10BufferFormat_IMPL

Definition at line 2968 of file AMDGPUBaseInfo.cpp.

◆ GET_Gfx11PlusBufferFormat_IMPL

#define GET_Gfx11PlusBufferFormat_IMPL

Definition at line 2969 of file AMDGPUBaseInfo.cpp.

◆ GET_Gfx9BufferFormat_IMPL

#define GET_Gfx9BufferFormat_IMPL

Definition at line 2967 of file AMDGPUBaseInfo.cpp.

◆ GET_INSTRINFO_NAMED_OPS

#define GET_INSTRINFO_NAMED_OPS

Definition at line 31 of file AMDGPUBaseInfo.cpp.

◆ GET_INSTRMAP_INFO

#define GET_INSTRMAP_INFO

Definition at line 32 of file AMDGPUBaseInfo.cpp.

◆ GET_isCvtScaleF32_F32F16ToF8F4Table_IMPL

#define GET_isCvtScaleF32_F32F16ToF8F4Table_IMPL

Definition at line 428 of file AMDGPUBaseInfo.cpp.

◆ GET_isMFMA_F8F6F4Table_IMPL

#define GET_isMFMA_F8F6F4Table_IMPL

Definition at line 427 of file AMDGPUBaseInfo.cpp.

◆ GET_MAIInstInfoTable_IMPL

#define GET_MAIInstInfoTable_IMPL

Definition at line 270 of file AMDGPUBaseInfo.cpp.

◆ GET_MIMGBaseOpcodesTable_IMPL

#define GET_MIMGBaseOpcodesTable_IMPL

Definition at line 262 of file AMDGPUBaseInfo.cpp.

◆ GET_MIMGBiasMappingTable_IMPL

#define GET_MIMGBiasMappingTable_IMPL

Definition at line 267 of file AMDGPUBaseInfo.cpp.

◆ GET_MIMGDimInfoTable_IMPL

#define GET_MIMGDimInfoTable_IMPL

Definition at line 263 of file AMDGPUBaseInfo.cpp.

◆ GET_MIMGG16MappingTable_IMPL

#define GET_MIMGG16MappingTable_IMPL

Definition at line 269 of file AMDGPUBaseInfo.cpp.

◆ GET_MIMGInfoTable_IMPL

#define GET_MIMGInfoTable_IMPL

Definition at line 264 of file AMDGPUBaseInfo.cpp.

◆ GET_MIMGLZMappingTable_IMPL

#define GET_MIMGLZMappingTable_IMPL

Definition at line 265 of file AMDGPUBaseInfo.cpp.

◆ GET_MIMGMIPMappingTable_IMPL

#define GET_MIMGMIPMappingTable_IMPL

Definition at line 266 of file AMDGPUBaseInfo.cpp.

◆ GET_MIMGOffsetMappingTable_IMPL

#define GET_MIMGOffsetMappingTable_IMPL

Definition at line 268 of file AMDGPUBaseInfo.cpp.

◆ GET_MTBUFInfoTable_DECL

#define GET_MTBUFInfoTable_DECL

Definition at line 395 of file AMDGPUBaseInfo.cpp.

◆ GET_MTBUFInfoTable_IMPL

#define GET_MTBUFInfoTable_IMPL

Definition at line 396 of file AMDGPUBaseInfo.cpp.

◆ GET_MUBUFInfoTable_DECL

#define GET_MUBUFInfoTable_DECL

Definition at line 397 of file AMDGPUBaseInfo.cpp.

◆ GET_MUBUFInfoTable_IMPL

#define GET_MUBUFInfoTable_IMPL

Definition at line 398 of file AMDGPUBaseInfo.cpp.

◆ GET_SMInfoTable_DECL

#define GET_SMInfoTable_DECL

Definition at line 399 of file AMDGPUBaseInfo.cpp.

◆ GET_SMInfoTable_IMPL

#define GET_SMInfoTable_IMPL

Definition at line 400 of file AMDGPUBaseInfo.cpp.

◆ GET_SourcesOfDivergence_IMPL

#define GET_SourcesOfDivergence_IMPL

Definition at line 2965 of file AMDGPUBaseInfo.cpp.

◆ GET_UniformIntrinsics_IMPL

#define GET_UniformIntrinsics_IMPL

Definition at line 2966 of file AMDGPUBaseInfo.cpp.

◆ GET_VOP1InfoTable_DECL

#define GET_VOP1InfoTable_DECL

Definition at line 401 of file AMDGPUBaseInfo.cpp.

◆ GET_VOP1InfoTable_IMPL

#define GET_VOP1InfoTable_IMPL

Definition at line 402 of file AMDGPUBaseInfo.cpp.

◆ GET_VOP2InfoTable_DECL

#define GET_VOP2InfoTable_DECL

Definition at line 403 of file AMDGPUBaseInfo.cpp.

◆ GET_VOP2InfoTable_IMPL

#define GET_VOP2InfoTable_IMPL

Definition at line 404 of file AMDGPUBaseInfo.cpp.

◆ GET_VOP3CAsmOnlyInfoTable_DECL

#define GET_VOP3CAsmOnlyInfoTable_DECL

Definition at line 413 of file AMDGPUBaseInfo.cpp.

◆ GET_VOP3CAsmOnlyInfoTable_IMPL

#define GET_VOP3CAsmOnlyInfoTable_IMPL

Definition at line 414 of file AMDGPUBaseInfo.cpp.

◆ GET_VOP3InfoTable_DECL

#define GET_VOP3InfoTable_DECL

Definition at line 405 of file AMDGPUBaseInfo.cpp.

◆ GET_VOP3InfoTable_IMPL

#define GET_VOP3InfoTable_IMPL

Definition at line 406 of file AMDGPUBaseInfo.cpp.

◆ GET_VOPC64DPP8Table_DECL

#define GET_VOPC64DPP8Table_DECL

Definition at line 409 of file AMDGPUBaseInfo.cpp.

◆ GET_VOPC64DPP8Table_IMPL

#define GET_VOPC64DPP8Table_IMPL

Definition at line 410 of file AMDGPUBaseInfo.cpp.

◆ GET_VOPC64DPPTable_DECL

#define GET_VOPC64DPPTable_DECL

Definition at line 407 of file AMDGPUBaseInfo.cpp.

◆ GET_VOPC64DPPTable_IMPL

#define GET_VOPC64DPPTable_IMPL

Definition at line 408 of file AMDGPUBaseInfo.cpp.

◆ GET_VOPCAsmOnlyInfoTable_DECL

#define GET_VOPCAsmOnlyInfoTable_DECL

Definition at line 411 of file AMDGPUBaseInfo.cpp.

◆ GET_VOPCAsmOnlyInfoTable_IMPL

#define GET_VOPCAsmOnlyInfoTable_IMPL

Definition at line 412 of file AMDGPUBaseInfo.cpp.

◆ GET_VOPDComponentTable_DECL

#define GET_VOPDComponentTable_DECL

Definition at line 415 of file AMDGPUBaseInfo.cpp.

◆ GET_VOPDComponentTable_IMPL

#define GET_VOPDComponentTable_IMPL

Definition at line 416 of file AMDGPUBaseInfo.cpp.

◆ GET_VOPDPairs_DECL

#define GET_VOPDPairs_DECL

Definition at line 417 of file AMDGPUBaseInfo.cpp.

◆ GET_VOPDPairs_IMPL

#define GET_VOPDPairs_IMPL

Definition at line 418 of file AMDGPUBaseInfo.cpp.

◆ GET_VOPTrue16Table_DECL

#define GET_VOPTrue16Table_DECL

Definition at line 419 of file AMDGPUBaseInfo.cpp.

◆ GET_VOPTrue16Table_IMPL

#define GET_VOPTrue16Table_IMPL

Definition at line 420 of file AMDGPUBaseInfo.cpp.

◆ GET_WMMAOpcode2AddrMappingTable_DECL

#define GET_WMMAOpcode2AddrMappingTable_DECL

Definition at line 421 of file AMDGPUBaseInfo.cpp.

◆ GET_WMMAOpcode2AddrMappingTable_IMPL

#define GET_WMMAOpcode2AddrMappingTable_IMPL

Definition at line 422 of file AMDGPUBaseInfo.cpp.

◆ GET_WMMAOpcode3AddrMappingTable_DECL

#define GET_WMMAOpcode3AddrMappingTable_DECL

Definition at line 423 of file AMDGPUBaseInfo.cpp.

◆ GET_WMMAOpcode3AddrMappingTable_IMPL

#define GET_WMMAOpcode3AddrMappingTable_IMPL

Definition at line 424 of file AMDGPUBaseInfo.cpp.

◆ MAP_REG2REG

#define MAP_REG2REG

Definition at line 2292 of file AMDGPUBaseInfo.cpp.

Variable Documentation

◆ DefaultAMDHSACodeObjectVersion

llvm::cl::opt< unsigned > DefaultAMDHSACodeObjectVersion("amdhsa-code-object-version", llvm::cl::Hidden, llvm::cl::init(llvm::AMDGPU::AMDHSA_COV5), llvm::cl::desc("Set default AMDHSA Code Object Version (module flag " "or asm directive still take priority if present)"))	(	"amdhsa-code-object-version"	,
		llvm::cl::Hidden	,
		llvm::cl::init(llvm::AMDGPU::AMDHSA_COV5)	,
		llvm::cl::desc("Set default AMDHSA Code Object Version (module flag " "or asm directive still take priority if present)")
	)

static

Referenced by llvm::AMDGPU::getDefaultAMDHSACodeObjectVersion().

◆ Intr

unsigned Intr

Definition at line 2956 of file AMDGPUBaseInfo.cpp.

Referenced by emitIntrinsicWithCC(), emitIntrinsicWithCCAndChain(), getBundleFromUse(), llvm::SITargetLowering::getTgtMemIntrinsic(), llvm::isPresplitCoroSuspendExitEdge(), llvm::AMDGPULegalizerInfo::legalizeImageIntrinsic(), packImage16bitOpsToDwords(), llvm::PPCTargetLowering::PerformDAGCombine(), promoteAllocaUserToVector(), requireAssignType(), llvm::salvageKnowledge(), llvm::AMDGPUInstructionSelector::select(), and simplifyInvariantGroupIntrinsic().

Classes

Namespaces

Macros

Functions

Variables