41#define DEBUG_TYPE "globalisel-utils"
44using namespace MIPatternMatch;
51 return MRI.createVirtualRegister(&RegClass);
63 assert(Reg.isVirtual() &&
"PhysReg not implemented");
69 auto *OldRegClass =
MRI.getRegClassOrNull(Reg);
73 if (ConstrainedReg != Reg) {
80 TII.get(TargetOpcode::COPY), ConstrainedReg)
85 TII.get(TargetOpcode::COPY), Reg)
89 Observer->changingInstr(*RegMO.
getParent());
91 RegMO.
setReg(ConstrainedReg);
93 Observer->changedInstr(*RegMO.
getParent());
95 }
else if (OldRegClass !=
MRI.getRegClassOrNull(Reg)) {
99 Observer->changedInstr(*RegDef);
101 Observer->changingAllUsesOfReg(
MRI, Reg);
102 Observer->finishedChangingAllUsesOfReg();
105 return ConstrainedReg;
115 assert(Reg.isVirtual() &&
"PhysReg not implemented");
128 if (
const auto *SubRC =
TRI.getCommonSubClass(
129 OpRC,
TRI.getConstrainedRegClassForOperand(RegMO,
MRI)))
132 OpRC =
TRI.getAllocatableClass(OpRC);
137 "Register class constraint is required unless either the "
138 "instruction is target independent or the operand is a use");
160 "A selected instruction is expected");
165 for (
unsigned OpI = 0, OpE =
I.getNumExplicitOperands(); OpI != OpE; ++OpI) {
173 assert(MO.
isReg() &&
"Unsupported non-reg operand");
177 if (Reg.isPhysical())
193 int DefIdx =
I.getDesc().getOperandConstraint(OpI,
MCOI::TIED_TO);
194 if (DefIdx != -1 && !
I.isRegTiedToUseOperand(DefIdx))
195 I.tieOperands(DefIdx, OpI);
207 if (
MRI.getType(DstReg) !=
MRI.getType(SrcReg))
211 const auto &DstRBC =
MRI.getRegClassOrRegBank(DstReg);
212 if (!DstRBC || DstRBC ==
MRI.getRegClassOrRegBank(SrcReg))
217 return DstRBC.is<
const RegisterBank *>() &&
MRI.getRegClassOrNull(SrcReg) &&
219 *
MRI.getRegClassOrNull(SrcReg));
229 if (
MI.getOpcode() == TargetOpcode::LOCAL_ESCAPE)
232 if (
MI.getOpcode() == TargetOpcode::LIFETIME_START ||
233 MI.getOpcode() == TargetOpcode::LIFETIME_END)
238 bool SawStore =
false;
239 if (!
MI.isSafeToMove(
nullptr, SawStore) && !
MI.isPHI())
243 for (
const auto &MO :
MI.all_defs()) {
245 if (Reg.isPhysical() || !
MRI.use_nodbg_empty(Reg))
256 bool IsFatal = Severity ==
DS_Error &&
260 if (!R.getLocation().isValid() || IsFatal)
261 R << (
" (in function: " + MF.
getName() +
")").str();
287 MI.getDebugLoc(),
MI.getParent());
299 assert((!ValAndVReg || ValAndVReg->VReg == VReg) &&
300 "Value found while looking through instrs");
303 return ValAndVReg->Value;
306std::optional<int64_t>
309 if (Val && Val->getBitWidth() <= 64)
310 return Val->getSExtValue();
328std::optional<ValueAndVReg>
330 bool LookThroughInstrs =
true,
331 bool LookThroughAnyExt =
false) {
335 while ((
MI =
MRI.getVRegDef(VReg)) && !IsConstantOpcode(
MI) &&
337 switch (
MI->getOpcode()) {
338 case TargetOpcode::G_ANYEXT:
339 if (!LookThroughAnyExt)
342 case TargetOpcode::G_TRUNC:
343 case TargetOpcode::G_SEXT:
344 case TargetOpcode::G_ZEXT:
347 MRI.getType(
MI->getOperand(0).getReg()).getSizeInBits()));
348 VReg =
MI->getOperand(1).getReg();
350 case TargetOpcode::COPY:
351 VReg =
MI->getOperand(1).getReg();
355 case TargetOpcode::G_INTTOPTR:
356 VReg =
MI->getOperand(1).getReg();
362 if (!
MI || !IsConstantOpcode(
MI))
366 if (!GetAPCstValue(
MI, Val))
368 for (
auto &Pair :
reverse(SeenOpcodes)) {
369 switch (Pair.first) {
370 case TargetOpcode::G_TRUNC:
371 Val = Val.
trunc(Pair.second);
373 case TargetOpcode::G_ANYEXT:
374 case TargetOpcode::G_SEXT:
375 Val = Val.
sext(Pair.second);
377 case TargetOpcode::G_ZEXT:
378 Val = Val.
zext(Pair.second);
389 return MI->getOpcode() == TargetOpcode::G_CONSTANT;
395 return MI->getOpcode() == TargetOpcode::G_FCONSTANT;
401 unsigned Opc =
MI->getOpcode();
402 return Opc == TargetOpcode::G_CONSTANT || Opc == TargetOpcode::G_FCONSTANT;
428 return getConstantVRegValWithLookThrough<isIConstant, getCImmAsAPInt>(
429 VReg,
MRI, LookThroughInstrs);
434 bool LookThroughAnyExt) {
435 return getConstantVRegValWithLookThrough<isAnyConstant,
436 getCImmOrFPImmAsAPInt>(
437 VReg,
MRI, LookThroughInstrs, LookThroughAnyExt);
443 getConstantVRegValWithLookThrough<isFConstant, getCImmOrFPImmAsAPInt>(
444 VReg,
MRI, LookThroughInstrs);
454 if (TargetOpcode::G_FCONSTANT !=
MI->getOpcode())
456 return MI->getOperand(1).getFPImm();
459std::optional<DefinitionAndSourceRegister>
464 if (!DstTy.isValid())
469 auto SrcTy =
MRI.getType(SrcReg);
470 if (!SrcTy.isValid())
481 std::optional<DefinitionAndSourceRegister> DefSrcReg =
483 return DefSrcReg ? DefSrcReg->MI :
nullptr;
488 std::optional<DefinitionAndSourceRegister> DefSrcReg =
490 return DefSrcReg ? DefSrcReg->Reg :
Register();
497 for (
int i = 0; i < NumParts; ++i)
511 unsigned NumParts =
RegSize / MainSize;
512 unsigned LeftoverSize =
RegSize - NumParts * MainSize;
515 if (LeftoverSize == 0) {
516 for (
unsigned I = 0;
I < NumParts; ++
I)
517 VRegs.
push_back(
MRI.createGenericVirtualRegister(MainTy));
530 unsigned LeftoverNumElts = RegNumElts % MainNumElts;
532 if (MainNumElts % LeftoverNumElts == 0 &&
533 RegNumElts % LeftoverNumElts == 0 &&
535 LeftoverNumElts > 1) {
541 extractParts(Reg, LeftoverTy, RegNumElts / LeftoverNumElts, UnmergeValues,
545 unsigned LeftoverPerMain = MainNumElts / LeftoverNumElts;
546 unsigned NumOfLeftoverVal =
547 ((RegNumElts % MainNumElts) / LeftoverNumElts);
551 for (
unsigned I = 0;
I < UnmergeValues.
size() - NumOfLeftoverVal;
I++) {
553 if (MergeValues.
size() == LeftoverPerMain) {
560 for (
unsigned I = UnmergeValues.
size() - NumOfLeftoverVal;
561 I < UnmergeValues.
size();
I++) {
572 for (
unsigned i = 0; i < RegPieces.
size() - 1; ++i)
575 LeftoverTy =
MRI.getType(LeftoverRegs[0]);
581 for (
unsigned I = 0;
I != NumParts; ++
I) {
582 Register NewReg =
MRI.createGenericVirtualRegister(MainTy);
589 Register NewReg =
MRI.createGenericVirtualRegister(LeftoverTy);
601 LLT RegTy =
MRI.getType(Reg);
607 unsigned LeftoverNumElts = RegNumElts % NumElts;
608 unsigned NumNarrowTyPieces = RegNumElts / NumElts;
611 if (LeftoverNumElts == 0)
612 return extractParts(Reg, NarrowTy, NumNarrowTyPieces, VRegs, MIRBuilder,
623 for (
unsigned i = 0; i < NumNarrowTyPieces; ++i,
Offset += NumElts) {
629 if (LeftoverNumElts == 1) {
654 APF.
convert(APFloat::IEEEhalf(), APFloat::rmNearestTiesToEven, &Ignored);
670 const APInt &C1 = MaybeOp1Cst->Value;
671 const APInt &C2 = MaybeOp2Cst->Value;
675 case TargetOpcode::G_ADD:
677 case TargetOpcode::G_PTR_ADD:
681 case TargetOpcode::G_AND:
683 case TargetOpcode::G_ASHR:
685 case TargetOpcode::G_LSHR:
687 case TargetOpcode::G_MUL:
689 case TargetOpcode::G_OR:
691 case TargetOpcode::G_SHL:
693 case TargetOpcode::G_SUB:
695 case TargetOpcode::G_XOR:
697 case TargetOpcode::G_UDIV:
698 if (!C2.getBoolValue())
701 case TargetOpcode::G_SDIV:
702 if (!C2.getBoolValue())
705 case TargetOpcode::G_UREM:
706 if (!C2.getBoolValue())
709 case TargetOpcode::G_SREM:
710 if (!C2.getBoolValue())
713 case TargetOpcode::G_SMIN:
715 case TargetOpcode::G_SMAX:
717 case TargetOpcode::G_UMIN:
719 case TargetOpcode::G_UMAX:
726std::optional<APFloat>
740 case TargetOpcode::G_FADD:
741 C1.
add(C2, APFloat::rmNearestTiesToEven);
743 case TargetOpcode::G_FSUB:
744 C1.
subtract(C2, APFloat::rmNearestTiesToEven);
746 case TargetOpcode::G_FMUL:
747 C1.
multiply(C2, APFloat::rmNearestTiesToEven);
749 case TargetOpcode::G_FDIV:
750 C1.
divide(C2, APFloat::rmNearestTiesToEven);
752 case TargetOpcode::G_FREM:
755 case TargetOpcode::G_FCOPYSIGN:
758 case TargetOpcode::G_FMINNUM:
760 case TargetOpcode::G_FMAXNUM:
762 case TargetOpcode::G_FMINIMUM:
764 case TargetOpcode::G_FMAXIMUM:
766 case TargetOpcode::G_FMINNUM_IEEE:
767 case TargetOpcode::G_FMAXNUM_IEEE:
784 auto *SrcVec2 = getOpcodeDef<GBuildVector>(Op2,
MRI);
788 auto *SrcVec1 = getOpcodeDef<GBuildVector>(Op1,
MRI);
793 for (
unsigned Idx = 0, E = SrcVec1->getNumSources();
Idx < E; ++
Idx) {
795 SrcVec2->getSourceReg(
Idx),
MRI);
800 return FoldedElements;
815 return !FPVal->getValueAPF().isNaN() ||
816 (SNaN && !FPVal->getValueAPF().isSignaling());
829 case TargetOpcode::G_FADD:
830 case TargetOpcode::G_FSUB:
831 case TargetOpcode::G_FMUL:
832 case TargetOpcode::G_FDIV:
833 case TargetOpcode::G_FREM:
834 case TargetOpcode::G_FSIN:
835 case TargetOpcode::G_FCOS:
836 case TargetOpcode::G_FTAN:
837 case TargetOpcode::G_FACOS:
838 case TargetOpcode::G_FASIN:
839 case TargetOpcode::G_FATAN:
840 case TargetOpcode::G_FCOSH:
841 case TargetOpcode::G_FSINH:
842 case TargetOpcode::G_FTANH:
843 case TargetOpcode::G_FMA:
844 case TargetOpcode::G_FMAD:
850 case TargetOpcode::G_FMINNUM_IEEE:
851 case TargetOpcode::G_FMAXNUM_IEEE: {
861 case TargetOpcode::G_FMINNUM:
862 case TargetOpcode::G_FMAXNUM: {
874 case TargetOpcode::G_FPEXT:
875 case TargetOpcode::G_FPTRUNC:
876 case TargetOpcode::G_FCANONICALIZE:
888 auto PSV = dyn_cast_if_present<const PseudoSourceValue *>(MPO.
V);
889 if (
auto FSPV = dyn_cast_or_null<FixedStackPseudoSourceValue>(PSV)) {
895 if (
const Value *V = dyn_cast_if_present<const Value *>(MPO.
V)) {
897 return V->getPointerAlignment(M->getDataLayout());
915 assert(Def->getParent() == &EntryMBB &&
"live-in copy not in entry block");
926 MRI.setType(LiveIn, RegTy);
944 case TargetOpcode::G_SEXT_INREG: {
945 LLT Ty =
MRI.getType(Op1);
963 case TargetOpcode::G_SEXT:
964 return Val->sext(DstSize);
965 case TargetOpcode::G_ZEXT:
966 case TargetOpcode::G_ANYEXT:
968 return Val->zext(DstSize);
976std::optional<APFloat>
979 assert(Opcode == TargetOpcode::G_SITOFP || Opcode == TargetOpcode::G_UITOFP);
983 APFloat::rmNearestTiesToEven);
989std::optional<SmallVector<unsigned>>
991 std::function<
unsigned(
APInt)> CB) {
992 LLT Ty =
MRI.getType(Src);
994 auto tryFoldScalar = [&](
Register R) -> std::optional<unsigned> {
998 return CB(*MaybeCst);
1002 auto *BV = getOpcodeDef<GBuildVector>(Src,
MRI);
1004 return std::nullopt;
1005 for (
unsigned SrcIdx = 0; SrcIdx < BV->getNumSources(); ++SrcIdx) {
1006 if (
auto MaybeFold = tryFoldScalar(BV->getSourceReg(SrcIdx))) {
1010 return std::nullopt;
1014 if (
auto MaybeCst = tryFoldScalar(Src)) {
1018 return std::nullopt;
1021std::optional<SmallVector<APInt>>
1024 LLT Ty =
MRI.getType(Op1);
1025 if (Ty !=
MRI.getType(Op2))
1026 return std::nullopt;
1032 if (!LHSCst || !RHSCst)
1033 return std::nullopt;
1036 case CmpInst::Predicate::ICMP_EQ:
1037 return APInt(1, LHSCst->eq(*RHSCst));
1038 case CmpInst::Predicate::ICMP_NE:
1039 return APInt(1, LHSCst->ne(*RHSCst));
1040 case CmpInst::Predicate::ICMP_UGT:
1041 return APInt(1, LHSCst->ugt(*RHSCst));
1042 case CmpInst::Predicate::ICMP_UGE:
1043 return APInt(1, LHSCst->uge(*RHSCst));
1044 case CmpInst::Predicate::ICMP_ULT:
1045 return APInt(1, LHSCst->ult(*RHSCst));
1046 case CmpInst::Predicate::ICMP_ULE:
1047 return APInt(1, LHSCst->ule(*RHSCst));
1048 case CmpInst::Predicate::ICMP_SGT:
1049 return APInt(1, LHSCst->sgt(*RHSCst));
1050 case CmpInst::Predicate::ICMP_SGE:
1051 return APInt(1, LHSCst->sge(*RHSCst));
1052 case CmpInst::Predicate::ICMP_SLT:
1053 return APInt(1, LHSCst->slt(*RHSCst));
1054 case CmpInst::Predicate::ICMP_SLE:
1055 return APInt(1, LHSCst->sle(*RHSCst));
1057 return std::nullopt;
1065 auto *BV1 = getOpcodeDef<GBuildVector>(Op1,
MRI);
1066 auto *BV2 = getOpcodeDef<GBuildVector>(Op2,
MRI);
1068 return std::nullopt;
1069 assert(BV1->getNumSources() == BV2->getNumSources() &&
"Invalid vectors");
1070 for (
unsigned I = 0;
I < BV1->getNumSources(); ++
I) {
1071 if (
auto MaybeFold =
1072 TryFoldScalar(BV1->getSourceReg(
I), BV2->getSourceReg(
I))) {
1076 return std::nullopt;
1081 if (
auto MaybeCst = TryFoldScalar(Op1, Op2)) {
1086 return std::nullopt;
1091 std::optional<DefinitionAndSourceRegister> DefSrcReg =
1097 const LLT Ty =
MRI.getType(Reg);
1099 switch (
MI.getOpcode()) {
1100 case TargetOpcode::G_CONSTANT: {
1105 case TargetOpcode::G_SHL: {
1117 case TargetOpcode::G_LSHR: {
1119 if (ConstLHS->isSignMask())
1125 case TargetOpcode::G_BUILD_VECTOR: {
1134 case TargetOpcode::G_BUILD_VECTOR_TRUNC: {
1140 if (!Const || !Const->zextOrTrunc(
BitWidth).isPowerOf2())
1181 "getLCMType not implemented between fixed and scalable vectors.");
1201 LLT VecTy = OrigTy.
isVector() ? OrigTy : TargetTy;
1202 LLT ScalarTy = OrigTy.
isVector() ? TargetTy : OrigTy;
1237 "getCoverTy not implemented between fixed and scalable vectors.");
1245 if (OrigTyNumElts % TargetTyNumElts == 0)
1248 unsigned NumElts =
alignTo(OrigTyNumElts, TargetTyNumElts);
1268 "getGCDType not implemented between fixed and scalable vectors.");
1308 assert(
MI.getOpcode() == TargetOpcode::G_SHUFFLE_VECTOR &&
1309 "Only G_SHUFFLE_VECTOR can have a splat index!");
1311 auto FirstDefinedIdx =
find_if(Mask, [](
int Elt) {
return Elt >= 0; });
1315 if (FirstDefinedIdx == Mask.end())
1320 int SplatValue = *FirstDefinedIdx;
1322 [&SplatValue](
int Elt) { return Elt >= 0 && Elt != SplatValue; }))
1323 return std::nullopt;
1329 return Opcode == TargetOpcode::G_BUILD_VECTOR ||
1330 Opcode == TargetOpcode::G_BUILD_VECTOR_TRUNC;
1335std::optional<ValueAndVReg> getAnyConstantSplat(
Register VReg,
1340 return std::nullopt;
1342 bool isConcatVectorsOp =
MI->getOpcode() == TargetOpcode::G_CONCAT_VECTORS;
1344 return std::nullopt;
1346 std::optional<ValueAndVReg> SplatValAndReg;
1351 auto ElementValAndReg =
1353 ? getAnyConstantSplat(Element,
MRI, AllowUndef)
1357 if (!ElementValAndReg) {
1358 if (AllowUndef && isa<GImplicitDef>(
MRI.getVRegDef(Element)))
1360 return std::nullopt;
1364 if (!SplatValAndReg)
1365 SplatValAndReg = ElementValAndReg;
1368 if (SplatValAndReg->Value != ElementValAndReg->Value)
1369 return std::nullopt;
1372 return SplatValAndReg;
1379 int64_t SplatValue,
bool AllowUndef) {
1380 if (
auto SplatValAndReg = getAnyConstantSplat(Reg,
MRI, AllowUndef))
1387 int64_t SplatValue,
bool AllowUndef) {
1394 if (
auto SplatValAndReg =
1395 getAnyConstantSplat(Reg,
MRI,
false)) {
1396 if (std::optional<ValueAndVReg> ValAndVReg =
1398 return ValAndVReg->Value;
1401 return std::nullopt;
1410std::optional<int64_t>
1413 if (
auto SplatValAndReg =
1414 getAnyConstantSplat(Reg,
MRI,
false))
1416 return std::nullopt;
1419std::optional<int64_t>
1425std::optional<FPValueAndVReg>
1428 if (
auto SplatValAndReg = getAnyConstantSplat(VReg,
MRI, AllowUndef))
1430 return std::nullopt;
1445std::optional<RegOrConstant>
1447 unsigned Opc =
MI.getOpcode();
1449 return std::nullopt;
1452 auto Reg =
MI.getOperand(1).getReg();
1455 return std::nullopt;
1461 bool AllowFP =
true,
1462 bool AllowOpaqueConstants =
true) {
1463 switch (
MI.getOpcode()) {
1464 case TargetOpcode::G_CONSTANT:
1465 case TargetOpcode::G_IMPLICIT_DEF:
1467 case TargetOpcode::G_FCONSTANT:
1469 case TargetOpcode::G_GLOBAL_VALUE:
1470 case TargetOpcode::G_FRAME_INDEX:
1471 case TargetOpcode::G_BLOCK_ADDR:
1472 case TargetOpcode::G_JUMP_TABLE:
1473 return AllowOpaqueConstants;
1487 for (
unsigned SrcIdx = 0; SrcIdx < BV->
getNumSources(); ++SrcIdx) {
1498 bool AllowFP,
bool AllowOpaqueConstants) {
1505 const unsigned NumOps =
MI.getNumOperands();
1506 for (
unsigned I = 1;
I != NumOps; ++
I) {
1523 return std::nullopt;
1524 const unsigned ScalarSize =
MRI.getType(Def).getScalarSizeInBits();
1525 return APInt(ScalarSize, *MaybeCst,
true);
1530 switch (
MI.getOpcode()) {
1531 case TargetOpcode::G_IMPLICIT_DEF:
1533 case TargetOpcode::G_CONSTANT:
1534 return MI.getOperand(1).getCImm()->isNullValue();
1535 case TargetOpcode::G_FCONSTANT: {
1549 switch (
MI.getOpcode()) {
1550 case TargetOpcode::G_IMPLICIT_DEF:
1552 case TargetOpcode::G_CONSTANT:
1553 return MI.getOperand(1).getCImm()->isAllOnesValue();
1563 std::function<
bool(
const Constant *ConstVal)>
Match,
bool AllowUndefs) {
1566 if (AllowUndefs && Def->getOpcode() == TargetOpcode::G_IMPLICIT_DEF)
1567 return Match(
nullptr);
1570 if (Def->getOpcode() == TargetOpcode::G_CONSTANT)
1571 return Match(Def->getOperand(1).getCImm());
1573 if (Def->getOpcode() != TargetOpcode::G_BUILD_VECTOR)
1576 for (
unsigned I = 1, E = Def->getNumOperands();
I != E; ++
I) {
1577 Register SrcElt = Def->getOperand(
I).getReg();
1579 if (AllowUndefs && SrcDef->
getOpcode() == TargetOpcode::G_IMPLICIT_DEF) {
1580 if (!
Match(
nullptr))
1585 if (SrcDef->
getOpcode() != TargetOpcode::G_CONSTANT ||
1596 case TargetLowering::UndefinedBooleanContent:
1598 case TargetLowering::ZeroOrOneBooleanContent:
1600 case TargetLowering::ZeroOrNegativeOneBooleanContent:
1607 bool IsVector,
bool IsFP) {
1609 case TargetLowering::UndefinedBooleanContent:
1611 case TargetLowering::ZeroOrOneBooleanContent:
1612 case TargetLowering::ZeroOrNegativeOneBooleanContent:
1621 case TargetLowering::UndefinedBooleanContent:
1622 case TargetLowering::ZeroOrOneBooleanContent:
1624 case TargetLowering::ZeroOrNegativeOneBooleanContent:
1633 return F.hasOptSize() ||
F.hasMinSize() ||
1641 if (
Op.isReg() &&
Op.getReg().isVirtual())
1642 DeadInstChain.
insert(
MRI.getVRegDef(
Op.getReg()));
1646 MI.eraseFromParent();
1658 while (!DeadInstChain.
empty()) {
1672 for (
auto &Def :
MI.defs()) {
1673 assert(Def.isReg() &&
"Must be a reg");
1676 for (
auto &MOUse :
MRI.use_operands(Def.getReg())) {
1684 if (!DbgUsers.
empty()) {
1692 case TargetOpcode::G_FABS:
1693 case TargetOpcode::G_FADD:
1694 case TargetOpcode::G_FCANONICALIZE:
1695 case TargetOpcode::G_FCEIL:
1696 case TargetOpcode::G_FCONSTANT:
1697 case TargetOpcode::G_FCOPYSIGN:
1698 case TargetOpcode::G_FCOS:
1699 case TargetOpcode::G_FDIV:
1700 case TargetOpcode::G_FEXP2:
1701 case TargetOpcode::G_FEXP:
1702 case TargetOpcode::G_FFLOOR:
1703 case TargetOpcode::G_FLOG10:
1704 case TargetOpcode::G_FLOG2:
1705 case TargetOpcode::G_FLOG:
1706 case TargetOpcode::G_FMA:
1707 case TargetOpcode::G_FMAD:
1708 case TargetOpcode::G_FMAXIMUM:
1709 case TargetOpcode::G_FMAXNUM:
1710 case TargetOpcode::G_FMAXNUM_IEEE:
1711 case TargetOpcode::G_FMINIMUM:
1712 case TargetOpcode::G_FMINNUM:
1713 case TargetOpcode::G_FMINNUM_IEEE:
1714 case TargetOpcode::G_FMUL:
1715 case TargetOpcode::G_FNEARBYINT:
1716 case TargetOpcode::G_FNEG:
1717 case TargetOpcode::G_FPEXT:
1718 case TargetOpcode::G_FPOW:
1719 case TargetOpcode::G_FPTRUNC:
1720 case TargetOpcode::G_FREM:
1721 case TargetOpcode::G_FRINT:
1722 case TargetOpcode::G_FSIN:
1723 case TargetOpcode::G_FTAN:
1724 case TargetOpcode::G_FACOS:
1725 case TargetOpcode::G_FASIN:
1726 case TargetOpcode::G_FATAN:
1727 case TargetOpcode::G_FCOSH:
1728 case TargetOpcode::G_FSINH:
1729 case TargetOpcode::G_FTANH:
1730 case TargetOpcode::G_FSQRT:
1731 case TargetOpcode::G_FSUB:
1732 case TargetOpcode::G_INTRINSIC_ROUND:
1733 case TargetOpcode::G_INTRINSIC_ROUNDEVEN:
1734 case TargetOpcode::G_INTRINSIC_TRUNC:
1744 LLT Ty =
MRI.getType(ShiftAmount);
1750 std::optional<ValueAndVReg> Val =
1762 for (
unsigned I = 0;
I < Sources; ++
I) {
1763 std::optional<ValueAndVReg> Val =
1791 bool ConsiderFlagsAndMetadata,
1796 if (
auto *GMI = dyn_cast<GenericMachineInstr>(RegDef))
1797 if (GMI->hasPoisonGeneratingFlags())
1802 case TargetOpcode::G_BUILD_VECTOR:
1803 case TargetOpcode::G_CONSTANT_FOLD_BARRIER:
1805 case TargetOpcode::G_SHL:
1806 case TargetOpcode::G_ASHR:
1807 case TargetOpcode::G_LSHR:
1810 case TargetOpcode::G_FPTOSI:
1811 case TargetOpcode::G_FPTOUI:
1815 case TargetOpcode::G_CTLZ:
1816 case TargetOpcode::G_CTTZ:
1817 case TargetOpcode::G_ABS:
1818 case TargetOpcode::G_CTPOP:
1819 case TargetOpcode::G_BSWAP:
1820 case TargetOpcode::G_BITREVERSE:
1821 case TargetOpcode::G_FSHL:
1822 case TargetOpcode::G_FSHR:
1823 case TargetOpcode::G_SMAX:
1824 case TargetOpcode::G_SMIN:
1825 case TargetOpcode::G_UMAX:
1826 case TargetOpcode::G_UMIN:
1827 case TargetOpcode::G_PTRMASK:
1828 case TargetOpcode::G_SADDO:
1829 case TargetOpcode::G_SSUBO:
1830 case TargetOpcode::G_UADDO:
1831 case TargetOpcode::G_USUBO:
1832 case TargetOpcode::G_SMULO:
1833 case TargetOpcode::G_UMULO:
1834 case TargetOpcode::G_SADDSAT:
1835 case TargetOpcode::G_UADDSAT:
1836 case TargetOpcode::G_SSUBSAT:
1837 case TargetOpcode::G_USUBSAT:
1839 case TargetOpcode::G_SSHLSAT:
1840 case TargetOpcode::G_USHLSAT:
1843 case TargetOpcode::G_INSERT_VECTOR_ELT: {
1846 std::optional<ValueAndVReg>
Index =
1850 LLT VecTy =
MRI.getType(Insert->getVectorReg());
1855 case TargetOpcode::G_EXTRACT_VECTOR_ELT: {
1858 std::optional<ValueAndVReg>
Index =
1867 case TargetOpcode::G_SHUFFLE_VECTOR: {
1872 case TargetOpcode::G_FNEG:
1873 case TargetOpcode::G_PHI:
1874 case TargetOpcode::G_SELECT:
1875 case TargetOpcode::G_UREM:
1876 case TargetOpcode::G_SREM:
1877 case TargetOpcode::G_FREEZE:
1878 case TargetOpcode::G_ICMP:
1879 case TargetOpcode::G_FCMP:
1880 case TargetOpcode::G_FADD:
1881 case TargetOpcode::G_FSUB:
1882 case TargetOpcode::G_FMUL:
1883 case TargetOpcode::G_FDIV:
1884 case TargetOpcode::G_FREM:
1885 case TargetOpcode::G_PTR_ADD:
1888 return !isa<GCastOp>(RegDef) && !isa<GBinOp>(RegDef);
1902 case TargetOpcode::G_FREEZE:
1904 case TargetOpcode::G_IMPLICIT_DEF:
1906 case TargetOpcode::G_CONSTANT:
1907 case TargetOpcode::G_FCONSTANT:
1909 case TargetOpcode::G_BUILD_VECTOR: {
1912 for (
unsigned I = 0;
I < NumSources; ++
I)
1918 case TargetOpcode::G_PHI: {
1919 GPhi *Phi = cast<GPhi>(RegDef);
1920 unsigned NumIncoming = Phi->getNumIncomingValues();
1921 for (
unsigned I = 0;
I < NumIncoming; ++
I)
1931 return ::isGuaranteedNotToBeUndefOrPoison(MO.getReg(),
MRI,
Depth + 1,
1942 bool ConsiderFlagsAndMetadata) {
1943 return ::canCreateUndefOrPoison(Reg,
MRI, ConsiderFlagsAndMetadata,
1948 bool ConsiderFlagsAndMetadata =
true) {
1949 return ::canCreateUndefOrPoison(Reg,
MRI, ConsiderFlagsAndMetadata,
1956 return ::isGuaranteedNotToBeUndefOrPoison(Reg,
MRI,
Depth,
1963 return ::isGuaranteedNotToBeUndefOrPoison(Reg,
MRI,
Depth,
1970 return ::isGuaranteedNotToBeUndefOrPoison(Reg,
MRI,
Depth,
unsigned const MachineRegisterInfo * MRI
MachineInstrBuilder MachineInstrBuilder & DefMI
This file declares a class to represent arbitrary precision floating point values and provide a varie...
This file implements a class to represent arbitrary precision integral constant values and operations...
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
static bool canCreateUndefOrPoison(Register Reg, const MachineRegisterInfo &MRI, bool ConsiderFlagsAndMetadata, UndefPoisonKind Kind)
static bool isGuaranteedNotToBeUndefOrPoison(Register Reg, const MachineRegisterInfo &MRI, unsigned Depth, UndefPoisonKind Kind)
static bool includesPoison(UndefPoisonKind Kind)
static bool includesUndef(UndefPoisonKind Kind)
static void reportGISelDiagnostic(DiagnosticSeverity Severity, MachineFunction &MF, const TargetPassConfig &TPC, MachineOptimizationRemarkEmitter &MORE, MachineOptimizationRemarkMissed &R)
static bool shiftAmountKnownInRange(Register ShiftAmount, const MachineRegisterInfo &MRI)
Shifts return poison if shiftwidth is larger than the bitwidth.
bool canCreatePoison(Register Reg, const MachineRegisterInfo &MRI, bool ConsiderFlagsAndMetadata=true)
static bool isBuildVectorOp(unsigned Opcode)
static bool isConstantScalar(const MachineInstr &MI, const MachineRegisterInfo &MRI, bool AllowFP=true, bool AllowOpaqueConstants=true)
This file contains the declarations for the subclasses of Constant, which represent the different fla...
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
This contains common code to allow clients to notify changes to machine instr.
Provides analysis for querying information about KnownBits during GISel passes.
Declares convenience wrapper classes for interpreting MachineInstr instances as specific generic oper...
const HexagonInstrInfo * TII
Tracks DebugLocs between checkpoints and verifies that they are transferred.
Contains matchers for matching SSA Machine Instructions.
This file declares the MachineIRBuilder class.
unsigned const TargetRegisterInfo * TRI
uint64_t IntrinsicInst * II
const char LLVMTargetMachineRef TM
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file describes how to lower LLVM code to machine code.
Target-Independent Code Generator Pass Configuration Options pass.
static const char PassName[]
Class recording the (high level) value of a variable.
opStatus divide(const APFloat &RHS, roundingMode RM)
void copySign(const APFloat &RHS)
opStatus convert(const fltSemantics &ToSemantics, roundingMode RM, bool *losesInfo)
opStatus subtract(const APFloat &RHS, roundingMode RM)
opStatus add(const APFloat &RHS, roundingMode RM)
opStatus convertFromAPInt(const APInt &Input, bool IsSigned, roundingMode RM)
opStatus multiply(const APFloat &RHS, roundingMode RM)
APInt bitcastToAPInt() const
opStatus mod(const APFloat &RHS)
Class for arbitrary precision integers.
APInt udiv(const APInt &RHS) const
Unsigned division operation.
APInt zext(unsigned width) const
Zero extend to a new width.
APInt zextOrTrunc(unsigned width) const
Zero extend or truncate to width.
APInt trunc(unsigned width) const
Truncate to new width.
APInt urem(const APInt &RHS) const
Unsigned remainder operation.
unsigned getBitWidth() const
Return the number of bits in the APInt.
APInt sdiv(const APInt &RHS) const
Signed division function for APInt.
APInt sextOrTrunc(unsigned width) const
Sign extend or truncate to width.
APInt ashr(unsigned ShiftAmt) const
Arithmetic right-shift function.
APInt srem(const APInt &RHS) const
Function for signed remainder operation.
APInt sext(unsigned width) const
Sign extend to a new width.
bool isPowerOf2() const
Check if this APInt's value is a power of two greater than zero.
APInt lshr(unsigned shiftAmt) const
Logical right-shift function.
Represent the analysis usage information of a pass.
AnalysisUsage & addPreserved()
Add the specified Pass class to the set of analyses preserved by this pass.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
BlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate IR basic block frequen...
ConstantFP - Floating Point Values [float, double].
const APFloat & getValueAPF() const
bool isNegative() const
Return true if the sign bit is set.
bool isZero() const
Return true if the value is positive or negative zero.
This is the shared class of boolean and integer constants.
const APInt & getValue() const
Return the constant as an APInt value reference.
This is an important base class in LLVM.
This class represents an Operation in the Expression.
static constexpr ElementCount getFixed(ScalarTy MinVal)
static constexpr ElementCount get(ScalarTy MinVal, bool Scalable)
Represents a G_BUILD_VECTOR.
Abstract class that contains various methods for clients to notify about changes.
KnownBits getKnownBits(Register R)
void insert(MachineInstr *I)
Add the specified instruction to the worklist if it isn't already in it.
MachineInstr * pop_back_val()
void remove(const MachineInstr *I)
Remove I from the worklist if it exists.
Represents an insert vector element.
Register getSourceReg(unsigned I) const
Returns the I'th source register.
unsigned getNumSources() const
Returns the number of source registers.
Represents a G_SHUFFLE_VECTOR.
ArrayRef< int > getMask() const
Module * getParent()
Get the module that this global value is contained inside of...
static IntegerType * get(LLVMContext &C, unsigned NumBits)
This static method is the primary way of constructing an IntegerType.
constexpr bool isScalableVector() const
Returns true if the LLT is a scalable vector.
constexpr unsigned getScalarSizeInBits() const
constexpr bool isScalar() const
static constexpr LLT vector(ElementCount EC, unsigned ScalarSizeInBits)
Get a low-level vector of some number of elements and element width.
static constexpr LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
constexpr bool isValid() const
constexpr uint16_t getNumElements() const
Returns the number of elements in a vector LLT.
constexpr bool isVector() const
constexpr bool isScalable() const
Returns true if the LLT is a scalable vector.
constexpr TypeSize getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
constexpr LLT getElementType() const
Returns the vector's element type. Only valid for vector types.
constexpr ElementCount getElementCount() const
static constexpr LLT fixed_vector(unsigned NumElements, unsigned ScalarSizeInBits)
Get a low-level fixed-width vector of some number of elements and element width.
constexpr bool isFixedVector() const
Returns true if the LLT is a fixed vector.
constexpr LLT getScalarType() const
static constexpr LLT scalarOrVector(ElementCount EC, LLT ScalarTy)
This is an important class for using LLVM in a threaded context.
void checkpoint(bool CheckDebugLocs=true)
Call this to indicate that it's a good point to assess whether locations have been lost.
Describe properties that are true of each instruction in the target description file.
Wrapper class representing physical registers. Should be passed by value.
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
bool isLiveIn(MCPhysReg Reg, LaneBitmask LaneMask=LaneBitmask::getAll()) const
Return true if the specified register is in the live in set.
void addLiveIn(MCRegister PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Align getObjectAlign(int ObjectIdx) const
Return the alignment of the specified stack object.
MachineFunctionProperties & set(Property P)
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
GISelChangeObserver * getObserver() const
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Function & getFunction()
Return the LLVM function that this machine code represents.
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
const MachineFunctionProperties & getProperties() const
Get the function properties.
const MachineBasicBlock & front() const
Register addLiveIn(MCRegister PReg, const TargetRegisterClass *RC)
addLiveIn - Add the specified physical register as a live-in value and create a corresponding virtual...
Helper class to build MachineInstr.
MachineInstrBuilder buildUnmerge(ArrayRef< LLT > Res, const SrcOp &Op)
Build and insert Res0, ... = G_UNMERGE_VALUES Op.
MachineInstrBuilder buildExtract(const DstOp &Res, const SrcOp &Src, uint64_t Index)
Build and insert Res0, ... = G_EXTRACT Src, Idx0.
MachineInstrBuilder buildMergeLikeInstr(const DstOp &Res, ArrayRef< Register > Ops)
Build and insert Res = G_MERGE_VALUES Op0, ... or Res = G_BUILD_VECTOR Op0, ... or Res = G_CONCAT_VEC...
Register getReg(unsigned Idx) const
Get the register for the operand index.
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Representation of each machine instruction.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
const MachineBasicBlock * getParent() const
bool getFlag(MIFlag Flag) const
Return whether an MI flag is set.
iterator_range< mop_iterator > uses()
Returns a range that includes all operands that are register uses.
const MachineFunction * getMF() const
Return the function that contains the basic block that this instruction belongs to.
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
const MachineOperand & getOperand(unsigned i) const
MachineOperand class - Representation of each machine instruction operand.
const ConstantInt * getCImm() const
bool isCImm() const
isCImm - Test if this is a MO_CImmediate operand.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
void setReg(Register Reg)
Change the register this operand corresponds to.
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
Register getReg() const
getReg - Returns the register number.
const ConstantFP * getFPImm() const
bool isFPImm() const
isFPImm - Tests if this is a MO_FPImmediate operand.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
A Module instance is used to store all the information related to an LLVM module.
Analysis providing profile information.
Represents a value which can be a Register or a constant.
Holds all the information related to register banks.
static const TargetRegisterClass * constrainGenericRegister(Register Reg, const TargetRegisterClass &RC, MachineRegisterInfo &MRI)
Constrain the (possibly generic) virtual register Reg to RC.
This class implements the register bank concept.
Wrapper class representing virtual and physical registers.
constexpr bool isPhysical() const
Return true if the specified register number is in the physical register namespace.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
reference emplace_back(ArgTypes &&... Args)
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
StringRef - Represent a constant reference to a string, i.e.
TargetInstrInfo - Interface to description of machine instruction set.
BooleanContent getBooleanContents(bool isVec, bool isFloat) const
For targets without i1 registers, this gives the nature of the high-bits of boolean values held in ty...
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Primary interface to the complete machine description for the target machine.
Target-Independent Code Generator Pass Configuration Options.
bool isGlobalISelAbortEnabled() const
Check whether or not GlobalISel should abort on error.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
The instances of the Type class are immutable: once they are created, they are never changed.
LLVM Value Representation.
constexpr ScalarTy getFixedValue() const
constexpr bool isScalable() const
Returns whether the quantity is scaled by a runtime quantity (vscale).
constexpr LeafTy multiplyCoefficientBy(ScalarTy RHS) const
constexpr ScalarTy getKnownMinValue() const
Returns the minimum value this quantity can represent.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
const APInt & smin(const APInt &A, const APInt &B)
Determine the smaller of two APInts considered to be signed.
const APInt & smax(const APInt &A, const APInt &B)
Determine the larger of two APInts considered to be signed.
const APInt & umin(const APInt &A, const APInt &B)
Determine the smaller of two APInts considered to be unsigned.
const APInt & umax(const APInt &A, const APInt &B)
Determine the larger of two APInts considered to be unsigned.
@ C
The default llvm calling convention, compatible with C.
SpecificConstantMatch m_SpecificICst(int64_t RequestedValue)
Matches a constant equal to RequestedValue.
bool mi_match(Reg R, const MachineRegisterInfo &MRI, Pattern &&P)
DiagnosticInfoMIROptimization::MachineArgument MNV
This is an optimization pass for GlobalISel generic memory operations.
Register getFunctionLiveInPhysReg(MachineFunction &MF, const TargetInstrInfo &TII, MCRegister PhysReg, const TargetRegisterClass &RC, const DebugLoc &DL, LLT RegTy=LLT())
Return a virtual register corresponding to the incoming argument register PhysReg.
auto drop_begin(T &&RangeOrContainer, size_t N=1)
Return a range covering RangeOrContainer with the first N elements excluded.
bool isBuildVectorAllZeros(const MachineInstr &MI, const MachineRegisterInfo &MRI, bool AllowUndef=false)
Return true if the specified instruction is a G_BUILD_VECTOR or G_BUILD_VECTOR_TRUNC where all of the...
Type * getTypeForLLT(LLT Ty, LLVMContext &C)
Get the type back from LLT.
bool all_of(R &&range, UnaryPredicate P)
Provide wrappers to std::all_of which take ranges instead of having to pass begin/end explicitly.
Register constrainOperandRegClass(const MachineFunction &MF, const TargetRegisterInfo &TRI, MachineRegisterInfo &MRI, const TargetInstrInfo &TII, const RegisterBankInfo &RBI, MachineInstr &InsertPt, const TargetRegisterClass &RegClass, MachineOperand &RegMO)
Constrain the Register operand OpIdx, so that it is now constrained to the TargetRegisterClass passed...
MachineInstr * getOpcodeDef(unsigned Opcode, Register Reg, const MachineRegisterInfo &MRI)
See if Reg is defined by an single def instruction that is Opcode.
const ConstantFP * getConstantFPVRegVal(Register VReg, const MachineRegisterInfo &MRI)
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
std::optional< APInt > getIConstantVRegVal(Register VReg, const MachineRegisterInfo &MRI)
If VReg is defined by a G_CONSTANT, return the corresponding value.
std::optional< APFloat > ConstantFoldIntToFloat(unsigned Opcode, LLT DstTy, Register Src, const MachineRegisterInfo &MRI)
std::optional< APInt > getIConstantSplatVal(const Register Reg, const MachineRegisterInfo &MRI)
bool isAllOnesOrAllOnesSplat(const MachineInstr &MI, const MachineRegisterInfo &MRI, bool AllowUndefs=false)
Return true if the value is a constant -1 integer or a splatted vector of a constant -1 integer (with...
const llvm::fltSemantics & getFltSemanticForLLT(LLT Ty)
Get the appropriate floating point arithmetic semantic based on the bit size of the given scalar LLT.
std::optional< APFloat > ConstantFoldFPBinOp(unsigned Opcode, const Register Op1, const Register Op2, const MachineRegisterInfo &MRI)
void salvageDebugInfo(const MachineRegisterInfo &MRI, MachineInstr &MI)
Assuming the instruction MI is going to be deleted, attempt to salvage debug users of MI by writing t...
bool constrainSelectedInstRegOperands(MachineInstr &I, const TargetInstrInfo &TII, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI)
Mutate the newly-selected instruction I to constrain its (possibly generic) virtual register operands...
bool isPreISelGenericOpcode(unsigned Opcode)
Check whether the given Opcode is a generic opcode that is not supposed to appear after ISel.
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
std::optional< SmallVector< unsigned > > ConstantFoldCountZeros(Register Src, const MachineRegisterInfo &MRI, std::function< unsigned(APInt)> CB)
Tries to constant fold a counting-zero operation (G_CTLZ or G_CTTZ) on Src.
std::optional< APInt > ConstantFoldExtOp(unsigned Opcode, const Register Op1, uint64_t Imm, const MachineRegisterInfo &MRI)
std::optional< RegOrConstant > getVectorSplat(const MachineInstr &MI, const MachineRegisterInfo &MRI)
LLVM_READONLY APFloat maximum(const APFloat &A, const APFloat &B)
Implements IEEE 754-2019 maximum semantics.
bool shouldOptimizeForSize(const MachineFunction *MF, ProfileSummaryInfo *PSI, const MachineBlockFrequencyInfo *BFI, PGSOQueryType QueryType=PGSOQueryType::Other)
Returns true if machine function MF is suggested to be size-optimized based on the profile.
bool isKnownToBeAPowerOfTwo(const Value *V, const DataLayout &DL, bool OrZero=false, unsigned Depth=0, AssumptionCache *AC=nullptr, const Instruction *CxtI=nullptr, const DominatorTree *DT=nullptr, bool UseInstrInfo=true)
Return true if the given value is known to have exactly one bit set when defined.
std::optional< APInt > isConstantOrConstantSplatVector(MachineInstr &MI, const MachineRegisterInfo &MRI)
Determines if MI defines a constant integer or a splat vector of constant integers.
bool isNullOrNullSplat(const MachineInstr &MI, const MachineRegisterInfo &MRI, bool AllowUndefs=false)
Return true if the value is a constant 0 integer or a splatted vector of a constant 0 integer (with n...
MachineInstr * getDefIgnoringCopies(Register Reg, const MachineRegisterInfo &MRI)
Find the def instruction for Reg, folding away any trivial copies.
bool matchUnaryPredicate(const MachineRegisterInfo &MRI, Register Reg, std::function< bool(const Constant *ConstVal)> Match, bool AllowUndefs=false)
Attempt to match a unary predicate against a scalar/splat constant or every element of a constant G_B...
bool isPreISelGenericOptimizationHint(unsigned Opcode)
bool isGuaranteedNotToBeUndef(const Value *V, AssumptionCache *AC=nullptr, const Instruction *CtxI=nullptr, const DominatorTree *DT=nullptr, unsigned Depth=0)
Returns true if V cannot be undef, but may be poison.
bool isConstTrueVal(const TargetLowering &TLI, int64_t Val, bool IsVector, bool IsFP)
Returns true if given the TargetLowering's boolean contents information, the value Val contains a tru...
LLVM_READNONE LLT getLCMType(LLT OrigTy, LLT TargetTy)
Return the least common multiple type of OrigTy and TargetTy, by changing the number of vector elemen...
std::optional< int64_t > getIConstantVRegSExtVal(Register VReg, const MachineRegisterInfo &MRI)
If VReg is defined by a G_CONSTANT fits in int64_t returns it.
std::optional< APInt > ConstantFoldBinOp(unsigned Opcode, const Register Op1, const Register Op2, const MachineRegisterInfo &MRI)
bool shouldOptForSize(const MachineBasicBlock &MBB, ProfileSummaryInfo *PSI, BlockFrequencyInfo *BFI)
Returns true if the given block should be optimized for size.
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
LLVM_READONLY APFloat maxnum(const APFloat &A, const APFloat &B)
Implements IEEE-754 2019 maximumNumber semantics.
bool isConstantOrConstantVector(const MachineInstr &MI, const MachineRegisterInfo &MRI, bool AllowFP=true, bool AllowOpaqueConstants=true)
Return true if the specified instruction is known to be a constant, or a vector of constants.
constexpr unsigned MaxAnalysisRecursionDepth
auto reverse(ContainerTy &&C)
bool canReplaceReg(Register DstReg, Register SrcReg, MachineRegisterInfo &MRI)
Check if DstReg can be replaced with SrcReg depending on the register constraints.
void saveUsesAndErase(MachineInstr &MI, MachineRegisterInfo &MRI, LostDebugLocObserver *LocObserver, SmallInstListTy &DeadInstChain)
void reportGISelFailure(MachineFunction &MF, const TargetPassConfig &TPC, MachineOptimizationRemarkEmitter &MORE, MachineOptimizationRemarkMissed &R)
Report an ISel error as a missed optimization remark to the LLVMContext's diagnostic stream.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
std::optional< SmallVector< APInt > > ConstantFoldICmp(unsigned Pred, const Register Op1, const Register Op2, const MachineRegisterInfo &MRI)
std::optional< ValueAndVReg > getAnyConstantVRegValWithLookThrough(Register VReg, const MachineRegisterInfo &MRI, bool LookThroughInstrs=true, bool LookThroughAnyExt=false)
If VReg is defined by a statically evaluable chain of instructions rooted on a G_CONSTANT or G_FCONST...
bool isBuildVectorAllOnes(const MachineInstr &MI, const MachineRegisterInfo &MRI, bool AllowUndef=false)
Return true if the specified instruction is a G_BUILD_VECTOR or G_BUILD_VECTOR_TRUNC where all of the...
bool canCreateUndefOrPoison(const Operator *Op, bool ConsiderFlagsAndMetadata=true)
canCreateUndefOrPoison returns true if Op can create undef or poison from non-undef & non-poison oper...
SmallVector< APInt > ConstantFoldVectorBinop(unsigned Opcode, const Register Op1, const Register Op2, const MachineRegisterInfo &MRI)
Tries to constant fold a vector binop with sources Op1 and Op2.
std::optional< FPValueAndVReg > getFConstantSplat(Register VReg, const MachineRegisterInfo &MRI, bool AllowUndef=true)
Returns a floating point scalar constant of a build vector splat if it exists.
std::optional< APInt > ConstantFoldCastOp(unsigned Opcode, LLT DstTy, const Register Op0, const MachineRegisterInfo &MRI)
void extractParts(Register Reg, LLT Ty, int NumParts, SmallVectorImpl< Register > &VRegs, MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI)
Helper function to split a wide generic register into bitwise blocks with the given Type (which impli...
void getSelectionDAGFallbackAnalysisUsage(AnalysisUsage &AU)
Modify analysis usage so it preserves passes required for the SelectionDAG fallback.
LLVM_READNONE LLT getCoverTy(LLT OrigTy, LLT TargetTy)
Return smallest type that covers both OrigTy and TargetTy and is multiple of TargetTy.
LLVM_READONLY APFloat minnum(const APFloat &A, const APFloat &B)
Implements IEEE-754 2019 minimumNumber semantics.
uint64_t alignTo(uint64_t Size, Align A)
Returns a multiple of A needed to store Size bytes.
bool isTargetSpecificOpcode(unsigned Opcode)
Check whether the given Opcode is a target-specific opcode.
bool isGuaranteedNotToBeUndefOrPoison(const Value *V, AssumptionCache *AC=nullptr, const Instruction *CtxI=nullptr, const DominatorTree *DT=nullptr, unsigned Depth=0)
Return true if this function can prove that V does not have undef bits and is never poison.
std::optional< FPValueAndVReg > getFConstantVRegValWithLookThrough(Register VReg, const MachineRegisterInfo &MRI, bool LookThroughInstrs=true)
If VReg is defined by a statically evaluable chain of instructions rooted on a G_FCONSTANT returns it...
bool isConstFalseVal(const TargetLowering &TLI, int64_t Val, bool IsVector, bool IsFP)
constexpr unsigned BitWidth
APFloat getAPFloatFromSize(double Val, unsigned Size)
Returns an APFloat from Val converted to the appropriate size.
bool isBuildVectorConstantSplat(const Register Reg, const MachineRegisterInfo &MRI, int64_t SplatValue, bool AllowUndef)
Return true if the specified register is defined by G_BUILD_VECTOR or G_BUILD_VECTOR_TRUNC where all ...
void eraseInstr(MachineInstr &MI, MachineRegisterInfo &MRI, LostDebugLocObserver *LocObserver=nullptr)
DiagnosticSeverity
Defines the different supported severity of a diagnostic.
Register constrainRegToClass(MachineRegisterInfo &MRI, const TargetInstrInfo &TII, const RegisterBankInfo &RBI, Register Reg, const TargetRegisterClass &RegClass)
Try to constrain Reg to the specified register class.
int64_t getICmpTrueVal(const TargetLowering &TLI, bool IsVector, bool IsFP)
Returns an integer representing true, as defined by the TargetBooleanContents.
std::optional< ValueAndVReg > getIConstantVRegValWithLookThrough(Register VReg, const MachineRegisterInfo &MRI, bool LookThroughInstrs=true)
If VReg is defined by a statically evaluable chain of instructions rooted on a G_CONSTANT returns its...
auto find_if(R &&Range, UnaryPredicate P)
Provide wrappers to std::find_if which take ranges instead of having to pass begin/end explicitly.
bool isPreISelGenericFloatingPointOpcode(unsigned Opc)
Returns whether opcode Opc is a pre-isel generic floating-point opcode, having only floating-point op...
bool isKnownNeverSNaN(Register Val, const MachineRegisterInfo &MRI)
Returns true if Val can be assumed to never be a signaling NaN.
std::optional< DefinitionAndSourceRegister > getDefSrcRegIgnoringCopies(Register Reg, const MachineRegisterInfo &MRI)
Find the def instruction for Reg, and underlying value Register folding away any copies.
bool is_contained(R &&Range, const E &Element)
Returns true if Element is found in Range.
Align commonAlignment(Align A, uint64_t Offset)
Returns the alignment that satisfies both alignments.
void eraseInstrs(ArrayRef< MachineInstr * > DeadInstrs, MachineRegisterInfo &MRI, LostDebugLocObserver *LocObserver=nullptr)
void salvageDebugInfoForDbgValue(const MachineRegisterInfo &MRI, MachineInstr &MI, ArrayRef< MachineOperand * > DbgUsers)
Assuming the instruction MI is going to be deleted, attempt to salvage debug users of MI by writing t...
bool isKnownNeverNaN(const Value *V, unsigned Depth, const SimplifyQuery &SQ)
Return true if the floating-point scalar value is not a NaN or if the floating-point vector value has...
Register getSrcRegIgnoringCopies(Register Reg, const MachineRegisterInfo &MRI)
Find the source register for Reg, folding away any trivial copies.
LLVM_READNONE LLT getGCDType(LLT OrigTy, LLT TargetTy)
Return a type where the total size is the greatest common divisor of OrigTy and TargetTy.
bool isGuaranteedNotToBePoison(const Value *V, AssumptionCache *AC=nullptr, const Instruction *CtxI=nullptr, const DominatorTree *DT=nullptr, unsigned Depth=0)
Returns true if V cannot be poison, but may be undef.
LLVM_READONLY APFloat minimum(const APFloat &A, const APFloat &B)
Implements IEEE 754-2019 minimum semantics.
std::optional< int64_t > getIConstantSplatSExtVal(const Register Reg, const MachineRegisterInfo &MRI)
void extractVectorParts(Register Reg, unsigned NumElts, SmallVectorImpl< Register > &VRegs, MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI)
Version which handles irregular sub-vector splits.
int getSplatIndex(ArrayRef< int > Mask)
If all non-negative Mask elements are the same value, return that value.
bool isTriviallyDead(const MachineInstr &MI, const MachineRegisterInfo &MRI)
Check whether an instruction MI is dead: it only defines dead virtual registers, and doesn't have oth...
Align inferAlignFromPtrInfo(MachineFunction &MF, const MachinePointerInfo &MPO)
void reportGISelWarning(MachineFunction &MF, const TargetPassConfig &TPC, MachineOptimizationRemarkEmitter &MORE, MachineOptimizationRemarkMissed &R)
Report an ISel warning as a missed optimization remark to the LLVMContext's diagnostic stream.
This struct is a compact representation of a valid (non-zero power of two) alignment.
Simple struct used to hold a Register value and the instruction which defines it.
unsigned countMaxPopulation() const
Returns the maximum number of bits that could be one.
unsigned countMinPopulation() const
Returns the number of bits known to be one.
This class contains a discriminated union of information about pointers in memory operands,...
int64_t Offset
Offset - This is an offset from the base Value*.
PointerUnion< const Value *, const PseudoSourceValue * > V
This is the IR pointer value for the access, or it is null if unknown.
Simple struct used to hold a constant integer value and a virtual register.