LLVM 20.0.0git
TargetPassConfig.h
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1//===- TargetPassConfig.h - Code Generation pass options --------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8/// \file
9/// Target-Independent Code Generator Pass Configuration Options pass.
10///
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_CODEGEN_TARGETPASSCONFIG_H
14#define LLVM_CODEGEN_TARGETPASSCONFIG_H
15
16#include "llvm/Pass.h"
18#include "llvm/Support/Error.h"
19#include <cassert>
20#include <string>
21
22namespace llvm {
23
24class LLVMTargetMachine;
25struct MachineSchedContext;
26class PassConfigImpl;
27class ScheduleDAGInstrs;
28class CSEConfigBase;
29class PassInstrumentationCallbacks;
30
31// The old pass manager infrastructure is hidden in a legacy namespace now.
32namespace legacy {
33
34class PassManagerBase;
35
36} // end namespace legacy
37
39
40/// Discriminated union of Pass ID types.
41///
42/// The PassConfig API prefers dealing with IDs because they are safer and more
43/// efficient. IDs decouple configuration from instantiation. This way, when a
44/// pass is overriden, it isn't unnecessarily instantiated. It is also unsafe to
45/// refer to a Pass pointer after adding it to a pass manager, which deletes
46/// redundant pass instances.
47///
48/// However, it is convient to directly instantiate target passes with
49/// non-default ctors. These often don't have a registered PassInfo. Rather than
50/// force all target passes to implement the pass registry boilerplate, allow
51/// the PassConfig API to handle either type.
52///
53/// AnalysisID is sadly char*, so PointerIntPair won't work.
55 union {
58 };
59 bool IsInstance = false;
60
61public:
62 IdentifyingPassPtr() : P(nullptr) {}
63 IdentifyingPassPtr(AnalysisID IDPtr) : ID(IDPtr) {}
64 IdentifyingPassPtr(Pass *InstancePtr) : P(InstancePtr), IsInstance(true) {}
65
66 bool isValid() const { return P; }
67 bool isInstance() const { return IsInstance; }
68
69 AnalysisID getID() const {
70 assert(!IsInstance && "Not a Pass ID");
71 return ID;
72 }
73
74 Pass *getInstance() const {
75 assert(IsInstance && "Not a Pass Instance");
76 return P;
77 }
78};
79
80
81/// Target-Independent Code Generator Pass Configuration Options.
82///
83/// This is an ImmutablePass solely for the purpose of exposing CodeGen options
84/// to the internals of other CodeGen passes.
86private:
87 PassManagerBase *PM = nullptr;
88 AnalysisID StartBefore = nullptr;
89 AnalysisID StartAfter = nullptr;
90 AnalysisID StopBefore = nullptr;
91 AnalysisID StopAfter = nullptr;
92
93 unsigned StartBeforeInstanceNum = 0;
94 unsigned StartBeforeCount = 0;
95
96 unsigned StartAfterInstanceNum = 0;
97 unsigned StartAfterCount = 0;
98
99 unsigned StopBeforeInstanceNum = 0;
100 unsigned StopBeforeCount = 0;
101
102 unsigned StopAfterInstanceNum = 0;
103 unsigned StopAfterCount = 0;
104
105 bool Started = true;
106 bool Stopped = false;
107 bool AddingMachinePasses = false;
108 bool DebugifyIsSafe = true;
109
110 /// Set the StartAfter, StartBefore and StopAfter passes to allow running only
111 /// a portion of the normal code-gen pass sequence.
112 ///
113 /// If the StartAfter and StartBefore pass ID is zero, then compilation will
114 /// begin at the normal point; otherwise, clear the Started flag to indicate
115 /// that passes should not be added until the starting pass is seen. If the
116 /// Stop pass ID is zero, then compilation will continue to the end.
117 ///
118 /// This function expects that at least one of the StartAfter or the
119 /// StartBefore pass IDs is null.
120 void setStartStopPasses();
121
122protected:
124 PassConfigImpl *Impl = nullptr; // Internal data structures
125 bool Initialized = false; // Flagged after all passes are configured.
126
127 // Target Pass Options
128 // Targets provide a default setting, user flags override.
129 bool DisableVerify = false;
130
131 /// Default setting for -enable-tail-merge on this target.
132 bool EnableTailMerge = true;
133
134 /// Enable sinking of instructions in MachineSink where a computation can be
135 /// folded into the addressing mode of a memory load/store instruction or
136 /// replace a copy.
137 bool EnableSinkAndFold = false;
138
139 /// Require processing of functions such that callees are generated before
140 /// callers.
142
143 /// Enable LoopTermFold immediately after LSR
144 bool EnableLoopTermFold = false;
145
146 /// Add the actual instruction selection passes. This does not include
147 /// preparation passes on IR.
148 bool addCoreISelPasses();
149
150public:
152 // Dummy constructor.
154
155 ~TargetPassConfig() override;
156
157 static char ID;
158
159 /// Get the right type of TargetMachine for this target.
160 template<typename TMC> TMC &getTM() const {
161 return *static_cast<TMC*>(TM);
162 }
163
164 //
165 void setInitialized() { Initialized = true; }
166
168
169 /// Returns true if one of the `-start-after`, `-start-before`, `-stop-after`
170 /// or `-stop-before` options is set.
171 static bool hasLimitedCodeGenPipeline();
172
173 /// Returns true if none of the `-stop-before` and `-stop-after` options is
174 /// set.
175 static bool willCompleteCodeGenPipeline();
176
177 /// If hasLimitedCodeGenPipeline is true, this method returns
178 /// a string with the name of the options that caused this
179 /// pipeline to be limited.
180 static std::string getLimitedCodeGenPipelineReason();
181
189 };
190
191 /// Returns pass name in `-stop-before` or `-stop-after`
192 /// NOTE: New pass manager migration only
195
197
198 bool getEnableTailMerge() const { return EnableTailMerge; }
200
203
207 }
208
209 /// Allow the target to override a specific pass without overriding the pass
210 /// pipeline. When passes are added to the standard pipeline at the
211 /// point where StandardID is expected, add TargetID in its place.
212 void substitutePass(AnalysisID StandardID, IdentifyingPassPtr TargetID);
213
214 /// Insert InsertedPassID pass after TargetPassID pass.
215 void insertPass(AnalysisID TargetPassID, IdentifyingPassPtr InsertedPassID);
216
217 /// Allow the target to enable a specific standard pass by default.
218 void enablePass(AnalysisID PassID) { substitutePass(PassID, PassID); }
219
220 /// Allow the target to disable a specific standard pass by default.
221 void disablePass(AnalysisID PassID) {
223 }
224
225 /// Return the pass substituted for StandardID by the target.
226 /// If no substitution exists, return StandardID.
228
229 /// Return true if the pass has been substituted by the target or
230 /// overridden on the command line.
232
233 /// Return true if the optimized regalloc pipeline is enabled.
234 bool getOptimizeRegAlloc() const;
235
236 /// Return true if the default global register allocator is in use and
237 /// has not be overriden on the command line with '-regalloc=...'
238 bool usingDefaultRegAlloc() const;
239
240 /// High level function that adds all passes necessary to go from llvm IR
241 /// representation to the MI representation.
242 /// Adds IR based lowering and target specific optimization passes and finally
243 /// the core instruction selection passes.
244 /// \returns true if an error occurred, false otherwise.
245 bool addISelPasses();
246
247 /// Add common target configurable passes that perform LLVM IR to IR
248 /// transforms following machine independent optimization.
249 virtual void addIRPasses();
250
251 /// Add passes to lower exception handling for the code generator.
253
254 /// Add pass to prepare the LLVM IR for code generation. This should be done
255 /// before exception handling preparation passes.
256 virtual void addCodeGenPrepare();
257
258 /// Add common passes that perform LLVM IR to IR transforms in preparation for
259 /// instruction selection.
260 virtual void addISelPrepare();
261
262 /// addInstSelector - This method should install an instruction selector pass,
263 /// which converts from LLVM code to machine instructions.
264 virtual bool addInstSelector() {
265 return true;
266 }
267
268 /// This method should install an IR translator pass, which converts from
269 /// LLVM code to machine instructions with possibly generic opcodes.
270 virtual bool addIRTranslator() { return true; }
271
272 /// This method may be implemented by targets that want to run passes
273 /// immediately before legalization.
274 virtual void addPreLegalizeMachineIR() {}
275
276 /// This method should install a legalize pass, which converts the instruction
277 /// sequence into one that can be selected by the target.
278 virtual bool addLegalizeMachineIR() { return true; }
279
280 /// This method may be implemented by targets that want to run passes
281 /// immediately before the register bank selection.
282 virtual void addPreRegBankSelect() {}
283
284 /// This method should install a register bank selector pass, which
285 /// assigns register banks to virtual registers without a register
286 /// class or register banks.
287 virtual bool addRegBankSelect() { return true; }
288
289 /// This method may be implemented by targets that want to run passes
290 /// immediately before the (global) instruction selection.
292
293 /// This method should install a (global) instruction selector pass, which
294 /// converts possibly generic instructions to fully target-specific
295 /// instructions, thereby constraining all generic virtual registers to
296 /// register classes.
297 virtual bool addGlobalInstructionSelect() { return true; }
298
299 /// Add the complete, standard set of LLVM CodeGen passes.
300 /// Fully developed targets will not generally override this.
301 virtual void addMachinePasses();
302
303 /// Create an instance of ScheduleDAGInstrs to be run within the standard
304 /// MachineScheduler pass for this function and target at the current
305 /// optimization level.
306 ///
307 /// This can also be used to plug a new MachineSchedStrategy into an instance
308 /// of the standard ScheduleDAGMI:
309 /// return new ScheduleDAGMI(C, std::make_unique<MyStrategy>(C), /*RemoveKillFlags=*/false)
310 ///
311 /// Return NULL to select the default (generic) machine scheduler.
312 virtual ScheduleDAGInstrs *
314 return nullptr;
315 }
316
317 /// Similar to createMachineScheduler but used when postRA machine scheduling
318 /// is enabled.
319 virtual ScheduleDAGInstrs *
321 return nullptr;
322 }
323
324 /// printAndVerify - Add a pass to dump then verify the machine function, if
325 /// those steps are enabled.
326 void printAndVerify(const std::string &Banner);
327
328 /// Add a pass to print the machine function if printing is enabled.
329 void addPrintPass(const std::string &Banner);
330
331 /// Add a pass to perform basic verification of the machine function if
332 /// verification is enabled.
333 void addVerifyPass(const std::string &Banner);
334
335 /// Add a pass to add synthesized debug info to the MIR.
336 void addDebugifyPass();
337
338 /// Add a pass to remove debug info from the MIR.
339 void addStripDebugPass();
340
341 /// Add a pass to check synthesized debug info for MIR.
342 void addCheckDebugPass();
343
344 /// Add standard passes before a pass that's about to be added. For example,
345 /// the DebugifyMachineModulePass if it is enabled.
346 void addMachinePrePasses(bool AllowDebugify = true);
347
348 /// Add standard passes after a pass that has just been added. For example,
349 /// the MachineVerifier if it is enabled.
350 void addMachinePostPasses(const std::string &Banner);
351
352 /// Check whether or not GlobalISel should abort on error.
353 /// When this is disabled, GlobalISel will fall back on SDISel instead of
354 /// erroring out.
355 bool isGlobalISelAbortEnabled() const;
356
357 /// Check whether or not a diagnostic should be emitted when GlobalISel
358 /// uses the fallback path. In other words, it will emit a diagnostic
359 /// when GlobalISel failed and isGlobalISelAbortEnabled is false.
360 virtual bool reportDiagnosticWhenGlobalISelFallback() const;
361
362 /// Check whether continuous CSE should be enabled in GISel passes.
363 /// By default, it's enabled for non O0 levels.
364 virtual bool isGISelCSEEnabled() const;
365
366 /// Returns the CSEConfig object to use for the current optimization level.
367 virtual std::unique_ptr<CSEConfigBase> getCSEConfig() const;
368
369protected:
370 // Helper to verify the analysis is really immutable.
371 void setOpt(bool &Opt, bool Val);
372
373 /// Return true if register allocator is specified by -regalloc=override.
375
376 /// Methods with trivial inline returns are convenient points in the common
377 /// codegen pass pipeline where targets may insert passes. Methods with
378 /// out-of-line standard implementations are major CodeGen stages called by
379 /// addMachinePasses. Some targets may override major stages when inserting
380 /// passes is insufficient, but maintaining overriden stages is more work.
381 ///
382
383 /// addPreISelPasses - This method should add any "last minute" LLVM->LLVM
384 /// passes (which are run just before instruction selector).
385 virtual bool addPreISel() {
386 return true;
387 }
388
389 /// addMachineSSAOptimization - Add standard passes that optimize machine
390 /// instructions in SSA form.
391 virtual void addMachineSSAOptimization();
392
393 /// Add passes that optimize instruction level parallelism for out-of-order
394 /// targets. These passes are run while the machine code is still in SSA
395 /// form, so they can use MachineTraceMetrics to control their heuristics.
396 ///
397 /// All passes added here should preserve the MachineDominatorTree,
398 /// MachineLoopInfo, and MachineTraceMetrics analyses.
399 virtual bool addILPOpts() {
400 return false;
401 }
402
403 /// This method may be implemented by targets that want to run passes
404 /// immediately before register allocation.
405 virtual void addPreRegAlloc() { }
406
407 /// createTargetRegisterAllocator - Create the register allocator pass for
408 /// this target at the current optimization level.
409 virtual FunctionPass *createTargetRegisterAllocator(bool Optimized);
410
411 /// addFastRegAlloc - Add the minimum set of target-independent passes that
412 /// are required for fast register allocation.
413 virtual void addFastRegAlloc();
414
415 /// addOptimizedRegAlloc - Add passes related to register allocation.
416 /// LLVMTargetMachine provides standard regalloc passes for most targets.
417 virtual void addOptimizedRegAlloc();
418
419 /// addPreRewrite - Add passes to the optimized register allocation pipeline
420 /// after register allocation is complete, but before virtual registers are
421 /// rewritten to physical registers.
422 ///
423 /// These passes must preserve VirtRegMap and LiveIntervals, and when running
424 /// after RABasic or RAGreedy, they should take advantage of LiveRegMatrix.
425 /// When these passes run, VirtRegMap contains legal physreg assignments for
426 /// all virtual registers.
427 ///
428 /// Note if the target overloads addRegAssignAndRewriteOptimized, this may not
429 /// be honored. This is also not generally used for the fast variant,
430 /// where the allocation and rewriting are done in one pass.
431 virtual bool addPreRewrite() {
432 return false;
433 }
434
435 /// addPostFastRegAllocRewrite - Add passes to the optimized register
436 /// allocation pipeline after fast register allocation is complete.
437 virtual bool addPostFastRegAllocRewrite() { return false; }
438
439 /// Add passes to be run immediately after virtual registers are rewritten
440 /// to physical registers.
441 virtual void addPostRewrite() { }
442
443 /// This method may be implemented by targets that want to run passes after
444 /// register allocation pass pipeline but before prolog-epilog insertion.
445 virtual void addPostRegAlloc() { }
446
447 /// Add passes that optimize machine instructions after register allocation.
448 virtual void addMachineLateOptimization();
449
450 /// This method may be implemented by targets that want to run passes after
451 /// prolog-epilog insertion and before the second instruction scheduling pass.
452 virtual void addPreSched2() { }
453
454 /// addGCPasses - Add late codegen passes that analyze code for garbage
455 /// collection. This should return true if GC info should be printed after
456 /// these passes.
457 virtual bool addGCPasses();
458
459 /// Add standard basic block placement passes.
460 virtual void addBlockPlacement();
461
462 /// This pass may be implemented by targets that want to run passes
463 /// immediately before machine code is emitted.
464 virtual void addPreEmitPass() { }
465
466 /// This pass may be implemented by targets that want to run passes
467 /// immediately after basic block sections are assigned.
468 virtual void addPostBBSections() {}
469
470 /// Targets may add passes immediately before machine code is emitted in this
471 /// callback. This is called even later than `addPreEmitPass`.
472 // FIXME: Rename `addPreEmitPass` to something more sensible given its actual
473 // position and remove the `2` suffix here as this callback is what
474 // `addPreEmitPass` *should* be but in reality isn't.
475 virtual void addPreEmitPass2() {}
476
477 /// Utilities for targets to add passes to the pass manager.
478 ///
479
480 /// Add a CodeGen pass at this point in the pipeline after checking overrides.
481 /// Return the pass that was added, or zero if no pass was added.
483
484 /// Add a pass to the PassManager if that pass is supposed to be run, as
485 /// determined by the StartAfter and StopAfter options. Takes ownership of the
486 /// pass.
487 void addPass(Pass *P);
488
489 /// addMachinePasses helper to create the target-selected or overriden
490 /// regalloc pass.
491 virtual FunctionPass *createRegAllocPass(bool Optimized);
492
493 /// Add core register allocator passes which do the actual register assignment
494 /// and rewriting. \returns true if any passes were added.
495 virtual bool addRegAssignAndRewriteFast();
496 virtual bool addRegAssignAndRewriteOptimized();
497};
498
499void registerCodeGenCallback(PassInstrumentationCallbacks &PIC,
500 LLVMTargetMachine &);
501
502} // end namespace llvm
503
504#endif // LLVM_CODEGEN_TARGETPASSCONFIG_H
basic Basic Alias true
#define P(N)
PassInstrumentationCallbacks PIC
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
Tagged union holding either a T or a Error.
Definition: Error.h:481
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:310
Discriminated union of Pass ID types.
AnalysisID getID() const
IdentifyingPassPtr(AnalysisID IDPtr)
IdentifyingPassPtr(Pass *InstancePtr)
ImmutablePass class - This class is used to provide information that does not need to be run.
Definition: Pass.h:281
This class describes a target machine that is implemented with the LLVM target-independent code gener...
This class manages callbacks registration, as well as provides a way for PassInstrumentation to pass ...
Pass interface - Implemented by all 'passes'.
Definition: Pass.h:94
A ScheduleDAG for scheduling lists of MachineInstr.
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
Target-Independent Code Generator Pass Configuration Options.
bool usingDefaultRegAlloc() const
Return true if the default global register allocator is in use and has not be overriden on the comman...
void enablePass(AnalysisID PassID)
Allow the target to enable a specific standard pass by default.
bool requiresCodeGenSCCOrder() const
void addCheckDebugPass()
Add a pass to check synthesized debug info for MIR.
LLVMTargetMachine * TM
virtual void addPreLegalizeMachineIR()
This method may be implemented by targets that want to run passes immediately before legalization.
void addPrintPass(const std::string &Banner)
Add a pass to print the machine function if printing is enabled.
virtual void addPreEmitPass2()
Targets may add passes immediately before machine code is emitted in this callback.
virtual std::unique_ptr< CSEConfigBase > getCSEConfig() const
Returns the CSEConfig object to use for the current optimization level.
bool RequireCodeGenSCCOrder
Require processing of functions such that callees are generated before callers.
bool EnableLoopTermFold
Enable LoopTermFold immediately after LSR.
void printAndVerify(const std::string &Banner)
printAndVerify - Add a pass to dump then verify the machine function, if those steps are enabled.
bool getEnableTailMerge() const
static bool hasLimitedCodeGenPipeline()
Returns true if one of the -start-after, -start-before, -stop-after or -stop-before options is set.
static Expected< StartStopInfo > getStartStopInfo(PassInstrumentationCallbacks &PIC)
Returns pass name in -stop-before or -stop-after NOTE: New pass manager migration only.
virtual void addCodeGenPrepare()
Add pass to prepare the LLVM IR for code generation.
void insertPass(AnalysisID TargetPassID, IdentifyingPassPtr InsertedPassID)
Insert InsertedPassID pass after TargetPassID pass.
void addMachinePostPasses(const std::string &Banner)
Add standard passes after a pass that has just been added.
virtual void addPreSched2()
This method may be implemented by targets that want to run passes after prolog-epilog insertion and b...
virtual bool isGISelCSEEnabled() const
Check whether continuous CSE should be enabled in GISel passes.
virtual bool addILPOpts()
Add passes that optimize instruction level parallelism for out-of-order targets.
virtual void addPostRegAlloc()
This method may be implemented by targets that want to run passes after register allocation pass pipe...
void addDebugifyPass()
Add a pass to add synthesized debug info to the MIR.
virtual bool addInstSelector()
addInstSelector - This method should install an instruction selector pass, which converts from LLVM c...
virtual ScheduleDAGInstrs * createPostMachineScheduler(MachineSchedContext *C) const
Similar to createMachineScheduler but used when postRA machine scheduling is enabled.
bool getEnableSinkAndFold() const
CodeGenOptLevel getOptLevel() const
virtual bool addPreISel()
Methods with trivial inline returns are convenient points in the common codegen pass pipeline where t...
void setOpt(bool &Opt, bool Val)
virtual void addBlockPlacement()
Add standard basic block placement passes.
virtual FunctionPass * createRegAllocPass(bool Optimized)
addMachinePasses helper to create the target-selected or overriden regalloc pass.
virtual void addPostBBSections()
This pass may be implemented by targets that want to run passes immediately after basic block section...
virtual void addOptimizedRegAlloc()
addOptimizedRegAlloc - Add passes related to register allocation.
virtual bool addRegAssignAndRewriteFast()
Add core register allocator passes which do the actual register assignment and rewriting.
virtual void addPreEmitPass()
This pass may be implemented by targets that want to run passes immediately before machine code is em...
bool isGlobalISelAbortEnabled() const
Check whether or not GlobalISel should abort on error.
bool getOptimizeRegAlloc() const
Return true if the optimized regalloc pipeline is enabled.
bool isCustomizedRegAlloc()
Return true if register allocator is specified by -regalloc=override.
virtual void addPreRegBankSelect()
This method may be implemented by targets that want to run passes immediately before the register ban...
virtual ScheduleDAGInstrs * createMachineScheduler(MachineSchedContext *C) const
Create an instance of ScheduleDAGInstrs to be run within the standard MachineScheduler pass for this ...
virtual bool reportDiagnosticWhenGlobalISelFallback() const
Check whether or not a diagnostic should be emitted when GlobalISel uses the fallback path.
virtual bool addPreRewrite()
addPreRewrite - Add passes to the optimized register allocation pipeline after register allocation is...
virtual bool addRegBankSelect()
This method should install a register bank selector pass, which assigns register banks to virtual reg...
void setEnableSinkAndFold(bool Enable)
void setRequiresCodeGenSCCOrder(bool Enable=true)
virtual void addMachineLateOptimization()
Add passes that optimize machine instructions after register allocation.
virtual void addMachinePasses()
Add the complete, standard set of LLVM CodeGen passes.
virtual void addIRPasses()
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
virtual void addPreGlobalInstructionSelect()
This method may be implemented by targets that want to run passes immediately before the (global) ins...
virtual void addFastRegAlloc()
addFastRegAlloc - Add the minimum set of target-independent passes that are required for fast registe...
virtual bool addLegalizeMachineIR()
This method should install a legalize pass, which converts the instruction sequence into one that can...
virtual void addMachineSSAOptimization()
addMachineSSAOptimization - Add standard passes that optimize machine instructions in SSA form.
void substitutePass(AnalysisID StandardID, IdentifyingPassPtr TargetID)
Allow the target to override a specific pass without overriding the pass pipeline.
virtual bool addRegAssignAndRewriteOptimized()
void disablePass(AnalysisID PassID)
Allow the target to disable a specific standard pass by default.
virtual bool addGlobalInstructionSelect()
This method should install a (global) instruction selector pass, which converts possibly generic inst...
virtual void addPreRegAlloc()
This method may be implemented by targets that want to run passes immediately before register allocat...
bool EnableSinkAndFold
Enable sinking of instructions in MachineSink where a computation can be folded into the addressing m...
static std::string getLimitedCodeGenPipelineReason()
If hasLimitedCodeGenPipeline is true, this method returns a string with the name of the options that ...
bool EnableTailMerge
Default setting for -enable-tail-merge on this target.
AnalysisID addPass(AnalysisID PassID)
Utilities for targets to add passes to the pass manager.
void addPassesToHandleExceptions()
Add passes to lower exception handling for the code generator.
void addStripDebugPass()
Add a pass to remove debug info from the MIR.
bool isPassSubstitutedOrOverridden(AnalysisID ID) const
Return true if the pass has been substituted by the target or overridden on the command line.
bool addCoreISelPasses()
Add the actual instruction selection passes.
void setEnableTailMerge(bool Enable)
void setDisableVerify(bool Disable)
TMC & getTM() const
Get the right type of TargetMachine for this target.
virtual void addISelPrepare()
Add common passes that perform LLVM IR to IR transforms in preparation for instruction selection.
static bool willCompleteCodeGenPipeline()
Returns true if none of the -stop-before and -stop-after options is set.
void addMachinePrePasses(bool AllowDebugify=true)
Add standard passes before a pass that's about to be added.
virtual bool addGCPasses()
addGCPasses - Add late codegen passes that analyze code for garbage collection.
virtual bool addIRTranslator()
This method should install an IR translator pass, which converts from LLVM code to machine instructio...
void addVerifyPass(const std::string &Banner)
Add a pass to perform basic verification of the machine function if verification is enabled.
virtual FunctionPass * createTargetRegisterAllocator(bool Optimized)
createTargetRegisterAllocator - Create the register allocator pass for this target at the current opt...
virtual bool addPostFastRegAllocRewrite()
addPostFastRegAllocRewrite - Add passes to the optimized register allocation pipeline after fast regi...
IdentifyingPassPtr getPassSubstitution(AnalysisID StandardID) const
Return the pass substituted for StandardID by the target.
bool addISelPasses()
High level function that adds all passes necessary to go from llvm IR representation to the MI repres...
virtual void addPostRewrite()
Add passes to be run immediately after virtual registers are rewritten to physical registers.
PassManagerBase - An abstract interface to allow code to add passes to a pass manager without having ...
@ C
The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
void registerCodeGenCallback(PassInstrumentationCallbacks &PIC, LLVMTargetMachine &)
CodeGenOptLevel
Code generation optimization level.
Definition: CodeGen.h:54
const void * AnalysisID
Definition: Pass.h:50
@ Enable
Enable colors.
@ Disable
Disable colors.
MachineSchedContext provides enough context from the MachineScheduler pass for the target to instanti...