98void SelectionDAG::DAGNodeDeletedListener::anchor() {}
99void SelectionDAG::DAGNodeInsertedListener::anchor() {}
101#define DEBUG_TYPE "selectiondag"
105 cl::desc(
"Gang up loads and stores generated by inlining of memcpy"));
108 cl::desc(
"Number limit for gluing ld/st of memcpy."),
113 cl::desc(
"DAG combiner limit number of steps when searching DAG "
114 "for predecessor nodes"));
152 if (
auto OptAPInt =
N->getOperand(0)->bitcastToAPInt()) {
154 N->getValueType(0).getVectorElementType().getSizeInBits();
155 SplatVal = OptAPInt->
trunc(EltSize);
165 unsigned SplatBitSize;
167 unsigned EltSize =
N->getValueType(0).getVectorElementType().getSizeInBits();
172 const bool IsBigEndian =
false;
173 return BV->isConstantSplat(SplatVal, SplatUndef, SplatBitSize, HasUndefs,
174 EltSize, IsBigEndian) &&
175 EltSize == SplatBitSize;
184 N =
N->getOperand(0).getNode();
193 unsigned i = 0, e =
N->getNumOperands();
196 while (i != e &&
N->getOperand(i).isUndef())
200 if (i == e)
return false;
212 unsigned EltSize =
N->getValueType(0).getScalarSizeInBits();
213 if (OptAPInt->countr_one() < EltSize)
221 for (++i; i != e; ++i)
222 if (
N->getOperand(i) != NotZero && !
N->getOperand(i).isUndef())
230 N =
N->getOperand(0).getNode();
239 bool IsAllUndef =
true;
252 if (
auto OptAPInt =
Op->bitcastToAPInt()) {
253 unsigned EltSize =
N->getValueType(0).getScalarSizeInBits();
254 if (OptAPInt->countr_zero() < EltSize)
302 assert(
N->getValueType(0).isVector() &&
"Expected a vector!");
304 unsigned EltSize =
N->getValueType(0).getScalarSizeInBits();
305 if (EltSize <= NewEltSize)
309 return (
N->getOperand(0).getValueType().getScalarSizeInBits() <=
314 return (
N->getOperand(0).getValueType().getScalarSizeInBits() <=
327 APInt C =
Op->getAsAPIntVal().trunc(EltSize);
328 if (
Signed &&
C.trunc(NewEltSize).sext(EltSize) !=
C)
330 if (!
Signed &&
C.trunc(NewEltSize).zext(EltSize) !=
C)
341 if (
N->getNumOperands() == 0)
347 return N->getOpcode() ==
ISD::FREEZE &&
N->getOperand(0).isUndef();
350template <
typename ConstNodeType>
352 std::function<
bool(ConstNodeType *)> Match,
353 bool AllowUndefs,
bool AllowTruncation) {
363 EVT SVT =
Op.getValueType().getScalarType();
364 for (
unsigned i = 0, e =
Op.getNumOperands(); i != e; ++i) {
365 if (AllowUndefs &&
Op.getOperand(i).isUndef()) {
372 if (!Cst || (!AllowTruncation && Cst->getValueType(0) != SVT) ||
387 bool AllowUndefs,
bool AllowTypeMismatch) {
388 if (!AllowTypeMismatch && LHS.getValueType() != RHS.getValueType())
394 return Match(LHSCst, RHSCst);
397 if (LHS.getOpcode() != RHS.getOpcode() ||
403 for (
unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) {
406 bool LHSUndef = AllowUndefs && LHSOp.
isUndef();
407 bool RHSUndef = AllowUndefs && RHSOp.
isUndef();
410 if ((!LHSCst && !LHSUndef) || (!RHSCst && !RHSUndef))
412 if (!AllowTypeMismatch && (LHSOp.
getValueType() != SVT ||
415 if (!Match(LHSCst, RHSCst))
452 switch (VecReduceOpcode) {
457 case ISD::VP_REDUCE_FADD:
458 case ISD::VP_REDUCE_SEQ_FADD:
462 case ISD::VP_REDUCE_FMUL:
463 case ISD::VP_REDUCE_SEQ_FMUL:
466 case ISD::VP_REDUCE_ADD:
469 case ISD::VP_REDUCE_MUL:
472 case ISD::VP_REDUCE_AND:
475 case ISD::VP_REDUCE_OR:
478 case ISD::VP_REDUCE_XOR:
481 case ISD::VP_REDUCE_SMAX:
484 case ISD::VP_REDUCE_SMIN:
487 case ISD::VP_REDUCE_UMAX:
490 case ISD::VP_REDUCE_UMIN:
493 case ISD::VP_REDUCE_FMAX:
496 case ISD::VP_REDUCE_FMIN:
499 case ISD::VP_REDUCE_FMAXIMUM:
502 case ISD::VP_REDUCE_FMINIMUM:
511#define BEGIN_REGISTER_VP_SDNODE(VPSD, ...) \
514#include "llvm/IR/VPIntrinsics.def"
522#define BEGIN_REGISTER_VP_SDNODE(VPSD, ...) case ISD::VPSD:
523#define VP_PROPERTY_BINARYOP return true;
524#define END_REGISTER_VP_SDNODE(VPSD) break;
525#include "llvm/IR/VPIntrinsics.def"
534 case ISD::VP_REDUCE_ADD:
535 case ISD::VP_REDUCE_MUL:
536 case ISD::VP_REDUCE_AND:
537 case ISD::VP_REDUCE_OR:
538 case ISD::VP_REDUCE_XOR:
539 case ISD::VP_REDUCE_SMAX:
540 case ISD::VP_REDUCE_SMIN:
541 case ISD::VP_REDUCE_UMAX:
542 case ISD::VP_REDUCE_UMIN:
543 case ISD::VP_REDUCE_FMAX:
544 case ISD::VP_REDUCE_FMIN:
545 case ISD::VP_REDUCE_FMAXIMUM:
546 case ISD::VP_REDUCE_FMINIMUM:
547 case ISD::VP_REDUCE_FADD:
548 case ISD::VP_REDUCE_FMUL:
549 case ISD::VP_REDUCE_SEQ_FADD:
550 case ISD::VP_REDUCE_SEQ_FMUL:
560#define BEGIN_REGISTER_VP_SDNODE(VPSD, LEGALPOS, TDNAME, MASKPOS, ...) \
563#include "llvm/IR/VPIntrinsics.def"
572#define BEGIN_REGISTER_VP_SDNODE(VPSD, LEGALPOS, TDNAME, MASKPOS, EVLPOS) \
575#include "llvm/IR/VPIntrinsics.def"
585#define BEGIN_REGISTER_VP_SDNODE(VPOPC, ...) case ISD::VPOPC:
586#define VP_PROPERTY_FUNCTIONAL_SDOPC(SDOPC) return ISD::SDOPC;
587#define END_REGISTER_VP_SDNODE(VPOPC) break;
588#include "llvm/IR/VPIntrinsics.def"
597#define BEGIN_REGISTER_VP_SDNODE(VPOPC, ...) break;
598#define VP_PROPERTY_FUNCTIONAL_SDOPC(SDOPC) case ISD::SDOPC:
599#define END_REGISTER_VP_SDNODE(VPOPC) return ISD::VPOPC;
600#include "llvm/IR/VPIntrinsics.def"
647 bool isIntegerLike) {
672 bool IsInteger =
Type.isInteger();
677 unsigned Op = Op1 | Op2;
693 bool IsInteger =
Type.isInteger();
728 ID.AddPointer(VTList.
VTs);
734 for (
const auto &
Op :
Ops) {
735 ID.AddPointer(
Op.getNode());
736 ID.AddInteger(
Op.getResNo());
743 for (
const auto &
Op :
Ops) {
744 ID.AddPointer(
Op.getNode());
745 ID.AddInteger(
Op.getResNo());
758 switch (
N->getOpcode()) {
767 ID.AddPointer(
C->getConstantIntValue());
768 ID.AddBoolean(
C->isOpaque());
832 ID.AddInteger(LD->getMemoryVT().getRawBits());
833 ID.AddInteger(LD->getRawSubclassData());
834 ID.AddInteger(LD->getPointerInfo().getAddrSpace());
835 ID.AddInteger(LD->getMemOperand()->getFlags());
840 ID.AddInteger(ST->getMemoryVT().getRawBits());
841 ID.AddInteger(ST->getRawSubclassData());
842 ID.AddInteger(ST->getPointerInfo().getAddrSpace());
843 ID.AddInteger(ST->getMemOperand()->getFlags());
854 case ISD::VP_LOAD_FF: {
856 ID.AddInteger(LD->getMemoryVT().getRawBits());
857 ID.AddInteger(LD->getRawSubclassData());
858 ID.AddInteger(LD->getPointerInfo().getAddrSpace());
859 ID.AddInteger(LD->getMemOperand()->getFlags());
862 case ISD::VP_STORE: {
870 case ISD::EXPERIMENTAL_VP_STRIDED_LOAD: {
877 case ISD::EXPERIMENTAL_VP_STRIDED_STORE: {
884 case ISD::VP_GATHER: {
892 case ISD::VP_SCATTER: {
991 ID.AddInteger(MN->getRawSubclassData());
992 ID.AddInteger(MN->getMemoryVT().getRawBits());
994 ID.AddInteger(MMO->getPointerInfo().getAddrSpace());
995 ID.AddInteger(MMO->getFlags());
1019 if (
N->getValueType(0) == MVT::Glue)
1022 switch (
N->getOpcode()) {
1030 for (
unsigned i = 1, e =
N->getNumValues(); i != e; ++i)
1031 if (
N->getValueType(i) == MVT::Glue)
1048 if (
Node.use_empty())
1063 while (!DeadNodes.
empty()) {
1072 DUL->NodeDeleted(
N,
nullptr);
1075 RemoveNodeFromCSEMaps(
N);
1106 RemoveNodeFromCSEMaps(
N);
1110 DeleteNodeNotInCSEMaps(
N);
1113void SelectionDAG::DeleteNodeNotInCSEMaps(
SDNode *
N) {
1114 assert(
N->getIterator() != AllNodes.begin() &&
1115 "Cannot delete the entry node!");
1116 assert(
N->use_empty() &&
"Cannot delete a node that is not dead!");
1125 assert(!(V->isVariadic() && isParameter));
1127 ByvalParmDbgValues.push_back(V);
1129 DbgValues.push_back(V);
1132 DbgValMap[
Node].push_back(V);
1136 DbgValMapType::iterator
I = DbgValMap.find(
Node);
1137 if (
I == DbgValMap.end())
1139 for (
auto &Val:
I->second)
1140 Val->setIsInvalidated();
1144void SelectionDAG::DeallocateNode(
SDNode *
N) {
1167void SelectionDAG::verifyNode(
SDNode *
N)
const {
1168 switch (
N->getOpcode()) {
1170 if (
N->isTargetOpcode())
1174 EVT VT =
N->getValueType(0);
1175 assert(
N->getNumValues() == 1 &&
"Too many results!");
1177 "Wrong return type!");
1178 assert(
N->getNumOperands() == 2 &&
"Wrong number of operands!");
1179 assert(
N->getOperand(0).getValueType() ==
N->getOperand(1).getValueType() &&
1180 "Mismatched operand types!");
1182 "Wrong operand type!");
1184 "Wrong return type size");
1188 assert(
N->getNumValues() == 1 &&
"Too many results!");
1189 assert(
N->getValueType(0).isVector() &&
"Wrong return type!");
1190 assert(
N->getNumOperands() ==
N->getValueType(0).getVectorNumElements() &&
1191 "Wrong number of operands!");
1192 EVT EltVT =
N->getValueType(0).getVectorElementType();
1193 for (
const SDUse &
Op :
N->ops()) {
1194 assert((
Op.getValueType() == EltVT ||
1195 (EltVT.
isInteger() &&
Op.getValueType().isInteger() &&
1196 EltVT.
bitsLE(
Op.getValueType()))) &&
1197 "Wrong operand type!");
1198 assert(
Op.getValueType() ==
N->getOperand(0).getValueType() &&
1199 "Operands must all have the same type");
1207 assert(
N->getNumValues() == 2 &&
"Wrong number of results!");
1208 assert(
N->getVTList().NumVTs == 2 &&
N->getNumOperands() == 2 &&
1209 "Invalid add/sub overflow op!");
1210 assert(
N->getVTList().VTs[0].isInteger() &&
1211 N->getVTList().VTs[1].isInteger() &&
1212 N->getOperand(0).getValueType() ==
N->getOperand(1).getValueType() &&
1213 N->getOperand(0).getValueType() ==
N->getVTList().VTs[0] &&
1214 "Binary operator types must match!");
1224void SelectionDAG::InsertNode(SDNode *
N) {
1225 AllNodes.push_back(
N);
1227 N->PersistentId = NextPersistentId++;
1231 DUL->NodeInserted(
N);
1238bool SelectionDAG::RemoveNodeFromCSEMaps(SDNode *
N) {
1239 bool Erased =
false;
1240 switch (
N->getOpcode()) {
1244 "Cond code doesn't exist!");
1253 Erased = TargetExternalSymbols.erase(std::pair<std::string, unsigned>(
1259 Erased = MCSymbols.erase(MCSN->getMCSymbol());
1265 Erased = ExtendedValueTypeNodes.erase(VT);
1276 Erased = CSEMap.RemoveNode(
N);
1283 if (!Erased &&
N->getValueType(
N->getNumValues()-1) != MVT::Glue &&
1298SelectionDAG::AddModifiedNodeToCSEMaps(SDNode *
N) {
1302 SDNode *Existing = CSEMap.GetOrInsertNode(
N);
1303 if (Existing !=
N) {
1314 DUL->NodeDeleted(
N, Existing);
1315 DeleteNodeNotInCSEMaps(
N);
1322 DUL->NodeUpdated(
N);
1329SDNode *SelectionDAG::FindModifiedNodeSlot(SDNode *
N,
SDValue Op,
1335 FoldingSetNodeID
ID;
1338 SDNode *
Node = FindNodeOrInsertPos(
ID, SDLoc(
N), InsertPos);
1340 Node->intersectFlagsWith(
N->getFlags());
1348SDNode *SelectionDAG::FindModifiedNodeSlot(SDNode *
N,
1355 FoldingSetNodeID
ID;
1358 SDNode *
Node = FindNodeOrInsertPos(
ID, SDLoc(
N), InsertPos);
1360 Node->intersectFlagsWith(
N->getFlags());
1373 FoldingSetNodeID
ID;
1376 SDNode *
Node = FindNodeOrInsertPos(
ID, SDLoc(
N), InsertPos);
1378 Node->intersectFlagsWith(
N->getFlags());
1391 : TM(tm), OptLevel(OL), EntryNode(
ISD::EntryToken, 0,
DebugLoc(),
1394 InsertNode(&EntryNode);
1406 SDAGISelPass = PassPtr;
1410 LibInfo = LibraryInfo;
1411 Libcalls = LibcallsInfo;
1412 Context = &MF->getFunction().getContext();
1417 FnVarLocs = VarLocs;
1421 assert(!UpdateListeners &&
"Dangling registered DAGUpdateListeners");
1423 OperandRecycler.clear(OperandAllocator);
1431void SelectionDAG::allnodes_clear() {
1432 assert(&*AllNodes.begin() == &EntryNode);
1433 AllNodes.remove(AllNodes.begin());
1434 while (!AllNodes.empty())
1435 DeallocateNode(&AllNodes.front());
1437 NextPersistentId = 0;
1443 SDNode *
N = CSEMap.FindNodeOrInsertPos(
ID, InsertPos);
1445 switch (
N->getOpcode()) {
1450 "debug location. Use another overload.");
1457 const SDLoc &
DL,
void *&InsertPos) {
1458 SDNode *
N = CSEMap.FindNodeOrInsertPos(
ID, InsertPos);
1460 switch (
N->getOpcode()) {
1466 if (
N->getDebugLoc() !=
DL.getDebugLoc())
1473 if (
DL.getIROrder() &&
DL.getIROrder() <
N->getIROrder())
1474 N->setDebugLoc(
DL.getDebugLoc());
1483 OperandRecycler.clear(OperandAllocator);
1484 OperandAllocator.Reset();
1487 ExtendedValueTypeNodes.clear();
1488 ExternalSymbols.clear();
1489 TargetExternalSymbols.clear();
1495 EntryNode.UseList =
nullptr;
1496 InsertNode(&EntryNode);
1502 return VT.
bitsGT(
Op.getValueType())
1508std::pair<SDValue, SDValue>
1512 "Strict no-op FP extend/round not allowed.");
1519 return std::pair<SDValue, SDValue>(Res,
SDValue(Res.
getNode(), 1));
1523 return VT.
bitsGT(
Op.getValueType()) ?
1529 return VT.
bitsGT(
Op.getValueType()) ?
1535 return VT.
bitsGT(
Op.getValueType()) ?
1543 auto Type =
Op.getValueType();
1547 auto Size =
Op.getValueSizeInBits();
1558 auto Type =
Op.getValueType();
1562 auto Size =
Op.getValueSizeInBits();
1573 auto Type =
Op.getValueType();
1577 auto Size =
Op.getValueSizeInBits();
1591 return getNode(TLI->getExtendForContent(BType), SL, VT,
Op);
1595 EVT OpVT =
Op.getValueType();
1597 "Cannot getZeroExtendInReg FP types");
1599 "getZeroExtendInReg type should be vector iff the operand "
1603 "Vector element counts must match in getZeroExtendInReg");
1621 EVT OpVT =
Op.getValueType();
1623 "Cannot getVPZeroExtendInReg FP types");
1625 "getVPZeroExtendInReg type and operand type should be vector!");
1627 "Vector element counts must match in getZeroExtendInReg");
1666 return getNode(ISD::VP_XOR,
DL, VT, Val, TrueValue, Mask, EVL);
1677 return getNode(ISD::VP_ZERO_EXTEND,
DL, VT,
Op, Mask, EVL);
1679 return getNode(ISD::VP_TRUNCATE,
DL, VT,
Op, Mask, EVL);
1688 switch (TLI->getBooleanContents(OpVT)) {
1699 bool isT,
bool isO) {
1705 bool isT,
bool isO) {
1706 return getConstant(*ConstantInt::get(*Context, Val),
DL, VT, isT, isO);
1710 EVT VT,
bool isT,
bool isO) {
1727 EltVT = TLI->getTypeToTransformTo(*
getContext(), EltVT);
1733 Elt = ConstantInt::get(*
getContext(), NewVal);
1745 EVT ViaEltVT = TLI->getTypeToTransformTo(*
getContext(), EltVT);
1752 "Can only handle an even split!");
1756 for (
unsigned i = 0; i != Parts; ++i)
1758 NewVal.
extractBits(ViaEltSizeInBits, i * ViaEltSizeInBits),
DL,
1759 ViaEltVT, isT, isO));
1764 unsigned ViaVecNumElts = VT.
getSizeInBits() / ViaEltSizeInBits;
1775 NewVal.
extractBits(ViaEltSizeInBits, i * ViaEltSizeInBits),
DL,
1776 ViaEltVT, isT, isO));
1781 std::reverse(EltParts.
begin(), EltParts.
end());
1800 "APInt size does not match type size!");
1809 if ((
N = FindNodeOrInsertPos(
ID,
DL, IP)))
1814 N = newSDNode<ConstantSDNode>(isT, isO, Elt, VTs);
1815 CSEMap.InsertNode(
N, IP);
1827 bool isT,
bool isO) {
1835 IsTarget, IsOpaque);
1867 EVT VT,
bool isTarget) {
1888 if ((
N = FindNodeOrInsertPos(
ID,
DL, IP)))
1893 N = newSDNode<ConstantFPSDNode>(isTarget, Elt, VTs);
1894 CSEMap.InsertNode(
N, IP);
1908 if (EltVT == MVT::f32)
1910 if (EltVT == MVT::f64)
1912 if (EltVT == MVT::f80 || EltVT == MVT::f128 || EltVT == MVT::ppcf128 ||
1913 EltVT == MVT::f16 || EltVT == MVT::bf16) {
1924 EVT VT, int64_t
Offset,
bool isTargetGA,
1925 unsigned TargetFlags) {
1926 assert((TargetFlags == 0 || isTargetGA) &&
1927 "Cannot set target flags on target-independent globals");
1945 ID.AddInteger(TargetFlags);
1947 if (
SDNode *E = FindNodeOrInsertPos(
ID,
DL, IP))
1950 auto *
N = newSDNode<GlobalAddressSDNode>(
1951 Opc,
DL.getIROrder(),
DL.getDebugLoc(), GV, VTs,
Offset, TargetFlags);
1952 CSEMap.InsertNode(
N, IP);
1966 auto *
N = newSDNode<DeactivationSymbolSDNode>(GV, VTs);
1967 CSEMap.InsertNode(
N, IP);
1979 if (
SDNode *E = FindNodeOrInsertPos(
ID, IP))
1982 auto *
N = newSDNode<FrameIndexSDNode>(FI, VTs, isTarget);
1983 CSEMap.InsertNode(
N, IP);
1989 unsigned TargetFlags) {
1990 assert((TargetFlags == 0 || isTarget) &&
1991 "Cannot set target flags on target-independent jump tables");
1997 ID.AddInteger(TargetFlags);
1999 if (
SDNode *E = FindNodeOrInsertPos(
ID, IP))
2002 auto *
N = newSDNode<JumpTableSDNode>(JTI, VTs, isTarget, TargetFlags);
2003 CSEMap.InsertNode(
N, IP);
2017 bool isTarget,
unsigned TargetFlags) {
2018 assert((TargetFlags == 0 || isTarget) &&
2019 "Cannot set target flags on target-independent globals");
2028 ID.AddInteger(Alignment->value());
2031 ID.AddInteger(TargetFlags);
2033 if (
SDNode *E = FindNodeOrInsertPos(
ID, IP))
2036 auto *
N = newSDNode<ConstantPoolSDNode>(isTarget,
C, VTs,
Offset, *Alignment,
2038 CSEMap.InsertNode(
N, IP);
2047 bool isTarget,
unsigned TargetFlags) {
2048 assert((TargetFlags == 0 || isTarget) &&
2049 "Cannot set target flags on target-independent globals");
2056 ID.AddInteger(Alignment->value());
2058 C->addSelectionDAGCSEId(
ID);
2059 ID.AddInteger(TargetFlags);
2061 if (
SDNode *E = FindNodeOrInsertPos(
ID, IP))
2064 auto *
N = newSDNode<ConstantPoolSDNode>(isTarget,
C, VTs,
Offset, *Alignment,
2066 CSEMap.InsertNode(
N, IP);
2076 if (
SDNode *E = FindNodeOrInsertPos(
ID, IP))
2079 auto *
N = newSDNode<BasicBlockSDNode>(
MBB);
2080 CSEMap.InsertNode(
N, IP);
2087 ValueTypeNodes.size())
2094 N = newSDNode<VTSDNode>(VT);
2100 SDNode *&
N = ExternalSymbols[Sym];
2102 N = newSDNode<ExternalSymbolSDNode>(
false, Sym, 0,
getVTList(VT));
2116 N = newSDNode<MCSymbolSDNode>(Sym,
getVTList(VT));
2122 unsigned TargetFlags) {
2124 TargetExternalSymbols[std::pair<std::string, unsigned>(Sym, TargetFlags)];
2126 N = newSDNode<ExternalSymbolSDNode>(
true, Sym, TargetFlags,
getVTList(VT));
2132 EVT VT,
unsigned TargetFlags) {
2138 if ((
unsigned)
Cond >= CondCodeNodes.size())
2139 CondCodeNodes.resize(
Cond+1);
2141 if (!CondCodeNodes[
Cond]) {
2142 auto *
N = newSDNode<CondCodeSDNode>(
Cond);
2143 CondCodeNodes[
Cond] =
N;
2152 "APInt size does not match type size!");
2170template <
typename Ty>
2172 EVT VT, Ty Quantity) {
2173 if (Quantity.isScalable())
2177 return DAG.
getConstant(Quantity.getKnownMinValue(),
DL, VT);
2203 const APInt &StepVal) {
2227 "Must have the same number of vector elements as mask elements!");
2229 "Invalid VECTOR_SHUFFLE");
2237 int NElts = Mask.size();
2239 [&](
int M) {
return M < (NElts * 2) && M >= -1; }) &&
2240 "Index out of range");
2248 for (
int i = 0; i != NElts; ++i)
2249 if (MaskVec[i] >= NElts) MaskVec[i] -= NElts;
2256 if (TLI->hasVectorBlend()) {
2265 for (
int i = 0; i < NElts; ++i) {
2266 if (MaskVec[i] <
Offset || MaskVec[i] >= (
Offset + NElts))
2270 if (UndefElements[MaskVec[i] -
Offset]) {
2276 if (!UndefElements[i])
2281 BlendSplat(N1BV, 0);
2283 BlendSplat(N2BV, NElts);
2288 bool AllLHS =
true, AllRHS =
true;
2290 for (
int i = 0; i != NElts; ++i) {
2291 if (MaskVec[i] >= NElts) {
2296 }
else if (MaskVec[i] >= 0) {
2300 if (AllLHS && AllRHS)
2302 if (AllLHS && !N2Undef)
2315 bool Identity =
true, AllSame =
true;
2316 for (
int i = 0; i != NElts; ++i) {
2317 if (MaskVec[i] >= 0 && MaskVec[i] != i) Identity =
false;
2318 if (MaskVec[i] != MaskVec[0]) AllSame =
false;
2320 if (Identity && NElts)
2353 if (AllSame && SameNumElts) {
2354 EVT BuildVT = BV->getValueType(0);
2371 for (
int i = 0; i != NElts; ++i)
2372 ID.AddInteger(MaskVec[i]);
2375 if (
SDNode *E = FindNodeOrInsertPos(
ID, dl, IP))
2381 int *MaskAlloc = OperandAllocator.Allocate<
int>(NElts);
2384 auto *
N = newSDNode<ShuffleVectorSDNode>(VTs, dl.
getIROrder(),
2386 createOperands(
N,
Ops);
2388 CSEMap.InsertNode(
N, IP);
2409 ID.AddInteger(Reg.id());
2411 if (
SDNode *E = FindNodeOrInsertPos(
ID, IP))
2414 auto *
N = newSDNode<RegisterSDNode>(Reg, VTs);
2415 N->SDNodeBits.IsDivergent = TLI->isSDNodeSourceOfDivergence(
N, FLI, UA);
2416 CSEMap.InsertNode(
N, IP);
2424 ID.AddPointer(RegMask);
2426 if (
SDNode *E = FindNodeOrInsertPos(
ID, IP))
2429 auto *
N = newSDNode<RegisterMaskSDNode>(RegMask);
2430 CSEMap.InsertNode(
N, IP);
2445 ID.AddPointer(Label);
2447 if (
SDNode *E = FindNodeOrInsertPos(
ID, IP))
2452 createOperands(
N,
Ops);
2454 CSEMap.InsertNode(
N, IP);
2460 int64_t
Offset,
bool isTarget,
2461 unsigned TargetFlags) {
2469 ID.AddInteger(TargetFlags);
2471 if (
SDNode *E = FindNodeOrInsertPos(
ID, IP))
2474 auto *
N = newSDNode<BlockAddressSDNode>(
Opc, VTs, BA,
Offset, TargetFlags);
2475 CSEMap.InsertNode(
N, IP);
2486 if (
SDNode *E = FindNodeOrInsertPos(
ID, IP))
2489 auto *
N = newSDNode<SrcValueSDNode>(V);
2490 CSEMap.InsertNode(
N, IP);
2501 if (
SDNode *E = FindNodeOrInsertPos(
ID, IP))
2504 auto *
N = newSDNode<MDNodeSDNode>(MD);
2505 CSEMap.InsertNode(
N, IP);
2511 if (VT == V.getValueType())
2518 unsigned SrcAS,
unsigned DestAS) {
2523 ID.AddInteger(SrcAS);
2524 ID.AddInteger(DestAS);
2527 if (
SDNode *E = FindNodeOrInsertPos(
ID, dl, IP))
2531 VTs, SrcAS, DestAS);
2532 createOperands(
N,
Ops);
2534 CSEMap.InsertNode(
N, IP);
2553 EVT OpTy =
Op.getValueType();
2555 if (OpTy == ShTy || OpTy.
isVector())
return Op;
2564 EVT VT =
Node->getValueType(0);
2573 if (MA && *MA > TLI.getMinStackArgumentAlignment()) {
2611 Align RedAlign = UseABI ?
DL.getABITypeAlign(Ty) :
DL.getPrefTypeAlign(Ty);
2613 if (TLI->isTypeLegal(VT) || !VT.
isVector())
2621 if (RedAlign > StackAlign) {
2624 unsigned NumIntermediates;
2625 TLI->getVectorTypeBreakdown(*
getContext(), VT, IntermediateVT,
2626 NumIntermediates, RegisterVT);
2628 Align RedAlign2 = UseABI ?
DL.getABITypeAlign(Ty) :
DL.getPrefTypeAlign(Ty);
2629 if (RedAlign2 < RedAlign)
2630 RedAlign = RedAlign2;
2635 RedAlign = std::min(RedAlign, StackAlign);
2650 false,
nullptr, StackID);
2665 "Don't know how to choose the maximum size when creating a stack "
2674 Align Align = std::max(
DL.getPrefTypeAlign(Ty1),
DL.getPrefTypeAlign(Ty2));
2683 auto GetUndefBooleanConstant = [&]() {
2685 TLI->getBooleanContents(OpVT) ==
2722 return GetUndefBooleanConstant();
2727 return GetUndefBooleanConstant();
2736 const APInt &C2 = N2C->getAPIntValue();
2738 const APInt &C1 = N1C->getAPIntValue();
2748 if (N1CFP && N2CFP) {
2753 return GetUndefBooleanConstant();
2758 return GetUndefBooleanConstant();
2764 return GetUndefBooleanConstant();
2769 return GetUndefBooleanConstant();
2774 return GetUndefBooleanConstant();
2780 return GetUndefBooleanConstant();
2807 if (!TLI->isCondCodeLegal(SwappedCond, OpVT.
getSimpleVT()))
2809 return getSetCC(dl, VT, N2, N1, SwappedCond, {},
2811 }
else if ((N2CFP && N2CFP->getValueAPF().isNaN()) ||
2826 return GetUndefBooleanConstant();
2837 unsigned BitWidth =
Op.getScalarValueSizeInBits();
2846 unsigned Opc =
Op.getOpcode();
2855 return (NoFPClass & TestMask) == TestMask;
2862 return Op->getFlags().hasNoNaNs();
2888 unsigned Depth)
const {
2896 const APInt &DemandedElts,
2897 unsigned Depth)
const {
2904 unsigned Depth )
const {
2910 unsigned Depth)
const {
2915 const APInt &DemandedElts,
2916 unsigned Depth)
const {
2917 EVT VT =
Op.getValueType();
2924 for (
unsigned EltIdx = 0; EltIdx != NumElts; ++EltIdx) {
2925 if (!DemandedElts[EltIdx])
2929 KnownZeroElements.
setBit(EltIdx);
2931 return KnownZeroElements;
2941 unsigned Opcode = V.getOpcode();
2942 EVT VT = V.getValueType();
2945 "scalable demanded bits are ignored");
2957 UndefElts = V.getOperand(0).isUndef()
2966 APInt UndefLHS, UndefRHS;
2975 (DemandedElts & UndefLHS) == (DemandedElts & UndefRHS)) {
2976 UndefElts = UndefLHS | UndefRHS;
2989 return TLI->isSplatValueForTargetNode(V, DemandedElts, UndefElts, *
this,
3006 for (
unsigned i = 0; i != NumElts; ++i) {
3012 if (!DemandedElts[i])
3014 if (Scl && Scl !=
Op)
3025 for (
int i = 0; i != (int)NumElts; ++i) {
3031 if (!DemandedElts[i])
3033 if (M < (
int)NumElts)
3036 DemandedRHS.
setBit(M - NumElts);
3048 auto CheckSplatSrc = [&](
SDValue Src,
const APInt &SrcElts) {
3050 return (SrcElts.popcount() == 1) ||
3052 (SrcElts & SrcUndefs).
isZero());
3054 if (!DemandedLHS.
isZero())
3055 return CheckSplatSrc(V.getOperand(0), DemandedLHS);
3056 return CheckSplatSrc(V.getOperand(1), DemandedRHS);
3062 if (Src.getValueType().isScalableVector())
3064 uint64_t Idx = V.getConstantOperandVal(1);
3065 unsigned NumSrcElts = Src.getValueType().getVectorNumElements();
3067 APInt DemandedSrcElts = DemandedElts.
zext(NumSrcElts).
shl(Idx);
3069 UndefElts = UndefSrcElts.
extractBits(NumElts, Idx);
3080 if (Src.getValueType().isScalableVector())
3084 APInt DemandedSrcElts = DemandedElts.
zext(NumSrcElts);
3086 UndefElts = UndefSrcElts.
trunc(NumElts);
3093 EVT SrcVT = Src.getValueType();
3103 if ((
BitWidth % SrcBitWidth) == 0) {
3105 unsigned Scale =
BitWidth / SrcBitWidth;
3107 APInt ScaledDemandedElts =
3109 for (
unsigned I = 0;
I != Scale; ++
I) {
3113 SubDemandedElts &= ScaledDemandedElts;
3117 if (!SubUndefElts.
isZero())
3131 EVT VT = V.getValueType();
3141 (AllowUndefs || !UndefElts);
3147 EVT VT = V.getValueType();
3148 unsigned Opcode = V.getOpcode();
3169 SplatIdx = (UndefElts & DemandedElts).
countr_one();
3184 if (!SVN->isSplat())
3186 int Idx = SVN->getSplatIndex();
3187 int NumElts = V.getValueType().getVectorNumElements();
3188 SplatIdx = Idx % NumElts;
3189 return V.getOperand(Idx / NumElts);
3201 if (LegalTypes && !TLI->isTypeLegal(SVT)) {
3204 LegalSVT = TLI->getTypeToTransformTo(*
getContext(), LegalSVT);
3205 if (LegalSVT.
bitsLT(SVT))
3213std::optional<ConstantRange>
3215 unsigned Depth)
const {
3218 "Unknown shift node");
3220 unsigned BitWidth = V.getScalarValueSizeInBits();
3223 const APInt &ShAmt = Cst->getAPIntValue();
3225 return std::nullopt;
3230 const APInt *MinAmt =
nullptr, *MaxAmt =
nullptr;
3231 for (
unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
3232 if (!DemandedElts[i])
3236 MinAmt = MaxAmt =
nullptr;
3239 const APInt &ShAmt = SA->getAPIntValue();
3241 return std::nullopt;
3242 if (!MinAmt || MinAmt->
ugt(ShAmt))
3244 if (!MaxAmt || MaxAmt->ult(ShAmt))
3247 assert(((!MinAmt && !MaxAmt) || (MinAmt && MaxAmt)) &&
3248 "Failed to find matching min/max shift amounts");
3249 if (MinAmt && MaxAmt)
3259 return std::nullopt;
3262std::optional<unsigned>
3264 unsigned Depth)
const {
3267 "Unknown shift node");
3268 if (std::optional<ConstantRange> AmtRange =
3270 if (
const APInt *ShAmt = AmtRange->getSingleElement())
3271 return ShAmt->getZExtValue();
3272 return std::nullopt;
3275std::optional<unsigned>
3277 EVT VT = V.getValueType();
3284std::optional<unsigned>
3286 unsigned Depth)
const {
3289 "Unknown shift node");
3290 if (std::optional<ConstantRange> AmtRange =
3292 return AmtRange->getUnsignedMin().getZExtValue();
3293 return std::nullopt;
3296std::optional<unsigned>
3298 EVT VT = V.getValueType();
3305std::optional<unsigned>
3307 unsigned Depth)
const {
3310 "Unknown shift node");
3311 if (std::optional<ConstantRange> AmtRange =
3313 return AmtRange->getUnsignedMax().getZExtValue();
3314 return std::nullopt;
3317std::optional<unsigned>
3319 EVT VT = V.getValueType();
3330 EVT VT =
Op.getValueType();
3345 unsigned Depth)
const {
3346 unsigned BitWidth =
Op.getScalarValueSizeInBits();
3350 if (
auto OptAPInt =
Op->bitcastToAPInt()) {
3360 assert((!
Op.getValueType().isScalableVector() || NumElts == 1) &&
3361 "DemandedElts for scalable vectors must be 1 to represent all lanes");
3362 assert((!
Op.getValueType().isFixedLengthVector() ||
3363 NumElts ==
Op.getValueType().getVectorNumElements()) &&
3364 "Unexpected vector size");
3369 unsigned Opcode =
Op.getOpcode();
3377 "Expected SPLAT_VECTOR implicit truncation");
3384 unsigned ScalarSize =
Op.getOperand(0).getScalarValueSizeInBits();
3386 "Expected SPLAT_VECTOR_PARTS scalars to cover element width");
3393 const APInt &Step =
Op.getConstantOperandAPInt(0);
3402 const APInt MinNumElts =
3408 .
umul_ov(MinNumElts, Overflow);
3412 const APInt MaxValue = (MaxNumElts - 1).
umul_ov(Step, Overflow);
3420 assert(!
Op.getValueType().isScalableVector());
3423 for (
unsigned i = 0, e =
Op.getNumOperands(); i != e; ++i) {
3424 if (!DemandedElts[i])
3433 "Expected BUILD_VECTOR implicit truncation");
3457 assert(!
Op.getValueType().isScalableVector());
3460 APInt DemandedLHS, DemandedRHS;
3464 DemandedLHS, DemandedRHS))
3469 if (!!DemandedLHS) {
3477 if (!!DemandedRHS) {
3486 const APInt &Multiplier =
Op.getConstantOperandAPInt(0);
3491 if (
Op.getValueType().isScalableVector())
3495 EVT SubVectorVT =
Op.getOperand(0).getValueType();
3497 unsigned NumSubVectors =
Op.getNumOperands();
3498 for (
unsigned i = 0; i != NumSubVectors; ++i) {
3500 DemandedElts.
extractBits(NumSubVectorElts, i * NumSubVectorElts);
3501 if (!!DemandedSub) {
3513 if (
Op.getValueType().isScalableVector())
3520 unsigned NumSubElts =
Sub.getValueType().getVectorNumElements();
3522 APInt DemandedSrcElts = DemandedElts;
3523 DemandedSrcElts.
clearBits(Idx, Idx + NumSubElts);
3526 if (!!DemandedSubElts) {
3531 if (!!DemandedSrcElts) {
3541 APInt DemandedSrcElts;
3542 if (Src.getValueType().isScalableVector())
3543 DemandedSrcElts =
APInt(1, 1);
3546 unsigned NumSrcElts = Src.getValueType().getVectorNumElements();
3547 DemandedSrcElts = DemandedElts.
zext(NumSrcElts).
shl(Idx);
3553 if (
Op.getValueType().isScalableVector())
3557 if (DemandedElts != 1)
3568 if (
Op.getValueType().isScalableVector())
3588 if ((
BitWidth % SubBitWidth) == 0) {
3595 unsigned SubScale =
BitWidth / SubBitWidth;
3596 APInt SubDemandedElts(NumElts * SubScale, 0);
3597 for (
unsigned i = 0; i != NumElts; ++i)
3598 if (DemandedElts[i])
3599 SubDemandedElts.
setBit(i * SubScale);
3601 for (
unsigned i = 0; i != SubScale; ++i) {
3604 unsigned Shifts = IsLE ? i : SubScale - 1 - i;
3605 Known.
insertBits(Known2, SubBitWidth * Shifts);
3610 if ((SubBitWidth %
BitWidth) == 0) {
3611 assert(
Op.getValueType().isVector() &&
"Expected bitcast to vector");
3616 unsigned SubScale = SubBitWidth /
BitWidth;
3617 APInt SubDemandedElts =
3622 for (
unsigned i = 0; i != NumElts; ++i)
3623 if (DemandedElts[i]) {
3624 unsigned Shifts = IsLE ? i : NumElts - 1 - i;
3655 bool SelfMultiply =
Op.getOperand(0) ==
Op.getOperand(1);
3659 Op.getOperand(0), DemandedElts,
false,
Depth + 1);
3665 if (
Op->getFlags().hasNoSignedWrap() &&
3666 Op.getOperand(0) ==
Op.getOperand(1) &&
3693 unsigned SignBits1 =
3697 unsigned SignBits0 =
3703 assert((
Op.getResNo() == 0 ||
Op.getResNo() == 1) &&
"Unknown result");
3706 bool SelfMultiply =
Op.getOperand(0) ==
Op.getOperand(1);
3707 if (
Op.getResNo() == 0)
3714 assert((
Op.getResNo() == 0 ||
Op.getResNo() == 1) &&
"Unknown result");
3717 bool SelfMultiply =
Op.getOperand(0) ==
Op.getOperand(1);
3718 if (
Op.getResNo() == 0)
3771 if (
Op.getResNo() != 1)
3777 if (TLI->getBooleanContents(
Op.getValueType().isVector(),
false) ==
3786 unsigned OpNo =
Op->isStrictFPOpcode() ? 1 : 0;
3788 if (TLI->getBooleanContents(
Op.getOperand(OpNo).getValueType()) ==
3798 bool NUW =
Op->getFlags().hasNoUnsignedWrap();
3799 bool NSW =
Op->getFlags().hasNoSignedWrap();
3806 if (std::optional<unsigned> ShMinAmt =
3815 Op->getFlags().hasExact());
3818 if (std::optional<unsigned> ShMinAmt =
3826 Op->getFlags().hasExact());
3832 unsigned Amt =
C->getAPIntValue().urem(
BitWidth);
3847 unsigned Amt =
C->getAPIntValue().urem(
BitWidth);
3853 DemandedElts,
Depth + 1);
3874 assert((
Op.getResNo() == 0 ||
Op.getResNo() == 1) &&
"Unknown result");
3877 unsigned LoBits =
Op.getOperand(0).getScalarValueSizeInBits();
3878 unsigned HiBits =
Op.getOperand(1).getScalarValueSizeInBits();
3881 Known = Known2.
concat(Known);
3895 if (
Op.getResNo() == 0)
3926 unsigned MinRedundantSignBits =
3930 Known =
Range.toKnownBits();
3966 const Constant *Cst = TLI->getTargetConstantFromLoad(LD);
3971 !
Op.getValueType().isScalableVector()) {
3984 for (
unsigned i = 0; i != NumElts; ++i) {
3985 if (!DemandedElts[i])
3995 APInt Value = CFP->getValueAPF().bitcastToAPInt();
4014 }
else if (
Op.getResNo() == 0) {
4015 unsigned ScalarMemorySize = LD->getMemoryVT().getScalarSizeInBits();
4016 KnownBits KnownScalarMemory(ScalarMemorySize);
4017 if (
const MDNode *MD = LD->getRanges())
4028 Known = KnownScalarMemory;
4035 if (
Op.getValueType().isScalableVector())
4037 EVT InVT =
Op.getOperand(0).getValueType();
4049 if (
Op.getValueType().isScalableVector())
4051 EVT InVT =
Op.getOperand(0).getValueType();
4067 if (
Op.getValueType().isScalableVector())
4069 EVT InVT =
Op.getOperand(0).getValueType();
4104 Known.
Zero |= (~InMask);
4105 Known.
One &= (~Known.Zero);
4125 if ((NoFPClass & NegativeTestMask) == NegativeTestMask) {
4131 if ((NoFPClass & PositiveTestMask) == PositiveTestMask) {
4148 Op.getOpcode() ==
ISD::ADD, Flags.hasNoSignedWrap(),
4149 Flags.hasNoUnsignedWrap(), Known, Known2);
4151 if (
Op.getOpcode() ==
ISD::ADD &&
Op.getOperand(0) ==
Op.getOperand(1) &&
4161 if (
Op.getResNo() == 1) {
4163 if (TLI->getBooleanContents(
Op.getOperand(0).getValueType()) ==
4172 "We only compute knownbits for the difference here.");
4179 Borrow = Borrow.
trunc(1);
4193 if (
Op.getResNo() == 1) {
4195 if (TLI->getBooleanContents(
Op.getOperand(0).getValueType()) ==
4204 assert(
Op.getResNo() == 0 &&
"We only compute knownbits for the sum here.");
4214 Carry = Carry.
trunc(1);
4250 const unsigned Index =
Op.getConstantOperandVal(1);
4251 const unsigned EltBitWidth =
Op.getValueSizeInBits();
4258 Known = Known.
trunc(EltBitWidth);
4274 Known = Known.
trunc(EltBitWidth);
4280 if (ConstEltNo && ConstEltNo->getAPIntValue().ult(NumSrcElts))
4290 if (
Op.getValueType().isScalableVector())
4299 bool DemandedVal =
true;
4300 APInt DemandedVecElts = DemandedElts;
4302 if (CEltNo && CEltNo->getAPIntValue().ult(NumElts)) {
4303 unsigned EltIdx = CEltNo->getZExtValue();
4304 DemandedVal = !!DemandedElts[EltIdx];
4312 if (!!DemandedVecElts) {
4330 Known = Known2.
abs();
4363 if (CstLow && CstHigh) {
4368 const APInt &ValueHigh = CstHigh->getAPIntValue();
4369 if (ValueLow.
sle(ValueHigh)) {
4372 unsigned MinSignBits = std::min(LowSignBits, HighSignBits);
4395 if (IsMax && CstLow) {
4425 if (
Op.getResNo() == 0) {
4427 unsigned ScalarMemorySize = AT->getMemoryVT().getScalarSizeInBits();
4428 KnownBits KnownScalarMemory(ScalarMemorySize);
4429 if (
const MDNode *MD = AT->getRanges())
4432 switch (AT->getExtensionType()) {
4440 switch (TLI->getExtendForAtomicOps()) {
4453 Known = KnownScalarMemory;
4461 if (
Op.getResNo() == 1) {
4466 if (TLI->getBooleanContents(
Op.getValueType().isVector(),
false) ==
4487 if (
Op.getResNo() == 0) {
4489 unsigned MemBits = AT->getMemoryVT().getScalarSizeInBits();
4511 if (
Op.getValueType().isScalableVector())
4515 TLI->computeKnownBitsForTargetNode(
Op, Known, DemandedElts, *
this,
Depth);
4649 unsigned Depth)
const {
4663 const APInt &DemandedElts,
4664 bool OrZero,
unsigned Depth)
const {
4670 [[maybe_unused]]
unsigned NumElts = DemandedElts.
getBitWidth();
4672 "DemandedElts for scalable vectors must be 1 to represent all lanes");
4675 "Unexpected vector size");
4679 return (OrZero && V.isZero()) || V.isPowerOf2();
4690 auto *C = dyn_cast<ConstantSDNode>(P.value());
4691 return !DemandedElts[P.index()] || (C && IsPowerOfTwoOrZero(C));
4699 if (IsPowerOfTwoOrZero(
C))
4717 APInt DemandedSrcElts =
4718 ConstEltNo && ConstEltNo->getAPIntValue().
ult(NumSrcElts)
4741 if (
C &&
C->getAPIntValue() == 1)
4752 if (
C &&
C->getAPIntValue().isSignMask())
4797 APInt DemandedLHS, DemandedRHS;
4801 DemandedLHS, DemandedRHS))
4825 return C1->getValueAPF().getExactLog2Abs() >= 0;
4834 EVT VT =
Op.getValueType();
4846 unsigned Depth)
const {
4847 EVT VT =
Op.getValueType();
4852 unsigned FirstAnswer = 1;
4855 "DemandedElts for scalable vectors must be 1 to represent all lanes");
4858 const APInt &Val =
C->getAPIntValue();
4868 unsigned Opcode =
Op.getOpcode();
4873 return VTBits-Tmp+1;
4887 unsigned NumSrcBits =
Op.getOperand(0).getValueSizeInBits();
4889 if (NumSrcSignBits > (NumSrcBits - VTBits))
4890 return NumSrcSignBits - (NumSrcBits - VTBits);
4896 for (
unsigned i = 0, e =
Op.getNumOperands(); (i < e) && (Tmp > 1); ++i) {
4897 if (!DemandedElts[i])
4904 APInt T =
C->getAPIntValue().trunc(VTBits);
4905 Tmp2 =
T.getNumSignBits();
4909 if (
SrcOp.getValueSizeInBits() != VTBits) {
4911 "Expected BUILD_VECTOR implicit truncation");
4912 unsigned ExtraBits =
SrcOp.getValueSizeInBits() - VTBits;
4913 Tmp2 = (Tmp2 > ExtraBits ? Tmp2 - ExtraBits : 1);
4916 Tmp = std::min(Tmp, Tmp2);
4927 Tmp = std::min(Tmp, Tmp2);
4934 APInt DemandedLHS, DemandedRHS;
4938 DemandedLHS, DemandedRHS))
4941 Tmp = std::numeric_limits<unsigned>::max();
4944 if (!!DemandedRHS) {
4946 Tmp = std::min(Tmp, Tmp2);
4951 assert(Tmp <= VTBits &&
"Failed to determine minimum sign bits");
4967 if (VTBits == SrcBits)
4973 if ((SrcBits % VTBits) == 0) {
4976 unsigned Scale = SrcBits / VTBits;
4977 APInt SrcDemandedElts =
4987 for (
unsigned i = 0; i != NumElts; ++i)
4988 if (DemandedElts[i]) {
4989 unsigned SubOffset = i % Scale;
4990 SubOffset = (IsLE ? ((Scale - 1) - SubOffset) : SubOffset);
4991 SubOffset = SubOffset * VTBits;
4992 if (Tmp <= SubOffset)
4994 Tmp2 = std::min(Tmp2, Tmp - SubOffset);
5004 return VTBits - Tmp + 1;
5006 Tmp = VTBits -
Op.getOperand(0).getScalarValueSizeInBits();
5013 return std::max(Tmp, Tmp2);
5018 EVT SrcVT = Src.getValueType();
5026 if (std::optional<unsigned> ShAmt =
5028 Tmp = std::min(Tmp + *ShAmt, VTBits);
5031 if (std::optional<ConstantRange> ShAmtRange =
5033 unsigned MaxShAmt = ShAmtRange->getUnsignedMax().getZExtValue();
5034 unsigned MinShAmt = ShAmtRange->getUnsignedMin().getZExtValue();
5045 unsigned SizeDifference =
5047 if (SizeDifference <= MinShAmt) {
5048 Tmp = SizeDifference +
5051 return Tmp - MaxShAmt;
5057 return Tmp - MaxShAmt;
5067 FirstAnswer = std::min(Tmp, Tmp2);
5077 if (Tmp == 1)
return 1;
5079 return std::min(Tmp, Tmp2);
5082 if (Tmp == 1)
return 1;
5084 return std::min(Tmp, Tmp2);
5096 if (CstLow && CstHigh) {
5101 Tmp2 = CstHigh->getAPIntValue().getNumSignBits();
5102 return std::min(Tmp, Tmp2);
5111 return std::min(Tmp, Tmp2);
5119 return std::min(Tmp, Tmp2);
5123 if (
Op.getResNo() == 0 &&
Op.getOperand(0) ==
Op.getOperand(1))
5134 if (
Op.getResNo() != 1)
5140 if (TLI->getBooleanContents(VT.
isVector(),
false) ==
5148 unsigned OpNo =
Op->isStrictFPOpcode() ? 1 : 0;
5150 if (TLI->getBooleanContents(
Op.getOperand(OpNo).getValueType()) ==
5165 unsigned RotAmt =
C->getAPIntValue().urem(VTBits);
5169 RotAmt = (VTBits - RotAmt) % VTBits;
5173 if (Tmp > (RotAmt + 1))
return (Tmp - RotAmt);
5180 if (Tmp == 1)
return 1;
5185 if (CRHS->isAllOnes()) {
5191 if ((Known.
Zero | 1).isAllOnes())
5201 if (Tmp2 == 1)
return 1;
5205 return std::min(Tmp, Tmp2) - 1;
5208 if (Tmp2 == 1)
return 1;
5213 if (CLHS->isZero()) {
5218 if ((Known.
Zero | 1).isAllOnes())
5232 if (Tmp == 1)
return 1;
5233 return std::min(Tmp, Tmp2) - 1;
5237 if (SignBitsOp0 == 1)
5240 if (SignBitsOp1 == 1)
5242 unsigned OutValidBits =
5243 (VTBits - SignBitsOp0 + 1) + (VTBits - SignBitsOp1 + 1);
5244 return OutValidBits > VTBits ? 1 : VTBits - OutValidBits + 1;
5252 return std::min(Tmp, Tmp2);
5261 unsigned NumSrcBits =
Op.getOperand(0).getScalarValueSizeInBits();
5263 if (NumSrcSignBits > (NumSrcBits - VTBits))
5264 return NumSrcSignBits - (NumSrcBits - VTBits);
5271 const int BitWidth =
Op.getValueSizeInBits();
5272 const int Items =
Op.getOperand(0).getValueSizeInBits() /
BitWidth;
5276 const int rIndex = Items - 1 -
Op.getConstantOperandVal(1);
5291 bool DemandedVal =
true;
5292 APInt DemandedVecElts = DemandedElts;
5294 if (CEltNo && CEltNo->getAPIntValue().ult(NumElts)) {
5295 unsigned EltIdx = CEltNo->getZExtValue();
5296 DemandedVal = !!DemandedElts[EltIdx];
5299 Tmp = std::numeric_limits<unsigned>::max();
5305 Tmp = std::min(Tmp, Tmp2);
5307 if (!!DemandedVecElts) {
5309 Tmp = std::min(Tmp, Tmp2);
5311 assert(Tmp <= VTBits &&
"Failed to determine minimum sign bits");
5321 const unsigned BitWidth =
Op.getValueSizeInBits();
5322 const unsigned EltBitWidth =
Op.getOperand(0).getScalarValueSizeInBits();
5335 if (ConstEltNo && ConstEltNo->getAPIntValue().ult(NumSrcElts))
5345 APInt DemandedSrcElts;
5346 if (Src.getValueType().isScalableVector())
5347 DemandedSrcElts =
APInt(1, 1);
5350 unsigned NumSrcElts = Src.getValueType().getVectorNumElements();
5351 DemandedSrcElts = DemandedElts.
zext(NumSrcElts).
shl(Idx);
5360 Tmp = std::numeric_limits<unsigned>::max();
5361 EVT SubVectorVT =
Op.getOperand(0).getValueType();
5363 unsigned NumSubVectors =
Op.getNumOperands();
5364 for (
unsigned i = 0; (i < NumSubVectors) && (Tmp > 1); ++i) {
5366 DemandedElts.
extractBits(NumSubVectorElts, i * NumSubVectorElts);
5370 Tmp = std::min(Tmp, Tmp2);
5372 assert(Tmp <= VTBits &&
"Failed to determine minimum sign bits");
5383 unsigned NumSubElts =
Sub.getValueType().getVectorNumElements();
5385 APInt DemandedSrcElts = DemandedElts;
5386 DemandedSrcElts.
clearBits(Idx, Idx + NumSubElts);
5388 Tmp = std::numeric_limits<unsigned>::max();
5389 if (!!DemandedSubElts) {
5394 if (!!DemandedSrcElts) {
5396 Tmp = std::min(Tmp, Tmp2);
5398 assert(Tmp <= VTBits &&
"Failed to determine minimum sign bits");
5403 if (
Op.getResNo() != 0)
5407 if (
const MDNode *Ranges = LD->getRanges()) {
5408 if (DemandedElts != 1)
5413 switch (LD->getExtensionType()) {
5431 unsigned ExtType = LD->getExtensionType();
5436 Tmp = LD->getMemoryVT().getScalarSizeInBits();
5437 return VTBits - Tmp + 1;
5439 Tmp = LD->getMemoryVT().getScalarSizeInBits();
5440 return VTBits - Tmp;
5442 if (
const Constant *Cst = TLI->getTargetConstantFromLoad(LD)) {
5445 Type *CstTy = Cst->getType();
5450 for (
unsigned i = 0; i != NumElts; ++i) {
5451 if (!DemandedElts[i])
5456 Tmp = std::min(Tmp,
Value.getNumSignBits());
5460 APInt Value = CFP->getValueAPF().bitcastToAPInt();
5461 Tmp = std::min(Tmp,
Value.getNumSignBits());
5493 if (
Op.getResNo() == 0) {
5494 Tmp = AT->getMemoryVT().getScalarSizeInBits();
5500 switch (AT->getExtensionType()) {
5504 return VTBits - Tmp + 1;
5506 return VTBits - Tmp;
5511 return VTBits - Tmp + 1;
5513 return VTBits - Tmp;
5528 TLI->ComputeNumSignBitsForTargetNode(
Op, DemandedElts, *
this,
Depth);
5530 FirstAnswer = std::max(FirstAnswer, NumBits);
5541 unsigned Depth)
const {
5543 return Op.getScalarValueSizeInBits() - SignBits + 1;
5547 const APInt &DemandedElts,
5548 unsigned Depth)
const {
5550 return Op.getScalarValueSizeInBits() - SignBits + 1;
5554 unsigned Depth)
const {
5559 EVT VT =
Op.getValueType();
5567 const APInt &DemandedElts,
5569 unsigned Depth)
const {
5570 unsigned Opcode =
Op.getOpcode();
5599 for (
unsigned i = 0, e =
Op.getNumOperands(); i < e; ++i) {
5600 if (!DemandedElts[i])
5610 if (Src.getValueType().isScalableVector())
5613 unsigned NumSrcElts = Src.getValueType().getVectorNumElements();
5614 APInt DemandedSrcElts = DemandedElts.
zext(NumSrcElts).
shl(Idx);
5620 if (
Op.getValueType().isScalableVector())
5625 unsigned NumSubElts =
Sub.getValueType().getVectorNumElements();
5627 APInt DemandedSrcElts = DemandedElts;
5628 DemandedSrcElts.
clearBits(Idx, Idx + NumSubElts);
5642 EVT SrcVT = Src.getValueType();
5646 IndexC->getZExtValue());
5661 if (DemandedElts[IndexC->getZExtValue()] &&
5664 APInt InVecDemandedElts = DemandedElts;
5665 InVecDemandedElts.
clearBit(IndexC->getZExtValue());
5666 if (!!InVecDemandedElts &&
5691 APInt DemandedLHS, DemandedRHS;
5694 DemandedElts, DemandedLHS, DemandedRHS,
5697 if (!DemandedLHS.
isZero() &&
5701 if (!DemandedRHS.
isZero() &&
5749 return isGuaranteedNotToBeUndefOrPoison(V, DemandedElts,
5750 PoisonOnly, Depth + 1);
5762 return TLI->isGuaranteedNotToBeUndefOrPoisonForTargetNode(
5775 return isGuaranteedNotToBeUndefOrPoison(V, PoisonOnly, Depth + 1);
5781 unsigned Depth)
const {
5782 EVT VT =
Op.getValueType();
5792 unsigned Depth)
const {
5793 if (ConsiderFlags &&
Op->hasPoisonGeneratingFlags())
5796 unsigned Opcode =
Op.getOpcode();
5877 if (
Op.getOperand(0).getValueType().isInteger())
5884 unsigned CCOp = Opcode ==
ISD::SETCC ? 2 : 4;
5886 return (
unsigned)CCCode & 0x10U;
5935 EVT VecVT =
Op.getOperand(0).getValueType();
5944 for (
auto [Idx, Elt] :
enumerate(SVN->getMask()))
5945 if (Elt < 0 && DemandedElts[Idx])
5957 return TLI->canCreateUndefOrPoisonForTargetNode(
5967 unsigned Opcode =
Op.getOpcode();
5969 return Op->getFlags().hasDisjoint() ||
5982 unsigned Depth)
const {
5983 EVT VT =
Op.getValueType();
5996 bool SNaN,
unsigned Depth)
const {
5997 assert(!DemandedElts.
isZero() &&
"No demanded elements");
6000 if (
Op->getFlags().hasNoNaNs())
6008 return !
C->getValueAPF().isNaN() ||
6009 (SNaN && !
C->getValueAPF().isSignaling());
6012 unsigned Opcode =
Op.getOpcode();
6114 EVT SrcVT = Src.getValueType();
6118 Idx->getZExtValue());
6125 if (Src.getValueType().isFixedLengthVector()) {
6126 unsigned Idx =
Op.getConstantOperandVal(1);
6127 unsigned NumSrcElts = Src.getValueType().getVectorNumElements();
6128 APInt DemandedSrcElts = DemandedElts.
zext(NumSrcElts).
shl(Idx);
6138 unsigned Idx =
Op.getConstantOperandVal(2);
6144 APInt DemandedMask =
6146 APInt DemandedSrcElts = DemandedElts & ~DemandedMask;
6149 bool NeverNaN =
true;
6150 if (!DemandedSrcElts.
isZero())
6153 if (NeverNaN && !DemandedSubElts.
isZero())
6162 unsigned NumElts =
Op.getNumOperands();
6163 for (
unsigned I = 0;
I != NumElts; ++
I)
6164 if (DemandedElts[
I] &&
6183 return TLI->isKnownNeverNaNForTargetNode(
Op, DemandedElts, *
this, SNaN,
6192 assert(
Op.getValueType().isFloatingPoint() &&
6193 "Floating point type expected");
6201 EVT VT =
Op.getValueType();
6214 unsigned Depth)
const {
6218 EVT OpVT =
Op.getValueType();
6221 assert(!
Op.getValueType().isFloatingPoint() &&
6222 "Floating point types unsupported - use isKnownNeverZeroFloat");
6235 switch (
Op.getOpcode()) {
6242 auto *C = dyn_cast<ConstantSDNode>(P.value());
6243 return !DemandedElts[P.index()] || (C && IsNeverZero(C));
6270 if (ConstEltNo && ConstEltNo->getAPIntValue().ult(NumSrcElts))
6287 if (
Op->getFlags().hasNoSignedWrap() ||
Op->getFlags().hasNoUnsignedWrap())
6292 if (ValKnown.
One[0])
6304 if (
Op.getValueType().isScalableVector())
6312 APInt DemandedLHS, DemandedRHS;
6314 assert(NumElts == SVN->getMask().size() &&
"Unexpected vector size");
6316 DemandedLHS, DemandedRHS))
6319 return (!DemandedLHS ||
6377 if (
Op->getFlags().hasExact())
6395 if (
Op->getFlags().hasExact())
6400 if (
Op->getFlags().hasNoUnsignedWrap())
6418 if (
Op->getFlags().hasNoSignedWrap() ||
Op->getFlags().hasNoUnsignedWrap())
6429 const APInt &Multiplier =
Op.getConstantOperandAPInt(0);
6443 return !C1->isNegative();
6445 switch (
Op.getOpcode()) {
6459 assert(
Use.getValueType().isFloatingPoint());
6461 if (
User->getFlags().hasNoSignedZeros())
6466 switch (
User->getOpcode()) {
6474 return OperandNo == 0;
6492 if (
Op->getFlags().hasNoSignedZeros())
6497 if (
Op->use_size() > 2)
6500 [&](
const SDUse &
Use) { return canIgnoreSignBitOfZero(Use); });
6505 if (
A ==
B)
return true;
6510 if (CA->isZero() && CB->isZero())
return true;
6545 NotOperand = NotOperand->getOperand(0);
6547 if (
Other == NotOperand)
6550 return NotOperand ==
Other->getOperand(0) ||
6551 NotOperand ==
Other->getOperand(1);
6557 A =
A->getOperand(0);
6560 B =
B->getOperand(0);
6563 return MatchNoCommonBitsPattern(
A->getOperand(0),
A->getOperand(1),
B) ||
6564 MatchNoCommonBitsPattern(
A->getOperand(1),
A->getOperand(0),
B);
6570 assert(
A.getValueType() ==
B.getValueType() &&
6571 "Values must have the same type");
6593 "BUILD_VECTOR cannot be used with scalable types");
6595 "Incorrect element count in BUILD_VECTOR!");
6603 bool IsIdentity =
true;
6604 for (
int i = 0; i !=
NumOps; ++i) {
6607 (IdentitySrc &&
Ops[i].getOperand(0) != IdentitySrc) ||
6609 Ops[i].getConstantOperandAPInt(1) != i) {
6613 IdentitySrc =
Ops[i].getOperand(0);
6626 assert(!
Ops.empty() &&
"Can't concatenate an empty list of vectors!");
6629 return Ops[0].getValueType() ==
Op.getValueType();
6631 "Concatenation of vectors with inconsistent value types!");
6634 "Incorrect element count in vector concatenation!");
6636 if (
Ops.size() == 1)
6647 bool IsIdentity =
true;
6648 for (
unsigned i = 0, e =
Ops.size(); i != e; ++i) {
6650 unsigned IdentityIndex = i *
Op.getValueType().getVectorMinNumElements();
6652 Op.getOperand(0).getValueType() != VT ||
6653 (IdentitySrc &&
Op.getOperand(0) != IdentitySrc) ||
6654 Op.getConstantOperandVal(1) != IdentityIndex) {
6658 assert((!IdentitySrc || IdentitySrc ==
Op.getOperand(0)) &&
6659 "Unexpected identity source vector for concat of extracts");
6660 IdentitySrc =
Op.getOperand(0);
6663 assert(IdentitySrc &&
"Failed to set source vector of extracts");
6679 EVT OpVT =
Op.getValueType();
6695 SVT = (SVT.
bitsLT(
Op.getValueType()) ?
Op.getValueType() : SVT);
6719 if (
SDNode *E = FindNodeOrInsertPos(
ID,
DL, IP))
6722 auto *
N = newSDNode<SDNode>(Opcode,
DL.getIROrder(),
DL.getDebugLoc(), VTs);
6723 CSEMap.InsertNode(
N, IP);
6735 Flags = Inserter->getFlags();
6736 return getNode(Opcode,
DL, VT, N1, Flags);
6788 "STEP_VECTOR can only be used with scalable types");
6791 "Unexpected step operand");
6812 "Invalid FP cast!");
6816 "Vector element count mismatch!");
6834 "Invalid SIGN_EXTEND!");
6836 "SIGN_EXTEND result type type should be vector iff the operand "
6841 "Vector element count mismatch!");
6864 unsigned NumSignExtBits =
6875 "Invalid ZERO_EXTEND!");
6877 "ZERO_EXTEND result type type should be vector iff the operand "
6882 "Vector element count mismatch!");
6920 "Invalid ANY_EXTEND!");
6922 "ANY_EXTEND result type type should be vector iff the operand "
6927 "Vector element count mismatch!");
6952 "Invalid TRUNCATE!");
6954 "TRUNCATE result type type should be vector iff the operand "
6959 "Vector element count mismatch!");
6986 assert(VT.
isVector() &&
"This DAG node is restricted to vector types.");
6988 "The input must be the same size or smaller than the result.");
6991 "The destination vector type must have fewer lanes than the input.");
7001 "BSWAP types must be a multiple of 16 bits!");
7015 "Cannot BITCAST between types of different sizes!");
7028 "Illegal SCALAR_TO_VECTOR node!");
7089 "Wrong operand type!");
7096 if (VT != MVT::Glue) {
7100 if (
SDNode *E = FindNodeOrInsertPos(
ID,
DL, IP)) {
7101 E->intersectFlagsWith(Flags);
7105 N = newSDNode<SDNode>(Opcode,
DL.getIROrder(),
DL.getDebugLoc(), VTs);
7107 createOperands(
N,
Ops);
7108 CSEMap.InsertNode(
N, IP);
7110 N = newSDNode<SDNode>(Opcode,
DL.getIROrder(),
DL.getDebugLoc(), VTs);
7111 createOperands(
N,
Ops);
7145 if (!C2.getBoolValue())
7149 if (!C2.getBoolValue())
7153 if (!C2.getBoolValue())
7157 if (!C2.getBoolValue())
7183 return std::nullopt;
7188 bool IsUndef1,
const APInt &C2,
7190 if (!(IsUndef1 || IsUndef2))
7198 return std::nullopt;
7206 if (!TLI->isOffsetFoldingLegal(GA))
7211 int64_t
Offset = C2->getSExtValue();
7231 assert(
Ops.size() == 2 &&
"Div/rem should have 2 operands");
7238 [](
SDValue V) { return V.isUndef() ||
7239 isNullConstant(V); });
7277 const APInt &Val =
C->getAPIntValue();
7281 C->isTargetOpcode(),
C->isOpaque());
7288 C->isTargetOpcode(),
C->isOpaque());
7293 C->isTargetOpcode(),
C->isOpaque());
7295 C->isTargetOpcode(),
C->isOpaque());
7319 C->isTargetOpcode(),
C->isOpaque());
7345 if (VT == MVT::f16 &&
C->getValueType(0) == MVT::i16)
7347 if (VT == MVT::f32 &&
C->getValueType(0) == MVT::i32)
7349 if (VT == MVT::f64 &&
C->getValueType(0) == MVT::i64)
7351 if (VT == MVT::f128 &&
C->getValueType(0) == MVT::i128)
7412 return getConstant(V.bitcastToAPInt().getZExtValue(),
DL, VT);
7415 if (VT == MVT::i16 &&
C->getValueType(0) == MVT::f16)
7418 if (VT == MVT::i16 &&
C->getValueType(0) == MVT::bf16)
7421 if (VT == MVT::i32 &&
C->getValueType(0) == MVT::f32)
7424 if (VT == MVT::i64 &&
C->getValueType(0) == MVT::f64)
7425 return getConstant(V.bitcastToAPInt().getZExtValue(),
DL, VT);
7442 if (C1->isOpaque() || C2->isOpaque())
7445 std::optional<APInt> FoldAttempt =
7446 FoldValue(Opcode, C1->getAPIntValue(), C2->getAPIntValue());
7452 "Can't fold vectors ops with scalar operands");
7460 if (TLI->isCommutativeBinOp(Opcode))
7476 const APInt &Val = C1->getAPIntValue();
7477 return SignExtendInReg(Val, VT);
7490 ScalarOps.
push_back(SignExtendInReg(Val, OpVT));
7498 SignExtendInReg(
Ops[0].getConstantOperandAPInt(0),
7509 if (C1 && C2 && C3) {
7510 if (C1->isOpaque() || C2->isOpaque() || C3->isOpaque())
7512 const APInt &V1 = C1->getAPIntValue(), &V2 = C2->getAPIntValue(),
7513 &V3 = C3->getAPIntValue();
7529 if (C1 && C2 && C3) {
7550 Ops[0].getValueType() == VT &&
Ops[1].getValueType() == VT &&
7563 if (BV1->getConstantRawBits(IsLE, EltBits, RawBits1, UndefElts1) &&
7564 BV2->getConstantRawBits(IsLE, EltBits, RawBits2, UndefElts2)) {
7568 Opcode, RawBits1[
I], UndefElts1[
I], RawBits2[
I], UndefElts2[
I]);
7579 BVEltVT = BV1->getOperand(0).getValueType();
7582 BVEltVT = BV2->getOperand(0).getValueType();
7588 DstBits, RawBits, DstUndefs,
7591 for (
unsigned I = 0, E = DstBits.
size();
I != E; ++
I) {
7609 ?
Ops[0].getConstantOperandAPInt(0) * RHSVal
7610 :
Ops[0].getConstantOperandAPInt(0) << RHSVal;
7615 auto IsScalarOrSameVectorSize = [NumElts](
const SDValue &
Op) {
7616 return !
Op.getValueType().isVector() ||
7617 Op.getValueType().getVectorElementCount() == NumElts;
7620 auto IsBuildVectorSplatVectorOrUndef = [](
const SDValue &
Op) {
7646 LegalSVT = TLI->getTypeToTransformTo(*
getContext(), LegalSVT);
7658 for (
unsigned I = 0;
I != NumVectorElts;
I++) {
7661 EVT InSVT =
Op.getValueType().getScalarType();
7704 if (LegalSVT != SVT)
7705 ScalarResult =
getNode(ExtendCode,
DL, LegalSVT, ScalarResult);
7719 if (
Ops.size() != 2)
7730 if (N1CFP && N2CFP) {
7781 if (N1C && N1C->getValueAPF().isNegZero() && N2.
isUndef())
7804 if (SrcEltVT == DstEltVT)
7812 if (SrcBitSize == DstBitSize) {
7817 if (
Op.getValueType() != SrcEltVT)
7860 for (
unsigned I = 0, E = RawBits.
size();
I != E; ++
I) {
7861 if (UndefElements[
I])
7882 ID.AddInteger(
A.value());
7885 if (
SDNode *E = FindNodeOrInsertPos(
ID,
DL, IP))
7889 newSDNode<AssertAlignSDNode>(
DL.getIROrder(),
DL.getDebugLoc(), VTs,
A);
7890 createOperands(
N, {Val});
7892 CSEMap.InsertNode(
N, IP);
7904 Flags = Inserter->getFlags();
7905 return getNode(Opcode,
DL, VT, N1, N2, Flags);
7910 if (!TLI->isCommutativeBinOp(Opcode))
7919 if ((N1C && !N2C) || (N1CFP && !N2CFP))
7933 "Operand is DELETED_NODE!");
7949 N2.
getValueType() == MVT::Other &&
"Invalid token factor!");
7953 if (N1 == N2)
return N1;
7969 assert(VT.
isInteger() &&
"This operator does not apply to FP types!");
7971 N1.
getValueType() == VT &&
"Binary operator types must match!");
7974 if (N2CV && N2CV->
isZero())
7984 assert(VT.
isInteger() &&
"This operator does not apply to FP types!");
7986 N1.
getValueType() == VT &&
"Binary operator types must match!");
7996 if (N2CV && N2CV->
isZero())
8010 assert(VT.
isInteger() &&
"This operator does not apply to FP types!");
8012 N1.
getValueType() == VT &&
"Binary operator types must match!");
8015 if (N2CV && N2CV->
isZero())
8019 const APInt &N2CImm = N2C->getAPIntValue();
8033 assert(VT.
isInteger() &&
"This operator does not apply to FP types!");
8035 N1.
getValueType() == VT &&
"Binary operator types must match!");
8048 "Types of operands of UCMP/SCMP must match");
8050 "Operands and return type of must both be scalars or vectors");
8054 "Result and operands must have the same number of elements");
8060 assert(VT.
isInteger() &&
"This operator does not apply to FP types!");
8062 N1.
getValueType() == VT &&
"Binary operator types must match!");
8066 assert(VT.
isInteger() &&
"This operator does not apply to FP types!");
8068 N1.
getValueType() == VT &&
"Binary operator types must match!");
8074 assert(VT.
isInteger() &&
"This operator does not apply to FP types!");
8076 N1.
getValueType() == VT &&
"Binary operator types must match!");
8082 assert(VT.
isInteger() &&
"This operator does not apply to FP types!");
8084 N1.
getValueType() == VT &&
"Binary operator types must match!");
8095 N1.
getValueType() == VT &&
"Binary operator types must match!");
8103 "Invalid FCOPYSIGN!");
8108 const APInt &ShiftImm = N2C->getAPIntValue();
8122 "Shift operators return type must be the same as their first arg");
8124 "Shifts only work on integers");
8126 "Vector shift amounts must be in the same as their first arg");
8133 "Invalid use of small shift amount with oversized value!");
8140 if (N2CV && N2CV->
isZero())
8146 (N2C->getZExtValue() == 0 || N2C->getZExtValue() == 1) &&
8152 "AssertNoFPClass is used for a non-floating type");
8157 "FPClassTest value too large");
8166 "Cannot *_EXTEND_INREG FP types");
8168 "AssertSExt/AssertZExt type should be the vector element type "
8169 "rather than the vector type!");
8178 "Cannot *_EXTEND_INREG FP types");
8180 "SIGN_EXTEND_INREG type should be vector iff the operand "
8184 "Vector element counts must match in SIGN_EXTEND_INREG");
8186 if (
EVT == VT)
return N1;
8194 "FP_TO_*INT_SAT type should be vector iff the operand type is "
8198 "Vector element counts must match in FP_TO_*INT_SAT");
8200 "Type to saturate to must be a scalar.");
8207 "The result of EXTRACT_VECTOR_ELT must be at least as wide as the \
8208 element type of the vector.");
8230 N2C->getZExtValue() % Factor);
8239 "BUILD_VECTOR used for scalable vectors");
8262 if (N1Op2C && N2C) {
8292 assert(N2C && (
unsigned)N2C->getZExtValue() < 2 &&
"Bad EXTRACT_ELEMENT!");
8296 "Wrong types for EXTRACT_ELEMENT!");
8307 unsigned Shift = ElementSize * N2C->getZExtValue();
8308 const APInt &Val = N1C->getAPIntValue();
8315 "Extract subvector VTs must be vectors!");
8317 "Extract subvector VTs must have the same element type!");
8319 "Cannot extract a scalable vector from a fixed length vector!");
8322 "Extract subvector must be from larger vector to smaller vector!");
8323 assert(N2C &&
"Extract subvector index must be a constant");
8327 "Extract subvector overflow!");
8328 assert(N2C->getAPIntValue().getBitWidth() ==
8330 "Constant index for EXTRACT_SUBVECTOR has an invalid size");
8332 "Extract index is not a multiple of the output vector length");
8347 return N1.
getOperand(N2C->getZExtValue() / Factor);
8388 if (TLI->isCommutativeBinOp(Opcode)) {
8467 if (VT != MVT::Glue) {
8471 if (
SDNode *E = FindNodeOrInsertPos(
ID,
DL, IP)) {
8472 E->intersectFlagsWith(Flags);
8476 N = newSDNode<SDNode>(Opcode,
DL.getIROrder(),
DL.getDebugLoc(), VTs);
8478 createOperands(
N,
Ops);
8479 CSEMap.InsertNode(
N, IP);
8481 N = newSDNode<SDNode>(Opcode,
DL.getIROrder(),
DL.getDebugLoc(), VTs);
8482 createOperands(
N,
Ops);
8495 Flags = Inserter->getFlags();
8496 return getNode(Opcode,
DL, VT, N1, N2, N3, Flags);
8505 "Operand is DELETED_NODE!");
8524 "SETCC operands must have the same type!");
8526 "SETCC type should be vector iff the operand type is vector!");
8529 "SETCC vector element counts must match!");
8553 "INSERT_VECTOR_ELT vector type mismatch");
8555 "INSERT_VECTOR_ELT scalar fp/int mismatch");
8558 "INSERT_VECTOR_ELT fp scalar type mismatch");
8561 "INSERT_VECTOR_ELT int scalar size mismatch");
8607 "Dest and insert subvector source types must match!");
8609 "Insert subvector VTs must be vectors!");
8611 "Insert subvector VTs must have the same element type!");
8613 "Cannot insert a scalable vector into a fixed length vector!");
8616 "Insert subvector must be from smaller vector to larger vector!");
8618 "Insert subvector index must be constant");
8622 "Insert subvector overflow!");
8625 "Constant index for INSERT_SUBVECTOR has an invalid size");
8669 case ISD::VP_TRUNCATE:
8670 case ISD::VP_SIGN_EXTEND:
8671 case ISD::VP_ZERO_EXTEND:
8680 assert(VT == VecVT &&
"Vector and result type don't match.");
8682 "All inputs must be vectors.");
8683 assert(VecVT == PassthruVT &&
"Vector and passthru types don't match.");
8685 "Vector and mask must have same number of elements.");
8700 "Expected the second and third operands of the PARTIAL_REDUCE_MLA "
8701 "node to have the same type!");
8703 "Expected the first operand of the PARTIAL_REDUCE_MLA node to have "
8704 "the same type as its result!");
8707 "Expected the element count of the second and third operands of the "
8708 "PARTIAL_REDUCE_MLA node to be a positive integer multiple of the "
8709 "element count of the first operand and the result!");
8711 "Expected the second and third operands of the PARTIAL_REDUCE_MLA "
8712 "node to have an element type which is the same as or smaller than "
8713 "the element type of the first operand and result!");
8735 if (VT != MVT::Glue) {
8739 if (
SDNode *E = FindNodeOrInsertPos(
ID,
DL, IP)) {
8740 E->intersectFlagsWith(Flags);
8744 N = newSDNode<SDNode>(Opcode,
DL.getIROrder(),
DL.getDebugLoc(), VTs);
8746 createOperands(
N,
Ops);
8747 CSEMap.InsertNode(
N, IP);
8749 N = newSDNode<SDNode>(Opcode,
DL.getIROrder(),
DL.getDebugLoc(), VTs);
8750 createOperands(
N,
Ops);
8770 Flags = Inserter->getFlags();
8771 return getNode(Opcode,
DL, VT, N1, N2, N3, N4, Flags);
8786 Flags = Inserter->getFlags();
8787 return getNode(Opcode,
DL, VT, N1, N2, N3, N4, N5, Flags);
8804 if (FI->getIndex() < 0)
8819 assert(
C->getAPIntValue().getBitWidth() == 8);
8824 return DAG.
getConstant(Val, dl, VT,
false, IsOpaque);
8829 assert(
Value.getValueType() == MVT::i8 &&
"memset with non-byte fill value?");
8845 if (VT !=
Value.getValueType())
8858 if (Slice.Array ==
nullptr) {
8867 unsigned NumVTBytes = NumVTBits / 8;
8868 unsigned NumBytes = std::min(NumVTBytes,
unsigned(Slice.Length));
8870 APInt Val(NumVTBits, 0);
8872 for (
unsigned i = 0; i != NumBytes; ++i)
8875 for (
unsigned i = 0; i != NumBytes; ++i)
8876 Val |= (
uint64_t)(
unsigned char)Slice[i] << (NumVTBytes-i-1)*8;
8899 if (TLI->shouldPreservePtrArith(this->getMachineFunction().getFunction(),
8914 else if (Src->isAnyAdd() &&
8918 SrcDelta = Src.getConstantOperandVal(1);
8924 SrcDelta +
G->getOffset());
8940 assert(OutLoadChains.
size() &&
"Missing loads in memcpy inlining");
8941 assert(OutStoreChains.
size() &&
"Missing stores in memcpy inlining");
8943 for (
unsigned i = From; i < To; ++i) {
8945 GluedLoadChains.
push_back(OutLoadChains[i]);
8952 for (
unsigned i = From; i < To; ++i) {
8955 ST->getBasePtr(), ST->getMemoryVT(),
8956 ST->getMemOperand());
8978 std::vector<EVT> MemOps;
8979 bool DstAlignCanChange =
false;
8985 DstAlignCanChange =
true;
8987 if (!SrcAlign || Alignment > *SrcAlign)
8988 SrcAlign = Alignment;
8989 assert(SrcAlign &&
"SrcAlign must be set");
8993 bool isZeroConstant = CopyFromConstant && Slice.Array ==
nullptr;
8995 const MemOp Op = isZeroConstant
8999 *SrcAlign, isVol, CopyFromConstant);
9005 if (DstAlignCanChange) {
9006 Type *Ty = MemOps[0].getTypeForEVT(
C);
9007 Align NewAlign =
DL.getABITypeAlign(Ty);
9013 if (!
TRI->hasStackRealignment(MF))
9015 NewAlign = std::min(NewAlign, *StackAlign);
9017 if (NewAlign > Alignment) {
9021 Alignment = NewAlign;
9031 BatchAA && SrcVal &&
9039 unsigned NumMemOps = MemOps.size();
9041 for (
unsigned i = 0; i != NumMemOps; ++i) {
9046 if (VTSize >
Size) {
9049 assert(i == NumMemOps-1 && i != 0);
9050 SrcOff -= VTSize -
Size;
9051 DstOff -= VTSize -
Size;
9054 if (CopyFromConstant &&
9062 if (SrcOff < Slice.Length) {
9064 SubSlice.
move(SrcOff);
9067 SubSlice.
Array =
nullptr;
9069 SubSlice.
Length = VTSize;
9072 if (
Value.getNode()) {
9076 DstPtrInfo.
getWithOffset(DstOff), Alignment, MMOFlags, NewAAInfo);
9081 if (!Store.getNode()) {
9090 bool isDereferenceable =
9093 if (isDereferenceable)
9108 DstPtrInfo.
getWithOffset(DstOff), VT, Alignment, MMOFlags, NewAAInfo);
9118 unsigned NumLdStInMemcpy = OutStoreChains.
size();
9120 if (NumLdStInMemcpy) {
9126 for (
unsigned i = 0; i < NumLdStInMemcpy; ++i) {
9132 if (NumLdStInMemcpy <= GluedLdStLimit) {
9134 NumLdStInMemcpy, OutLoadChains,
9137 unsigned NumberLdChain = NumLdStInMemcpy / GluedLdStLimit;
9138 unsigned RemainingLdStInMemcpy = NumLdStInMemcpy % GluedLdStLimit;
9139 unsigned GlueIter = 0;
9142 if (RemainingLdStInMemcpy) {
9144 DAG, dl, OutChains, NumLdStInMemcpy - RemainingLdStInMemcpy,
9145 NumLdStInMemcpy, OutLoadChains, OutStoreChains);
9148 for (
unsigned cnt = 0; cnt < NumberLdChain; ++cnt) {
9149 unsigned IndexFrom = NumLdStInMemcpy - RemainingLdStInMemcpy -
9150 GlueIter - GluedLdStLimit;
9151 unsigned IndexTo = NumLdStInMemcpy - RemainingLdStInMemcpy - GlueIter;
9153 OutLoadChains, OutStoreChains);
9154 GlueIter += GluedLdStLimit;
9165 bool isVol,
bool AlwaysInline,
9179 std::vector<EVT> MemOps;
9180 bool DstAlignCanChange =
false;
9186 DstAlignCanChange =
true;
9188 if (!SrcAlign || Alignment > *SrcAlign)
9189 SrcAlign = Alignment;
9190 assert(SrcAlign &&
"SrcAlign must be set");
9200 if (DstAlignCanChange) {
9201 Type *Ty = MemOps[0].getTypeForEVT(
C);
9202 Align NewAlign =
DL.getABITypeAlign(Ty);
9208 if (!
TRI->hasStackRealignment(MF))
9210 NewAlign = std::min(NewAlign, *StackAlign);
9212 if (NewAlign > Alignment) {
9216 Alignment = NewAlign;
9230 unsigned NumMemOps = MemOps.size();
9231 for (
unsigned i = 0; i < NumMemOps; i++) {
9236 bool isDereferenceable =
9239 if (isDereferenceable)
9245 SrcPtrInfo.
getWithOffset(SrcOff), *SrcAlign, SrcMMOFlags, NewAAInfo);
9252 for (
unsigned i = 0; i < NumMemOps; i++) {
9258 Chain, dl, LoadValues[i],
9260 DstPtrInfo.
getWithOffset(DstOff), Alignment, MMOFlags, NewAAInfo);
9300 std::vector<EVT> MemOps;
9301 bool DstAlignCanChange =
false;
9308 DstAlignCanChange =
true;
9315 MemOp::Set(
Size, DstAlignCanChange, Alignment, IsZeroVal, isVol),
9320 if (DstAlignCanChange) {
9323 Align NewAlign =
DL.getABITypeAlign(Ty);
9329 if (!
TRI->hasStackRealignment(MF))
9331 NewAlign = std::min(NewAlign, *StackAlign);
9333 if (NewAlign > Alignment) {
9337 Alignment = NewAlign;
9343 unsigned NumMemOps = MemOps.size();
9348 LargestVT = MemOps[0];
9349 for (
unsigned i = 1; i < NumMemOps; i++)
9350 if (MemOps[i].bitsGT(LargestVT))
9351 LargestVT = MemOps[i];
9359 for (
unsigned i = 0; i < NumMemOps; i++) {
9364 assert(
Size > 0 &&
"Target specified more stores than needed in "
9365 "findOptimalMemOpLowering");
9366 if (VTSize >
Size) {
9369 assert(i == NumMemOps-1 && i != 0);
9370 DstOff -= VTSize -
Size;
9377 if (VT.
bitsLT(LargestVT)) {
9397 assert(
Value.getValueType() == VT &&
"Value with wrong type.");
9408 if (VTSize >
Size) {
9417 assert(
Size == 0 &&
"Target's findOptimalMemOpLowering did not specify "
9418 "stores that exactly cover the memset size");
9435 bool AllowReturnsFirstArg) {
9441 AllowReturnsFirstArg &&
9445static std::pair<SDValue, SDValue>
9452 if (LCImpl == RTLIB::Unsupported)
9464 CI->
getType(), Callee, std::move(Args))
9477 RTLIB::STRCMP,
this, TLI);
9487 RTLIB::STRSTR,
this, TLI);
9503 RTLIB::MEMCCPY,
this, TLI);
9506std::pair<SDValue, SDValue>
9515 RTLIB::MEMCMP,
this, TLI);
9525 RTLIB::STRCPY,
this, TLI);
9536 RTLIB::STRLEN,
this, TLI);
9541 Align Alignment,
bool isVol,
bool AlwaysInline,
const CallInst *CI,
9550 if (ConstantSize->
isZero())
9554 *
this, dl, Chain, Dst, Src, ConstantSize->
getZExtValue(), Alignment,
9555 isVol,
false, DstPtrInfo, SrcPtrInfo, AAInfo, BatchAA);
9556 if (Result.getNode())
9563 SDValue Result = TSI->EmitTargetCodeForMemcpy(
9564 *
this, dl, Chain, Dst, Src,
Size, Alignment, isVol, AlwaysInline,
9565 DstPtrInfo, SrcPtrInfo);
9566 if (Result.getNode())
9573 assert(ConstantSize &&
"AlwaysInline requires a constant size!");
9575 *
this, dl, Chain, Dst, Src, ConstantSize->
getZExtValue(), Alignment,
9576 isVol,
true, DstPtrInfo, SrcPtrInfo, AAInfo, BatchAA);
9591 Args.emplace_back(Dst, PtrTy);
9592 Args.emplace_back(Src, PtrTy);
9596 bool IsTailCall =
false;
9597 RTLIB::LibcallImpl MemCpyImpl = TLI->getMemcpyImpl();
9599 if (OverrideTailCall.has_value()) {
9600 IsTailCall = *OverrideTailCall;
9602 bool LowersToMemcpy = MemCpyImpl == RTLIB::impl_memcpy;
9609 Libcalls->getLibcallImplCallingConv(MemCpyImpl),
9610 Dst.getValueType().getTypeForEVT(*
getContext()),
9616 std::pair<SDValue,SDValue> CallResult = TLI->LowerCallTo(CLI);
9617 return CallResult.second;
9622 Type *SizeTy,
unsigned ElemSz,
9629 Args.emplace_back(Dst, ArgTy);
9630 Args.emplace_back(Src, ArgTy);
9631 Args.emplace_back(
Size, SizeTy);
9633 RTLIB::Libcall LibraryCall =
9635 RTLIB::LibcallImpl LibcallImpl = Libcalls->getLibcallImpl(LibraryCall);
9636 if (LibcallImpl == RTLIB::Unsupported)
9643 Libcalls->getLibcallImplCallingConv(LibcallImpl),
9650 std::pair<SDValue, SDValue> CallResult = TLI->LowerCallTo(CLI);
9651 return CallResult.second;
9657 std::optional<bool> OverrideTailCall,
9667 if (ConstantSize->
isZero())
9671 *
this, dl, Chain, Dst, Src, ConstantSize->
getZExtValue(), Alignment,
9672 isVol,
false, DstPtrInfo, SrcPtrInfo, AAInfo);
9673 if (Result.getNode())
9681 TSI->EmitTargetCodeForMemmove(*
this, dl, Chain, Dst, Src,
Size,
9682 Alignment, isVol, DstPtrInfo, SrcPtrInfo);
9683 if (Result.getNode())
9696 Args.emplace_back(Dst, PtrTy);
9697 Args.emplace_back(Src, PtrTy);
9702 RTLIB::LibcallImpl MemmoveImpl = Libcalls->getLibcallImpl(RTLIB::MEMMOVE);
9704 bool IsTailCall =
false;
9705 if (OverrideTailCall.has_value()) {
9706 IsTailCall = *OverrideTailCall;
9708 bool LowersToMemmove = MemmoveImpl == RTLIB::impl_memmove;
9715 Libcalls->getLibcallImplCallingConv(MemmoveImpl),
9716 Dst.getValueType().getTypeForEVT(*
getContext()),
9722 std::pair<SDValue,SDValue> CallResult = TLI->LowerCallTo(CLI);
9723 return CallResult.second;
9728 Type *SizeTy,
unsigned ElemSz,
9735 Args.emplace_back(Dst, IntPtrTy);
9736 Args.emplace_back(Src, IntPtrTy);
9737 Args.emplace_back(
Size, SizeTy);
9739 RTLIB::Libcall LibraryCall =
9741 RTLIB::LibcallImpl LibcallImpl = Libcalls->getLibcallImpl(LibraryCall);
9742 if (LibcallImpl == RTLIB::Unsupported)
9749 Libcalls->getLibcallImplCallingConv(LibcallImpl),
9756 std::pair<SDValue, SDValue> CallResult = TLI->LowerCallTo(CLI);
9757 return CallResult.second;
9762 bool isVol,
bool AlwaysInline,
9771 if (ConstantSize->
isZero())
9776 isVol,
false, DstPtrInfo, AAInfo);
9778 if (Result.getNode())
9785 SDValue Result = TSI->EmitTargetCodeForMemset(
9786 *
this, dl, Chain, Dst, Src,
Size, Alignment, isVol, AlwaysInline, DstPtrInfo);
9787 if (Result.getNode())
9794 assert(ConstantSize &&
"AlwaysInline requires a constant size!");
9797 isVol,
true, DstPtrInfo, AAInfo);
9799 "getMemsetStores must return a valid sequence when AlwaysInline");
9813 RTLIB::LibcallImpl BzeroImpl = Libcalls->getLibcallImpl(RTLIB::BZERO);
9814 bool UseBZero = BzeroImpl != RTLIB::Unsupported &&
isNullConstant(Src);
9820 Args.emplace_back(
Size,
DL.getIntPtrType(Ctx));
9825 RTLIB::LibcallImpl MemsetImpl = Libcalls->getLibcallImpl(RTLIB::MEMSET);
9829 Args.emplace_back(Src, Src.getValueType().getTypeForEVT(Ctx));
9830 Args.emplace_back(
Size,
DL.getIntPtrType(Ctx));
9831 CLI.
setLibCallee(Libcalls->getLibcallImplCallingConv(MemsetImpl),
9832 Dst.getValueType().getTypeForEVT(Ctx),
9837 RTLIB::LibcallImpl MemsetImpl = Libcalls->getLibcallImpl(RTLIB::MEMSET);
9838 bool LowersToMemset = MemsetImpl == RTLIB::impl_memset;
9849 std::pair<SDValue, SDValue> CallResult = TLI->LowerCallTo(CLI);
9850 return CallResult.second;
9855 Type *SizeTy,
unsigned ElemSz,
9862 Args.emplace_back(
Size, SizeTy);
9864 RTLIB::Libcall LibraryCall =
9866 RTLIB::LibcallImpl LibcallImpl = Libcalls->getLibcallImpl(LibraryCall);
9867 if (LibcallImpl == RTLIB::Unsupported)
9874 Libcalls->getLibcallImplCallingConv(LibcallImpl),
9881 std::pair<SDValue, SDValue> CallResult = TLI->LowerCallTo(CLI);
9882 return CallResult.second;
9892 ID.AddInteger(getSyntheticNodeSubclassData<AtomicSDNode>(
9893 dl.
getIROrder(), Opcode, VTList, MemVT, MMO, ExtType));
9898 E->refineAlignment(MMO);
9899 E->refineRanges(MMO);
9904 VTList, MemVT, MMO, ExtType);
9905 createOperands(
N,
Ops);
9907 CSEMap.InsertNode(
N, IP);
9944 "Invalid Atomic Op");
9964 if (
Ops.size() == 1)
9979 if (
Size.hasValue() && !
Size.getValue())
9984 MF.getMachineMemOperand(PtrInfo, Flags,
Size, Alignment, AAInfo);
10000 assert(!MMOs.
empty() &&
"Must have at least one MMO");
10004 (Opcode <= (
unsigned)std::numeric_limits<int>::max() &&
10006 "Opcode is not a memory-accessing opcode!");
10009 if (MMOs.
size() == 1) {
10015 void *Buffer = Allocator.Allocate(AllocSize,
alignof(
size_t));
10016 size_t *CountPtr =
static_cast<size_t *
>(Buffer);
10017 *CountPtr = MMOs.
size();
10026 if (VTList.
VTs[VTList.
NumVTs-1] != MVT::Glue) {
10029 ID.AddInteger(getSyntheticNodeSubclassData<MemIntrinsicSDNode>(
10030 Opcode, dl.
getIROrder(), VTList, MemVT, MemRefs));
10033 ID.AddInteger(MMO->getPointerInfo().getAddrSpace());
10034 ID.AddInteger(MMO->getFlags());
10036 void *IP =
nullptr;
10037 if (
SDNode *E = FindNodeOrInsertPos(
ID, dl, IP)) {
10043 VTList, MemVT, MemRefs);
10044 createOperands(
N,
Ops);
10045 CSEMap.InsertNode(
N, IP);
10048 VTList, MemVT, MemRefs);
10049 createOperands(
N,
Ops);
10058 SDValue Chain,
int FrameIndex) {
10060 const auto VTs =
getVTList(MVT::Other);
10069 ID.AddInteger(FrameIndex);
10070 void *IP =
nullptr;
10071 if (
SDNode *E = FindNodeOrInsertPos(
ID, dl, IP))
10076 createOperands(
N,
Ops);
10077 CSEMap.InsertNode(
N, IP);
10088 const auto VTs =
getVTList(MVT::Other);
10093 ID.AddInteger(Index);
10094 void *IP =
nullptr;
10095 if (
SDNode *E = FindNodeOrInsertPos(
ID, Dl, IP))
10098 auto *
N = newSDNode<PseudoProbeSDNode>(
10100 createOperands(
N,
Ops);
10101 CSEMap.InsertNode(
N, IP);
10118 FI->getIndex(),
Offset);
10155 "Invalid chain type");
10167 Alignment, AAInfo, Ranges);
10168 return getLoad(AM, ExtType, VT, dl, Chain, Ptr,
Offset, MemVT, MMO);
10178 assert(VT == MemVT &&
"Non-extending load from different memory type!");
10182 "Should only be an extending load, not truncating!");
10184 "Cannot convert from FP to Int or Int -> FP!");
10186 "Cannot use an ext load to convert to or from a vector!");
10189 "Cannot use an ext load to change the number of vector elements!");
10196 "Range metadata and load type must match!");
10207 ID.AddInteger(getSyntheticNodeSubclassData<LoadSDNode>(
10208 dl.
getIROrder(), VTs, AM, ExtType, MemVT, MMO));
10211 void *IP =
nullptr;
10213 E->refineAlignment(MMO);
10214 E->refineRanges(MMO);
10218 ExtType, MemVT, MMO);
10219 createOperands(
N,
Ops);
10221 CSEMap.InsertNode(
N, IP);
10235 PtrInfo, VT, Alignment, MMOFlags, AAInfo, Ranges);
10253 MemVT, Alignment, MMOFlags, AAInfo);
10268 assert(LD->getOffset().isUndef() &&
"Load is already a indexed load!");
10271 LD->getMemOperand()->getFlags() &
10274 LD->getChain(),
Base,
Offset, LD->getPointerInfo(),
10275 LD->getMemoryVT(), LD->getAlign(), MMOFlags, LD->getAAInfo());
10294 MF.getMachineMemOperand(PtrInfo, MMOFlags,
Size, Alignment, AAInfo);
10295 return getStore(Chain, dl, Val, Ptr, MMO);
10308 bool IsTruncating) {
10312 IsTruncating =
false;
10313 }
else if (!IsTruncating) {
10314 assert(VT == SVT &&
"No-truncating store from different memory type!");
10317 "Should only be a truncating store, not extending!");
10320 "Cannot use trunc store to convert to or from a vector!");
10323 "Cannot use trunc store to change the number of vector elements!");
10334 ID.AddInteger(getSyntheticNodeSubclassData<StoreSDNode>(
10335 dl.
getIROrder(), VTs, AM, IsTruncating, SVT, MMO));
10338 void *IP =
nullptr;
10339 if (
SDNode *E = FindNodeOrInsertPos(
ID, dl, IP)) {
10344 IsTruncating, SVT, MMO);
10345 createOperands(
N,
Ops);
10347 CSEMap.InsertNode(
N, IP);
10360 "Invalid chain type");
10370 PtrInfo, MMOFlags, SVT.
getStoreSize(), Alignment, AAInfo);
10385 assert(ST->getOffset().isUndef() &&
"Store is already a indexed store!");
10387 ST->getMemoryVT(), ST->getMemOperand(), AM,
10388 ST->isTruncatingStore());
10396 const MDNode *Ranges,
bool IsExpanding) {
10407 Alignment, AAInfo, Ranges);
10408 return getLoadVP(AM, ExtType, VT, dl, Chain, Ptr,
Offset, Mask, EVL, MemVT,
10417 bool IsExpanding) {
10419 assert(Mask.getValueType().getVectorElementCount() ==
10421 "Vector width mismatch between mask and data");
10432 ID.AddInteger(getSyntheticNodeSubclassData<VPLoadSDNode>(
10433 dl.
getIROrder(), VTs, AM, ExtType, IsExpanding, MemVT, MMO));
10436 void *IP =
nullptr;
10438 E->refineAlignment(MMO);
10439 E->refineRanges(MMO);
10443 ExtType, IsExpanding, MemVT, MMO);
10444 createOperands(
N,
Ops);
10446 CSEMap.InsertNode(
N, IP);
10459 bool IsExpanding) {
10462 Mask, EVL, PtrInfo, VT, Alignment, MMOFlags, AAInfo, Ranges,
10471 Mask, EVL, VT, MMO, IsExpanding);
10480 const AAMDNodes &AAInfo,
bool IsExpanding) {
10483 EVL, PtrInfo, MemVT, Alignment, MMOFlags, AAInfo,
nullptr,
10493 EVL, MemVT, MMO, IsExpanding);
10500 assert(LD->getOffset().isUndef() &&
"Load is already a indexed load!");
10503 LD->getMemOperand()->getFlags() &
10506 LD->getChain(),
Base,
Offset, LD->getMask(),
10507 LD->getVectorLength(), LD->getPointerInfo(),
10508 LD->getMemoryVT(), LD->getAlign(), MMOFlags, LD->getAAInfo(),
10509 nullptr, LD->isExpandingLoad());
10516 bool IsCompressing) {
10518 assert(Mask.getValueType().getVectorElementCount() ==
10520 "Vector width mismatch between mask and data");
10530 ID.AddInteger(getSyntheticNodeSubclassData<VPStoreSDNode>(
10531 dl.
getIROrder(), VTs, AM, IsTruncating, IsCompressing, MemVT, MMO));
10534 void *IP =
nullptr;
10535 if (
SDNode *E = FindNodeOrInsertPos(
ID, dl, IP)) {
10540 IsTruncating, IsCompressing, MemVT, MMO);
10541 createOperands(
N,
Ops);
10543 CSEMap.InsertNode(
N, IP);
10556 bool IsCompressing) {
10567 PtrInfo, MMOFlags, SVT.
getStoreSize(), Alignment, AAInfo);
10576 bool IsCompressing) {
10583 false, IsCompressing);
10586 "Should only be a truncating store, not extending!");
10589 "Cannot use trunc store to convert to or from a vector!");
10592 "Cannot use trunc store to change the number of vector elements!");
10600 ID.AddInteger(getSyntheticNodeSubclassData<VPStoreSDNode>(
10604 void *IP =
nullptr;
10605 if (
SDNode *E = FindNodeOrInsertPos(
ID, dl, IP)) {
10612 createOperands(
N,
Ops);
10614 CSEMap.InsertNode(
N, IP);
10625 assert(ST->getOffset().isUndef() &&
"Store is already an indexed store!");
10628 Offset, ST->getMask(), ST->getVectorLength()};
10631 ID.AddInteger(ST->getMemoryVT().getRawBits());
10632 ID.AddInteger(ST->getRawSubclassData());
10633 ID.AddInteger(ST->getPointerInfo().getAddrSpace());
10634 ID.AddInteger(ST->getMemOperand()->getFlags());
10635 void *IP =
nullptr;
10636 if (
SDNode *E = FindNodeOrInsertPos(
ID, dl, IP))
10639 auto *
N = newSDNode<VPStoreSDNode>(
10641 ST->isCompressingStore(), ST->getMemoryVT(), ST->getMemOperand());
10642 createOperands(
N,
Ops);
10644 CSEMap.InsertNode(
N, IP);
10664 ID.AddInteger(getSyntheticNodeSubclassData<VPStridedLoadSDNode>(
10665 DL.getIROrder(), VTs, AM, ExtType, IsExpanding, MemVT, MMO));
10668 void *IP =
nullptr;
10669 if (
SDNode *E = FindNodeOrInsertPos(
ID,
DL, IP)) {
10675 newSDNode<VPStridedLoadSDNode>(
DL.getIROrder(),
DL.getDebugLoc(), VTs, AM,
10676 ExtType, IsExpanding, MemVT, MMO);
10677 createOperands(
N,
Ops);
10678 CSEMap.InsertNode(
N, IP);
10689 bool IsExpanding) {
10692 Undef, Stride, Mask, EVL, VT, MMO, IsExpanding);
10701 Stride, Mask, EVL, MemVT, MMO, IsExpanding);
10710 bool IsTruncating,
bool IsCompressing) {
10720 ID.AddInteger(getSyntheticNodeSubclassData<VPStridedStoreSDNode>(
10721 DL.getIROrder(), VTs, AM, IsTruncating, IsCompressing, MemVT, MMO));
10723 void *IP =
nullptr;
10724 if (
SDNode *E = FindNodeOrInsertPos(
ID,
DL, IP)) {
10728 auto *
N = newSDNode<VPStridedStoreSDNode>(
DL.getIROrder(),
DL.getDebugLoc(),
10729 VTs, AM, IsTruncating,
10730 IsCompressing, MemVT, MMO);
10731 createOperands(
N,
Ops);
10733 CSEMap.InsertNode(
N, IP);
10745 bool IsCompressing) {
10752 false, IsCompressing);
10755 "Should only be a truncating store, not extending!");
10758 "Cannot use trunc store to convert to or from a vector!");
10761 "Cannot use trunc store to change the number of vector elements!");
10769 ID.AddInteger(getSyntheticNodeSubclassData<VPStridedStoreSDNode>(
10772 void *IP =
nullptr;
10773 if (
SDNode *E = FindNodeOrInsertPos(
ID,
DL, IP)) {
10777 auto *
N = newSDNode<VPStridedStoreSDNode>(
DL.getIROrder(),
DL.getDebugLoc(),
10779 IsCompressing, SVT, MMO);
10780 createOperands(
N,
Ops);
10782 CSEMap.InsertNode(
N, IP);
10792 assert(
Ops.size() == 6 &&
"Incompatible number of operands");
10797 ID.AddInteger(getSyntheticNodeSubclassData<VPGatherSDNode>(
10801 void *IP =
nullptr;
10802 if (
SDNode *E = FindNodeOrInsertPos(
ID, dl, IP)) {
10808 VT, MMO, IndexType);
10809 createOperands(
N,
Ops);
10811 assert(
N->getMask().getValueType().getVectorElementCount() ==
10812 N->getValueType(0).getVectorElementCount() &&
10813 "Vector width mismatch between mask and data");
10814 assert(
N->getIndex().getValueType().getVectorElementCount().isScalable() ==
10815 N->getValueType(0).getVectorElementCount().isScalable() &&
10816 "Scalable flags of index and data do not match");
10818 N->getIndex().getValueType().getVectorElementCount(),
10819 N->getValueType(0).getVectorElementCount()) &&
10820 "Vector width mismatch between index and data");
10822 N->getScale()->getAsAPIntVal().isPowerOf2() &&
10823 "Scale should be a constant power of 2");
10825 CSEMap.InsertNode(
N, IP);
10836 assert(
Ops.size() == 7 &&
"Incompatible number of operands");
10841 ID.AddInteger(getSyntheticNodeSubclassData<VPScatterSDNode>(
10845 void *IP =
nullptr;
10846 if (
SDNode *E = FindNodeOrInsertPos(
ID, dl, IP)) {
10851 VT, MMO, IndexType);
10852 createOperands(
N,
Ops);
10854 assert(
N->getMask().getValueType().getVectorElementCount() ==
10855 N->getValue().getValueType().getVectorElementCount() &&
10856 "Vector width mismatch between mask and data");
10858 N->getIndex().getValueType().getVectorElementCount().isScalable() ==
10859 N->getValue().getValueType().getVectorElementCount().isScalable() &&
10860 "Scalable flags of index and data do not match");
10862 N->getIndex().getValueType().getVectorElementCount(),
10863 N->getValue().getValueType().getVectorElementCount()) &&
10864 "Vector width mismatch between index and data");
10866 N->getScale()->getAsAPIntVal().isPowerOf2() &&
10867 "Scale should be a constant power of 2");
10869 CSEMap.InsertNode(
N, IP);
10884 "Unindexed masked load with an offset!");
10891 ID.AddInteger(getSyntheticNodeSubclassData<MaskedLoadSDNode>(
10892 dl.
getIROrder(), VTs, AM, ExtTy, isExpanding, MemVT, MMO));
10895 void *IP =
nullptr;
10896 if (
SDNode *E = FindNodeOrInsertPos(
ID, dl, IP)) {
10901 AM, ExtTy, isExpanding, MemVT, MMO);
10902 createOperands(
N,
Ops);
10904 CSEMap.InsertNode(
N, IP);
10915 assert(LD->getOffset().isUndef() &&
"Masked load is already a indexed load!");
10917 Offset, LD->getMask(), LD->getPassThru(),
10918 LD->getMemoryVT(), LD->getMemOperand(), AM,
10919 LD->getExtensionType(), LD->isExpandingLoad());
10927 bool IsCompressing) {
10929 "Invalid chain type");
10932 "Unindexed masked store with an offset!");
10939 ID.AddInteger(getSyntheticNodeSubclassData<MaskedStoreSDNode>(
10940 dl.
getIROrder(), VTs, AM, IsTruncating, IsCompressing, MemVT, MMO));
10943 void *IP =
nullptr;
10944 if (
SDNode *E = FindNodeOrInsertPos(
ID, dl, IP)) {
10950 IsTruncating, IsCompressing, MemVT, MMO);
10951 createOperands(
N,
Ops);
10953 CSEMap.InsertNode(
N, IP);
10964 assert(ST->getOffset().isUndef() &&
10965 "Masked store is already a indexed store!");
10967 ST->getMask(), ST->getMemoryVT(), ST->getMemOperand(),
10968 AM, ST->isTruncatingStore(), ST->isCompressingStore());
10976 assert(
Ops.size() == 6 &&
"Incompatible number of operands");
10981 ID.AddInteger(getSyntheticNodeSubclassData<MaskedGatherSDNode>(
10982 dl.
getIROrder(), VTs, MemVT, MMO, IndexType, ExtTy));
10985 void *IP =
nullptr;
10986 if (
SDNode *E = FindNodeOrInsertPos(
ID, dl, IP)) {
10992 VTs, MemVT, MMO, IndexType, ExtTy);
10993 createOperands(
N,
Ops);
10995 assert(
N->getPassThru().getValueType() ==
N->getValueType(0) &&
10996 "Incompatible type of the PassThru value in MaskedGatherSDNode");
10997 assert(
N->getMask().getValueType().getVectorElementCount() ==
10998 N->getValueType(0).getVectorElementCount() &&
10999 "Vector width mismatch between mask and data");
11000 assert(
N->getIndex().getValueType().getVectorElementCount().isScalable() ==
11001 N->getValueType(0).getVectorElementCount().isScalable() &&
11002 "Scalable flags of index and data do not match");
11004 N->getIndex().getValueType().getVectorElementCount(),
11005 N->getValueType(0).getVectorElementCount()) &&
11006 "Vector width mismatch between index and data");
11008 N->getScale()->getAsAPIntVal().isPowerOf2() &&
11009 "Scale should be a constant power of 2");
11011 CSEMap.InsertNode(
N, IP);
11023 assert(
Ops.size() == 6 &&
"Incompatible number of operands");
11028 ID.AddInteger(getSyntheticNodeSubclassData<MaskedScatterSDNode>(
11029 dl.
getIROrder(), VTs, MemVT, MMO, IndexType, IsTrunc));
11032 void *IP =
nullptr;
11033 if (
SDNode *E = FindNodeOrInsertPos(
ID, dl, IP)) {
11039 VTs, MemVT, MMO, IndexType, IsTrunc);
11040 createOperands(
N,
Ops);
11042 assert(
N->getMask().getValueType().getVectorElementCount() ==
11043 N->getValue().getValueType().getVectorElementCount() &&
11044 "Vector width mismatch between mask and data");
11046 N->getIndex().getValueType().getVectorElementCount().isScalable() ==
11047 N->getValue().getValueType().getVectorElementCount().isScalable() &&
11048 "Scalable flags of index and data do not match");
11050 N->getIndex().getValueType().getVectorElementCount(),
11051 N->getValue().getValueType().getVectorElementCount()) &&
11052 "Vector width mismatch between index and data");
11054 N->getScale()->getAsAPIntVal().isPowerOf2() &&
11055 "Scale should be a constant power of 2");
11057 CSEMap.InsertNode(
N, IP);
11068 assert(
Ops.size() == 7 &&
"Incompatible number of operands");
11073 ID.AddInteger(getSyntheticNodeSubclassData<MaskedHistogramSDNode>(
11074 dl.
getIROrder(), VTs, MemVT, MMO, IndexType));
11077 void *IP =
nullptr;
11078 if (
SDNode *E = FindNodeOrInsertPos(
ID, dl, IP)) {
11084 VTs, MemVT, MMO, IndexType);
11085 createOperands(
N,
Ops);
11087 assert(
N->getMask().getValueType().getVectorElementCount() ==
11088 N->getIndex().getValueType().getVectorElementCount() &&
11089 "Vector width mismatch between mask and data");
11091 N->getScale()->getAsAPIntVal().isPowerOf2() &&
11092 "Scale should be a constant power of 2");
11093 assert(
N->getInc().getValueType().isInteger() &&
"Non integer update value");
11095 CSEMap.InsertNode(
N, IP);
11110 ID.AddInteger(getSyntheticNodeSubclassData<VPLoadFFSDNode>(
DL.getIROrder(),
11114 void *IP =
nullptr;
11115 if (
SDNode *E = FindNodeOrInsertPos(
ID,
DL, IP)) {
11119 auto *
N = newSDNode<VPLoadFFSDNode>(
DL.getIROrder(),
DL.getDebugLoc(), VTs,
11121 createOperands(
N,
Ops);
11123 CSEMap.InsertNode(
N, IP);
11138 ID.AddInteger(getSyntheticNodeSubclassData<FPStateAccessSDNode>(
11142 void *IP =
nullptr;
11143 if (
SDNode *E = FindNodeOrInsertPos(
ID, dl, IP))
11148 createOperands(
N,
Ops);
11150 CSEMap.InsertNode(
N, IP);
11165 ID.AddInteger(getSyntheticNodeSubclassData<FPStateAccessSDNode>(
11169 void *IP =
nullptr;
11170 if (
SDNode *E = FindNodeOrInsertPos(
ID, dl, IP))
11175 createOperands(
N,
Ops);
11177 CSEMap.InsertNode(
N, IP);
11188 if (
Cond.isUndef())
11223 return !Val || Val->getAPIntValue().uge(
X.getScalarValueSizeInBits());
11229 if (
X.getValueType().getScalarType() == MVT::i1)
11242 bool HasNan = (XC && XC->
getValueAPF().isNaN()) ||
11244 bool HasInf = (XC && XC->
getValueAPF().isInfinity()) ||
11247 if (Flags.hasNoNaNs() && (HasNan ||
X.isUndef() ||
Y.isUndef()))
11250 if (Flags.hasNoInfs() && (HasInf ||
X.isUndef() ||
Y.isUndef()))
11273 if (Opcode ==
ISD::FMUL && Flags.hasNoNaNs() && Flags.hasNoSignedZeros())
11288 switch (
Ops.size()) {
11289 case 0:
return getNode(Opcode,
DL, VT);
11299 return getNode(Opcode,
DL, VT, NewOps);
11306 Flags = Inserter->getFlags();
11314 case 0:
return getNode(Opcode,
DL, VT);
11315 case 1:
return getNode(Opcode,
DL, VT,
Ops[0], Flags);
11322 for (
const auto &
Op :
Ops)
11324 "Operand is DELETED_NODE!");
11341 "LHS and RHS of condition must have same type!");
11343 "True and False arms of SelectCC must have same type!");
11345 "select_cc node must be of same type as true and false value!");
11349 "Expected select_cc with vector result to have the same sized "
11350 "comparison type!");
11355 "LHS/RHS of comparison should match types!");
11361 Opcode = ISD::VP_XOR;
11366 Opcode = ISD::VP_AND;
11368 case ISD::VP_REDUCE_MUL:
11371 Opcode = ISD::VP_REDUCE_AND;
11373 case ISD::VP_REDUCE_ADD:
11376 Opcode = ISD::VP_REDUCE_XOR;
11378 case ISD::VP_REDUCE_SMAX:
11379 case ISD::VP_REDUCE_UMIN:
11383 Opcode = ISD::VP_REDUCE_AND;
11385 case ISD::VP_REDUCE_SMIN:
11386 case ISD::VP_REDUCE_UMAX:
11390 Opcode = ISD::VP_REDUCE_OR;
11398 if (VT != MVT::Glue) {
11401 void *IP =
nullptr;
11403 if (
SDNode *E = FindNodeOrInsertPos(
ID,
DL, IP)) {
11404 E->intersectFlagsWith(Flags);
11408 N = newSDNode<SDNode>(Opcode,
DL.getIROrder(),
DL.getDebugLoc(), VTs);
11409 createOperands(
N,
Ops);
11411 CSEMap.InsertNode(
N, IP);
11413 N = newSDNode<SDNode>(Opcode,
DL.getIROrder(),
DL.getDebugLoc(), VTs);
11414 createOperands(
N,
Ops);
11417 N->setFlags(Flags);
11428 Flags = Inserter->getFlags();
11442 Flags = Inserter->getFlags();
11452 for (
const auto &
Op :
Ops)
11454 "Operand is DELETED_NODE!");
11463 "Invalid add/sub overflow op!");
11465 Ops[0].getValueType() ==
Ops[1].getValueType() &&
11466 Ops[0].getValueType() == VTList.
VTs[0] &&
11467 "Binary operator types must match!");
11474 if (N2CV && N2CV->
isZero()) {
11505 "Invalid add/sub overflow op!");
11507 Ops[0].getValueType() ==
Ops[1].getValueType() &&
11508 Ops[0].getValueType() == VTList.
VTs[0] &&
11509 Ops[2].getValueType() == VTList.
VTs[1] &&
11510 "Binary operator types must match!");
11514 assert(VTList.
NumVTs == 2 &&
Ops.size() == 2 &&
"Invalid mul lo/hi op!");
11516 VTList.
VTs[0] ==
Ops[0].getValueType() &&
11517 VTList.
VTs[0] ==
Ops[1].getValueType() &&
11518 "Binary operator types must match!");
11524 unsigned OutWidth = Width * 2;
11525 APInt Val = LHS->getAPIntValue();
11528 Val = Val.
sext(OutWidth);
11529 Mul =
Mul.sext(OutWidth);
11531 Val = Val.
zext(OutWidth);
11532 Mul =
Mul.zext(OutWidth);
11544 assert(VTList.
NumVTs == 2 &&
Ops.size() == 1 &&
"Invalid ffrexp op!");
11546 VTList.
VTs[0] ==
Ops[0].getValueType() &&
"frexp type mismatch");
11554 DL, VTList.
VTs[1]);
11562 "Invalid STRICT_FP_EXTEND!");
11564 Ops[1].getValueType().isFloatingPoint() &&
"Invalid FP cast!");
11566 "STRICT_FP_EXTEND result type should be vector iff the operand "
11567 "type is vector!");
11570 Ops[1].getValueType().getVectorElementCount()) &&
11571 "Vector element count mismatch!");
11573 "Invalid fpext node, dst <= src!");
11576 assert(VTList.
NumVTs == 2 &&
Ops.size() == 3 &&
"Invalid STRICT_FP_ROUND!");
11578 "STRICT_FP_ROUND result type should be vector iff the operand "
11579 "type is vector!");
11582 Ops[1].getValueType().getVectorElementCount()) &&
11583 "Vector element count mismatch!");
11585 Ops[1].getValueType().isFloatingPoint() &&
11588 (
Ops[2]->getAsZExtVal() == 0 ||
Ops[2]->getAsZExtVal() == 1) &&
11589 "Invalid STRICT_FP_ROUND!");
11595 if (VTList.
VTs[VTList.
NumVTs-1] != MVT::Glue) {
11598 void *IP =
nullptr;
11599 if (
SDNode *E = FindNodeOrInsertPos(
ID,
DL, IP)) {
11600 E->intersectFlagsWith(Flags);
11604 N = newSDNode<SDNode>(Opcode,
DL.getIROrder(),
DL.getDebugLoc(), VTList);
11605 createOperands(
N,
Ops);
11606 CSEMap.InsertNode(
N, IP);
11608 N = newSDNode<SDNode>(Opcode,
DL.getIROrder(),
DL.getDebugLoc(), VTList);
11609 createOperands(
N,
Ops);
11612 N->setFlags(Flags);
11659 return makeVTList(&(*EVTs.insert(VT).first), 1);
11668 void *IP =
nullptr;
11671 EVT *Array = Allocator.Allocate<
EVT>(2);
11674 Result =
new (Allocator)
SDVTListNode(
ID.Intern(Allocator), Array, 2);
11675 VTListMap.InsertNode(Result, IP);
11677 return Result->getSDVTList();
11687 void *IP =
nullptr;
11690 EVT *Array = Allocator.Allocate<
EVT>(3);
11694 Result =
new (Allocator)
SDVTListNode(
ID.Intern(Allocator), Array, 3);
11695 VTListMap.InsertNode(Result, IP);
11697 return Result->getSDVTList();
11708 void *IP =
nullptr;
11711 EVT *Array = Allocator.Allocate<
EVT>(4);
11716 Result =
new (Allocator)
SDVTListNode(
ID.Intern(Allocator), Array, 4);
11717 VTListMap.InsertNode(Result, IP);
11719 return Result->getSDVTList();
11723 unsigned NumVTs = VTs.
size();
11725 ID.AddInteger(NumVTs);
11726 for (
unsigned index = 0; index < NumVTs; index++) {
11727 ID.AddInteger(VTs[index].getRawBits());
11730 void *IP =
nullptr;
11733 EVT *Array = Allocator.Allocate<
EVT>(NumVTs);
11735 Result =
new (Allocator)
SDVTListNode(
ID.Intern(Allocator), Array, NumVTs);
11736 VTListMap.InsertNode(Result, IP);
11738 return Result->getSDVTList();
11749 assert(
N->getNumOperands() == 1 &&
"Update with wrong number of operands");
11752 if (
Op ==
N->getOperand(0))
return N;
11755 void *InsertPos =
nullptr;
11756 if (
SDNode *Existing = FindModifiedNodeSlot(
N,
Op, InsertPos))
11761 if (!RemoveNodeFromCSEMaps(
N))
11762 InsertPos =
nullptr;
11765 N->OperandList[0].set(
Op);
11769 if (InsertPos) CSEMap.InsertNode(
N, InsertPos);
11774 assert(
N->getNumOperands() == 2 &&
"Update with wrong number of operands");
11777 if (Op1 ==
N->getOperand(0) && Op2 ==
N->getOperand(1))
11781 void *InsertPos =
nullptr;
11782 if (
SDNode *Existing = FindModifiedNodeSlot(
N, Op1, Op2, InsertPos))
11787 if (!RemoveNodeFromCSEMaps(
N))
11788 InsertPos =
nullptr;
11791 if (
N->OperandList[0] != Op1)
11792 N->OperandList[0].set(Op1);
11793 if (
N->OperandList[1] != Op2)
11794 N->OperandList[1].set(Op2);
11798 if (InsertPos) CSEMap.InsertNode(
N, InsertPos);
11818 SDValue Ops[] = { Op1, Op2, Op3, Op4, Op5 };
11826 "Update with wrong number of operands");
11829 if (std::equal(
Ops.begin(),
Ops.end(),
N->op_begin()))
11833 void *InsertPos =
nullptr;
11834 if (
SDNode *Existing = FindModifiedNodeSlot(
N,
Ops, InsertPos))
11839 if (!RemoveNodeFromCSEMaps(
N))
11840 InsertPos =
nullptr;
11843 for (
unsigned i = 0; i !=
NumOps; ++i)
11844 if (
N->OperandList[i] !=
Ops[i])
11845 N->OperandList[i].set(
Ops[i]);
11849 if (InsertPos) CSEMap.InsertNode(
N, InsertPos);
11866 if (NewMemRefs.
empty()) {
11872 if (NewMemRefs.
size() == 1) {
11873 N->MemRefs = NewMemRefs[0];
11879 Allocator.template Allocate<MachineMemOperand *>(NewMemRefs.
size());
11881 N->MemRefs = MemRefsBuffer;
11882 N->NumMemRefs =
static_cast<int>(NewMemRefs.
size());
11954 New->setNodeId(-1);
11974 unsigned Order = std::min(
N->getIROrder(), OLoc.
getIROrder());
11975 N->setIROrder(Order);
11998 void *IP =
nullptr;
11999 if (VTs.
VTs[VTs.
NumVTs-1] != MVT::Glue) {
12003 return UpdateSDLocOnMergeSDNode(ON,
SDLoc(
N));
12006 if (!RemoveNodeFromCSEMaps(
N))
12011 N->ValueList = VTs.
VTs;
12021 if (Used->use_empty())
12022 DeadNodeSet.
insert(Used);
12027 MN->clearMemRefs();
12031 createOperands(
N,
Ops);
12035 if (!DeadNodeSet.
empty()) {
12037 for (
SDNode *
N : DeadNodeSet)
12038 if (
N->use_empty())
12044 CSEMap.InsertNode(
N, IP);
12049 unsigned OrigOpc =
Node->getOpcode();
12054#define DAG_INSTRUCTION(NAME, NARG, ROUND_MODE, INTRINSIC, DAGN) \
12055 case ISD::STRICT_##DAGN: NewOpc = ISD::DAGN; break;
12056#define CMP_INSTRUCTION(NAME, NARG, ROUND_MODE, INTRINSIC, DAGN) \
12057 case ISD::STRICT_##DAGN: NewOpc = ISD::SETCC; break;
12058#include "llvm/IR/ConstrainedOps.def"
12061 assert(
Node->getNumValues() == 2 &&
"Unexpected number of results!");
12069 for (
unsigned i = 1, e =
Node->getNumOperands(); i != e; ++i)
12070 Ops.push_back(
Node->getOperand(i));
12187 bool DoCSE = VTs.
VTs[VTs.
NumVTs-1] != MVT::Glue;
12189 void *IP =
nullptr;
12195 if (
SDNode *E = FindNodeOrInsertPos(
ID,
DL, IP)) {
12201 N = newSDNode<MachineSDNode>(~Opcode,
DL.getIROrder(),
DL.getDebugLoc(), VTs);
12202 createOperands(
N,
Ops);
12205 CSEMap.InsertNode(
N, IP);
12218 VT, Operand, SRIdxVal);
12228 VT, Operand, Subreg, SRIdxVal);
12236 bool AllowCommute) {
12239 Flags = Inserter->getFlags();
12246 bool AllowCommute) {
12247 if (VTList.
VTs[VTList.
NumVTs - 1] == MVT::Glue)
12253 void *IP =
nullptr;
12254 if (
SDNode *E = FindNodeOrInsertPos(
ID, IP)) {
12255 E->intersectFlagsWith(Flags);
12264 if (AllowCommute && TLI->isCommutativeBinOp(Opcode))
12273 if (VTList.
VTs[VTList.
NumVTs - 1] != MVT::Glue) {
12276 void *IP =
nullptr;
12277 if (FindNodeOrInsertPos(
ID,
SDLoc(), IP))
12287 SDNode *
N,
unsigned R,
bool IsIndirect,
12290 "Expected inlined-at fields to agree");
12291 return new (DbgInfo->getAlloc())
12293 {}, IsIndirect,
DL, O,
12303 "Expected inlined-at fields to agree");
12304 return new (DbgInfo->getAlloc())
12317 "Expected inlined-at fields to agree");
12329 "Expected inlined-at fields to agree");
12330 return new (DbgInfo->getAlloc())
12332 Dependencies, IsIndirect,
DL, O,
12341 "Expected inlined-at fields to agree");
12342 return new (DbgInfo->getAlloc())
12344 {}, IsIndirect,
DL, O,
12352 unsigned O,
bool IsVariadic) {
12354 "Expected inlined-at fields to agree");
12355 return new (DbgInfo->getAlloc())
12356 SDDbgValue(DbgInfo->getAlloc(), Var, Expr, Locs, Dependencies, IsIndirect,
12357 DL, O, IsVariadic);
12361 unsigned OffsetInBits,
unsigned SizeInBits,
12362 bool InvalidateDbg) {
12365 assert(FromNode && ToNode &&
"Can't modify dbg values");
12370 if (From == To || FromNode == ToNode)
12382 if (Dbg->isInvalidated())
12390 auto NewLocOps = Dbg->copyLocationOps();
12392 NewLocOps.begin(), NewLocOps.end(),
12394 bool Match = Op == FromLocOp;
12404 auto *Expr = Dbg->getExpression();
12410 if (
auto FI = Expr->getFragmentInfo())
12411 if (OffsetInBits + SizeInBits > FI->SizeInBits)
12420 auto AdditionalDependencies = Dbg->getAdditionalDependencies();
12423 Var, Expr, NewLocOps, AdditionalDependencies, Dbg->isIndirect(),
12424 Dbg->getDebugLoc(), std::max(ToNode->
getIROrder(), Dbg->getOrder()),
12425 Dbg->isVariadic());
12428 if (InvalidateDbg) {
12430 Dbg->setIsInvalidated();
12431 Dbg->setIsEmitted();
12437 "Transferred DbgValues should depend on the new SDNode");
12443 if (!
N.getHasDebugValue())
12446 auto GetLocationOperand = [](
SDNode *
Node,
unsigned ResNo) {
12454 if (DV->isInvalidated())
12456 switch (
N.getOpcode()) {
12466 Offset =
N.getConstantOperandVal(1);
12469 if (!RHSConstant && DV->isIndirect())
12476 auto *DIExpr = DV->getExpression();
12477 auto NewLocOps = DV->copyLocationOps();
12479 size_t OrigLocOpsSize = NewLocOps.size();
12480 for (
size_t i = 0; i < OrigLocOpsSize; ++i) {
12485 NewLocOps[i].getSDNode() != &
N)
12496 const auto *TmpDIExpr =
12504 NewLocOps.push_back(RHS);
12513 DV->isVariadic() || OrigLocOpsSize != NewLocOps.size();
12515 auto AdditionalDependencies = DV->getAdditionalDependencies();
12517 DV->getVariable(), DIExpr, NewLocOps, AdditionalDependencies,
12518 DV->isIndirect(), DV->getDebugLoc(), DV->getOrder(), IsVariadic);
12520 DV->setIsInvalidated();
12521 DV->setIsEmitted();
12523 N0.
getNode()->dumprFull(
this);
12524 dbgs() <<
" into " << *DIExpr <<
'\n');
12531 TypeSize ToSize =
N.getValueSizeInBits(0);
12535 auto NewLocOps = DV->copyLocationOps();
12537 for (
size_t i = 0; i < NewLocOps.size(); ++i) {
12539 NewLocOps[i].getSDNode() != &
N)
12551 DV->getAdditionalDependencies(), DV->isIndirect(),
12552 DV->getDebugLoc(), DV->getOrder(), DV->isVariadic());
12555 DV->setIsInvalidated();
12556 DV->setIsEmitted();
12558 dbgs() <<
" into " << *DbgExpression <<
'\n');
12565 assert((!Dbg->getSDNodes().empty() ||
12568 return Op.getKind() == SDDbgOperand::FRAMEIX;
12570 "Salvaged DbgValue should depend on a new SDNode");
12579 "Expected inlined-at fields to agree");
12580 return new (DbgInfo->getAlloc())
SDDbgLabel(Label,
DL, O);
12595 while (UI != UE &&
N == UI->
getUser())
12603 :
SelectionDAG::DAGUpdateListener(d), UI(ui), UE(ue) {}
12616 "Cannot replace with this method!");
12617 assert(From != To.
getNode() &&
"Cannot replace uses of with self");
12632 RAUWUpdateListener Listener(*
this, UI, UE);
12637 RemoveNodeFromCSEMaps(
User);
12652 AddModifiedNodeToCSEMaps(
User);
12668 for (
unsigned i = 0, e = From->
getNumValues(); i != e; ++i)
12671 "Cannot use this version of ReplaceAllUsesWith!");
12679 for (
unsigned i = 0, e = From->
getNumValues(); i != e; ++i)
12681 assert((i < To->getNumValues()) &&
"Invalid To location");
12690 RAUWUpdateListener Listener(*
this, UI, UE);
12695 RemoveNodeFromCSEMaps(
User);
12711 AddModifiedNodeToCSEMaps(
User);
12728 for (
unsigned i = 0, e = From->
getNumValues(); i != e; ++i) {
12738 RAUWUpdateListener Listener(*
this, UI, UE);
12743 RemoveNodeFromCSEMaps(
User);
12749 bool To_IsDivergent =
false;
12764 AddModifiedNodeToCSEMaps(
User);
12777 if (From == To)
return;
12793 RAUWUpdateListener Listener(*
this, UI, UE);
12796 bool UserRemovedFromCSEMaps =
false;
12813 if (!UserRemovedFromCSEMaps) {
12814 RemoveNodeFromCSEMaps(
User);
12815 UserRemovedFromCSEMaps =
true;
12825 if (!UserRemovedFromCSEMaps)
12830 AddModifiedNodeToCSEMaps(
User);
12849bool operator<(
const UseMemo &L,
const UseMemo &R) {
12850 return (intptr_t)L.User < (intptr_t)R.User;
12857 SmallVectorImpl<UseMemo> &
Uses;
12859 void NodeDeleted(SDNode *
N, SDNode *
E)
override {
12860 for (UseMemo &Memo :
Uses)
12861 if (Memo.User ==
N)
12862 Memo.User =
nullptr;
12866 RAUOVWUpdateListener(SelectionDAG &d, SmallVectorImpl<UseMemo> &uses)
12867 : SelectionDAG::DAGUpdateListener(d),
Uses(uses) {}
12874 switch (
Node->getOpcode()) {
12886 if (TLI->isSDNodeAlwaysUniform(
N)) {
12887 assert(!TLI->isSDNodeSourceOfDivergence(
N, FLI, UA) &&
12888 "Conflicting divergence information!");
12891 if (TLI->isSDNodeSourceOfDivergence(
N, FLI, UA))
12893 for (
const auto &
Op :
N->ops()) {
12894 EVT VT =
Op.getValueType();
12897 if (VT != MVT::Other &&
Op.getNode()->isDivergent() &&
12909 if (
N->SDNodeBits.IsDivergent != IsDivergent) {
12910 N->SDNodeBits.IsDivergent = IsDivergent;
12913 }
while (!Worklist.
empty());
12916void SelectionDAG::CreateTopologicalOrder(std::vector<SDNode *> &Order) {
12918 Order.reserve(AllNodes.size());
12920 unsigned NOps =
N.getNumOperands();
12923 Order.push_back(&
N);
12925 for (
size_t I = 0;
I != Order.size(); ++
I) {
12927 for (
auto *U :
N->users()) {
12928 unsigned &UnsortedOps = Degree[U];
12929 if (0 == --UnsortedOps)
12930 Order.push_back(U);
12935#if !defined(NDEBUG) && LLVM_ENABLE_ABI_BREAKING_CHECKS
12936void SelectionDAG::VerifyDAGDivergence() {
12937 std::vector<SDNode *> TopoOrder;
12938 CreateTopologicalOrder(TopoOrder);
12939 for (
auto *
N : TopoOrder) {
12941 "Divergence bit inconsistency detected");
12964 for (
unsigned i = 0; i != Num; ++i) {
12965 unsigned FromResNo = From[i].
getResNo();
12968 if (
Use.getResNo() == FromResNo) {
12970 Uses.push_back(Memo);
12977 RAUOVWUpdateListener Listener(*
this,
Uses);
12979 for (
unsigned UseIndex = 0, UseIndexEnd =
Uses.size();
12980 UseIndex != UseIndexEnd; ) {
12986 if (
User ==
nullptr) {
12992 RemoveNodeFromCSEMaps(
User);
12999 unsigned i =
Uses[UseIndex].Index;
13004 }
while (UseIndex != UseIndexEnd &&
Uses[UseIndex].
User ==
User);
13008 AddModifiedNodeToCSEMaps(
User);
13016 unsigned DAGSize = 0;
13032 unsigned Degree =
N.getNumOperands();
13035 N.setNodeId(DAGSize++);
13037 if (Q != SortedPos)
13038 SortedPos = AllNodes.insert(SortedPos, AllNodes.remove(Q));
13039 assert(SortedPos != AllNodes.end() &&
"Overran node list");
13043 N.setNodeId(Degree);
13055 unsigned Degree =
P->getNodeId();
13056 assert(Degree != 0 &&
"Invalid node degree");
13060 P->setNodeId(DAGSize++);
13061 if (
P->getIterator() != SortedPos)
13062 SortedPos = AllNodes.insert(SortedPos, AllNodes.remove(
P));
13063 assert(SortedPos != AllNodes.end() &&
"Overran node list");
13067 P->setNodeId(Degree);
13070 if (
Node.getIterator() == SortedPos) {
13074 dbgs() <<
"Overran sorted position:\n";
13076 dbgs() <<
"Checking if this is due to cycles\n";
13083 assert(SortedPos == AllNodes.end() &&
13084 "Topological sort incomplete!");
13086 "First node in topological sort is not the entry token!");
13087 assert(AllNodes.front().getNodeId() == 0 &&
13088 "First node in topological sort has non-zero id!");
13089 assert(AllNodes.front().getNumOperands() == 0 &&
13090 "First node in topological sort has operands!");
13091 assert(AllNodes.back().getNodeId() == (
int)DAGSize-1 &&
13092 "Last node in topologic sort has unexpected id!");
13093 assert(AllNodes.back().use_empty() &&
13094 "Last node in topologic sort has users!");
13101 SortedNodes.
clear();
13108 unsigned NumOperands =
N.getNumOperands();
13109 if (NumOperands == 0)
13113 RemainingOperands[&
N] = NumOperands;
13118 for (
unsigned i = 0U; i < SortedNodes.
size(); ++i) {
13119 const SDNode *
N = SortedNodes[i];
13120 for (
const SDNode *U :
N->users()) {
13125 unsigned &NumRemOperands = RemainingOperands[U];
13126 assert(NumRemOperands &&
"Invalid number of remaining operands");
13128 if (!NumRemOperands)
13133 assert(SortedNodes.
size() == AllNodes.size() &&
"Node count mismatch");
13135 "First node in topological sort is not the entry token");
13136 assert(SortedNodes.
front()->getNumOperands() == 0 &&
13137 "First node in topological sort has operands");
13143 for (
SDNode *SD : DB->getSDNodes()) {
13146 assert(DbgInfo->getSDDbgValues(SD).empty() || SD->getHasDebugValue());
13147 SD->setHasDebugValue(
true);
13149 DbgInfo->add(DB, isParameter);
13162 if (OldChain == NewMemOpChain || OldChain.
use_empty())
13163 return NewMemOpChain;
13166 OldChain, NewMemOpChain);
13169 return TokenFactor;
13188 if (OutFunction !=
nullptr)
13196 std::string ErrorStr;
13198 ErrorFormatter <<
"Undefined external symbol ";
13199 ErrorFormatter <<
'"' << Symbol <<
'"';
13209 return Const !=
nullptr && Const->isZero();
13218 return Const !=
nullptr && Const->isZero() && !Const->isNegative();
13223 return Const !=
nullptr && Const->isAllOnes();
13228 return Const !=
nullptr && Const->isOne();
13233 return Const !=
nullptr && Const->isMinSignedValue();
13237 unsigned OperandNo) {
13242 APInt Const = ConstV->getAPIntValue().trunc(V.getScalarValueSizeInBits());
13248 return Const.isZero();
13250 return Const.isOne();
13253 return Const.isAllOnes();
13255 return Const.isMinSignedValue();
13257 return Const.isMaxSignedValue();
13262 return OperandNo == 1 && Const.isZero();
13265 return OperandNo == 1 && Const.isOne();
13270 return ConstFP->isZero() &&
13271 (Flags.hasNoSignedZeros() || ConstFP->isNegative());
13273 return OperandNo == 1 && ConstFP->isZero() &&
13274 (Flags.hasNoSignedZeros() || !ConstFP->isNegative());
13276 return ConstFP->isExactlyValue(1.0);
13278 return OperandNo == 1 && ConstFP->isExactlyValue(1.0);
13282 EVT VT = V.getValueType();
13284 APFloat NeutralAF = !Flags.hasNoNaNs()
13286 : !Flags.hasNoInfs()
13292 return ConstFP->isExactlyValue(NeutralAF);
13306 while (V.getOpcode() ==
ISD::BITCAST && V.getOperand(0).hasOneUse())
13325 !DemandedElts[IndexC->getZExtValue()]) {
13344 unsigned NumBits = V.getScalarValueSizeInBits();
13347 return C && (
C->getAPIntValue().
countr_one() >= NumBits);
13351 bool AllowTruncation) {
13352 EVT VT =
N.getValueType();
13361 bool AllowTruncation) {
13368 EVT VecEltVT =
N->getValueType(0).getVectorElementType();
13370 EVT CVT = CN->getValueType(0);
13371 assert(CVT.
bitsGE(VecEltVT) &&
"Illegal splat_vector element extension");
13372 if (AllowTruncation || CVT == VecEltVT)
13379 ConstantSDNode *CN = BV->getConstantSplatNode(DemandedElts, &UndefElements);
13384 if (CN && (UndefElements.
none() || AllowUndefs)) {
13386 EVT NSVT =
N.getValueType().getScalarType();
13387 assert(CVT.
bitsGE(NSVT) &&
"Illegal build vector element extension");
13388 if (AllowTruncation || (CVT == NSVT))
13397 EVT VT =
N.getValueType();
13405 const APInt &DemandedElts,
13406 bool AllowUndefs) {
13413 BV->getConstantFPSplatNode(DemandedElts, &UndefElements);
13415 if (CN && (UndefElements.
none() || AllowUndefs))
13430 return C &&
C->isZero();
13436 return C &&
C->isOne();
13441 return C &&
C->isExactlyValue(1.0);
13446 unsigned BitWidth =
N.getScalarValueSizeInBits();
13448 return C &&
C->isAllOnes() &&
C->getValueSizeInBits(0) ==
BitWidth;
13454 APInt(
C->getAPIntValue().getBitWidth(), 1));
13460 return C &&
C->isZero();
13465 return C &&
C->isZero();
13476 bool IsVolatile =
false;
13477 bool IsNonTemporal =
false;
13478 bool IsDereferenceable =
true;
13479 bool IsInvariant =
true;
13481 IsVolatile |= MMO->isVolatile();
13482 IsNonTemporal |= MMO->isNonTemporal();
13483 IsDereferenceable &= MMO->isDereferenceable();
13484 IsInvariant &= MMO->isInvariant();
13510 std::vector<EVT> VTs;
13523const EVT *SDNode::getValueTypeList(
MVT VT) {
13524 static EVTArray SimpleVTArray;
13527 return &SimpleVTArray.VTs[VT.
SimpleTy];
13536 if (U.getResNo() ==
Value)
13574 return any_of(
N->op_values(),
13575 [
this](
SDValue Op) { return this == Op.getNode(); });
13589 unsigned Depth)
const {
13590 if (*
this == Dest)
return true;
13594 if (
Depth == 0)
return false;
13614 return Op.reachesChainWithoutSideEffects(Dest, Depth - 1);
13620 if (Ld->isUnordered())
13621 return Ld->getChain().reachesChainWithoutSideEffects(Dest,
Depth-1);
13634 this->Flags &= Flags;
13640 bool AllowPartials) {
13655 unsigned CandidateBinOp =
Op.getOpcode();
13656 if (
Op.getValueType().isFloatingPoint()) {
13658 switch (CandidateBinOp) {
13660 if (!Flags.hasNoSignedZeros() || !Flags.hasAllowReassociation())
13670 auto PartialReduction = [&](
SDValue Op,
unsigned NumSubElts) {
13671 if (!AllowPartials || !
Op)
13673 EVT OpVT =
Op.getValueType();
13676 if (!TLI->isExtractSubvectorCheap(SubVT, OpVT, 0))
13695 unsigned Stages =
Log2_32(
Op.getValueType().getVectorNumElements());
13697 for (
unsigned i = 0; i < Stages; ++i) {
13698 unsigned MaskEnd = (1 << i);
13700 if (
Op.getOpcode() != CandidateBinOp)
13701 return PartialReduction(PrevOp, MaskEnd);
13717 return PartialReduction(PrevOp, MaskEnd);
13720 for (
int Index = 0; Index < (int)MaskEnd; ++Index)
13721 if (Shuffle->
getMaskElt(Index) != (
int)(MaskEnd + Index))
13722 return PartialReduction(PrevOp, MaskEnd);
13729 while (
Op.getOpcode() == CandidateBinOp) {
13730 unsigned NumElts =
Op.getValueType().getVectorNumElements();
13739 if (NumSrcElts != (2 * NumElts))
13754 EVT VT =
N->getValueType(0);
13763 else if (NE > ResNE)
13766 if (
N->getNumValues() == 2) {
13769 EVT VT1 =
N->getValueType(1);
13773 for (i = 0; i != NE; ++i) {
13774 for (
unsigned j = 0, e =
N->getNumOperands(); j != e; ++j) {
13775 SDValue Operand =
N->getOperand(j);
13783 SDValue EltOp =
getNode(
N->getOpcode(), dl, {EltVT, EltVT1}, Operands);
13788 for (; i < ResNE; ++i) {
13800 assert(
N->getNumValues() == 1 &&
13801 "Can't unroll a vector with multiple results!");
13807 for (i= 0; i != NE; ++i) {
13808 for (
unsigned j = 0, e =
N->getNumOperands(); j != e; ++j) {
13809 SDValue Operand =
N->getOperand(j);
13817 Operands[j] = Operand;
13821 switch (
N->getOpcode()) {
13849 ASC->getSrcAddressSpace(),
13850 ASC->getDestAddressSpace()));
13856 for (; i < ResNE; ++i)
13865 unsigned Opcode =
N->getOpcode();
13869 "Expected an overflow opcode");
13871 EVT ResVT =
N->getValueType(0);
13872 EVT OvVT =
N->getValueType(1);
13881 else if (NE > ResNE)
13893 for (
unsigned i = 0; i < NE; ++i) {
13894 SDValue Res =
getNode(Opcode, dl, VTs, LHSScalars[i], RHSScalars[i]);
13917 if (LD->isVolatile() ||
Base->isVolatile())
13920 if (!LD->isSimple())
13922 if (LD->isIndexed() ||
Base->isIndexed())
13924 if (LD->getChain() !=
Base->getChain())
13926 EVT VT = LD->getMemoryVT();
13934 if (BaseLocDecomp.equalBaseIndex(LocDecomp, *
this,
Offset))
13935 return (Dist * (int64_t)Bytes ==
Offset);
13944 int64_t GVOffset = 0;
13945 if (TLI->isGAPlusOffset(Ptr.
getNode(), GV, GVOffset)) {
13956 int FrameIdx = INT_MIN;
13957 int64_t FrameOffset = 0;
13959 FrameIdx = FI->getIndex();
13967 if (FrameIdx != INT_MIN) {
13972 return std::nullopt;
13982 "Split node must be a scalar type");
13987 return std::make_pair(
Lo,
Hi);
13996 LoVT = HiVT = TLI->getTypeToTransformTo(*
getContext(), VT);
14000 return std::make_pair(LoVT, HiVT);
14008 bool *HiIsEmpty)
const {
14018 "Mixing fixed width and scalable vectors when enveloping a type");
14023 *HiIsEmpty =
false;
14031 return std::make_pair(LoVT, HiVT);
14036std::pair<SDValue, SDValue>
14041 "Splitting vector with an invalid mixture of fixed and scalable "
14044 N.getValueType().getVectorMinNumElements() &&
14045 "More vector elements requested than available!");
14054 return std::make_pair(
Lo,
Hi);
14061 EVT VT =
N.getValueType();
14063 "Expecting the mask to be an evenly-sized vector");
14068 return std::make_pair(
Lo,
Hi);
14073 EVT VT =
N.getValueType();
14081 unsigned Start,
unsigned Count,
14083 EVT VT =
Op.getValueType();
14086 if (EltVT ==
EVT())
14089 for (
unsigned i = Start, e = Start +
Count; i != e; ++i) {
14101 return Val.MachineCPVal->getType();
14102 return Val.ConstVal->getType();
14106 unsigned &SplatBitSize,
14107 bool &HasAnyUndefs,
14108 unsigned MinSplatBits,
14109 bool IsBigEndian)
const {
14113 if (MinSplatBits > VecWidth)
14118 SplatValue =
APInt(VecWidth, 0);
14119 SplatUndef =
APInt(VecWidth, 0);
14126 assert(
NumOps > 0 &&
"isConstantSplat has 0-size build vector");
14129 for (
unsigned j = 0; j <
NumOps; ++j) {
14130 unsigned i = IsBigEndian ?
NumOps - 1 - j : j;
14132 unsigned BitPos = j * EltWidth;
14135 SplatUndef.
setBits(BitPos, BitPos + EltWidth);
14137 SplatValue.
insertBits(CN->getAPIntValue().zextOrTrunc(EltWidth), BitPos);
14139 SplatValue.
insertBits(CN->getValueAPF().bitcastToAPInt(), BitPos);
14146 HasAnyUndefs = (SplatUndef != 0);
14149 while (VecWidth > 8) {
14154 unsigned HalfSize = VecWidth / 2;
14161 if ((HighValue & ~LowUndef) != (LowValue & ~HighUndef) ||
14162 MinSplatBits > HalfSize)
14165 SplatValue = HighValue | LowValue;
14166 SplatUndef = HighUndef & LowUndef;
14168 VecWidth = HalfSize;
14177 SplatBitSize = VecWidth;
14184 if (UndefElements) {
14185 UndefElements->
clear();
14192 for (
unsigned i = 0; i !=
NumOps; ++i) {
14193 if (!DemandedElts[i])
14196 if (
Op.isUndef()) {
14198 (*UndefElements)[i] =
true;
14199 }
else if (!Splatted) {
14201 }
else if (Splatted !=
Op) {
14207 unsigned FirstDemandedIdx = DemandedElts.
countr_zero();
14209 "Can only have a splat without a constant for all undefs.");
14226 if (UndefElements) {
14227 UndefElements->
clear();
14238 (*UndefElements)[
I] =
true;
14241 for (
unsigned SeqLen = 1; SeqLen <
NumOps; SeqLen *= 2) {
14242 Sequence.append(SeqLen,
SDValue());
14243 for (
unsigned I = 0;
I !=
NumOps; ++
I) {
14244 if (!DemandedElts[
I])
14246 SDValue &SeqOp = Sequence[
I % SeqLen];
14248 if (
Op.isUndef()) {
14253 if (SeqOp && !SeqOp.
isUndef() && SeqOp !=
Op) {
14259 if (!Sequence.empty())
14263 assert(Sequence.empty() &&
"Failed to empty non-repeating sequence pattern");
14304 const APFloat &APF = CN->getValueAPF();
14310 return IntVal.exactLogBase2();
14316 bool IsLittleEndian,
unsigned DstEltSizeInBits,
14324 assert(((NumSrcOps * SrcEltSizeInBits) % DstEltSizeInBits) == 0 &&
14325 "Invalid bitcast scale");
14330 BitVector SrcUndeElements(NumSrcOps,
false);
14332 for (
unsigned I = 0;
I != NumSrcOps; ++
I) {
14334 if (
Op.isUndef()) {
14335 SrcUndeElements.
set(
I);
14340 assert((CInt || CFP) &&
"Unknown constant");
14341 SrcBitElements[
I] = CInt ? CInt->getAPIntValue().trunc(SrcEltSizeInBits)
14342 : CFP->getValueAPF().bitcastToAPInt();
14346 recastRawBits(IsLittleEndian, DstEltSizeInBits, RawBitElements,
14347 SrcBitElements, UndefElements, SrcUndeElements);
14352 unsigned DstEltSizeInBits,
14357 unsigned NumSrcOps = SrcBitElements.
size();
14358 unsigned SrcEltSizeInBits = SrcBitElements[0].getBitWidth();
14359 assert(((NumSrcOps * SrcEltSizeInBits) % DstEltSizeInBits) == 0 &&
14360 "Invalid bitcast scale");
14361 assert(NumSrcOps == SrcUndefElements.
size() &&
14362 "Vector size mismatch");
14364 unsigned NumDstOps = (NumSrcOps * SrcEltSizeInBits) / DstEltSizeInBits;
14365 DstUndefElements.
clear();
14366 DstUndefElements.
resize(NumDstOps,
false);
14370 if (SrcEltSizeInBits <= DstEltSizeInBits) {
14371 unsigned Scale = DstEltSizeInBits / SrcEltSizeInBits;
14372 for (
unsigned I = 0;
I != NumDstOps; ++
I) {
14373 DstUndefElements.
set(
I);
14374 APInt &DstBits = DstBitElements[
I];
14375 for (
unsigned J = 0; J != Scale; ++J) {
14376 unsigned Idx = (
I * Scale) + (IsLittleEndian ? J : (Scale - J - 1));
14377 if (SrcUndefElements[Idx])
14379 DstUndefElements.
reset(
I);
14380 const APInt &SrcBits = SrcBitElements[Idx];
14382 "Illegal constant bitwidths");
14383 DstBits.
insertBits(SrcBits, J * SrcEltSizeInBits);
14390 unsigned Scale = SrcEltSizeInBits / DstEltSizeInBits;
14391 for (
unsigned I = 0;
I != NumSrcOps; ++
I) {
14392 if (SrcUndefElements[
I]) {
14393 DstUndefElements.
set(
I * Scale, (
I + 1) * Scale);
14396 const APInt &SrcBits = SrcBitElements[
I];
14397 for (
unsigned J = 0; J != Scale; ++J) {
14398 unsigned Idx = (
I * Scale) + (IsLittleEndian ? J : (Scale - J - 1));
14399 APInt &DstBits = DstBitElements[Idx];
14400 DstBits = SrcBits.
extractBits(DstEltSizeInBits, J * DstEltSizeInBits);
14407 unsigned Opc =
Op.getOpcode();
14414std::optional<std::pair<APInt, APInt>>
14418 return std::nullopt;
14421 APInt Start, Stride;
14422 int FirstIdx = -1, SecondIdx = -1;
14426 for (
unsigned I = 0;
I <
NumOps; ++
I) {
14431 return std::nullopt;
14434 if (FirstIdx < 0) {
14437 }
else if (SecondIdx < 0) {
14443 unsigned IdxDiff =
I - FirstIdx;
14444 APInt ValDiff = Val - Start;
14449 return std::nullopt;
14450 IdxDiff >>= CommonPow2Bits;
14458 return std::nullopt;
14461 Start -= Stride * FirstIdx;
14464 if (Val != Start + Stride *
I)
14465 return std::nullopt;
14471 return std::nullopt;
14473 return std::make_pair(Start, Stride);
14479 for (i = 0, e = Mask.size(); i != e && Mask[i] < 0; ++i)
14489 for (
int Idx = Mask[i]; i != e; ++i)
14490 if (Mask[i] >= 0 && Mask[i] != Idx)
14498 SDValue N,
bool AllowOpaques)
const {
14502 return AllowOpaques || !
C->isOpaque();
14511 TLI->isOffsetFoldingLegal(GA))
14539 return std::nullopt;
14541 EVT VT =
N->getValueType(0);
14543 switch (TLI->getBooleanContents(
N.getValueType())) {
14549 return std::nullopt;
14555 return std::nullopt;
14563 assert(!
Node->OperandList &&
"Node already has operands");
14565 "too many operands to fit into SDNode");
14566 SDUse *
Ops = OperandRecycler.allocate(
14569 bool IsDivergent =
false;
14570 for (
unsigned I = 0;
I != Vals.
size(); ++
I) {
14572 Ops[
I].setInitial(Vals[
I]);
14573 EVT VT =
Ops[
I].getValueType();
14576 if (VT != MVT::Other &&
14579 IsDivergent =
true;
14584 if (!TLI->isSDNodeAlwaysUniform(Node)) {
14585 IsDivergent |= TLI->isSDNodeSourceOfDivergence(Node, FLI, UA);
14586 Node->SDNodeBits.IsDivergent = IsDivergent;
14594 while (Vals.
size() > Limit) {
14595 unsigned SliceIdx = Vals.
size() - Limit;
14671 const SDLoc &DLoc) {
14675 RTLIB::LibcallImpl LibcallImpl =
14676 Libcalls->getLibcallImpl(
static_cast<RTLIB::Libcall
>(LibFunc));
14677 if (LibcallImpl == RTLIB::Unsupported)
14684 Libcalls->getLibcallImplCallingConv(LibcallImpl),
14686 return TLI->LowerCallTo(CLI).second;
14690 assert(From && To &&
"Invalid SDNode; empty source SDValue?");
14691 auto I = SDEI.find(From);
14692 if (
I == SDEI.end())
14697 NodeExtraInfo NEI =
I->second;
14706 SDEI[To] = std::move(NEI);
14723 auto VisitFrom = [&](
auto &&Self,
const SDNode *
N,
int MaxDepth) {
14724 if (MaxDepth == 0) {
14730 if (!FromReach.
insert(
N).second)
14733 Self(Self,
Op.getNode(), MaxDepth - 1);
14738 auto DeepCopyTo = [&](
auto &&Self,
const SDNode *
N) {
14741 if (!Visited.
insert(
N).second)
14746 if (
N == To &&
Op.getNode() == EntrySDN) {
14751 if (!Self(Self,
Op.getNode()))
14755 SDEI[
N] = std::move(NEI);
14765 for (
int PrevDepth = 0, MaxDepth = 16; MaxDepth <= 1024;
14766 PrevDepth = MaxDepth, MaxDepth *= 2, Visited.
clear()) {
14771 for (
const SDNode *
N : StartFrom)
14772 VisitFrom(VisitFrom,
N, MaxDepth - PrevDepth);
14776 LLVM_DEBUG(
dbgs() << __func__ <<
": MaxDepth=" << MaxDepth <<
" too low\n");
14784 errs() <<
"warning: incomplete propagation of SelectionDAG::NodeExtraInfo\n";
14785 assert(
false &&
"From subgraph too complex - increase max. MaxDepth?");
14787 SDEI[To] = std::move(NEI);
14801 if (!Visited.
insert(
N).second) {
14802 errs() <<
"Detected cycle in SelectionDAG\n";
14803 dbgs() <<
"Offending node:\n";
14804 N->dumprFull(DAG);
dbgs() <<
"\n";
14820 bool check = force;
14821#ifdef EXPENSIVE_CHECKS
14825 assert(
N &&
"Checking nonexistent SDNode");
assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")
static bool isConstant(const MachineInstr &MI)
This file declares a class to represent arbitrary precision floating point values and provide a varie...
This file implements a class to represent arbitrary precision integral constant values and operations...
This file implements the APSInt class, which is a simple class that represents an arbitrary sized int...
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
This file implements the BitVector class.
static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
static std::optional< bool > isBigEndian(const SmallDenseMap< int64_t, int64_t, 8 > &MemOffset2Idx, int64_t LowestIdx)
Given a map from byte offsets in memory to indices in a load/store, determine if that map corresponds...
#define __asan_unpoison_memory_region(p, size)
#define LLVM_LIKELY(EXPR)
This file contains the declarations for the subclasses of Constant, which represent the different fla...
This file defines the DenseSet and SmallDenseSet classes.
This file contains constants used for implementing Dwarf debug support.
This file defines a hash set that can be used to remove duplication of nodes in a graph.
std::pair< Instruction::BinaryOps, Value * > OffsetOp
Find all possible pairs (BinOp, RHS) that BinOp V, RHS can be simplified.
const size_t AbstractManglingParser< Derived, Alloc >::NumOps
const AbstractManglingParser< Derived, Alloc >::OperatorInfo AbstractManglingParser< Derived, Alloc >::Ops[]
static Register getMemsetValue(Register Val, LLT Ty, MachineIRBuilder &MIB)
static bool shouldLowerMemFuncForSize(const MachineFunction &MF)
static bool isZero(Value *V, const DataLayout &DL, DominatorTree *DT, AssumptionCache *AC)
static Align getPrefTypeAlign(EVT VT, SelectionDAG &DAG)
This file declares the MachineConstantPool class which is an abstract constant pool to keep track of ...
Register const TargetRegisterInfo * TRI
This file provides utility analysis objects describing memory locations.
static MCRegister getReg(const MCDisassembler *D, unsigned RC, unsigned RegNo)
ConstantRange Range(APInt(BitWidth, Low), APInt(BitWidth, High))
PowerPC Reduce CR logical Operation
const SmallVectorImpl< MachineOperand > & Cond
Remove Loads Into Fake Uses
static bool isValid(const char C)
Returns true if C is a valid mangled character: <0-9a-zA-Z_>.
Contains matchers for matching SelectionDAG nodes and values.
static Type * getValueType(Value *V)
Returns the type of the given value/instruction V.
static uint64_t umul_ov(uint64_t i, uint64_t j, bool &Overflow)
static SDValue getMemcpyLoadsAndStores(SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Src, uint64_t Size, Align Alignment, bool isVol, bool AlwaysInline, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo, const AAMDNodes &AAInfo, BatchAAResults *BatchAA)
static SDValue getFixedOrScalableQuantity(SelectionDAG &DAG, const SDLoc &DL, EVT VT, Ty Quantity)
static std::pair< SDValue, SDValue > getRuntimeCallSDValueHelper(SDValue Chain, const SDLoc &dl, TargetLowering::ArgListTy &&Args, const CallInst *CI, RTLIB::Libcall Call, SelectionDAG *DAG, const TargetLowering *TLI)
static SDValue getMemsetStores(SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Src, uint64_t Size, Align Alignment, bool isVol, bool AlwaysInline, MachinePointerInfo DstPtrInfo, const AAMDNodes &AAInfo)
Lower the call to 'memset' intrinsic function into a series of store operations.
static std::optional< APInt > FoldValueWithUndef(unsigned Opcode, const APInt &C1, bool IsUndef1, const APInt &C2, bool IsUndef2)
static SDValue FoldSTEP_VECTOR(const SDLoc &DL, EVT VT, SDValue Step, SelectionDAG &DAG)
static void AddNodeIDNode(FoldingSetNodeID &ID, unsigned OpC, SDVTList VTList, ArrayRef< SDValue > OpList)
static SDValue getMemsetStringVal(EVT VT, const SDLoc &dl, SelectionDAG &DAG, const TargetLowering &TLI, const ConstantDataArraySlice &Slice)
getMemsetStringVal - Similar to getMemsetValue.
static cl::opt< bool > EnableMemCpyDAGOpt("enable-memcpy-dag-opt", cl::Hidden, cl::init(true), cl::desc("Gang up loads and stores generated by inlining of memcpy"))
static bool haveNoCommonBitsSetCommutative(SDValue A, SDValue B)
static void AddNodeIDValueTypes(FoldingSetNodeID &ID, SDVTList VTList)
AddNodeIDValueTypes - Value type lists are intern'd so we can represent them solely with their pointe...
static void commuteShuffle(SDValue &N1, SDValue &N2, MutableArrayRef< int > M)
Swaps the values of N1 and N2.
static bool isMemSrcFromConstant(SDValue Src, ConstantDataArraySlice &Slice)
Returns true if memcpy source is constant data.
static SDValue getMemmoveLoadsAndStores(SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Src, uint64_t Size, Align Alignment, bool isVol, bool AlwaysInline, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo, const AAMDNodes &AAInfo)
static void AddNodeIDOpcode(FoldingSetNodeID &ID, unsigned OpC)
AddNodeIDOpcode - Add the node opcode to the NodeID data.
static ISD::CondCode getSetCCInverseImpl(ISD::CondCode Op, bool isIntegerLike)
static bool doNotCSE(SDNode *N)
doNotCSE - Return true if CSE should not be performed for this node.
static cl::opt< int > MaxLdStGlue("ldstmemcpy-glue-max", cl::desc("Number limit for gluing ld/st of memcpy."), cl::Hidden, cl::init(0))
static void AddNodeIDOperands(FoldingSetNodeID &ID, ArrayRef< SDValue > Ops)
AddNodeIDOperands - Various routines for adding operands to the NodeID data.
static SDValue foldCONCAT_VECTORS(const SDLoc &DL, EVT VT, ArrayRef< SDValue > Ops, SelectionDAG &DAG)
Try to simplify vector concatenation to an input value, undef, or build vector.
static MachinePointerInfo InferPointerInfo(const MachinePointerInfo &Info, SelectionDAG &DAG, SDValue Ptr, int64_t Offset=0)
InferPointerInfo - If the specified ptr/offset is a frame index, infer a MachinePointerInfo record fr...
static bool isInTailCallPositionWrapper(const CallInst *CI, const SelectionDAG *SelDAG, bool AllowReturnsFirstArg)
static void AddNodeIDCustom(FoldingSetNodeID &ID, const SDNode *N)
If this is an SDNode with special info, add this info to the NodeID data.
static bool gluePropagatesDivergence(const SDNode *Node)
Return true if a glue output should propagate divergence information.
static void NewSDValueDbgMsg(SDValue V, StringRef Msg, SelectionDAG *G)
static SDVTList makeVTList(const EVT *VTs, unsigned NumVTs)
makeVTList - Return an instance of the SDVTList struct initialized with the specified members.
static void checkForCyclesHelper(const SDNode *N, SmallPtrSetImpl< const SDNode * > &Visited, SmallPtrSetImpl< const SDNode * > &Checked, const llvm::SelectionDAG *DAG)
static void chainLoadsAndStoresForMemcpy(SelectionDAG &DAG, const SDLoc &dl, SmallVector< SDValue, 32 > &OutChains, unsigned From, unsigned To, SmallVector< SDValue, 16 > &OutLoadChains, SmallVector< SDValue, 16 > &OutStoreChains)
static int isSignedOp(ISD::CondCode Opcode)
For an integer comparison, return 1 if the comparison is a signed operation and 2 if the result is an...
static std::optional< APInt > FoldValue(unsigned Opcode, const APInt &C1, const APInt &C2)
static SDValue FoldBUILD_VECTOR(const SDLoc &DL, EVT VT, ArrayRef< SDValue > Ops, SelectionDAG &DAG)
static void checkAddrSpaceIsValidForLibcall(const TargetLowering *TLI, unsigned AS)
static cl::opt< unsigned > MaxSteps("has-predecessor-max-steps", cl::Hidden, cl::init(8192), cl::desc("DAG combiner limit number of steps when searching DAG " "for predecessor nodes"))
This file defines the SmallPtrSet class.
This file defines the SmallVector class.
static TableGen::Emitter::Opt Y("gen-skeleton-entry", EmitSkeleton, "Generate example skeleton entry")
static SymbolRef::Type getType(const Symbol *Sym)
This file describes how to lower LLVM code to machine code.
static void removeOperands(MachineInstr &MI, unsigned i)
static std::optional< unsigned > getOpcode(ArrayRef< VPValue * > Values)
Returns the opcode of Values or ~0 if they do not all agree.
static OverflowResult mapOverflowResult(ConstantRange::OverflowResult OR)
Convert ConstantRange OverflowResult into ValueTracking OverflowResult.
static int Lookup(ArrayRef< TableEntry > Table, unsigned Opcode)
static unsigned getSize(unsigned Kind)
static const fltSemantics & IEEEsingle()
cmpResult
IEEE-754R 5.11: Floating Point Comparison Relations.
static constexpr roundingMode rmTowardZero
static const fltSemantics & BFloat()
static const fltSemantics & IEEEquad()
static const fltSemantics & IEEEdouble()
static constexpr roundingMode rmTowardNegative
static constexpr roundingMode rmNearestTiesToEven
static constexpr roundingMode rmTowardPositive
static const fltSemantics & IEEEhalf()
opStatus
IEEE-754R 7: Default exception handling.
static APFloat getQNaN(const fltSemantics &Sem, bool Negative=false, const APInt *payload=nullptr)
Factory for QNaN values.
opStatus divide(const APFloat &RHS, roundingMode RM)
void copySign(const APFloat &RHS)
LLVM_ABI opStatus convert(const fltSemantics &ToSemantics, roundingMode RM, bool *losesInfo)
opStatus subtract(const APFloat &RHS, roundingMode RM)
bool isExactlyValue(double V) const
We don't rely on operator== working on double values, as it returns true for things that are clearly ...
opStatus add(const APFloat &RHS, roundingMode RM)
opStatus convertFromAPInt(const APInt &Input, bool IsSigned, roundingMode RM)
opStatus multiply(const APFloat &RHS, roundingMode RM)
opStatus fusedMultiplyAdd(const APFloat &Multiplicand, const APFloat &Addend, roundingMode RM)
static APFloat getLargest(const fltSemantics &Sem, bool Negative=false)
Returns the largest finite number in the given semantics.
opStatus convertToInteger(MutableArrayRef< integerPart > Input, unsigned int Width, bool IsSigned, roundingMode RM, bool *IsExact) const
static APFloat getInf(const fltSemantics &Sem, bool Negative=false)
Factory for Positive and Negative Infinity.
opStatus mod(const APFloat &RHS)
static APFloat getNaN(const fltSemantics &Sem, bool Negative=false, uint64_t payload=0)
Factory for NaN values.
Class for arbitrary precision integers.
LLVM_ABI APInt umul_ov(const APInt &RHS, bool &Overflow) const
LLVM_ABI APInt usub_sat(const APInt &RHS) const
LLVM_ABI APInt udiv(const APInt &RHS) const
Unsigned division operation.
static APInt getAllOnes(unsigned numBits)
Return an APInt of a specified width with all bits set.
void clearBit(unsigned BitPosition)
Set a given bit to 0.
LLVM_ABI APInt zext(unsigned width) const
Zero extend to a new width.
static APInt getSignMask(unsigned BitWidth)
Get the SignMask for a specific bit width.
uint64_t getZExtValue() const
Get zero extended value.
void setHighBits(unsigned hiBits)
Set the top hiBits bits.
unsigned popcount() const
Count the number of bits set.
void setBitsFrom(unsigned loBit)
Set the top bits starting from loBit.
LLVM_ABI APInt getHiBits(unsigned numBits) const
Compute an APInt containing numBits highbits from this APInt.
LLVM_ABI APInt zextOrTrunc(unsigned width) const
Zero extend or truncate to width.
unsigned getActiveBits() const
Compute the number of active bits in the value.
LLVM_ABI APInt trunc(unsigned width) const
Truncate to new width.
void setBit(unsigned BitPosition)
Set the given bit to 1 whose position is given as "bitPosition".
APInt abs() const
Get the absolute value.
LLVM_ABI APInt sadd_sat(const APInt &RHS) const
bool isAllOnes() const
Determine if all bits are set. This is true for zero-width values.
bool ugt(const APInt &RHS) const
Unsigned greater than comparison.
static APInt getBitsSet(unsigned numBits, unsigned loBit, unsigned hiBit)
Get a value with a block of bits set.
bool isZero() const
Determine if this value is zero, i.e. all bits are clear.
LLVM_ABI APInt urem(const APInt &RHS) const
Unsigned remainder operation.
unsigned getBitWidth() const
Return the number of bits in the APInt.
bool ult(const APInt &RHS) const
Unsigned less than comparison.
static APInt getSignedMaxValue(unsigned numBits)
Gets maximum signed value of APInt for a specific bit width.
bool isNegative() const
Determine sign of this APInt.
LLVM_ABI APInt sdiv(const APInt &RHS) const
Signed division function for APInt.
void clearAllBits()
Set every bit to 0.
LLVM_ABI APInt rotr(unsigned rotateAmt) const
Rotate right by rotateAmt.
LLVM_ABI APInt reverseBits() const
void ashrInPlace(unsigned ShiftAmt)
Arithmetic right-shift this APInt by ShiftAmt in place.
bool sle(const APInt &RHS) const
Signed less or equal comparison.
unsigned countr_zero() const
Count the number of trailing zero bits.
unsigned getNumSignBits() const
Computes the number of leading bits of this APInt that are equal to its sign bit.
unsigned countl_zero() const
The APInt version of std::countl_zero.
static LLVM_ABI APInt getSplat(unsigned NewLen, const APInt &V)
Return a value containing V broadcasted over NewLen bits.
static APInt getSignedMinValue(unsigned numBits)
Gets minimum signed value of APInt for a specific bit width.
LLVM_ABI APInt sshl_sat(const APInt &RHS) const
LLVM_ABI APInt ushl_sat(const APInt &RHS) const
LLVM_ABI APInt sextOrTrunc(unsigned width) const
Sign extend or truncate to width.
static bool isSameValue(const APInt &I1, const APInt &I2, bool SignedCompare=false)
Determine if two APInts have the same value, after zero-extending or sign-extending (if SignedCompare...
LLVM_ABI APInt rotl(unsigned rotateAmt) const
Rotate left by rotateAmt.
LLVM_ABI void insertBits(const APInt &SubBits, unsigned bitPosition)
Insert the bits from a smaller APInt starting at bitPosition.
void clearLowBits(unsigned loBits)
Set bottom loBits bits to 0.
unsigned logBase2() const
LLVM_ABI APInt uadd_sat(const APInt &RHS) const
APInt ashr(unsigned ShiftAmt) const
Arithmetic right-shift function.
LLVM_ABI APInt multiplicativeInverse() const
LLVM_ABI APInt srem(const APInt &RHS) const
Function for signed remainder operation.
bool isNonNegative() const
Determine if this APInt Value is non-negative (>= 0)
bool ule(const APInt &RHS) const
Unsigned less or equal comparison.
LLVM_ABI APInt sext(unsigned width) const
Sign extend to a new width.
void setBits(unsigned loBit, unsigned hiBit)
Set the bits from loBit (inclusive) to hiBit (exclusive) to 1.
APInt shl(unsigned shiftAmt) const
Left-shift function.
LLVM_ABI APInt byteSwap() const
bool isSubsetOf(const APInt &RHS) const
This operation checks that all bits set in this APInt are also set in RHS.
bool isPowerOf2() const
Check if this APInt's value is a power of two greater than zero.
static APInt getLowBitsSet(unsigned numBits, unsigned loBitsSet)
Constructs an APInt value that has the bottom loBitsSet bits set.
void clearBits(unsigned LoBit, unsigned HiBit)
Clear the bits from LoBit (inclusive) to HiBit (exclusive) to 0.
static APInt getZero(unsigned numBits)
Get the '0' value for the specified bit-width.
void setLowBits(unsigned loBits)
Set the bottom loBits bits.
LLVM_ABI APInt extractBits(unsigned numBits, unsigned bitPosition) const
Return an APInt with the extracted bits [bitPosition,bitPosition+numBits).
bool sge(const APInt &RHS) const
Signed greater or equal comparison.
bool isOne() const
Determine if this is a value of 1.
static APInt getBitsSetFrom(unsigned numBits, unsigned loBit)
Constructs an APInt value that has a contiguous range of bits set.
static APInt getOneBitSet(unsigned numBits, unsigned BitNo)
Return an APInt with exactly one bit set in the result.
void lshrInPlace(unsigned ShiftAmt)
Logical right-shift this APInt by ShiftAmt in place.
APInt lshr(unsigned shiftAmt) const
Logical right-shift function.
bool uge(const APInt &RHS) const
Unsigned greater or equal comparison.
LLVM_ABI APInt ssub_sat(const APInt &RHS) const
An arbitrary precision integer that knows its signedness.
unsigned getSrcAddressSpace() const
unsigned getDestAddressSpace() const
static Capacity get(size_t N)
Get the capacity of an array that can hold at least N elements.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
size_t size() const
size - Get the array size.
bool empty() const
empty - Check if the array is empty.
This is an SDNode representing atomic operations.
static LLVM_ABI BaseIndexOffset match(const SDNode *N, const SelectionDAG &DAG)
Parses tree in N for base, index, offset addresses.
This class is a wrapper over an AAResults, and it is intended to be used only when there are no IR ch...
bool pointsToConstantMemory(const MemoryLocation &Loc, bool OrLocal=false)
void resize(unsigned N, bool t=false)
resize - Grow or shrink the bitvector.
void clear()
clear - Removes all bits from the bitvector.
bool none() const
none - Returns true if none of the bits are set.
size_type size() const
size - Returns the number of bits in this bitvector.
int64_t getOffset() const
unsigned getTargetFlags() const
const BlockAddress * getBlockAddress() const
The address of a basic block.
BlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate IR basic block frequen...
A "pseudo-class" with methods for operating on BUILD_VECTORs.
LLVM_ABI bool getConstantRawBits(bool IsLittleEndian, unsigned DstEltSizeInBits, SmallVectorImpl< APInt > &RawBitElements, BitVector &UndefElements) const
Extract the raw bit data from a build vector of Undef, Constant or ConstantFP node elements.
static LLVM_ABI void recastRawBits(bool IsLittleEndian, unsigned DstEltSizeInBits, SmallVectorImpl< APInt > &DstBitElements, ArrayRef< APInt > SrcBitElements, BitVector &DstUndefElements, const BitVector &SrcUndefElements)
Recast bit data SrcBitElements to DstEltSizeInBits wide elements.
LLVM_ABI bool getRepeatedSequence(const APInt &DemandedElts, SmallVectorImpl< SDValue > &Sequence, BitVector *UndefElements=nullptr) const
Find the shortest repeating sequence of values in the build vector.
LLVM_ABI ConstantFPSDNode * getConstantFPSplatNode(const APInt &DemandedElts, BitVector *UndefElements=nullptr) const
Returns the demanded splatted constant FP or null if this is not a constant FP splat.
LLVM_ABI SDValue getSplatValue(const APInt &DemandedElts, BitVector *UndefElements=nullptr) const
Returns the demanded splatted value or a null value if this is not a splat.
LLVM_ABI bool isConstantSplat(APInt &SplatValue, APInt &SplatUndef, unsigned &SplatBitSize, bool &HasAnyUndefs, unsigned MinSplatBits=0, bool isBigEndian=false) const
Check if this is a constant splat, and if so, find the smallest element size that splats the vector.
LLVM_ABI ConstantSDNode * getConstantSplatNode(const APInt &DemandedElts, BitVector *UndefElements=nullptr) const
Returns the demanded splatted constant or null if this is not a constant splat.
LLVM_ABI int32_t getConstantFPSplatPow2ToLog2Int(BitVector *UndefElements, uint32_t BitWidth) const
If this is a constant FP splat and the splatted constant FP is an exact power or 2,...
LLVM_ABI std::optional< std::pair< APInt, APInt > > isArithmeticSequence() const
If this BuildVector is constant and represents an arithmetic sequence "<a, a+n, a+2n,...
LLVM_ABI bool isConstant() const
This class represents a function call, abstracting a target machine's calling convention.
static LLVM_ABI bool isValueValidForType(EVT VT, const APFloat &Val)
const APFloat & getValueAPF() const
bool isExactlyValue(double V) const
We don't rely on operator== working on double values, as it returns true for things that are clearly ...
ConstantFP - Floating Point Values [float, double].
const APFloat & getValue() const
This is the shared class of boolean and integer constants.
unsigned getBitWidth() const
getBitWidth - Return the scalar bitwidth of this constant.
const APInt & getValue() const
Return the constant as an APInt value reference.
MachineConstantPoolValue * getMachineCPVal() const
bool isMachineConstantPoolEntry() const
const Constant * getConstVal() const
LLVM_ABI Type * getType() const
unsigned getTargetFlags() const
This class represents a range of values.
LLVM_ABI ConstantRange multiply(const ConstantRange &Other) const
Return a new range representing the possible values resulting from a multiplication of a value in thi...
const APInt * getSingleElement() const
If this set contains a single element, return it, otherwise return null.
static LLVM_ABI ConstantRange fromKnownBits(const KnownBits &Known, bool IsSigned)
Initialize a range based on a known bits constraint.
LLVM_ABI OverflowResult unsignedSubMayOverflow(const ConstantRange &Other) const
Return whether unsigned sub of the two ranges always/never overflows.
LLVM_ABI OverflowResult unsignedAddMayOverflow(const ConstantRange &Other) const
Return whether unsigned add of the two ranges always/never overflows.
LLVM_ABI KnownBits toKnownBits() const
Return known bits for values in this range.
LLVM_ABI ConstantRange zeroExtend(uint32_t BitWidth) const
Return a new range in the specified integer type, which must be strictly larger than the current type...
LLVM_ABI APInt getSignedMin() const
Return the smallest signed value contained in the ConstantRange.
LLVM_ABI OverflowResult unsignedMulMayOverflow(const ConstantRange &Other) const
Return whether unsigned mul of the two ranges always/never overflows.
LLVM_ABI ConstantRange signExtend(uint32_t BitWidth) const
Return a new range in the specified integer type, which must be strictly larger than the current type...
LLVM_ABI bool contains(const APInt &Val) const
Return true if the specified value is in the set.
LLVM_ABI APInt getUnsignedMax() const
Return the largest unsigned value contained in the ConstantRange.
LLVM_ABI APInt getSignedMax() const
Return the largest signed value contained in the ConstantRange.
OverflowResult
Represents whether an operation on the given constant range is known to always or never overflow.
@ NeverOverflows
Never overflows.
@ AlwaysOverflowsHigh
Always overflows in the direction of signed/unsigned max value.
@ AlwaysOverflowsLow
Always overflows in the direction of signed/unsigned min value.
@ MayOverflow
May or may not overflow.
uint32_t getBitWidth() const
Get the bit width of this ConstantRange.
LLVM_ABI OverflowResult signedSubMayOverflow(const ConstantRange &Other) const
Return whether signed sub of the two ranges always/never overflows.
uint64_t getZExtValue() const
const APInt & getAPIntValue() const
This is an important base class in LLVM.
LLVM_ABI Constant * getSplatValue(bool AllowPoison=false) const
If all elements of the vector constant have the same value, return that value.
LLVM_ABI Constant * getAggregateElement(unsigned Elt) const
For aggregates (struct/array/vector) return the constant that corresponds to the specified element if...
static LLVM_ABI ExtOps getExtOps(unsigned FromSize, unsigned ToSize, bool Signed)
Returns the ops for a zero- or sign-extension in a DIExpression.
static LLVM_ABI void appendOffset(SmallVectorImpl< uint64_t > &Ops, int64_t Offset)
Append Ops with operations to apply the Offset.
static LLVM_ABI DIExpression * appendOpsToArg(const DIExpression *Expr, ArrayRef< uint64_t > Ops, unsigned ArgNo, bool StackValue=false)
Create a copy of Expr by appending the given list of Ops to each instance of the operand DW_OP_LLVM_a...
static LLVM_ABI const DIExpression * convertToVariadicExpression(const DIExpression *Expr)
If Expr is a non-variadic expression (i.e.
static LLVM_ABI std::optional< DIExpression * > createFragmentExpression(const DIExpression *Expr, unsigned OffsetInBits, unsigned SizeInBits)
Create a DIExpression to describe one part of an aggregate variable that is fragmented across multipl...
Base class for variables.
A parsed version of the target data layout string in and methods for querying it.
bool isLittleEndian() const
Layout endianness...
LLVM_ABI IntegerType * getIntPtrType(LLVMContext &C, unsigned AddressSpace=0) const
Returns an integer type with size at least as big as that of a pointer in the given address space.
LLVM_ABI Align getABITypeAlign(Type *Ty) const
Returns the minimum ABI-required alignment for the specified type.
LLVM_ABI unsigned getPointerTypeSizeInBits(Type *) const
The pointer representation size in bits for this type.
LLVM_ABI Align getPrefTypeAlign(Type *Ty) const
Returns the preferred stack/global alignment for the specified type.
Implements a dense probed hash-table based set.
const char * getSymbol() const
unsigned getTargetFlags() const
FoldingSetNodeID - This class is used to gather all the unique data bits of a node.
Data structure describing the variable locations in a function.
bool hasMinSize() const
Optimize this function for minimum size (-Oz).
AttributeList getAttributes() const
Return the attribute list for this Function.
int64_t getOffset() const
LLVM_ABI unsigned getAddressSpace() const
unsigned getTargetFlags() const
const GlobalValue * getGlobal() const
bool isThreadLocal() const
If the value is "Thread Local", its value isn't shared by the threads.
unsigned getAddressSpace() const
Module * getParent()
Get the module that this global value is contained inside of...
PointerType * getType() const
Global values are always pointers.
This class is used to form a handle around another node that is persistent and is updated across invo...
const SDValue & getValue() const
static LLVM_ABI bool compare(const APInt &LHS, const APInt &RHS, ICmpInst::Predicate Pred)
Return result of LHS Pred RHS comparison.
This is an important class for using LLVM in a threaded context.
Tracks which library functions to use for a particular subtarget.
LLVM_ABI CallingConv::ID getLibcallImplCallingConv(RTLIB::LibcallImpl Call) const
Get the CallingConv that should be used for the specified libcall.
LLVM_ABI RTLIB::LibcallImpl getLibcallImpl(RTLIB::Libcall Call) const
Return the lowering's selection of implementation call for Call.
This SDNode is used for LIFETIME_START/LIFETIME_END values.
This class is used to represent ISD::LOAD nodes.
static LocationSize precise(uint64_t Value)
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
const MDOperand & getOperand(unsigned I) const
static MVT getIntegerVT(unsigned BitWidth)
Abstract base class for all machine specific constantpool value subclasses.
virtual void addSelectionDAGCSEId(FoldingSetNodeID &ID)=0
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
LLVM_ABI int CreateStackObject(uint64_t Size, Align Alignment, bool isSpillSlot, const AllocaInst *Alloca=nullptr, uint8_t ID=0)
Create a new statically sized stack object, returning a nonnegative identifier to represent it.
Align getObjectAlign(int ObjectIdx) const
Return the alignment of the specified stack object.
bool isFixedObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a fixed stack object.
void setObjectAlignment(int ObjectIdx, Align Alignment)
setObjectAlignment - Change the alignment of the specified stack object.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Function & getFunction()
Return the LLVM function that this machine code represents.
const TargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
A description of a memory reference used in the backend.
const MDNode * getRanges() const
Return the range tag for the memory reference.
Flags
Flags values. These may be or'd together.
@ MOVolatile
The memory access is volatile.
@ MODereferenceable
The memory access is dereferenceable (i.e., doesn't trap).
@ MOLoad
The memory access reads data.
@ MOInvariant
The memory access always returns the same value (or traps).
@ MOStore
The memory access writes data.
const MachinePointerInfo & getPointerInfo() const
Flags getFlags() const
Return the raw flags of the source value,.
This class contains meta information specific to a module.
An SDNode that represents everything that will be needed to construct a MachineInstr.
This class is used to represent an MGATHER node.
This class is used to represent an MLOAD node.
This class is used to represent an MSCATTER node.
This class is used to represent an MSTORE node.
This SDNode is used for target intrinsics that touch memory and need an associated MachineMemOperand.
size_t getNumMemOperands() const
Return the number of memory operands.
LLVM_ABI MemSDNode(unsigned Opc, unsigned Order, const DebugLoc &dl, SDVTList VTs, EVT memvt, PointerUnion< MachineMemOperand *, MachineMemOperand ** > memrefs)
Constructor that supports single or multiple MMOs.
PointerUnion< MachineMemOperand *, MachineMemOperand ** > MemRefs
Memory reference information.
MachineMemOperand * getMemOperand() const
Return the unique MachineMemOperand object describing the memory reference performed by operation.
const MachinePointerInfo & getPointerInfo() const
ArrayRef< MachineMemOperand * > memoperands() const
Return the memory operands for this node.
unsigned getRawSubclassData() const
Return the SubclassData value, without HasDebugValue.
EVT getMemoryVT() const
Return the type of the in-memory value.
Representation for a specific memory location.
A Module instance is used to store all the information related to an LLVM module.
Function * getFunction(StringRef Name) const
Look up the specified function in the module symbol table.
MutableArrayRef - Represent a mutable reference to an array (0 or more elements consecutively in memo...
Pass interface - Implemented by all 'passes'.
Class to represent pointers.
static PointerType * getUnqual(Type *ElementType)
This constructs a pointer to an object of the specified type in the default address space (address sp...
unsigned getAddressSpace() const
Return the address space of the Pointer type.
static LLVM_ABI PointerType * get(Type *ElementType, unsigned AddressSpace)
This constructs a pointer to an object of the specified type in a numbered address space.
A discriminated union of two or more pointer types, with the discriminator in the low bit of the poin...
bool isNull() const
Test if the pointer held in the union is null, regardless of which type it is.
Analysis providing profile information.
void Deallocate(SubClass *E)
Deallocate - Release storage for the pointed-to object.
Wrapper class representing virtual and physical registers.
Keeps track of dbg_value information through SDISel.
LLVM_ABI void add(SDDbgValue *V, bool isParameter)
LLVM_ABI void erase(const SDNode *Node)
Invalidate all DbgValues attached to the node and remove it from the Node-to-DbgValues map.
Holds the information from a dbg_label node through SDISel.
Holds the information for a single machine location through SDISel; either an SDNode,...
static SDDbgOperand fromNode(SDNode *Node, unsigned ResNo)
static SDDbgOperand fromFrameIdx(unsigned FrameIdx)
static SDDbgOperand fromVReg(Register VReg)
static SDDbgOperand fromConst(const Value *Const)
@ SDNODE
Value is the result of an expression.
Holds the information from a dbg_value node through SDISel.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
const DebugLoc & getDebugLoc() const
unsigned getIROrder() const
This class provides iterator support for SDUse operands that use a specific SDNode.
Represents one node in the SelectionDAG.
ArrayRef< SDUse > ops() const
const APInt & getAsAPIntVal() const
Helper method returns the APInt value of a ConstantSDNode.
LLVM_ABI void dumprFull(const SelectionDAG *G=nullptr) const
printrFull to dbgs().
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
LLVM_ABI bool isOnlyUserOf(const SDNode *N) const
Return true if this node is the only use of N.
iterator_range< value_op_iterator > op_values() const
unsigned getIROrder() const
Return the node ordering.
static constexpr size_t getMaxNumOperands()
Return the maximum number of operands that a SDNode can hold.
iterator_range< use_iterator > uses()
MemSDNodeBitfields MemSDNodeBits
LLVM_ABI void Profile(FoldingSetNodeID &ID) const
Gather unique data for the node.
bool getHasDebugValue() const
SDNodeFlags getFlags() const
void setNodeId(int Id)
Set unique node id.
LLVM_ABI void intersectFlagsWith(const SDNodeFlags Flags)
Clear any flags in this node that aren't also set in Flags.
static bool hasPredecessorHelper(const SDNode *N, SmallPtrSetImpl< const SDNode * > &Visited, SmallVectorImpl< const SDNode * > &Worklist, unsigned int MaxSteps=0, bool TopologicalPrune=false)
Returns true if N is a predecessor of any node in Worklist.
uint64_t getAsZExtVal() const
Helper method returns the zero-extended integer value of a ConstantSDNode.
bool use_empty() const
Return true if there are no uses of this node.
unsigned getNumValues() const
Return the number of values defined/returned by this operator.
unsigned getNumOperands() const
Return the number of values used by this operation.
const SDValue & getOperand(unsigned Num) const
static LLVM_ABI bool areOnlyUsersOf(ArrayRef< const SDNode * > Nodes, const SDNode *N)
Return true if all the users of N are contained in Nodes.
use_iterator use_begin() const
Provide iteration support to walk over all uses of an SDNode.
LLVM_ABI bool isOperandOf(const SDNode *N) const
Return true if this node is an operand of N.
const APInt & getConstantOperandAPInt(unsigned Num) const
Helper method returns the APInt of a ConstantSDNode operand.
std::optional< APInt > bitcastToAPInt() const
LLVM_ABI bool hasPredecessor(const SDNode *N) const
Return true if N is a predecessor of this node.
LLVM_ABI bool hasAnyUseOfValue(unsigned Value) const
Return true if there are any use of the indicated value.
EVT getValueType(unsigned ResNo) const
Return the type of a specified result.
bool isUndef() const
Returns true if the node type is UNDEF or POISON.
op_iterator op_end() const
op_iterator op_begin() const
static use_iterator use_end()
LLVM_ABI void DropOperands()
Release the operands and set this node to have zero operands.
SDNode(unsigned Opc, unsigned Order, DebugLoc dl, SDVTList VTs)
Create an SDNode.
Represents a use of a SDNode.
SDNode * getUser()
This returns the SDNode that contains this Use.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
SDNode * getNode() const
get the SDNode which holds the desired result
bool hasOneUse() const
Return true if there is exactly one node using value ResNo of Node.
LLVM_ABI bool isOperandOf(const SDNode *N) const
Return true if the referenced return value is an operand of N.
LLVM_ABI bool reachesChainWithoutSideEffects(SDValue Dest, unsigned Depth=2) const
Return true if this operand (which must be a chain) reaches the specified operand without crossing an...
SDValue getValue(unsigned R) const
EVT getValueType() const
Return the ValueType of the referenced return value.
TypeSize getValueSizeInBits() const
Returns the size of the value in bits.
const SDValue & getOperand(unsigned i) const
bool use_empty() const
Return true if there are no nodes using value ResNo of Node.
const APInt & getConstantOperandAPInt(unsigned i) const
uint64_t getScalarValueSizeInBits() const
unsigned getResNo() const
get the index which selects a specific result in the SDNode
uint64_t getConstantOperandVal(unsigned i) const
unsigned getOpcode() const
virtual void verifyTargetNode(const SelectionDAG &DAG, const SDNode *N) const
Checks that the given target-specific node is valid. Aborts if it is not.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
LLVM_ABI SDValue getElementCount(const SDLoc &DL, EVT VT, ElementCount EC)
LLVM_ABI Align getReducedAlign(EVT VT, bool UseABI)
In most cases this function returns the ABI alignment for a given type, except for illegal vector typ...
LLVM_ABI SDValue getVPZeroExtendInReg(SDValue Op, SDValue Mask, SDValue EVL, const SDLoc &DL, EVT VT)
Return the expression required to zero extend the Op value assuming it was the smaller SrcTy value.
LLVM_ABI SDValue getShiftAmountOperand(EVT LHSTy, SDValue Op)
Return the specified value casted to the target's desired shift amount type.
LLVM_ABI SDValue getExtLoad(ISD::LoadExtType ExtType, const SDLoc &dl, EVT VT, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, EVT MemVT, MaybeAlign Alignment=MaybeAlign(), MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
LLVM_ABI std::pair< SDValue, SDValue > getMemccpy(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue C, SDValue Size, const CallInst *CI)
Lower a memccpy operation into a target library call and return the resulting chain and call result a...
LLVM_ABI SDValue getExtLoadVP(ISD::LoadExtType ExtType, const SDLoc &dl, EVT VT, SDValue Chain, SDValue Ptr, SDValue Mask, SDValue EVL, MachinePointerInfo PtrInfo, EVT MemVT, MaybeAlign Alignment, MachineMemOperand::Flags MMOFlags, const AAMDNodes &AAInfo, bool IsExpanding=false)
SDValue getExtractVectorElt(const SDLoc &DL, EVT VT, SDValue Vec, unsigned Idx)
Extract element at Idx from Vec.
LLVM_ABI SDValue getSplatSourceVector(SDValue V, int &SplatIndex)
If V is a splatted value, return the source vector and its splat index.
LLVM_ABI SDValue getLabelNode(unsigned Opcode, const SDLoc &dl, SDValue Root, MCSymbol *Label)
LLVM_ABI OverflowKind computeOverflowForUnsignedSub(SDValue N0, SDValue N1) const
Determine if the result of the unsigned sub of 2 nodes can overflow.
LLVM_ABI unsigned ComputeMaxSignificantBits(SDValue Op, unsigned Depth=0) const
Get the upper bound on bit size for this Value Op as a signed integer.
const SDValue & getRoot() const
Return the root tag of the SelectionDAG.
LLVM_ABI std::pair< SDValue, SDValue > getStrlen(SDValue Chain, const SDLoc &dl, SDValue Src, const CallInst *CI)
Lower a strlen operation into a target library call and return the resulting chain and call result as...
LLVM_ABI SDValue getMaskedGather(SDVTList VTs, EVT MemVT, const SDLoc &dl, ArrayRef< SDValue > Ops, MachineMemOperand *MMO, ISD::MemIndexType IndexType, ISD::LoadExtType ExtTy)
LLVM_ABI SDValue getAddrSpaceCast(const SDLoc &dl, EVT VT, SDValue Ptr, unsigned SrcAS, unsigned DestAS)
Return an AddrSpaceCastSDNode.
LLVM_ABI SDValue FoldSetCC(EVT VT, SDValue N1, SDValue N2, ISD::CondCode Cond, const SDLoc &dl, SDNodeFlags Flags={})
Constant fold a setcc to true or false.
bool isKnownNeverSNaN(SDValue Op, const APInt &DemandedElts, unsigned Depth=0) const
LLVM_ABI std::optional< bool > isBoolConstant(SDValue N) const
Check if a value \op N is a constant using the target's BooleanContent for its type.
LLVM_ABI SDValue getStackArgumentTokenFactor(SDValue Chain)
Compute a TokenFactor to force all the incoming stack arguments to be loaded from the stack.
const TargetSubtargetInfo & getSubtarget() const
LLVM_ABI SDValue getMergeValues(ArrayRef< SDValue > Ops, const SDLoc &dl)
Create a MERGE_VALUES node from the given operands.
LLVM_ABI SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
LLVM_ABI SDValue getShiftAmountConstant(uint64_t Val, EVT VT, const SDLoc &DL)
LLVM_ABI void updateDivergence(SDNode *N)
LLVM_ABI SDValue getSplatValue(SDValue V, bool LegalTypes=false)
If V is a splat vector, return its scalar source operand by extracting that element from the source v...
LLVM_ABI SDValue getAllOnesConstant(const SDLoc &DL, EVT VT, bool IsTarget=false, bool IsOpaque=false)
LLVM_ABI MachineSDNode * getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT)
These are used for target selectors to create a new node with specified return type(s),...
LLVM_ABI void ExtractVectorElements(SDValue Op, SmallVectorImpl< SDValue > &Args, unsigned Start=0, unsigned Count=0, EVT EltVT=EVT())
Append the extracted elements from Start to Count out of the vector Op in Args.
LLVM_ABI SDValue getNeutralElement(unsigned Opcode, const SDLoc &DL, EVT VT, SDNodeFlags Flags)
Get the (commutative) neutral element for the given opcode, if it exists.
LLVM_ABI SDValue getAtomicMemset(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Value, SDValue Size, Type *SizeTy, unsigned ElemSz, bool isTailCall, MachinePointerInfo DstPtrInfo)
LLVM_ABI SDValue getAtomicLoad(ISD::LoadExtType ExtType, const SDLoc &dl, EVT MemVT, EVT VT, SDValue Chain, SDValue Ptr, MachineMemOperand *MMO)
LLVM_ABI SDNode * getNodeIfExists(unsigned Opcode, SDVTList VTList, ArrayRef< SDValue > Ops, const SDNodeFlags Flags, bool AllowCommute=false)
Get the specified node if it's already available, or else return NULL.
LLVM_ABI SDValue getPseudoProbeNode(const SDLoc &Dl, SDValue Chain, uint64_t Guid, uint64_t Index, uint32_t Attr)
Creates a PseudoProbeSDNode with function GUID Guid and the index of the block Index it is probing,...
LLVM_ABI SDValue getFreeze(SDValue V)
Return a freeze using the SDLoc of the value operand.
LLVM_ABI SDNode * SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT)
These are used for target selectors to mutate the specified node to have the specified return type,...
LLVM_ABI void init(MachineFunction &NewMF, OptimizationRemarkEmitter &NewORE, Pass *PassPtr, const TargetLibraryInfo *LibraryInfo, const LibcallLoweringInfo *LibcallsInfo, UniformityInfo *UA, ProfileSummaryInfo *PSIin, BlockFrequencyInfo *BFIin, MachineModuleInfo &MMI, FunctionVarLocs const *FnVarLocs)
Prepare this SelectionDAG to process code in the given MachineFunction.
LLVM_ABI SelectionDAG(const TargetMachine &TM, CodeGenOptLevel)
LLVM_ABI SDValue getMemset(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, Align Alignment, bool isVol, bool AlwaysInline, const CallInst *CI, MachinePointerInfo DstPtrInfo, const AAMDNodes &AAInfo=AAMDNodes())
LLVM_ABI SDValue getBitcastedSExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT)
Convert Op, which must be of integer type, to the integer type VT, by first bitcasting (from potentia...
LLVM_ABI SDValue getConstantPool(const Constant *C, EVT VT, MaybeAlign Align=std::nullopt, int Offs=0, bool isT=false, unsigned TargetFlags=0)
LLVM_ABI SDValue getStridedLoadVP(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, EVT VT, const SDLoc &DL, SDValue Chain, SDValue Ptr, SDValue Offset, SDValue Stride, SDValue Mask, SDValue EVL, EVT MemVT, MachineMemOperand *MMO, bool IsExpanding=false)
LLVM_ABI SDValue getAtomicCmpSwap(unsigned Opcode, const SDLoc &dl, EVT MemVT, SDVTList VTs, SDValue Chain, SDValue Ptr, SDValue Cmp, SDValue Swp, MachineMemOperand *MMO)
Gets a node for an atomic cmpxchg op.
LLVM_ABI SDValue makeEquivalentMemoryOrdering(SDValue OldChain, SDValue NewMemOpChain)
If an existing load has uses of its chain, create a token factor node with that chain and the new mem...
LLVM_ABI bool isConstantIntBuildVectorOrConstantInt(SDValue N, bool AllowOpaques=true) const
Test whether the given value is a constant int or similar node.
LLVM_ABI void ReplaceAllUsesOfValuesWith(const SDValue *From, const SDValue *To, unsigned Num)
Like ReplaceAllUsesOfValueWith, but for multiple values at once.
LLVM_ABI SDValue getJumpTableDebugInfo(int JTI, SDValue Chain, const SDLoc &DL)
LLVM_ABI SDValue getSymbolFunctionGlobalAddress(SDValue Op, Function **TargetFunction=nullptr)
Return a GlobalAddress of the function from the current module with name matching the given ExternalS...
LLVM_ABI std::optional< unsigned > getValidMaximumShiftAmount(SDValue V, const APInt &DemandedElts, unsigned Depth=0) const
If a SHL/SRA/SRL node V has shift amounts that are all less than the element bit-width of the shift n...
LLVM_ABI SDValue UnrollVectorOp(SDNode *N, unsigned ResNE=0)
Utility function used by legalize and lowering to "unroll" a vector operation by splitting out the sc...
LLVM_ABI SDValue getVScale(const SDLoc &DL, EVT VT, APInt MulImm)
Return a node that represents the runtime scaling 'MulImm * RuntimeVL'.
LLVM_ABI SDValue getConstantFP(double Val, const SDLoc &DL, EVT VT, bool isTarget=false)
Create a ConstantFPSDNode wrapping a constant value.
OverflowKind
Used to represent the possible overflow behavior of an operation.
static LLVM_ABI unsigned getHasPredecessorMaxSteps()
LLVM_ABI bool haveNoCommonBitsSet(SDValue A, SDValue B) const
Return true if A and B have no common bits set.
SDValue getExtractSubvector(const SDLoc &DL, EVT VT, SDValue Vec, unsigned Idx)
Return the VT typed sub-vector of Vec at Idx.
LLVM_ABI bool cannotBeOrderedNegativeFP(SDValue Op) const
Test whether the given float value is known to be positive.
LLVM_ABI SDValue getRegister(Register Reg, EVT VT)
LLVM_ABI bool calculateDivergence(SDNode *N)
LLVM_ABI std::pair< SDValue, SDValue > getStrcmp(SDValue Chain, const SDLoc &dl, SDValue S0, SDValue S1, const CallInst *CI)
Lower a strcmp operation into a target library call and return the resulting chain and call result as...
LLVM_ABI SDValue getGetFPEnv(SDValue Chain, const SDLoc &dl, SDValue Ptr, EVT MemVT, MachineMemOperand *MMO)
LLVM_ABI SDValue getAssertAlign(const SDLoc &DL, SDValue V, Align A)
Return an AssertAlignSDNode.
LLVM_ABI SDNode * mutateStrictFPToFP(SDNode *Node)
Mutate the specified strict FP node to its non-strict equivalent, unlinking the node from its chain a...
LLVM_ABI SDValue getLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, MaybeAlign Alignment=MaybeAlign(), MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
Loads are not normal binary operators: their result type is not determined by their operands,...
LLVM_ABI bool canIgnoreSignBitOfZero(const SDUse &Use) const
Check if a use of a float value is insensitive to signed zeros.
LLVM_ABI bool SignBitIsZeroFP(SDValue Op, unsigned Depth=0) const
Return true if the sign bit of Op is known to be zero, for a floating-point value.
LLVM_ABI SDValue getMemIntrinsicNode(unsigned Opcode, const SDLoc &dl, SDVTList VTList, ArrayRef< SDValue > Ops, EVT MemVT, MachinePointerInfo PtrInfo, Align Alignment, MachineMemOperand::Flags Flags=MachineMemOperand::MOLoad|MachineMemOperand::MOStore, LocationSize Size=LocationSize::precise(0), const AAMDNodes &AAInfo=AAMDNodes())
Creates a MemIntrinsicNode that may produce a result and takes a list of operands.
SDValue getInsertSubvector(const SDLoc &DL, SDValue Vec, SDValue SubVec, unsigned Idx)
Insert SubVec at the Idx element of Vec.
LLVM_ABI SDValue getBitcastedZExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT)
Convert Op, which must be of integer type, to the integer type VT, by first bitcasting (from potentia...
LLVM_ABI SDValue getStepVector(const SDLoc &DL, EVT ResVT, const APInt &StepVal)
Returns a vector of type ResVT whose elements contain the linear sequence <0, Step,...
SDValue getSetCC(const SDLoc &DL, EVT VT, SDValue LHS, SDValue RHS, ISD::CondCode Cond, SDValue Chain=SDValue(), bool IsSignaling=false, SDNodeFlags Flags={})
Helper function to make it easier to build SetCC's if you just have an ISD::CondCode instead of an SD...
LLVM_ABI SDValue getAtomic(unsigned Opcode, const SDLoc &dl, EVT MemVT, SDValue Chain, SDValue Ptr, SDValue Val, MachineMemOperand *MMO)
Gets a node for an atomic op, produces result (if relevant) and chain and takes 2 operands.
LLVM_ABI SDValue getMemcpy(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, Align Alignment, bool isVol, bool AlwaysInline, const CallInst *CI, std::optional< bool > OverrideTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo, const AAMDNodes &AAInfo=AAMDNodes(), BatchAAResults *BatchAA=nullptr)
LLVM_ABI Align getEVTAlign(EVT MemoryVT) const
Compute the default alignment value for the given type.
LLVM_ABI bool shouldOptForSize() const
LLVM_ABI SDValue getNOT(const SDLoc &DL, SDValue Val, EVT VT)
Create a bitwise NOT operation as (XOR Val, -1).
LLVM_ABI SDValue getVPZExtOrTrunc(const SDLoc &DL, EVT VT, SDValue Op, SDValue Mask, SDValue EVL)
Convert a vector-predicated Op, which must be an integer vector, to the vector-type VT,...
const TargetLowering & getTargetLoweringInfo() const
LLVM_ABI bool isEqualTo(SDValue A, SDValue B) const
Test whether two SDValues are known to compare equal.
static constexpr unsigned MaxRecursionDepth
LLVM_ABI SDValue getStridedStoreVP(SDValue Chain, const SDLoc &DL, SDValue Val, SDValue Ptr, SDValue Offset, SDValue Stride, SDValue Mask, SDValue EVL, EVT MemVT, MachineMemOperand *MMO, ISD::MemIndexedMode AM, bool IsTruncating=false, bool IsCompressing=false)
bool isGuaranteedNotToBePoison(SDValue Op, unsigned Depth=0) const
Return true if this function can prove that Op is never poison.
LLVM_ABI SDValue expandVACopy(SDNode *Node)
Expand the specified ISD::VACOPY node as the Legalize pass would.
LLVM_ABI SDValue getIndexedMaskedLoad(SDValue OrigLoad, const SDLoc &dl, SDValue Base, SDValue Offset, ISD::MemIndexedMode AM)
LLVM_ABI APInt computeVectorKnownZeroElements(SDValue Op, const APInt &DemandedElts, unsigned Depth=0) const
For each demanded element of a vector, see if it is known to be zero.
LLVM_ABI void AddDbgValue(SDDbgValue *DB, bool isParameter)
Add a dbg_value SDNode.
bool NewNodesMustHaveLegalTypes
When true, additional steps are taken to ensure that getConstant() and similar functions return DAG n...
LLVM_ABI std::pair< EVT, EVT > GetSplitDestVTs(const EVT &VT) const
Compute the VTs needed for the low/hi parts of a type which is split (or expanded) into two not neces...
LLVM_ABI void salvageDebugInfo(SDNode &N)
To be invoked on an SDNode that is slated to be erased.
LLVM_ABI SDNode * MorphNodeTo(SDNode *N, unsigned Opc, SDVTList VTs, ArrayRef< SDValue > Ops)
This mutates the specified node to have the specified return type, opcode, and operands.
LLVM_ABI std::pair< SDValue, SDValue > UnrollVectorOverflowOp(SDNode *N, unsigned ResNE=0)
Like UnrollVectorOp(), but for the [US](ADD|SUB|MUL)O family of opcodes.
allnodes_const_iterator allnodes_begin() const
SDValue getUNDEF(EVT VT)
Return an UNDEF node. UNDEF does not have a useful SDLoc.
LLVM_ABI SDValue getGatherVP(SDVTList VTs, EVT VT, const SDLoc &dl, ArrayRef< SDValue > Ops, MachineMemOperand *MMO, ISD::MemIndexType IndexType)
SDValue getBuildVector(EVT VT, const SDLoc &DL, ArrayRef< SDValue > Ops)
Return an ISD::BUILD_VECTOR node.
LLVM_ABI SDValue getBitcastedAnyExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT)
Convert Op, which must be of integer type, to the integer type VT, by first bitcasting (from potentia...
LLVM_ABI bool isSplatValue(SDValue V, const APInt &DemandedElts, APInt &UndefElts, unsigned Depth=0) const
Test whether V has a splatted value for all the demanded elements.
LLVM_ABI void DeleteNode(SDNode *N)
Remove the specified node from the system.
LLVM_ABI SDValue getBitcast(EVT VT, SDValue V)
Return a bitcast using the SDLoc of the value operand, and casting to the provided type.
LLVM_ABI SDDbgValue * getDbgValueList(DIVariable *Var, DIExpression *Expr, ArrayRef< SDDbgOperand > Locs, ArrayRef< SDNode * > Dependencies, bool IsIndirect, const DebugLoc &DL, unsigned O, bool IsVariadic)
Creates a SDDbgValue node from a list of locations.
LLVM_ABI std::pair< SDValue, SDValue > getStrcpy(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, const CallInst *CI)
Lower a strcpy operation into a target library call and return the resulting chain and call result as...
SDValue getSelect(const SDLoc &DL, EVT VT, SDValue Cond, SDValue LHS, SDValue RHS, SDNodeFlags Flags=SDNodeFlags())
Helper function to make it easier to build Select's if you just have operands and don't want to check...
LLVM_ABI SDValue getNegative(SDValue Val, const SDLoc &DL, EVT VT)
Create negative operation as (SUB 0, Val).
LLVM_ABI std::optional< unsigned > getValidShiftAmount(SDValue V, const APInt &DemandedElts, unsigned Depth=0) const
If a SHL/SRA/SRL node V has a uniform shift amount that is less than the element bit-width of the shi...
LLVM_ABI void setNodeMemRefs(MachineSDNode *N, ArrayRef< MachineMemOperand * > NewMemRefs)
Mutate the specified machine node's memory references to the provided list.
LLVM_ABI SDValue simplifySelect(SDValue Cond, SDValue TVal, SDValue FVal)
Try to simplify a select/vselect into 1 of its operands or a constant.
LLVM_ABI SDValue getZeroExtendInReg(SDValue Op, const SDLoc &DL, EVT VT)
Return the expression required to zero extend the Op value assuming it was the smaller SrcTy value.
LLVM_ABI bool isConstantFPBuildVectorOrConstantFP(SDValue N) const
Test whether the given value is a constant FP or similar node.
const DataLayout & getDataLayout() const
LLVM_ABI SDValue expandVAArg(SDNode *Node)
Expand the specified ISD::VAARG node as the Legalize pass would.
LLVM_ABI SDValue getTokenFactor(const SDLoc &DL, SmallVectorImpl< SDValue > &Vals)
Creates a new TokenFactor containing Vals.
LLVM_ABI bool doesNodeExist(unsigned Opcode, SDVTList VTList, ArrayRef< SDValue > Ops)
Check if a node exists without modifying its flags.
const SelectionDAGTargetInfo & getSelectionDAGInfo() const
LLVM_ABI bool areNonVolatileConsecutiveLoads(LoadSDNode *LD, LoadSDNode *Base, unsigned Bytes, int Dist) const
Return true if loads are next to each other and can be merged.
LLVM_ABI SDValue getMaskedHistogram(SDVTList VTs, EVT MemVT, const SDLoc &dl, ArrayRef< SDValue > Ops, MachineMemOperand *MMO, ISD::MemIndexType IndexType)
LLVM_ABI SDDbgLabel * getDbgLabel(DILabel *Label, const DebugLoc &DL, unsigned O)
Creates a SDDbgLabel node.
LLVM_ABI SDValue getStoreVP(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, SDValue Offset, SDValue Mask, SDValue EVL, EVT MemVT, MachineMemOperand *MMO, ISD::MemIndexedMode AM, bool IsTruncating=false, bool IsCompressing=false)
LLVM_ABI OverflowKind computeOverflowForUnsignedMul(SDValue N0, SDValue N1) const
Determine if the result of the unsigned mul of 2 nodes can overflow.
LLVM_ABI void copyExtraInfo(SDNode *From, SDNode *To)
Copy extra info associated with one node to another.
LLVM_ABI SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
Create a ConstantSDNode wrapping a constant value.
LLVM_ABI SDValue getMemBasePlusOffset(SDValue Base, TypeSize Offset, const SDLoc &DL, const SDNodeFlags Flags=SDNodeFlags())
Returns sum of the base pointer and offset.
LLVM_ABI SDValue getGlobalAddress(const GlobalValue *GV, const SDLoc &DL, EVT VT, int64_t offset=0, bool isTargetGA=false, unsigned TargetFlags=0)
LLVM_ABI SDValue getVAArg(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, SDValue SV, unsigned Align)
VAArg produces a result and token chain, and takes a pointer and a source value as input.
LLVM_ABI SDValue getTruncStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, EVT SVT, Align Alignment, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
LLVM_ABI SDValue getLoadFFVP(EVT VT, const SDLoc &DL, SDValue Chain, SDValue Ptr, SDValue Mask, SDValue EVL, MachineMemOperand *MMO)
LLVM_ABI SDValue getTypeSize(const SDLoc &DL, EVT VT, TypeSize TS)
LLVM_ABI SDValue getMDNode(const MDNode *MD)
Return an MDNodeSDNode which holds an MDNode.
LLVM_ABI void clear()
Clear state and free memory necessary to make this SelectionDAG ready to process a new block.
LLVM_ABI std::pair< SDValue, SDValue > getMemcmp(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, const CallInst *CI)
Lower a memcmp operation into a target library call and return the resulting chain and call result as...
LLVM_ABI void ReplaceAllUsesWith(SDValue From, SDValue To)
Modify anything using 'From' to use 'To' instead.
LLVM_ABI SDValue getCommutedVectorShuffle(const ShuffleVectorSDNode &SV)
Returns an ISD::VECTOR_SHUFFLE node semantically equivalent to the shuffle node in input but with swa...
LLVM_ABI std::pair< SDValue, SDValue > SplitVector(const SDValue &N, const SDLoc &DL, const EVT &LoVT, const EVT &HiVT)
Split the vector with EXTRACT_SUBVECTOR using the provided VTs and return the low/high part.
LLVM_ABI SDValue makeStateFunctionCall(unsigned LibFunc, SDValue Ptr, SDValue InChain, const SDLoc &DLoc)
Helper used to make a call to a library function that has one argument of pointer type.
LLVM_ABI bool isGuaranteedNotToBeUndefOrPoison(SDValue Op, bool PoisonOnly=false, unsigned Depth=0) const
Return true if this function can prove that Op is never poison and, if PoisonOnly is false,...
LLVM_ABI SDValue getStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, Align Alignment, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
Helper function to build ISD::STORE nodes.
LLVM_ABI SDValue getSignedConstant(int64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
LLVM_ABI SDValue getIndexedLoadVP(SDValue OrigLoad, const SDLoc &dl, SDValue Base, SDValue Offset, ISD::MemIndexedMode AM)
LLVM_ABI SDValue getSrcValue(const Value *v)
Construct a node to track a Value* through the backend.
SDValue getSplatVector(EVT VT, const SDLoc &DL, SDValue Op)
LLVM_ABI SDValue getAtomicMemcpy(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, Type *SizeTy, unsigned ElemSz, bool isTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo)
LLVM_ABI OverflowKind computeOverflowForSignedMul(SDValue N0, SDValue N1) const
Determine if the result of the signed mul of 2 nodes can overflow.
LLVM_ABI MaybeAlign InferPtrAlign(SDValue Ptr) const
Infer alignment of a load / store address.
LLVM_ABI void dump() const
Dump the textual format of this DAG.
LLVM_ABI bool MaskedValueIsAllOnes(SDValue Op, const APInt &Mask, unsigned Depth=0) const
Return true if '(Op & Mask) == Mask'.
LLVM_ABI bool SignBitIsZero(SDValue Op, unsigned Depth=0) const
Return true if the sign bit of Op is known to be zero.
LLVM_ABI void RemoveDeadNodes()
This method deletes all unreachable nodes in the SelectionDAG.
LLVM_ABI void RemoveDeadNode(SDNode *N)
Remove the specified node from the system.
LLVM_ABI void AddDbgLabel(SDDbgLabel *DB)
Add a dbg_label SDNode.
bool isConstantValueOfAnyType(SDValue N) const
LLVM_ABI SDValue getTargetExtractSubreg(int SRIdx, const SDLoc &DL, EVT VT, SDValue Operand)
A convenience function for creating TargetInstrInfo::EXTRACT_SUBREG nodes.
LLVM_ABI SDValue getBasicBlock(MachineBasicBlock *MBB)
LLVM_ABI SDValue getSExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT)
Convert Op, which must be of integer type, to the integer type VT, by either sign-extending or trunca...
LLVM_ABI SDDbgValue * getVRegDbgValue(DIVariable *Var, DIExpression *Expr, Register VReg, bool IsIndirect, const DebugLoc &DL, unsigned O)
Creates a VReg SDDbgValue node.
LLVM_ABI SDValue getEHLabel(const SDLoc &dl, SDValue Root, MCSymbol *Label)
LLVM_ABI SDValue getIndexedStoreVP(SDValue OrigStore, const SDLoc &dl, SDValue Base, SDValue Offset, ISD::MemIndexedMode AM)
LLVM_ABI bool isKnownNeverZero(SDValue Op, unsigned Depth=0) const
Test whether the given SDValue is known to contain non-zero value(s).
LLVM_ABI SDValue getIndexedStore(SDValue OrigStore, const SDLoc &dl, SDValue Base, SDValue Offset, ISD::MemIndexedMode AM)
LLVM_ABI SDValue FoldConstantArithmetic(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDValue > Ops, SDNodeFlags Flags=SDNodeFlags())
LLVM_ABI std::optional< unsigned > getValidMinimumShiftAmount(SDValue V, const APInt &DemandedElts, unsigned Depth=0) const
If a SHL/SRA/SRL node V has shift amounts that are all less than the element bit-width of the shift n...
LLVM_ABI SDValue getSetFPEnv(SDValue Chain, const SDLoc &dl, SDValue Ptr, EVT MemVT, MachineMemOperand *MMO)
LLVM_ABI SDValue getBoolExtOrTrunc(SDValue Op, const SDLoc &SL, EVT VT, EVT OpVT)
Convert Op, which must be of integer type, to the integer type VT, by using an extension appropriate ...
LLVM_ABI SDValue getMaskedStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Base, SDValue Offset, SDValue Mask, EVT MemVT, MachineMemOperand *MMO, ISD::MemIndexedMode AM, bool IsTruncating=false, bool IsCompressing=false)
LLVM_ABI SDValue getExternalSymbol(const char *Sym, EVT VT)
const TargetMachine & getTarget() const
LLVM_ABI std::pair< SDValue, SDValue > getStrictFPExtendOrRound(SDValue Op, SDValue Chain, const SDLoc &DL, EVT VT)
Convert Op, which must be a STRICT operation of float type, to the float type VT, by either extending...
LLVM_ABI std::pair< SDValue, SDValue > SplitEVL(SDValue N, EVT VecVT, const SDLoc &DL)
Split the explicit vector length parameter of a VP operation.
LLVM_ABI SDValue getPtrExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT)
Convert Op, which must be of integer type, to the integer type VT, by either truncating it or perform...
LLVM_ABI SDValue getVPLogicalNOT(const SDLoc &DL, SDValue Val, SDValue Mask, SDValue EVL, EVT VT)
Create a vector-predicated logical NOT operation as (VP_XOR Val, BooleanOne, Mask,...
LLVM_ABI SDValue getMaskFromElementCount(const SDLoc &DL, EVT VT, ElementCount Len)
Return a vector with the first 'Len' lanes set to true and remaining lanes set to false.
LLVM_ABI SDValue getAnyExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT)
Convert Op, which must be of integer type, to the integer type VT, by either any-extending or truncat...
iterator_range< allnodes_iterator > allnodes()
LLVM_ABI SDValue getBlockAddress(const BlockAddress *BA, EVT VT, int64_t Offset=0, bool isTarget=false, unsigned TargetFlags=0)
LLVM_ABI SDValue WidenVector(const SDValue &N, const SDLoc &DL)
Widen the vector up to the next power of two using INSERT_SUBVECTOR.
LLVM_ABI bool isKnownNeverZeroFloat(SDValue Op) const
Test whether the given floating point SDValue is known to never be positive or negative zero.
const LibcallLoweringInfo & getLibcalls() const
LLVM_ABI SDValue getLoadVP(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, SDValue Offset, SDValue Mask, SDValue EVL, MachinePointerInfo PtrInfo, EVT MemVT, Align Alignment, MachineMemOperand::Flags MMOFlags, const AAMDNodes &AAInfo, const MDNode *Ranges=nullptr, bool IsExpanding=false)
LLVM_ABI SDValue getIntPtrConstant(uint64_t Val, const SDLoc &DL, bool isTarget=false)
LLVM_ABI SDDbgValue * getConstantDbgValue(DIVariable *Var, DIExpression *Expr, const Value *C, const DebugLoc &DL, unsigned O)
Creates a constant SDDbgValue node.
LLVM_ABI SDValue getScatterVP(SDVTList VTs, EVT VT, const SDLoc &dl, ArrayRef< SDValue > Ops, MachineMemOperand *MMO, ISD::MemIndexType IndexType)
LLVM_ABI SDValue getValueType(EVT)
LLVM_ABI SDValue getLifetimeNode(bool IsStart, const SDLoc &dl, SDValue Chain, int FrameIndex)
Creates a LifetimeSDNode that starts (IsStart==true) or ends (IsStart==false) the lifetime of the Fra...
ArrayRef< SDDbgValue * > GetDbgValues(const SDNode *SD) const
Get the debug values which reference the given SDNode.
LLVM_ABI SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
LLVM_ABI OverflowKind computeOverflowForSignedAdd(SDValue N0, SDValue N1) const
Determine if the result of the signed addition of 2 nodes can overflow.
LLVM_ABI SDValue getFPExtendOrRound(SDValue Op, const SDLoc &DL, EVT VT)
Convert Op, which must be of float type, to the float type VT, by either extending or rounding (by tr...
LLVM_ABI unsigned AssignTopologicalOrder()
Topological-sort the AllNodes list and a assign a unique node id for each node in the DAG based on th...
ilist< SDNode >::size_type allnodes_size() const
LLVM_ABI bool isKnownNeverNaN(SDValue Op, const APInt &DemandedElts, bool SNaN=false, unsigned Depth=0) const
Test whether the given SDValue (or all elements of it, if it is a vector) is known to never be NaN in...
LLVM_ABI SDValue FoldConstantBuildVector(BuildVectorSDNode *BV, const SDLoc &DL, EVT DstEltVT)
Fold BUILD_VECTOR of constants/undefs to the destination type BUILD_VECTOR of constants/undefs elemen...
LLVM_ABI SDValue getAtomicMemmove(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, Type *SizeTy, unsigned ElemSz, bool isTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo)
LLVM_ABI SDValue getIndexedMaskedStore(SDValue OrigStore, const SDLoc &dl, SDValue Base, SDValue Offset, ISD::MemIndexedMode AM)
LLVM_ABI SDValue getTruncStoreVP(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, SDValue Mask, SDValue EVL, MachinePointerInfo PtrInfo, EVT SVT, Align Alignment, MachineMemOperand::Flags MMOFlags, const AAMDNodes &AAInfo, bool IsCompressing=false)
SDValue getTargetConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isOpaque=false)
LLVM_ABI unsigned ComputeNumSignBits(SDValue Op, unsigned Depth=0) const
Return the number of times the sign bit of the register is replicated into the other bits.
LLVM_ABI bool MaskedVectorIsZero(SDValue Op, const APInt &DemandedElts, unsigned Depth=0) const
Return true if 'Op' is known to be zero in DemandedElts.
LLVM_ABI SDValue getBoolConstant(bool V, const SDLoc &DL, EVT VT, EVT OpVT)
Create a true or false constant of type VT using the target's BooleanContent for type OpVT.
LLVM_ABI SDDbgValue * getFrameIndexDbgValue(DIVariable *Var, DIExpression *Expr, unsigned FI, bool IsIndirect, const DebugLoc &DL, unsigned O)
Creates a FrameIndex SDDbgValue node.
LLVM_ABI SDValue getExtStridedLoadVP(ISD::LoadExtType ExtType, const SDLoc &DL, EVT VT, SDValue Chain, SDValue Ptr, SDValue Stride, SDValue Mask, SDValue EVL, EVT MemVT, MachineMemOperand *MMO, bool IsExpanding=false)
LLVM_ABI SDValue getMemmove(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, Align Alignment, bool isVol, const CallInst *CI, std::optional< bool > OverrideTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo, const AAMDNodes &AAInfo=AAMDNodes(), BatchAAResults *BatchAA=nullptr)
LLVM_ABI SDValue getJumpTable(int JTI, EVT VT, bool isTarget=false, unsigned TargetFlags=0)
LLVM_ABI bool isBaseWithConstantOffset(SDValue Op) const
Return true if the specified operand is an ISD::ADD with a ConstantSDNode on the right-hand side,...
LLVM_ABI SDValue getVPPtrExtOrTrunc(const SDLoc &DL, EVT VT, SDValue Op, SDValue Mask, SDValue EVL)
Convert a vector-predicated Op, which must be of integer type, to the vector-type integer type VT,...
LLVM_ABI SDValue getVectorIdxConstant(uint64_t Val, const SDLoc &DL, bool isTarget=false)
LLVM_ABI void getTopologicallyOrderedNodes(SmallVectorImpl< const SDNode * > &SortedNodes) const
Get all the nodes in their topological order without modifying any states.
LLVM_ABI void ReplaceAllUsesOfValueWith(SDValue From, SDValue To)
Replace any uses of From with To, leaving uses of other values produced by From.getNode() alone.
MachineFunction & getMachineFunction() const
LLVM_ABI std::pair< SDValue, SDValue > getStrstr(SDValue Chain, const SDLoc &dl, SDValue S0, SDValue S1, const CallInst *CI)
Lower a strstr operation into a target library call and return the resulting chain and call result as...
LLVM_ABI SDValue getPtrExtendInReg(SDValue Op, const SDLoc &DL, EVT VT)
Return the expression required to extend the Op as a pointer value assuming it was the smaller SrcTy ...
LLVM_ABI bool canCreateUndefOrPoison(SDValue Op, const APInt &DemandedElts, bool PoisonOnly=false, bool ConsiderFlags=true, unsigned Depth=0) const
Return true if Op can create undef or poison from non-undef & non-poison operands.
LLVM_ABI OverflowKind computeOverflowForUnsignedAdd(SDValue N0, SDValue N1) const
Determine if the result of the unsigned addition of 2 nodes can overflow.
SDValue getPOISON(EVT VT)
Return a POISON node. POISON does not have a useful SDLoc.
SDValue getSplatBuildVector(EVT VT, const SDLoc &DL, SDValue Op)
Return a splat ISD::BUILD_VECTOR node, consisting of Op splatted to all elements.
LLVM_ABI SDValue getFrameIndex(int FI, EVT VT, bool isTarget=false)
LLVM_ABI SDValue getTruncStridedStoreVP(SDValue Chain, const SDLoc &DL, SDValue Val, SDValue Ptr, SDValue Stride, SDValue Mask, SDValue EVL, EVT SVT, MachineMemOperand *MMO, bool IsCompressing=false)
LLVM_ABI void canonicalizeCommutativeBinop(unsigned Opcode, SDValue &N1, SDValue &N2) const
Swap N1 and N2 if Opcode is a commutative binary opcode and the canonical form expects the opposite o...
LLVM_ABI KnownBits computeKnownBits(SDValue Op, unsigned Depth=0) const
Determine which bits of Op are known to be either zero or one and return them in Known.
LLVM_ABI SDValue getRegisterMask(const uint32_t *RegMask)
LLVM_ABI SDValue getZExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT)
Convert Op, which must be of integer type, to the integer type VT, by either zero-extending or trunca...
LLVM_ABI SDValue getCondCode(ISD::CondCode Cond)
LLVM_ABI bool MaskedValueIsZero(SDValue Op, const APInt &Mask, unsigned Depth=0) const
Return true if 'Op & Mask' is known to be zero.
LLVM_ABI bool isKnownToBeAPowerOfTwoFP(SDValue Val, unsigned Depth=0) const
Test if the given fp value is known to be an integer power-of-2, either positive or negative.
LLVM_ABI OverflowKind computeOverflowForSignedSub(SDValue N0, SDValue N1) const
Determine if the result of the signed sub of 2 nodes can overflow.
SDValue getObjectPtrOffset(const SDLoc &SL, SDValue Ptr, TypeSize Offset)
Create an add instruction with appropriate flags when used for addressing some offset of an object.
LLVMContext * getContext() const
LLVM_ABI SDValue simplifyFPBinop(unsigned Opcode, SDValue X, SDValue Y, SDNodeFlags Flags)
Try to simplify a floating-point binary operation into 1 of its operands or a constant.
const SDValue & setRoot(SDValue N)
Set the current root tag of the SelectionDAG.
LLVM_ABI bool isKnownToBeAPowerOfTwo(SDValue Val, bool OrZero=false, unsigned Depth=0) const
Test if the given value is known to have exactly one bit set.
LLVM_ABI SDValue getDeactivationSymbol(const GlobalValue *GV)
LLVM_ABI SDValue getTargetExternalSymbol(const char *Sym, EVT VT, unsigned TargetFlags=0)
LLVM_ABI SDValue getMCSymbol(MCSymbol *Sym, EVT VT)
LLVM_ABI bool isUndef(unsigned Opcode, ArrayRef< SDValue > Ops)
Return true if the result of this operation is always undefined.
LLVM_ABI SDValue CreateStackTemporary(TypeSize Bytes, Align Alignment)
Create a stack temporary based on the size in bytes and the alignment.
LLVM_ABI SDNode * UpdateNodeOperands(SDNode *N, SDValue Op)
Mutate the specified node in-place to have the specified operands.
LLVM_ABI std::pair< EVT, EVT > GetDependentSplitDestVTs(const EVT &VT, const EVT &EnvVT, bool *HiIsEmpty) const
Compute the VTs needed for the low/hi parts of a type, dependent on an enveloping VT that has been sp...
LLVM_ABI SDValue foldConstantFPMath(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDValue > Ops)
Fold floating-point operations when all operands are constants and/or undefined.
LLVM_ABI std::optional< ConstantRange > getValidShiftAmountRange(SDValue V, const APInt &DemandedElts, unsigned Depth) const
If a SHL/SRA/SRL node V has shift amounts that are all less than the element bit-width of the shift n...
LLVM_ABI SDValue FoldSymbolOffset(unsigned Opcode, EVT VT, const GlobalAddressSDNode *GA, const SDNode *N2)
LLVM_ABI SDValue getIndexedLoad(SDValue OrigLoad, const SDLoc &dl, SDValue Base, SDValue Offset, ISD::MemIndexedMode AM)
LLVM_ABI SDValue getTargetInsertSubreg(int SRIdx, const SDLoc &DL, EVT VT, SDValue Operand, SDValue Subreg)
A convenience function for creating TargetInstrInfo::INSERT_SUBREG nodes.
SDValue getEntryNode() const
Return the token chain corresponding to the entry of the function.
LLVM_ABI SDDbgValue * getDbgValue(DIVariable *Var, DIExpression *Expr, SDNode *N, unsigned R, bool IsIndirect, const DebugLoc &DL, unsigned O)
Creates a SDDbgValue node.
LLVM_ABI SDValue getMaskedLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Base, SDValue Offset, SDValue Mask, SDValue Src0, EVT MemVT, MachineMemOperand *MMO, ISD::MemIndexedMode AM, ISD::LoadExtType, bool IsExpanding=false)
SDValue getSplat(EVT VT, const SDLoc &DL, SDValue Op)
Returns a node representing a splat of one value into all lanes of the provided vector type.
LLVM_ABI std::pair< SDValue, SDValue > SplitScalar(const SDValue &N, const SDLoc &DL, const EVT &LoVT, const EVT &HiVT)
Split the scalar node with EXTRACT_ELEMENT using the provided VTs and return the low/high part.
LLVM_ABI SDValue matchBinOpReduction(SDNode *Extract, ISD::NodeType &BinOp, ArrayRef< ISD::NodeType > CandidateBinOps, bool AllowPartials=false)
Match a binop + shuffle pyramid that represents a horizontal reduction over the elements of a vector ...
LLVM_ABI bool isADDLike(SDValue Op, bool NoWrap=false) const
Return true if the specified operand is an ISD::OR or ISD::XOR node that can be treated as an ISD::AD...
LLVM_ABI SDValue getVectorShuffle(EVT VT, const SDLoc &dl, SDValue N1, SDValue N2, ArrayRef< int > Mask)
Return an ISD::VECTOR_SHUFFLE node.
LLVM_ABI SDValue simplifyShift(SDValue X, SDValue Y)
Try to simplify a shift into 1 of its operands or a constant.
LLVM_ABI void transferDbgValues(SDValue From, SDValue To, unsigned OffsetInBits=0, unsigned SizeInBits=0, bool InvalidateDbg=true)
Transfer debug values from one node to another, while optionally generating fragment expressions for ...
LLVM_ABI SDValue getLogicalNOT(const SDLoc &DL, SDValue Val, EVT VT)
Create a logical NOT operation as (XOR Val, BooleanOne).
LLVM_ABI SDValue getMaskedScatter(SDVTList VTs, EVT MemVT, const SDLoc &dl, ArrayRef< SDValue > Ops, MachineMemOperand *MMO, ISD::MemIndexType IndexType, bool IsTruncating=false)
ilist< SDNode >::iterator allnodes_iterator
This SDNode is used to implement the code generator support for the llvm IR shufflevector instruction...
int getMaskElt(unsigned Idx) const
ArrayRef< int > getMask() const
static void commuteMask(MutableArrayRef< int > Mask)
Change values in a shuffle permute mask assuming the two vector operands have swapped position.
static LLVM_ABI bool isSplatMask(ArrayRef< int > Mask)
A templated base class for SmallPtrSet which provides the typesafe interface that is common across al...
bool erase(PtrType Ptr)
Remove pointer from the set.
size_type count(ConstPtrType Ptr) const
count - Return 1 if the specified pointer is in the set, 0 otherwise.
std::pair< iterator, bool > insert(PtrType Ptr)
Inserts Ptr if and only if there is no element in the container equal to Ptr.
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
void assign(size_type NumElts, ValueParamT Elt)
reference emplace_back(ArgTypes &&... Args)
void reserve(size_type N)
iterator erase(const_iterator CI)
void append(ItTy in_start, ItTy in_end)
Add the specified range to the end of the SmallVector.
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
This class is used to represent ISD::STORE nodes.
StringRef - Represent a constant reference to a string, i.e.
constexpr const char * data() const
data - Get a pointer to the start of the string (which may not be null terminated).
Information about stack frame layout on the target.
virtual TargetStackID::Value getStackIDForScalableVectors() const
Returns the StackID that scalable vectors should be associated with.
Align getStackAlign() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
Completely target-dependent object reference.
int64_t getOffset() const
unsigned getTargetFlags() const
Provides information about what library functions are available for the current target.
virtual bool shouldConvertConstantLoadToIntImm(const APInt &Imm, Type *Ty) const
Return true if it is beneficial to convert a load of a constant to just the constant itself.
const TargetMachine & getTargetMachine() const
virtual bool isZExtFree(Type *FromTy, Type *ToTy) const
Return true if any actual instruction that defines a value of type FromTy implicitly zero-extends the...
unsigned getMaxStoresPerMemcpy(bool OptSize) const
Get maximum # of store operations permitted for llvm.memcpy.
unsigned getMaxStoresPerMemset(bool OptSize) const
Get maximum # of store operations permitted for llvm.memset.
virtual bool shallExtractConstSplatVectorElementToStore(Type *VectorTy, unsigned ElemSizeInBits, unsigned &Index) const
Return true if the target shall perform extract vector element and store given that the vector is kno...
virtual bool isTruncateFree(Type *FromTy, Type *ToTy) const
Return true if it's free to truncate a value of type FromTy to type ToTy.
virtual EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const
For types supported by the target, this is an identity function.
bool isTypeLegal(EVT VT) const
Return true if the target has native support for the specified value type.
virtual MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
BooleanContent
Enum that describes how the target represents true/false values.
@ ZeroOrOneBooleanContent
@ UndefinedBooleanContent
@ ZeroOrNegativeOneBooleanContent
virtual unsigned getMaxGluedStoresPerMemcpy() const
Get maximum # of store operations to be glued together.
std::vector< ArgListEntry > ArgListTy
unsigned getMaxStoresPerMemmove(bool OptSize) const
Get maximum # of store operations permitted for llvm.memmove.
virtual bool isLegalStoreImmediate(int64_t Value) const
Return true if the specified immediate is legal for the value input of a store instruction.
static ISD::NodeType getExtendForContent(BooleanContent Content)
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
virtual bool findOptimalMemOpLowering(LLVMContext &Context, std::vector< EVT > &MemOps, unsigned Limit, const MemOp &Op, unsigned DstAS, unsigned SrcAS, const AttributeList &FuncAttributes, EVT *LargestVT=nullptr) const
Determines the optimal series of memory ops to replace the memset / memcpy.
std::pair< SDValue, SDValue > LowerCallTo(CallLoweringInfo &CLI) const
This function lowers an abstract call to a function into an actual call.
Primary interface to the complete machine description for the target machine.
virtual bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const
Returns true if a cast between SrcAS and DestAS is a noop.
const Triple & getTargetTriple() const
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
virtual const SelectionDAGTargetInfo * getSelectionDAGInfo() const
virtual const TargetRegisterInfo * getRegisterInfo() const =0
Return the target's register information.
virtual const TargetLowering * getTargetLowering() const
bool isOSDarwin() const
Is this a "Darwin" OS (macOS, iOS, tvOS, watchOS, DriverKit, XROS, or bridgeOS).
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
static constexpr TypeSize getFixed(ScalarTy ExactSize)
The instances of the Type class are immutable: once they are created, they are never changed.
bool isVectorTy() const
True if this is an instance of VectorType.
static LLVM_ABI IntegerType * getInt32Ty(LLVMContext &C)
static LLVM_ABI Type * getVoidTy(LLVMContext &C)
static LLVM_ABI IntegerType * getInt8Ty(LLVMContext &C)
LLVM_ABI TypeSize getPrimitiveSizeInBits() const LLVM_READONLY
Return the basic size of this type if it is a primitive type.
LLVM_ABI unsigned getScalarSizeInBits() const LLVM_READONLY
If this is a vector type, return the getPrimitiveSizeInBits value for the element type.
A Use represents the edge between a Value definition and its users.
LLVM_ABI unsigned getOperandNo() const
Return the operand # of this use in its User.
LLVM_ABI void set(Value *Val)
User * getUser() const
Returns the User that contains this Use.
Value * getOperand(unsigned i) const
This class is used to represent an VP_GATHER node.
This class is used to represent a VP_LOAD node.
This class is used to represent an VP_SCATTER node.
This class is used to represent a VP_STORE node.
This class is used to represent an EXPERIMENTAL_VP_STRIDED_LOAD node.
This class is used to represent an EXPERIMENTAL_VP_STRIDED_STORE node.
LLVM Value Representation.
Type * getType() const
All values are typed, get the type of this value.
std::pair< iterator, bool > insert(const ValueT &V)
bool contains(const_arg_type_t< ValueT > V) const
Check if the set contains the given element.
constexpr bool hasKnownScalarFactor(const FixedOrScalableQuantity &RHS) const
Returns true if there exists a value X where RHS.multiplyCoefficientBy(X) will result in a value whos...
constexpr ScalarTy getFixedValue() const
static constexpr bool isKnownLE(const FixedOrScalableQuantity &LHS, const FixedOrScalableQuantity &RHS)
constexpr bool isScalable() const
Returns whether the quantity is scaled by a runtime quantity (vscale).
constexpr bool isKnownEven() const
A return value of true indicates we know at compile time that the number of elements (vscale * Min) i...
constexpr ScalarTy getKnownMinValue() const
Returns the minimum value this quantity can represent.
constexpr LeafTy divideCoefficientBy(ScalarTy RHS) const
We do not provide the '/' operator here because division for polynomial types does not work in the sa...
static constexpr bool isKnownGE(const FixedOrScalableQuantity &LHS, const FixedOrScalableQuantity &RHS)
A raw_ostream that writes to an std::string.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
LLVM_ABI APInt clmulr(const APInt &LHS, const APInt &RHS)
Perform a reversed carry-less multiply.
LLVM_ABI APInt mulhu(const APInt &C1, const APInt &C2)
Performs (2*N)-bit multiplication on zero-extended operands.
LLVM_ABI APInt avgCeilU(const APInt &C1, const APInt &C2)
Compute the ceil of the unsigned average of C1 and C2.
LLVM_ABI APInt avgFloorU(const APInt &C1, const APInt &C2)
Compute the floor of the unsigned average of C1 and C2.
LLVM_ABI APInt fshr(const APInt &Hi, const APInt &Lo, const APInt &Shift)
Perform a funnel shift right.
LLVM_ABI APInt mulhs(const APInt &C1, const APInt &C2)
Performs (2*N)-bit multiplication on sign-extended operands.
LLVM_ABI APInt clmul(const APInt &LHS, const APInt &RHS)
Perform a carry-less multiply, also known as XOR multiplication, and return low-bits.
APInt abds(const APInt &A, const APInt &B)
Determine the absolute difference of two APInts considered to be signed.
LLVM_ABI APInt fshl(const APInt &Hi, const APInt &Lo, const APInt &Shift)
Perform a funnel shift left.
LLVM_ABI APInt ScaleBitMask(const APInt &A, unsigned NewBitWidth, bool MatchAllBits=false)
Splat/Merge neighboring bits to widen/narrow the bitmask represented by.
LLVM_ABI APInt clmulh(const APInt &LHS, const APInt &RHS)
Perform a carry-less multiply, and return high-bits.
APInt abdu(const APInt &A, const APInt &B)
Determine the absolute difference of two APInts considered to be unsigned.
LLVM_ABI APInt avgFloorS(const APInt &C1, const APInt &C2)
Compute the floor of the signed average of C1 and C2.
LLVM_ABI APInt avgCeilS(const APInt &C1, const APInt &C2)
Compute the ceil of the signed average of C1 and C2.
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
@ C
The default llvm calling convention, compatible with C.
LLVM_ABI CondCode getSetCCInverse(CondCode Operation, bool isIntegerLike)
Return the operation corresponding to !(X op Y), where 'op' is a valid SetCC operation.
ISD namespace - This namespace contains an enum which represents all of the SelectionDAG node types a...
LLVM_ABI CondCode getSetCCAndOperation(CondCode Op1, CondCode Op2, EVT Type)
Return the result of a logical AND between different comparisons of identical values: ((X op1 Y) & (X...
LLVM_ABI bool isConstantSplatVectorAllOnes(const SDNode *N, bool BuildVectorOnly=false)
Return true if the specified node is a BUILD_VECTOR or SPLAT_VECTOR where all of the elements are ~0 ...
bool isNON_EXTLoad(const SDNode *N)
Returns true if the specified node is a non-extending load.
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
@ SETCC
SetCC operator - This evaluates to a true value iff the condition is true.
@ MERGE_VALUES
MERGE_VALUES - This node takes multiple discrete operands and returns them all as its individual resu...
@ MDNODE_SDNODE
MDNODE_SDNODE - This is a node that holdes an MDNode*, which is used to reference metadata in the IR.
@ STRICT_FSETCC
STRICT_FSETCC/STRICT_FSETCCS - Constrained versions of SETCC, used for floating-point operands only.
@ PTRADD
PTRADD represents pointer arithmetic semantics, for targets that opt in using shouldPreservePtrArith(...
@ DELETED_NODE
DELETED_NODE - This is an illegal value that is used to catch errors.
@ POISON
POISON - A poison node.
@ PARTIAL_REDUCE_SMLA
PARTIAL_REDUCE_[U|S]MLA(Accumulator, Input1, Input2) The partial reduction nodes sign or zero extend ...
@ VECREDUCE_SEQ_FADD
Generic reduction nodes.
@ MLOAD
Masked load and store - consecutive vector load and store operations with additional mask operand tha...
@ FGETSIGN
INT = FGETSIGN(FP) - Return the sign bit of the specified floating point value as an integer 0/1 valu...
@ SMUL_LOHI
SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing a signed/unsigned value of type i[2...
@ INSERT_SUBVECTOR
INSERT_SUBVECTOR(VECTOR1, VECTOR2, IDX) - Returns a vector with VECTOR2 inserted into VECTOR1.
@ JUMP_TABLE_DEBUG_INFO
JUMP_TABLE_DEBUG_INFO - Jumptable debug info.
@ BSWAP
Byte Swap and Counting operators.
@ DEACTIVATION_SYMBOL
Untyped node storing deactivation symbol reference (DeactivationSymbolSDNode).
@ ATOMIC_STORE
OUTCHAIN = ATOMIC_STORE(INCHAIN, val, ptr) This corresponds to "store atomic" instruction.
@ ADDC
Carry-setting nodes for multiple precision addition and subtraction.
@ FMAD
FMAD - Perform a * b + c, while getting the same result as the separately rounded operations.
@ ADD
Simple integer binary arithmetic operators.
@ LOAD
LOAD and STORE have token chains as their first operand, then the same operands as an LLVM load/store...
@ ANY_EXTEND
ANY_EXTEND - Used for integer types. The high bits are undefined.
@ FMA
FMA - Perform a * b + c with no intermediate rounding step.
@ FATAN2
FATAN2 - atan2, inspired by libm.
@ INTRINSIC_VOID
OUTCHAIN = INTRINSIC_VOID(INCHAIN, INTRINSICID, arg1, arg2, ...) This node represents a target intrin...
@ ATOMIC_CMP_SWAP_WITH_SUCCESS
Val, Success, OUTCHAIN = ATOMIC_CMP_SWAP_WITH_SUCCESS(INCHAIN, ptr, cmp, swap) N.b.
@ SINT_TO_FP
[SU]INT_TO_FP - These operators convert integers (whose interpreted sign depends on the first letter)...
@ CONCAT_VECTORS
CONCAT_VECTORS(VECTOR0, VECTOR1, ...) - Given a number of values of vector type with the same length ...
@ VECREDUCE_FMAX
FMIN/FMAX nodes can have flags, for NaN/NoNaN variants.
@ FADD
Simple binary floating point operators.
@ VECREDUCE_FMAXIMUM
FMINIMUM/FMAXIMUM nodes propatate NaNs and signed zeroes using the llvm.minimum and llvm....
@ ABS
ABS - Determine the unsigned absolute value of a signed integer value of the same bitwidth.
@ SIGN_EXTEND_VECTOR_INREG
SIGN_EXTEND_VECTOR_INREG(Vector) - This operator represents an in-register sign-extension of the low ...
@ FP16_TO_FP
FP16_TO_FP, FP_TO_FP16 - These operators are used to perform promotions and truncation for half-preci...
@ FMULADD
FMULADD - Performs a * b + c, with, or without, intermediate rounding.
@ BITCAST
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
@ BUILD_PAIR
BUILD_PAIR - This is the opposite of EXTRACT_ELEMENT in some ways.
@ CLMUL
Carry-less multiplication operations.
@ FLDEXP
FLDEXP - ldexp, inspired by libm (op0 * 2**op1).
@ BUILTIN_OP_END
BUILTIN_OP_END - This must be the last enum value in this list.
@ SRCVALUE
SRCVALUE - This is a node type that holds a Value* that is used to make reference to a value in the L...
@ EH_LABEL
EH_LABEL - Represents a label in mid basic block used to track locations needed for debug and excepti...
@ SIGN_EXTEND
Conversion operators.
@ AVGCEILS
AVGCEILS/AVGCEILU - Rounding averaging add - Add two integers using an integer of type i[N+2],...
@ SCALAR_TO_VECTOR
SCALAR_TO_VECTOR(VAL) - This represents the operation of loading a scalar value into element 0 of the...
@ VECREDUCE_FADD
These reductions have relaxed evaluation order semantics, and have a single vector operand.
@ CTTZ_ZERO_UNDEF
Bit counting operators with an undefined result for zero inputs.
@ TargetIndex
TargetIndex - Like a constant pool entry, but with completely target-dependent semantics.
@ PREFETCH
PREFETCH - This corresponds to a prefetch intrinsic.
@ SETCCCARRY
Like SetCC, ops #0 and #1 are the LHS and RHS operands to compare, but op #2 is a boolean indicating ...
@ FNEG
Perform various unary floating-point operations inspired by libm.
@ BR_CC
BR_CC - Conditional branch.
@ SSUBO
Same for subtraction.
@ STEP_VECTOR
STEP_VECTOR(IMM) - Returns a scalable vector whose lanes are comprised of a linear sequence of unsign...
@ FCANONICALIZE
Returns platform specific canonical encoding of a floating point number.
@ SSUBSAT
RESULT = [US]SUBSAT(LHS, RHS) - Perform saturation subtraction on 2 integers with the same bit width ...
@ SELECT
Select(COND, TRUEVAL, FALSEVAL).
@ ATOMIC_LOAD
Val, OUTCHAIN = ATOMIC_LOAD(INCHAIN, ptr) This corresponds to "load atomic" instruction.
@ UNDEF
UNDEF - An undefined node.
@ EXTRACT_ELEMENT
EXTRACT_ELEMENT - This is used to get the lower or upper (determined by a Constant,...
@ SPLAT_VECTOR
SPLAT_VECTOR(VAL) - Returns a vector with the scalar value VAL duplicated in all lanes.
@ AssertAlign
AssertAlign - These nodes record if a register contains a value that has a known alignment and the tr...
@ GET_ACTIVE_LANE_MASK
GET_ACTIVE_LANE_MASK - this corrosponds to the llvm.get.active.lane.mask intrinsic.
@ BasicBlock
Various leaf nodes.
@ CopyFromReg
CopyFromReg - This node indicates that the input value is a virtual or physical register that is defi...
@ SADDO
RESULT, BOOL = [SU]ADDO(LHS, RHS) - Overflow-aware nodes for addition.
@ TargetGlobalAddress
TargetGlobalAddress - Like GlobalAddress, but the DAG does no folding or anything else with this node...
@ ARITH_FENCE
ARITH_FENCE - This corresponds to a arithmetic fence intrinsic.
@ CTLS
Count leading redundant sign bits.
@ VECREDUCE_ADD
Integer reductions may have a result type larger than the vector element type.
@ MULHU
MULHU/MULHS - Multiply high - Multiply two integers of type iN, producing an unsigned/signed value of...
@ SHL
Shift and rotation operations.
@ AssertNoFPClass
AssertNoFPClass - These nodes record if a register contains a float value that is known to be not som...
@ VECTOR_SHUFFLE
VECTOR_SHUFFLE(VEC1, VEC2) - Returns a vector, of the same type as VEC1/VEC2.
@ EXTRACT_SUBVECTOR
EXTRACT_SUBVECTOR(VECTOR, IDX) - Returns a subvector from VECTOR.
@ FMINNUM_IEEE
FMINNUM_IEEE/FMAXNUM_IEEE - Perform floating-point minimumNumber or maximumNumber on two values,...
@ EntryToken
EntryToken - This is the marker used to indicate the start of a region.
@ EXTRACT_VECTOR_ELT
EXTRACT_VECTOR_ELT(VECTOR, IDX) - Returns a single element from VECTOR identified by the (potentially...
@ CopyToReg
CopyToReg - This node has three operands: a chain, a register number to set to this value,...
@ ZERO_EXTEND
ZERO_EXTEND - Used for integer types, zeroing the new bits.
@ SELECT_CC
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
@ VSCALE
VSCALE(IMM) - Returns the runtime scaling factor used to calculate the number of elements within a sc...
@ ATOMIC_CMP_SWAP
Val, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmp, swap) For double-word atomic operations: ValLo,...
@ FMINNUM
FMINNUM/FMAXNUM - Perform floating-point minimum maximum on two values, following IEEE-754 definition...
@ SSHLSAT
RESULT = [US]SHLSAT(LHS, RHS) - Perform saturation left shift.
@ SMULO
Same for multiplication.
@ VECTOR_SPLICE_LEFT
VECTOR_SPLICE_LEFT(VEC1, VEC2, OFFSET) - Shifts CONCAT_VECTORS(VEC1, VEC2) left by OFFSET elements an...
@ ANY_EXTEND_VECTOR_INREG
ANY_EXTEND_VECTOR_INREG(Vector) - This operator represents an in-register any-extension of the low la...
@ SIGN_EXTEND_INREG
SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to sign extend a small value in ...
@ SMIN
[US]{MIN/MAX} - Binary minimum or maximum of signed or unsigned integers.
@ LIFETIME_START
This corresponds to the llvm.lifetime.
@ FP_EXTEND
X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.
@ VSELECT
Select with a vector condition (op #0) and two vector operands (ops #1 and #2), returning a vector re...
@ UADDO_CARRY
Carry-using nodes for multiple precision addition and subtraction.
@ MGATHER
Masked gather and scatter - load and store operations for a vector of random addresses with additiona...
@ HANDLENODE
HANDLENODE node - Used as a handle for various purposes.
@ BF16_TO_FP
BF16_TO_FP, FP_TO_BF16 - These operators are used to perform promotions and truncation for bfloat16.
@ STRICT_FP_ROUND
X = STRICT_FP_ROUND(Y, TRUNC) - Rounding 'Y' from a larger floating point type down to the precision ...
@ FMINIMUM
FMINIMUM/FMAXIMUM - NaN-propagating minimum/maximum that also treat -0.0 as less than 0....
@ FP_TO_SINT
FP_TO_[US]INT - Convert a floating point value to a signed or unsigned integer.
@ TargetConstant
TargetConstant* - Like Constant*, but the DAG does not do any folding, simplification,...
@ STRICT_FP_EXTEND
X = STRICT_FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.
@ AND
Bitwise operators - logical and, logical or, logical xor.
@ INTRINSIC_WO_CHAIN
RESULT = INTRINSIC_WO_CHAIN(INTRINSICID, arg1, arg2, ...) This node represents a target intrinsic fun...
@ GET_FPENV_MEM
Gets the current floating-point environment.
@ PSEUDO_PROBE
Pseudo probe for AutoFDO, as a place holder in a basic block to improve the sample counts quality.
@ SCMP
[US]CMP - 3-way comparison of signed or unsigned integers.
@ AVGFLOORS
AVGFLOORS/AVGFLOORU - Averaging add - Add two integers using an integer of type i[N+1],...
@ VECTOR_SPLICE_RIGHT
VECTOR_SPLICE_RIGHT(VEC1, VEC2, OFFSET) - Shifts CONCAT_VECTORS(VEC1,VEC2) right by OFFSET elements a...
@ ADDE
Carry-using nodes for multiple precision addition and subtraction.
@ SPLAT_VECTOR_PARTS
SPLAT_VECTOR_PARTS(SCALAR1, SCALAR2, ...) - Returns a vector with the scalar values joined together a...
@ FREEZE
FREEZE - FREEZE(VAL) returns an arbitrary value if VAL is UNDEF (or is evaluated to UNDEF),...
@ INSERT_VECTOR_ELT
INSERT_VECTOR_ELT(VECTOR, VAL, IDX) - Returns VECTOR with the element at IDX replaced with VAL.
@ TokenFactor
TokenFactor - This node takes multiple tokens as input and produces a single token result.
@ ATOMIC_SWAP
Val, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amt) Val, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN,...
@ FFREXP
FFREXP - frexp, extract fractional and exponent component of a floating-point value.
@ FP_ROUND
X = FP_ROUND(Y, TRUNC) - Rounding 'Y' from a larger floating point type down to the precision of the ...
@ VECTOR_COMPRESS
VECTOR_COMPRESS(Vec, Mask, Passthru) consecutively place vector elements based on mask e....
@ ZERO_EXTEND_VECTOR_INREG
ZERO_EXTEND_VECTOR_INREG(Vector) - This operator represents an in-register zero-extension of the low ...
@ ADDRSPACECAST
ADDRSPACECAST - This operator converts between pointers of different address spaces.
@ EXPERIMENTAL_VECTOR_HISTOGRAM
Experimental vector histogram intrinsic Operands: Input Chain, Inc, Mask, Base, Index,...
@ FP_TO_SINT_SAT
FP_TO_[US]INT_SAT - Convert floating point value in operand 0 to a signed or unsigned scalar integer ...
@ TRUNCATE
TRUNCATE - Completely drop the high bits.
@ VAARG
VAARG - VAARG has four operands: an input chain, a pointer, a SRCVALUE, and the alignment.
@ SHL_PARTS
SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded integer shift operations.
@ AssertSext
AssertSext, AssertZext - These nodes record if a register contains a value that has already been zero...
@ FCOPYSIGN
FCOPYSIGN(X, Y) - Return the value of X with the sign of Y.
@ SADDSAT
RESULT = [US]ADDSAT(LHS, RHS) - Perform saturation addition on 2 integers with the same bit width (W)...
@ SET_FPENV_MEM
Sets the current floating point environment.
@ FMINIMUMNUM
FMINIMUMNUM/FMAXIMUMNUM - minimumnum/maximumnum that is same with FMINNUM_IEEE and FMAXNUM_IEEE besid...
@ TRUNCATE_SSAT_S
TRUNCATE_[SU]SAT_[SU] - Truncate for saturated operand [SU] located in middle, prefix for SAT means i...
@ ABDS
ABDS/ABDU - Absolute difference - Return the absolute difference between two numbers interpreted as s...
@ SADDO_CARRY
Carry-using overflow-aware nodes for multiple precision addition and subtraction.
@ INTRINSIC_W_CHAIN
RESULT,OUTCHAIN = INTRINSIC_W_CHAIN(INCHAIN, INTRINSICID, arg1, ...) This node represents a target in...
@ BUILD_VECTOR
BUILD_VECTOR(ELT0, ELT1, ELT2, ELT3,...) - Return a fixed-width vector with the specified,...
LLVM_ABI NodeType getOppositeSignednessMinMaxOpcode(unsigned MinMaxOpc)
Given a MinMaxOpc of ISD::(U|S)MIN or ISD::(U|S)MAX, returns the corresponding opcode with the opposi...
LLVM_ABI bool isBuildVectorOfConstantSDNodes(const SDNode *N)
Return true if the specified node is a BUILD_VECTOR node of all ConstantSDNode or undef.
LLVM_ABI NodeType getExtForLoadExtType(bool IsFP, LoadExtType)
bool isZEXTLoad(const SDNode *N)
Returns true if the specified node is a ZEXTLOAD.
bool matchUnaryFpPredicate(SDValue Op, std::function< bool(ConstantFPSDNode *)> Match, bool AllowUndefs=false)
Hook for matching ConstantFPSDNode predicate.
bool isExtOpcode(unsigned Opcode)
LLVM_ABI bool isConstantSplatVectorAllZeros(const SDNode *N, bool BuildVectorOnly=false)
Return true if the specified node is a BUILD_VECTOR or SPLAT_VECTOR where all of the elements are 0 o...
LLVM_ABI bool isVectorShrinkable(const SDNode *N, unsigned NewEltSize, bool Signed)
Returns true if the specified node is a vector where all elements can be truncated to the specified e...
LLVM_ABI bool isVPBinaryOp(unsigned Opcode)
Whether this is a vector-predicated binary operation opcode.
LLVM_ABI CondCode getSetCCInverse(CondCode Operation, EVT Type)
Return the operation corresponding to !(X op Y), where 'op' is a valid SetCC operation.
LLVM_ABI std::optional< unsigned > getBaseOpcodeForVP(unsigned Opcode, bool hasFPExcept)
Translate this VP Opcode to its corresponding non-VP Opcode.
bool isTrueWhenEqual(CondCode Cond)
Return true if the specified condition returns true if the two operands to the condition are equal.
LLVM_ABI std::optional< unsigned > getVPMaskIdx(unsigned Opcode)
The operand position of the vector mask.
unsigned getUnorderedFlavor(CondCode Cond)
This function returns 0 if the condition is always false if an operand is a NaN, 1 if the condition i...
LLVM_ABI std::optional< unsigned > getVPExplicitVectorLengthIdx(unsigned Opcode)
The operand position of the explicit vector length parameter.
bool isEXTLoad(const SDNode *N)
Returns true if the specified node is a EXTLOAD.
LLVM_ABI bool allOperandsUndef(const SDNode *N)
Return true if the node has at least one operand and all operands of the specified node are ISD::UNDE...
LLVM_ABI bool isFreezeUndef(const SDNode *N)
Return true if the specified node is FREEZE(UNDEF).
LLVM_ABI CondCode getSetCCSwappedOperands(CondCode Operation)
Return the operation corresponding to (Y op X) when given the operation for (X op Y).
LLVM_ABI std::optional< unsigned > getVPForBaseOpcode(unsigned Opcode)
Translate this non-VP Opcode to its corresponding VP Opcode.
MemIndexType
MemIndexType enum - This enum defines how to interpret MGATHER/SCATTER's index parameter when calcula...
LLVM_ABI bool isBuildVectorAllZeros(const SDNode *N)
Return true if the specified node is a BUILD_VECTOR where all of the elements are 0 or undef.
bool matchUnaryPredicateImpl(SDValue Op, std::function< bool(ConstNodeType *)> Match, bool AllowUndefs=false, bool AllowTruncation=false)
Attempt to match a unary predicate against a scalar/splat constant or every element of a constant BUI...
LLVM_ABI bool isConstantSplatVector(const SDNode *N, APInt &SplatValue)
Node predicates.
LLVM_ABI NodeType getInverseMinMaxOpcode(unsigned MinMaxOpc)
Given a MinMaxOpc of ISD::(U|S)MIN or ISD::(U|S)MAX, returns ISD::(U|S)MAX and ISD::(U|S)MIN,...
LLVM_ABI bool matchBinaryPredicate(SDValue LHS, SDValue RHS, std::function< bool(ConstantSDNode *, ConstantSDNode *)> Match, bool AllowUndefs=false, bool AllowTypeMismatch=false)
Attempt to match a binary predicate against a pair of scalar/splat constants or every element of a pa...
LLVM_ABI bool isVPReduction(unsigned Opcode)
Whether this is a vector-predicated reduction opcode.
bool matchUnaryPredicate(SDValue Op, std::function< bool(ConstantSDNode *)> Match, bool AllowUndefs=false, bool AllowTruncation=false)
Hook for matching ConstantSDNode predicate.
MemIndexedMode
MemIndexedMode enum - This enum defines the load / store indexed addressing modes.
LLVM_ABI bool isBuildVectorOfConstantFPSDNodes(const SDNode *N)
Return true if the specified node is a BUILD_VECTOR node of all ConstantFPSDNode or undef.
bool isSEXTLoad(const SDNode *N)
Returns true if the specified node is a SEXTLOAD.
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...
LLVM_ABI bool isBuildVectorAllOnes(const SDNode *N)
Return true if the specified node is a BUILD_VECTOR where all of the elements are ~0 or undef.
LLVM_ABI NodeType getVecReduceBaseOpcode(unsigned VecReduceOpcode)
Get underlying scalar opcode for VECREDUCE opcode.
LoadExtType
LoadExtType enum - This enum defines the three variants of LOADEXT (load with extension).
LLVM_ABI bool isVPOpcode(unsigned Opcode)
Whether this is a vector-predicated Opcode.
LLVM_ABI CondCode getSetCCOrOperation(CondCode Op1, CondCode Op2, EVT Type)
Return the result of a logical OR between different comparisons of identical values: ((X op1 Y) | (X ...
BinaryOp_match< SpecificConstantMatch, SrcTy, TargetOpcode::G_SUB > m_Neg(const SrcTy &&Src)
Matches a register negated by a G_SUB.
BinaryOp_match< LHS, RHS, Instruction::And > m_And(const LHS &L, const RHS &R)
deferredval_ty< Value > m_Deferred(Value *const &V)
Like m_Specific(), but works if the specific value to match is determined as part of the same match()...
class_match< Value > m_Value()
Match an arbitrary value and ignore it.
LLVM_ABI Libcall getMEMCPY_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize)
getMEMCPY_ELEMENT_UNORDERED_ATOMIC - Return MEMCPY_ELEMENT_UNORDERED_ATOMIC_* value for the given ele...
LLVM_ABI Libcall getMEMSET_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize)
getMEMSET_ELEMENT_UNORDERED_ATOMIC - Return MEMSET_ELEMENT_UNORDERED_ATOMIC_* value for the given ele...
LLVM_ABI Libcall getMEMMOVE_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize)
getMEMMOVE_ELEMENT_UNORDERED_ATOMIC - Return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_* value for the given e...
bool sd_match(SDNode *N, const SelectionDAG *DAG, Pattern &&P)
initializer< Ty > init(const Ty &Val)
@ DW_OP_LLVM_arg
Only used in LLVM metadata.
std::enable_if_t< detail::IsValidPointer< X, Y >::value, X * > extract(Y &&MD)
Extract a Value from Metadata.
NodeAddr< NodeBase * > Node
This is an optimization pass for GlobalISel generic memory operations.
GenericUniformityInfo< SSAContext > UniformityInfo
unsigned Log2_32_Ceil(uint32_t Value)
Return the ceil log base 2 of the specified value, 32 if the value is zero.
bool operator<(int64_t V1, const APSInt &V2)
ISD::CondCode getICmpCondCode(ICmpInst::Predicate Pred)
getICmpCondCode - Return the ISD condition code corresponding to the given LLVM IR integer condition ...
void fill(R &&Range, T &&Value)
Provide wrappers to std::fill which take ranges instead of having to pass begin/end explicitly.
LLVM_ABI SDValue peekThroughExtractSubvectors(SDValue V)
Return the non-extracted vector source operand of V if it exists.
bool all_of(R &&range, UnaryPredicate P)
Provide wrappers to std::all_of which take ranges instead of having to pass begin/end explicitly.
MaybeAlign getAlign(const CallInst &I, unsigned Index)
LLVM_ABI bool isNullConstant(SDValue V)
Returns true if V is a constant integer zero.
LLVM_ABI bool isAllOnesOrAllOnesSplat(const MachineInstr &MI, const MachineRegisterInfo &MRI, bool AllowUndefs=false)
Return true if the value is a constant -1 integer or a splatted vector of a constant -1 integer (with...
LLVM_ABI SDValue getBitwiseNotOperand(SDValue V, SDValue Mask, bool AllowUndefs)
If V is a bitwise not, returns the inverted operand.
@ Undef
Value of the register doesn't matter.
LLVM_ABI SDValue peekThroughBitcasts(SDValue V)
Return the non-bitcasted source operand of V if it exists.
auto enumerate(FirstRange &&First, RestRanges &&...Rest)
Given two or more input ranges, returns a new range whose values are tuples (A, B,...
decltype(auto) dyn_cast(const From &Val)
dyn_cast<X> - Return the argument parameter cast to the specified type.
int countr_one(T Value)
Count the number of ones from the least significant bit to the first zero bit.
bool isIntOrFPConstant(SDValue V)
Return true if V is either a integer or FP constant.
auto dyn_cast_if_present(const Y &Val)
dyn_cast_if_present<X> - Functionally identical to dyn_cast, except that a null (or none in the case ...
LLVM_ABI bool getConstantDataArrayInfo(const Value *V, ConstantDataArraySlice &Slice, unsigned ElementSize, uint64_t Offset=0)
Returns true if the value V is a pointer into a ConstantDataArray.
LLVM_ABI bool isOneOrOneSplatFP(SDValue V, bool AllowUndefs=false)
Return true if the value is a constant floating-point value, or a splatted vector of a constant float...
int bit_width(T Value)
Returns the number of bits needed to represent Value if Value is nonzero.
LLVM_READONLY APFloat maximum(const APFloat &A, const APFloat &B)
Implements IEEE 754-2019 maximum semantics.
void append_range(Container &C, Range &&R)
Wrapper function to append range R to container C.
constexpr bool isUIntN(unsigned N, uint64_t x)
Checks if an unsigned integer fits into the given (dynamic) bit width.
LLVM_ABI bool shouldOptimizeForSize(const MachineFunction *MF, ProfileSummaryInfo *PSI, const MachineBlockFrequencyInfo *BFI, PGSOQueryType QueryType=PGSOQueryType::Other)
Returns true if machine function MF is suggested to be size-optimized based on the profile.
iterator_range< early_inc_iterator_impl< detail::IterOfRange< RangeT > > > make_early_inc_range(RangeT &&Range)
Make a range that does early increment to allow mutation of the underlying range without disrupting i...
auto cast_or_null(const Y &Val)
LLVM_ABI bool isNullOrNullSplat(const MachineInstr &MI, const MachineRegisterInfo &MRI, bool AllowUndefs=false)
Return true if the value is a constant 0 integer or a splatted vector of a constant 0 integer (with n...
LLVM_ABI bool isMinSignedConstant(SDValue V)
Returns true if V is a constant min signed integer value.
LLVM_ABI ConstantFPSDNode * isConstOrConstSplatFP(SDValue N, bool AllowUndefs=false)
Returns the SDNode if it is a constant splat BuildVector or constant float.
LLVM_ABI ConstantRange getConstantRangeFromMetadata(const MDNode &RangeMD)
Parse out a conservative ConstantRange from !range metadata.
APFloat frexp(const APFloat &X, int &Exp, APFloat::roundingMode RM)
Equivalent of C standard library function.
int countr_zero(T Val)
Count number of 0's from the least significant bit to the most stopping at the first 1.
auto dyn_cast_or_null(const Y &Val)
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
LLVM_ABI bool getShuffleDemandedElts(int SrcWidth, ArrayRef< int > Mask, const APInt &DemandedElts, APInt &DemandedLHS, APInt &DemandedRHS, bool AllowUndefElts=false)
Transform a shuffle mask's output demanded element mask into demanded element masks for the 2 operand...
LLVM_READONLY APFloat maxnum(const APFloat &A, const APFloat &B)
Implements IEEE-754 2008 maxNum semantics.
unsigned Log2_32(uint32_t Value)
Return the floor log base 2 of the specified value, -1 if the value is zero.
LLVM_ABI bool isBitwiseNot(SDValue V, bool AllowUndefs=false)
Returns true if V is a bitwise not operation.
LLVM_ABI SDValue peekThroughInsertVectorElt(SDValue V, const APInt &DemandedElts)
Recursively peek through INSERT_VECTOR_ELT nodes, returning the source vector operand of V,...
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
decltype(auto) get(const PointerIntPair< PointerTy, IntBits, IntType, PtrTraits, Info > &Pair)
LLVM_ABI void checkForCycles(const SelectionDAG *DAG, bool force=false)
void sort(IteratorTy Start, IteratorTy End)
LLVM_READONLY APFloat minimumnum(const APFloat &A, const APFloat &B)
Implements IEEE 754-2019 minimumNumber semantics.
FPClassTest
Floating-point class tests, supported by 'is_fpclass' intrinsic.
LLVM_ABI void computeKnownBits(const Value *V, KnownBits &Known, const DataLayout &DL, AssumptionCache *AC=nullptr, const Instruction *CxtI=nullptr, const DominatorTree *DT=nullptr, bool UseInstrInfo=true, unsigned Depth=0)
Determine which bits of V are known to be either zero or one and return them in the KnownZero/KnownOn...
LLVM_ABI raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
LLVM_ABI SDValue peekThroughTruncates(SDValue V)
Return the non-truncated source operand of V if it exists.
bool none_of(R &&Range, UnaryPredicate P)
Provide wrappers to std::none_of which take ranges instead of having to pass begin/end explicitly.
LLVM_ABI void report_fatal_error(Error Err, bool gen_crash_diag=true)
constexpr std::underlying_type_t< Enum > to_underlying(Enum E)
Returns underlying integer value of an enum.
FunctionAddr VTableAddr Count
LLVM_ABI ConstantRange getVScaleRange(const Function *F, unsigned BitWidth)
Determine the possible constant range of vscale with the given bit width, based on the vscale_range f...
LLVM_ABI SDValue peekThroughOneUseBitcasts(SDValue V)
Return the non-bitcasted and one-use source operand of V if it exists.
CodeGenOptLevel
Code generation optimization level.
bool isa(const From &Val)
isa<X> - Return true if the parameter to the template is an instance of one of the template type argu...
LLVM_ABI bool isOneOrOneSplat(SDValue V, bool AllowUndefs=false)
Return true if the value is a constant 1 integer or a splatted vector of a constant 1 integer (with n...
LLVM_ABI raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.
LLVM_READONLY APFloat minnum(const APFloat &A, const APFloat &B)
Implements IEEE-754 2008 minNum semantics.
@ Mul
Product of integers.
@ Sub
Subtraction of integers.
LLVM_ABI bool isNullConstantOrUndef(SDValue V)
Returns true if V is a constant integer zero or an UNDEF node.
bool isInTailCallPosition(const CallBase &Call, const TargetMachine &TM, bool ReturnsFirstArg=false)
Test if the given instruction is in a position to be optimized with a tail-call.
DWARFExpression::Operation Op
ArrayRef(const T &OneElt) -> ArrayRef< T >
LLVM_ABI ConstantSDNode * isConstOrConstSplat(SDValue N, bool AllowUndefs=false, bool AllowTruncation=false)
Returns the SDNode if it is a constant splat BuildVector or constant int.
OutputIt copy(R &&Range, OutputIt Out)
constexpr unsigned BitWidth
bool funcReturnsFirstArgOfCall(const CallInst &CI)
Returns true if the parent of CI returns CI's first argument after calling CI.
decltype(auto) cast(const From &Val)
cast<X> - Return the argument parameter cast to the specified type.
LLVM_ABI bool isZeroOrZeroSplat(SDValue N, bool AllowUndefs=false)
Return true if the value is a constant 0 integer or a splatted vector of a constant 0 integer (with n...
LLVM_ABI bool isOneConstant(SDValue V)
Returns true if V is a constant integer one.
bool is_contained(R &&Range, const E &Element)
Returns true if Element is found in Range.
Align commonAlignment(Align A, uint64_t Offset)
Returns the alignment that satisfies both alignments.
LLVM_ABI bool isNullFPConstant(SDValue V)
Returns true if V is an FP constant with a value of positive zero.
constexpr int64_t SignExtend64(uint64_t x)
Sign-extend the number in the bottom B bits of X to a 64-bit integer.
unsigned Log2(Align A)
Returns the log2 of the alignment.
LLVM_ABI bool isZeroOrZeroSplatFP(SDValue N, bool AllowUndefs=false)
Return true if the value is a constant (+/-)0.0 floating-point value or a splatted vector thereof (wi...
LLVM_ABI void computeKnownBitsFromRangeMetadata(const MDNode &Ranges, KnownBits &Known)
Compute known bits from the range metadata.
LLVM_READONLY APFloat minimum(const APFloat &A, const APFloat &B)
Implements IEEE 754-2019 minimum semantics.
LLVM_READONLY APFloat maximumnum(const APFloat &A, const APFloat &B)
Implements IEEE 754-2019 maximumNumber semantics.
LLVM_ABI bool isOnesOrOnesSplat(SDValue N, bool AllowUndefs=false)
Return true if the value is a constant 1 integer or a splatted vector of a constant 1 integer (with n...
LLVM_ABI bool isNeutralConstant(unsigned Opc, SDNodeFlags Flags, SDValue V, unsigned OperandNo)
Returns true if V is a neutral element of Opc with Flags.
LLVM_ABI bool isAllOnesConstant(SDValue V)
Returns true if V is an integer constant with all bits set.
constexpr uint64_t NextPowerOf2(uint64_t A)
Returns the next power of two (in 64-bits) that is strictly greater than A.
LLVM_ABI void reportFatalUsageError(Error Err)
Report a fatal error that does not indicate a bug in LLVM.
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
A collection of metadata nodes that might be associated with a memory access used by the alias-analys...
MDNode * TBAAStruct
The tag for type-based alias analysis (tbaa struct).
MDNode * TBAA
The tag for type-based alias analysis.
This struct is a compact representation of a valid (non-zero power of two) alignment.
constexpr uint64_t value() const
This is a hole in the type system and should not be abused.
Represents offset+length into a ConstantDataArray.
uint64_t Length
Length of the slice.
uint64_t Offset
Slice starts at this Offset.
void move(uint64_t Delta)
Moves the Offset and adjusts Length accordingly.
const ConstantDataArray * Array
ConstantDataArray pointer.
TypeSize getStoreSize() const
Return the number of bytes overwritten by a store of the specified value type.
bool isSimple() const
Test if the given EVT is simple (as opposed to being extended).
intptr_t getRawBits() const
static EVT getVectorVT(LLVMContext &Context, EVT VT, unsigned NumElements, bool IsScalable=false)
Returns the EVT that represents a vector NumElements in length, where each element is of type VT.
EVT changeTypeToInteger() const
Return the type converted to an equivalently sized integer or vector with integer element type.
bool bitsGT(EVT VT) const
Return true if this has more bits than VT.
bool bitsLT(EVT VT) const
Return true if this has less bits than VT.
bool isFloatingPoint() const
Return true if this is a FP or a vector FP type.
ElementCount getVectorElementCount() const
TypeSize getSizeInBits() const
Return the size of the specified value type in bits.
unsigned getVectorMinNumElements() const
Given a vector type, return the minimum number of elements it contains.
uint64_t getScalarSizeInBits() const
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
static EVT getIntegerVT(LLVMContext &Context, unsigned BitWidth)
Returns the EVT that represents an integer with the given number of bits.
bool isFixedLengthVector() const
bool isVector() const
Return true if this is a vector value type.
EVT getScalarType() const
If this is a vector type, return the element type, otherwise return this.
bool bitsGE(EVT VT) const
Return true if this has no less bits than VT.
bool bitsEq(EVT VT) const
Return true if this has the same number of bits as VT.
LLVM_ABI Type * getTypeForEVT(LLVMContext &Context) const
This method returns an LLVM type corresponding to the specified EVT.
bool isScalableVector() const
Return true if this is a vector type where the runtime length is machine dependent.
EVT getVectorElementType() const
Given a vector type, return the type of each element.
bool isExtended() const
Test if the given EVT is extended (as opposed to being simple).
LLVM_ABI const fltSemantics & getFltSemantics() const
Returns an APFloat semantics tag appropriate for the value type.
unsigned getVectorNumElements() const
Given a vector type, return the number of elements it contains.
bool bitsLE(EVT VT) const
Return true if this has no more bits than VT.
EVT getHalfNumVectorElementsVT(LLVMContext &Context) const
bool isInteger() const
Return true if this is an integer or a vector integer type.
static KnownBits makeConstant(const APInt &C)
Create known bits from a known constant.
LLVM_ABI KnownBits sextInReg(unsigned SrcBitWidth) const
Return known bits for a in-register sign extension of the value we're tracking.
static LLVM_ABI KnownBits mulhu(const KnownBits &LHS, const KnownBits &RHS)
Compute known bits from zero-extended multiply-hi.
unsigned countMinSignBits() const
Returns the number of times the sign bit is replicated into the other bits.
static LLVM_ABI KnownBits smax(const KnownBits &LHS, const KnownBits &RHS)
Compute known bits for smax(LHS, RHS).
bool isNonNegative() const
Returns true if this value is known to be non-negative.
bool isZero() const
Returns true if value is all zero.
void makeNonNegative()
Make this value non-negative.
static LLVM_ABI KnownBits usub_sat(const KnownBits &LHS, const KnownBits &RHS)
Compute knownbits resulting from llvm.usub.sat(LHS, RHS)
unsigned countMinTrailingZeros() const
Returns the minimum number of trailing zero bits.
static LLVM_ABI KnownBits ashr(const KnownBits &LHS, const KnownBits &RHS, bool ShAmtNonZero=false, bool Exact=false)
Compute known bits for ashr(LHS, RHS).
static LLVM_ABI KnownBits urem(const KnownBits &LHS, const KnownBits &RHS)
Compute known bits for urem(LHS, RHS).
bool isUnknown() const
Returns true if we don't know any bits.
unsigned countMaxTrailingZeros() const
Returns the maximum number of trailing zero bits possible.
static LLVM_ABI std::optional< bool > ne(const KnownBits &LHS, const KnownBits &RHS)
Determine if these known bits always give the same ICMP_NE result.
void makeNegative()
Make this value negative.
void setAllConflict()
Make all bits known to be both zero and one.
KnownBits trunc(unsigned BitWidth) const
Return known bits for a truncation of the value we're tracking.
KnownBits byteSwap() const
unsigned countMaxPopulation() const
Returns the maximum number of bits that could be one.
void setAllZero()
Make all bits known to be zero and discard any previous information.
KnownBits reverseBits() const
KnownBits concat(const KnownBits &Lo) const
Concatenate the bits from Lo onto the bottom of *this.
unsigned getBitWidth() const
Get the bit width of this value.
static LLVM_ABI KnownBits umax(const KnownBits &LHS, const KnownBits &RHS)
Compute known bits for umax(LHS, RHS).
KnownBits zext(unsigned BitWidth) const
Return known bits for a zero extension of the value we're tracking.
void resetAll()
Resets the known state of all bits.
KnownBits unionWith(const KnownBits &RHS) const
Returns KnownBits information that is known to be true for either this or RHS or both.
static LLVM_ABI KnownBits lshr(const KnownBits &LHS, const KnownBits &RHS, bool ShAmtNonZero=false, bool Exact=false)
Compute known bits for lshr(LHS, RHS).
bool isNonZero() const
Returns true if this value is known to be non-zero.
static LLVM_ABI KnownBits abdu(const KnownBits &LHS, const KnownBits &RHS)
Compute known bits for abdu(LHS, RHS).
KnownBits extractBits(unsigned NumBits, unsigned BitPosition) const
Return a subset of the known bits from [bitPosition,bitPosition+numBits).
static LLVM_ABI KnownBits avgFloorU(const KnownBits &LHS, const KnownBits &RHS)
Compute knownbits resulting from APIntOps::avgFloorU.
KnownBits intersectWith(const KnownBits &RHS) const
Returns KnownBits information that is known to be true for both this and RHS.
KnownBits sext(unsigned BitWidth) const
Return known bits for a sign extension of the value we're tracking.
static LLVM_ABI KnownBits computeForSubBorrow(const KnownBits &LHS, KnownBits RHS, const KnownBits &Borrow)
Compute known bits results from subtracting RHS from LHS with 1-bit Borrow.
KnownBits zextOrTrunc(unsigned BitWidth) const
Return known bits for a zero extension or truncation of the value we're tracking.
APInt getMaxValue() const
Return the maximal unsigned value possible given these KnownBits.
static LLVM_ABI KnownBits abds(KnownBits LHS, KnownBits RHS)
Compute known bits for abds(LHS, RHS).
static LLVM_ABI KnownBits smin(const KnownBits &LHS, const KnownBits &RHS)
Compute known bits for smin(LHS, RHS).
static LLVM_ABI KnownBits mulhs(const KnownBits &LHS, const KnownBits &RHS)
Compute known bits from sign-extended multiply-hi.
static LLVM_ABI KnownBits srem(const KnownBits &LHS, const KnownBits &RHS)
Compute known bits for srem(LHS, RHS).
static LLVM_ABI KnownBits udiv(const KnownBits &LHS, const KnownBits &RHS, bool Exact=false)
Compute known bits for udiv(LHS, RHS).
static LLVM_ABI KnownBits computeForAddSub(bool Add, bool NSW, bool NUW, const KnownBits &LHS, const KnownBits &RHS)
Compute known bits resulting from adding LHS and RHS.
bool isStrictlyPositive() const
Returns true if this value is known to be positive.
static LLVM_ABI KnownBits sdiv(const KnownBits &LHS, const KnownBits &RHS, bool Exact=false)
Compute known bits for sdiv(LHS, RHS).
static LLVM_ABI KnownBits avgFloorS(const KnownBits &LHS, const KnownBits &RHS)
Compute knownbits resulting from APIntOps::avgFloorS.
static bool haveNoCommonBitsSet(const KnownBits &LHS, const KnownBits &RHS)
Return true if LHS and RHS have no common bits set.
bool isNegative() const
Returns true if this value is known to be negative.
LLVM_ABI KnownBits truncSSat(unsigned BitWidth) const
Truncate with signed saturation (signed input -> signed output)
static LLVM_ABI KnownBits computeForAddCarry(const KnownBits &LHS, const KnownBits &RHS, const KnownBits &Carry)
Compute known bits resulting from adding LHS, RHS and a 1-bit Carry.
unsigned countMaxLeadingZeros() const
Returns the maximum number of leading zero bits possible.
void insertBits(const KnownBits &SubBits, unsigned BitPosition)
Insert the bits from a smaller known bits starting at bitPosition.
static LLVM_ABI KnownBits avgCeilU(const KnownBits &LHS, const KnownBits &RHS)
Compute knownbits resulting from APIntOps::avgCeilU.
static LLVM_ABI KnownBits mul(const KnownBits &LHS, const KnownBits &RHS, bool NoUndefSelfMultiply=false)
Compute known bits resulting from multiplying LHS and RHS.
KnownBits anyext(unsigned BitWidth) const
Return known bits for an "any" extension of the value we're tracking, where we don't know anything ab...
static LLVM_ABI KnownBits clmul(const KnownBits &LHS, const KnownBits &RHS)
Compute known bits for clmul(LHS, RHS).
LLVM_ABI KnownBits abs(bool IntMinIsPoison=false) const
Compute known bits for the absolute value.
LLVM_ABI KnownBits truncUSat(unsigned BitWidth) const
Truncate with unsigned saturation (unsigned input -> unsigned output)
static LLVM_ABI KnownBits shl(const KnownBits &LHS, const KnownBits &RHS, bool NUW=false, bool NSW=false, bool ShAmtNonZero=false)
Compute known bits for shl(LHS, RHS).
static LLVM_ABI KnownBits umin(const KnownBits &LHS, const KnownBits &RHS)
Compute known bits for umin(LHS, RHS).
LLVM_ABI KnownBits truncSSatU(unsigned BitWidth) const
Truncate with signed saturation to unsigned (signed input -> unsigned output)
static LLVM_ABI KnownBits avgCeilS(const KnownBits &LHS, const KnownBits &RHS)
Compute knownbits resulting from APIntOps::avgCeilS.
This class contains a discriminated union of information about pointers in memory operands,...
LLVM_ABI bool isDereferenceable(unsigned Size, LLVMContext &C, const DataLayout &DL) const
Return true if memory region [V, V+Offset+Size) is known to be dereferenceable.
LLVM_ABI unsigned getAddrSpace() const
Return the LLVM IR address space number that this pointer points into.
PointerUnion< const Value *, const PseudoSourceValue * > V
This is the IR pointer value for the access, or it is null if unknown.
MachinePointerInfo getWithOffset(int64_t O) const
static LLVM_ABI MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
This struct is a compact representation of a valid (power of two) or undefined (0) alignment.
static MemOp Set(uint64_t Size, bool DstAlignCanChange, Align DstAlign, bool IsZeroMemset, bool IsVolatile)
static MemOp Copy(uint64_t Size, bool DstAlignCanChange, Align DstAlign, Align SrcAlign, bool IsVolatile, bool MemcpyStrSrc=false)
static StringRef getLibcallImplName(RTLIB::LibcallImpl CallImpl)
Get the libcall routine name for the specified libcall implementation.
These are IR-level optimization flags that may be propagated to SDNodes.
This represents a list of ValueType's that has been intern'd by a SelectionDAG.
Clients of various APIs that cause global effects on the DAG can optionally implement this interface.
DAGUpdateListener *const Next
virtual void NodeDeleted(SDNode *N, SDNode *E)
The node N that was deleted and, if E is not null, an equivalent node E that replaced it.
virtual void NodeInserted(SDNode *N)
The node N that was inserted.
virtual void NodeUpdated(SDNode *N)
The node N that was updated.
This structure contains all information that is necessary for lowering calls.
CallLoweringInfo & setLibCallee(CallingConv::ID CC, Type *ResultType, SDValue Target, ArgListTy &&ArgsList)
CallLoweringInfo & setDiscardResult(bool Value=true)
CallLoweringInfo & setDebugLoc(const SDLoc &dl)
CallLoweringInfo & setTailCall(bool Value=true)
CallLoweringInfo & setChain(SDValue InChain)