LoongArchISelLowering.cpp File Reference

#include "LoongArchISelLowering.h"
#include "LoongArch.h"
#include "LoongArchMachineFunctionInfo.h"
#include "LoongArchRegisterInfo.h"
#include "LoongArchSelectionDAGInfo.h"
#include "LoongArchSubtarget.h"
#include "MCTargetDesc/LoongArchBaseInfo.h"
#include "MCTargetDesc/LoongArchMCTargetDesc.h"
#include "MCTargetDesc/LoongArchMatInt.h"
#include "llvm/ADT/SmallSet.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/ADT/StringExtras.h"
#include "llvm/CodeGen/ISDOpcodes.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/RuntimeLibcallUtil.h"
#include "llvm/CodeGen/SelectionDAGNodes.h"
#include "llvm/IR/IRBuilder.h"
#include "llvm/IR/IntrinsicInst.h"
#include "llvm/IR/IntrinsicsLoongArch.h"
#include "llvm/Support/CodeGen.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/KnownBits.h"
#include "llvm/Support/MathExtras.h"
#include <llvm/Analysis/VectorUtils.h>
#include "LoongArchGenAsmMatcher.inc"

Go to the source code of this file.

Macros
#define	DEBUG_TYPE   "loongarch-isel-lowering"
#define	IOCSRRD_CASE(NAME, NODE)
#define	IOCSRWR_CASE(NAME, NODE)
#define	ASRT_LE_GT_CASE(NAME)
#define	CRC_CASE_EXT_BINARYOP(NAME, NODE)
#define	CRC_CASE_EXT_UNARYOP(NAME, NODE)
#define	CSR_CASE(ID)
#define	IOCSRRD_CASE(NAME, NODE)
#define	GET_REGISTER_MATCHER

Enumerations
enum	MaterializeFPImm {   NoMaterializeFPImm = 0 , MaterializeFPImm2Ins = 2 , MaterializeFPImm3Ins = 3 , MaterializeFPImm4Ins = 4 ,   MaterializeFPImm5Ins = 5 , MaterializeFPImm6Ins = 6 }

Functions
	STATISTIC (NumTailCalls, "Number of tail calls")
static SDValue	isNOT (SDValue V, SelectionDAG &DAG)
static std::optional< bool >	matchSetCC (SDValue LHS, SDValue RHS, ISD::CondCode CC, SDValue Val)
static SDValue	combineSelectToBinOp (SDNode *N, SelectionDAG &DAG, const LoongArchSubtarget &Subtarget)
static SDValue	foldBinOpIntoSelectIfProfitable (SDNode *BO, SelectionDAG &DAG, const LoongArchSubtarget &Subtarget)
static void	translateSetCCForBranch (const SDLoc &DL, SDValue &LHS, SDValue &RHS, ISD::CondCode &CC, SelectionDAG &DAG)
static SDValue	widenShuffleMask (const SDLoc &DL, ArrayRef< int > Mask, MVT VT, SDValue V1, SDValue V2, SelectionDAG &DAG)
static int	matchShuffleAsShift (MVT &ShiftVT, unsigned &Opcode, unsigned ScalarSizeInBits, ArrayRef< int > Mask, int MaskOffset, const APInt &Zeroable)
	Attempts to match a shuffle mask against the VBSLL, VBSRL, VSLLI and VSRLI instruction.
static SDValue	lowerVECTOR_SHUFFLEAsShift (const SDLoc &DL, ArrayRef< int > Mask, MVT VT, SDValue V1, SDValue V2, SelectionDAG &DAG, const LoongArchSubtarget &Subtarget, const APInt &Zeroable)
	Lower VECTOR_SHUFFLE as shift (if possible).
template<typename ValType>
static bool	fitsRegularPattern (typename SmallVectorImpl< ValType >::const_iterator Begin, unsigned CheckStride, typename SmallVectorImpl< ValType >::const_iterator End, ValType ExpectedIndex, unsigned ExpectedIndexStride)
	Determine whether a range fits a regular pattern of values.
static void	computeZeroableShuffleElements (ArrayRef< int > Mask, SDValue V1, SDValue V2, APInt &KnownUndef, APInt &KnownZero)
	Compute whether each element of a shuffle is zeroable.
static bool	isRepeatedShuffleMask (unsigned LaneSizeInBits, MVT VT, ArrayRef< int > Mask, SmallVectorImpl< int > &RepeatedMask)
	Test whether a shuffle mask is equivalent within each sub-lane.
static int	matchShuffleAsByteRotate (MVT VT, SDValue &V1, SDValue &V2, ArrayRef< int > Mask)
	Attempts to match vector shuffle as byte rotation.
static SDValue	lowerVECTOR_SHUFFLEAsByteRotate (const SDLoc &DL, ArrayRef< int > Mask, MVT VT, SDValue V1, SDValue V2, SelectionDAG &DAG, const LoongArchSubtarget &Subtarget)
	Lower VECTOR_SHUFFLE as byte rotate (if possible).
static SDValue	lowerVECTOR_SHUFFLEAsZeroOrAnyExtend (const SDLoc &DL, ArrayRef< int > Mask, MVT VT, SDValue V1, SDValue V2, SelectionDAG &DAG, const APInt &Zeroable)
	Lower VECTOR_SHUFFLE as ZERO_EXTEND Or ANY_EXTEND (if possible).
static SDValue	lowerVECTOR_SHUFFLE_VREPLVEI (const SDLoc &DL, ArrayRef< int > Mask, MVT VT, SDValue V1, SelectionDAG &DAG, const LoongArchSubtarget &Subtarget)
	Lower VECTOR_SHUFFLE into VREPLVEI (if possible).
static SDValue	lowerVECTOR_SHUFFLE_VSHUF4I (const SDLoc &DL, ArrayRef< int > Mask, MVT VT, SDValue V1, SDValue V2, SelectionDAG &DAG, const LoongArchSubtarget &Subtarget)
	Lower VECTOR_SHUFFLE into VSHUF4I (if possible).
static SDValue	lowerVECTOR_SHUFFLE_IsReverse (const SDLoc &DL, ArrayRef< int > Mask, MVT VT, SDValue V1, SelectionDAG &DAG, const LoongArchSubtarget &Subtarget)
	Lower VECTOR_SHUFFLE whose result is the reversed source vector.
static SDValue	lowerVECTOR_SHUFFLE_VPACKEV (const SDLoc &DL, ArrayRef< int > Mask, MVT VT, SDValue V1, SDValue V2, SelectionDAG &DAG)
	Lower VECTOR_SHUFFLE into VPACKEV (if possible).
static SDValue	lowerVECTOR_SHUFFLE_VPACKOD (const SDLoc &DL, ArrayRef< int > Mask, MVT VT, SDValue V1, SDValue V2, SelectionDAG &DAG)
	Lower VECTOR_SHUFFLE into VPACKOD (if possible).
static SDValue	lowerVECTOR_SHUFFLE_VILVH (const SDLoc &DL, ArrayRef< int > Mask, MVT VT, SDValue V1, SDValue V2, SelectionDAG &DAG)
	Lower VECTOR_SHUFFLE into VILVH (if possible).
static SDValue	lowerVECTOR_SHUFFLE_VILVL (const SDLoc &DL, ArrayRef< int > Mask, MVT VT, SDValue V1, SDValue V2, SelectionDAG &DAG)
	Lower VECTOR_SHUFFLE into VILVL (if possible).
static SDValue	lowerVECTOR_SHUFFLE_VPICKEV (const SDLoc &DL, ArrayRef< int > Mask, MVT VT, SDValue V1, SDValue V2, SelectionDAG &DAG)
	Lower VECTOR_SHUFFLE into VPICKEV (if possible).
static SDValue	lowerVECTOR_SHUFFLE_VPICKOD (const SDLoc &DL, ArrayRef< int > Mask, MVT VT, SDValue V1, SDValue V2, SelectionDAG &DAG)
	Lower VECTOR_SHUFFLE into VPICKOD (if possible).
static SDValue	lowerVECTOR_SHUFFLE_VSHUF (const SDLoc &DL, ArrayRef< int > Mask, MVT VT, SDValue V1, SDValue V2, SelectionDAG &DAG, const LoongArchSubtarget &Subtarget)
	Lower VECTOR_SHUFFLE into VSHUF.
static SDValue	lower128BitShuffle (const SDLoc &DL, ArrayRef< int > Mask, MVT VT, SDValue V1, SDValue V2, SelectionDAG &DAG, const LoongArchSubtarget &Subtarget)
	Dispatching routine to lower various 128-bit LoongArch vector shuffles.
static SDValue	lowerVECTOR_SHUFFLE_XVREPLVEI (const SDLoc &DL, ArrayRef< int > Mask, MVT VT, SDValue V1, SelectionDAG &DAG, const LoongArchSubtarget &Subtarget)
	Lower VECTOR_SHUFFLE into XVREPLVEI (if possible).
static SDValue	lowerVECTOR_SHUFFLE_XVSHUF4I (const SDLoc &DL, ArrayRef< int > Mask, MVT VT, SDValue V1, SDValue V2, SelectionDAG &DAG, const LoongArchSubtarget &Subtarget)
	Lower VECTOR_SHUFFLE into XVSHUF4I (if possible).
static SDValue	lowerVECTOR_SHUFFLE_XVPERMI (const SDLoc &DL, ArrayRef< int > Mask, MVT VT, SDValue V1, SelectionDAG &DAG, const LoongArchSubtarget &Subtarget)
	Lower VECTOR_SHUFFLE into XVPERMI (if possible).
static SDValue	lowerVECTOR_SHUFFLE_XVPERM (const SDLoc &DL, ArrayRef< int > Mask, MVT VT, SDValue V1, SelectionDAG &DAG, const LoongArchSubtarget &Subtarget)
	Lower VECTOR_SHUFFLE into XVPERM (if possible).
static SDValue	lowerVECTOR_SHUFFLE_XVPACKEV (const SDLoc &DL, ArrayRef< int > Mask, MVT VT, SDValue V1, SDValue V2, SelectionDAG &DAG)
	Lower VECTOR_SHUFFLE into XVPACKEV (if possible).
static SDValue	lowerVECTOR_SHUFFLE_XVPACKOD (const SDLoc &DL, ArrayRef< int > Mask, MVT VT, SDValue V1, SDValue V2, SelectionDAG &DAG)
	Lower VECTOR_SHUFFLE into XVPACKOD (if possible).
static SDValue	lowerVECTOR_SHUFFLE_XVILVH (const SDLoc &DL, ArrayRef< int > Mask, MVT VT, SDValue V1, SDValue V2, SelectionDAG &DAG)
	Lower VECTOR_SHUFFLE into XVILVH (if possible).
static SDValue	lowerVECTOR_SHUFFLE_XVILVL (const SDLoc &DL, ArrayRef< int > Mask, MVT VT, SDValue V1, SDValue V2, SelectionDAG &DAG)
	Lower VECTOR_SHUFFLE into XVILVL (if possible).
static SDValue	lowerVECTOR_SHUFFLE_XVPICKEV (const SDLoc &DL, ArrayRef< int > Mask, MVT VT, SDValue V1, SDValue V2, SelectionDAG &DAG)
	Lower VECTOR_SHUFFLE into XVPICKEV (if possible).
static SDValue	lowerVECTOR_SHUFFLE_XVPICKOD (const SDLoc &DL, ArrayRef< int > Mask, MVT VT, SDValue V1, SDValue V2, SelectionDAG &DAG)
	Lower VECTOR_SHUFFLE into XVPICKOD (if possible).
static SDValue	lowerVECTOR_SHUFFLE_XVINSVE0 (const SDLoc &DL, ArrayRef< int > Mask, MVT VT, SDValue V1, SDValue V2, SelectionDAG &DAG, const LoongArchSubtarget &Subtarget)
	Lower VECTOR_SHUFFLE into XVINSVE0 (if possible).
static SDValue	lowerVECTOR_SHUFFLE_XVSHUF (const SDLoc &DL, ArrayRef< int > Mask, MVT VT, SDValue V1, SDValue V2, SelectionDAG &DAG)
	Lower VECTOR_SHUFFLE into XVSHUF (if possible).
static bool	canonicalizeShuffleVectorByLane (const SDLoc &DL, MutableArrayRef< int > Mask, MVT VT, SDValue &V1, SDValue &V2, SelectionDAG &DAG, const LoongArchSubtarget &Subtarget)
	Shuffle vectors by lane to generate more optimized instructions.
static SDValue	lowerVECTOR_SHUFFLEAsLanePermuteAndShuffle (const SDLoc &DL, ArrayRef< int > Mask, MVT VT, SDValue V1, SDValue V2, SelectionDAG &DAG)
	Lower VECTOR_SHUFFLE as lane permute and then shuffle (if possible).
static SDValue	lower256BitShuffle (const SDLoc &DL, ArrayRef< int > Mask, MVT VT, SDValue V1, SDValue V2, SelectionDAG &DAG, const LoongArchSubtarget &Subtarget)
	Dispatching routine to lower various 256-bit LoongArch vector shuffles.
static SDValue	lowerBUILD_VECTORAsBroadCastLoad (BuildVectorSDNode *BVOp, const SDLoc &DL, SelectionDAG &DAG)
static void	fillVector (ArrayRef< SDValue > Ops, SelectionDAG &DAG, SDLoc DL, const LoongArchSubtarget &Subtarget, SDValue &Vector, EVT ResTy)
static SDValue	fillSubVectorFromBuildVector (BuildVectorSDNode *Node, SelectionDAG &DAG, SDLoc DL, const LoongArchSubtarget &Subtarget, EVT ResTy, unsigned first)
static SDValue	getTargetNode (GlobalAddressSDNode *N, SDLoc DL, EVT Ty, SelectionDAG &DAG, unsigned Flags)
static SDValue	getTargetNode (BlockAddressSDNode *N, SDLoc DL, EVT Ty, SelectionDAG &DAG, unsigned Flags)
static SDValue	getTargetNode (ConstantPoolSDNode *N, SDLoc DL, EVT Ty, SelectionDAG &DAG, unsigned Flags)
static SDValue	getTargetNode (JumpTableSDNode *N, SDLoc DL, EVT Ty, SelectionDAG &DAG, unsigned Flags)
template<unsigned N>
static SDValue	checkIntrinsicImmArg (SDValue Op, unsigned ImmOp, SelectionDAG &DAG, bool IsSigned=false)
static SDValue	emitIntrinsicWithChainErrorMessage (SDValue Op, StringRef ErrorMsg, SelectionDAG &DAG)
static SDValue	emitIntrinsicErrorMessage (SDValue Op, StringRef ErrorMsg, SelectionDAG &DAG)
static unsigned	getLoongArchWOpcode (unsigned Opcode)
static SDValue	customLegalizeToWOp (SDNode *N, SelectionDAG &DAG, int NumOp, unsigned ExtOpc=ISD::ANY_EXTEND)
static SDValue	customLegalizeToWOpWithSExt (SDNode *N, SelectionDAG &DAG)
static void	emitErrorAndReplaceIntrinsicResults (SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG, StringRef ErrorMsg, bool WithChain=true)
template<unsigned N>
static void	replaceVPICKVE2GRResults (SDNode *Node, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG, const LoongArchSubtarget &Subtarget, unsigned ResOp)
static void	replaceVecCondBranchResults (SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG, const LoongArchSubtarget &Subtarget, unsigned ResOp)
static void	replaceINTRINSIC_WO_CHAINResults (SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG, const LoongArchSubtarget &Subtarget)
static void	replaceCMP_XCHG_128Results (SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG)
static SDValue	combineAndNotIntoVANDN (SDNode *N, const SDLoc &DL, SelectionDAG &DAG)
	Try to fold: (and (xor X, -1), Y) -> (vandn X, Y).
static SDValue	performANDCombine (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const LoongArchSubtarget &Subtarget)
static SDValue	performSRLCombine (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const LoongArchSubtarget &Subtarget)
static bool	checkBitcastSrcVectorSize (SDValue Src, unsigned Size, unsigned Depth)
static SDValue	signExtendBitcastSrcVector (SelectionDAG &DAG, EVT SExtVT, SDValue Src, const SDLoc &DL)
static SDValue	performSETCC_BITCASTCombine (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const LoongArchSubtarget &Subtarget)
static SDValue	performBITCASTCombine (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const LoongArchSubtarget &Subtarget)
static SDValue	performORCombine (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const LoongArchSubtarget &Subtarget)
static bool	checkValueWidth (SDValue V, ISD::LoadExtType &ExtType)
static SDValue	performSETCCCombine (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const LoongArchSubtarget &Subtarget)
static SDValue	performBITREV_WCombine (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const LoongArchSubtarget &Subtarget)
static bool	combine_CC (SDValue &LHS, SDValue &RHS, SDValue &CC, const SDLoc &DL, SelectionDAG &DAG, const LoongArchSubtarget &Subtarget)
static SDValue	performBR_CCCombine (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const LoongArchSubtarget &Subtarget)
static SDValue	performSELECT_CCCombine (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const LoongArchSubtarget &Subtarget)
template<unsigned N>
static SDValue	legalizeIntrinsicImmArg (SDNode *Node, unsigned ImmOp, SelectionDAG &DAG, const LoongArchSubtarget &Subtarget, bool IsSigned=false)
template<unsigned N>
static SDValue	lowerVectorSplatImm (SDNode *Node, unsigned ImmOp, SelectionDAG &DAG, bool IsSigned=false)
static SDValue	truncateVecElts (SDNode *Node, SelectionDAG &DAG)
static SDValue	lowerVectorBitClear (SDNode *Node, SelectionDAG &DAG)
template<unsigned N>
static SDValue	lowerVectorBitClearImm (SDNode *Node, SelectionDAG &DAG)
template<unsigned N>
static SDValue	lowerVectorBitSetImm (SDNode *Node, SelectionDAG &DAG)
template<unsigned N>
static SDValue	lowerVectorBitRevImm (SDNode *Node, SelectionDAG &DAG)
template<unsigned W>
static SDValue	lowerVectorPickVE2GR (SDNode *N, SelectionDAG &DAG, unsigned ResOp)
static SDValue	performINTRINSIC_WO_CHAINCombine (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const LoongArchSubtarget &Subtarget)
static SDValue	performMOVGR2FR_WCombine (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const LoongArchSubtarget &Subtarget)
static SDValue	performMOVFR2GR_SCombine (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const LoongArchSubtarget &Subtarget)
static SDValue	performVMSKLTZCombine (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const LoongArchSubtarget &Subtarget)
static SDValue	performSPLIT_PAIR_F64Combine (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const LoongArchSubtarget &Subtarget)
static SDValue	performEXTRACT_VECTOR_ELTCombine (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const LoongArchSubtarget &Subtarget)
static SDValue	performVANDNCombine (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const LoongArchSubtarget &Subtarget)
	Do target-specific dag combines on LoongArchISD::VANDN nodes.
static SDValue	performSINT_TO_FPCombine (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const LoongArchSubtarget &Subtarget)
static MachineBasicBlock *	insertDivByZeroTrap (MachineInstr &MI, MachineBasicBlock *MBB)
static MachineBasicBlock *	emitVecCondBranchPseudo (MachineInstr &MI, MachineBasicBlock *BB, const LoongArchSubtarget &Subtarget)
static MachineBasicBlock *	emitPseudoXVINSGR2VR (MachineInstr &MI, MachineBasicBlock *BB, const LoongArchSubtarget &Subtarget)
static MachineBasicBlock *	emitPseudoCTPOP (MachineInstr &MI, MachineBasicBlock *BB, const LoongArchSubtarget &Subtarget)
static MachineBasicBlock *	emitPseudoVMSKCOND (MachineInstr &MI, MachineBasicBlock *BB, const LoongArchSubtarget &Subtarget)
static MachineBasicBlock *	emitSplitPairF64Pseudo (MachineInstr &MI, MachineBasicBlock *BB, const LoongArchSubtarget &Subtarget)
static MachineBasicBlock *	emitBuildPairF64Pseudo (MachineInstr &MI, MachineBasicBlock *BB, const LoongArchSubtarget &Subtarget)
static bool	isSelectPseudo (MachineInstr &MI)
static MachineBasicBlock *	emitSelectPseudo (MachineInstr &MI, MachineBasicBlock *BB, const LoongArchSubtarget &Subtarget)
static bool	CC_LoongArchAssign2GRLen (unsigned GRLen, CCState &State, CCValAssign VA1, ISD::ArgFlagsTy ArgFlags1, unsigned ValNo2, MVT ValVT2, MVT LocVT2, ISD::ArgFlagsTy ArgFlags2)
static bool	CC_LoongArch (const DataLayout &DL, LoongArchABI::ABI ABI, unsigned ValNo, MVT ValVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State, bool IsRet, Type *OrigTy)
static SDValue	convertLocVTToValVT (SelectionDAG &DAG, SDValue Val, const CCValAssign &VA, const SDLoc &DL)
static SDValue	unpackFromRegLoc (SelectionDAG &DAG, SDValue Chain, const CCValAssign &VA, const SDLoc &DL, const ISD::InputArg &In, const LoongArchTargetLowering &TLI)
static SDValue	unpackFromMemLoc (SelectionDAG &DAG, SDValue Chain, const CCValAssign &VA, const SDLoc &DL)
static SDValue	unpackF64OnLA32DSoftABI (SelectionDAG &DAG, SDValue Chain, const CCValAssign &VA, const CCValAssign &HiVA, const SDLoc &DL)
static SDValue	convertValVTToLocVT (SelectionDAG &DAG, SDValue Val, const CCValAssign &VA, const SDLoc &DL)
static bool	CC_LoongArch_GHC (unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State)
static Align	getPrefTypeAlign (EVT VT, SelectionDAG &DAG)
static Intrinsic::ID	getIntrinsicForMaskedAtomicRMWBinOp (unsigned GRLen, AtomicRMWInst::BinOp BinOp)
static int	getEstimateRefinementSteps (EVT VT, const LoongArchSubtarget &Subtarget)

Variables
static cl::opt< MaterializeFPImm >	MaterializeFPImmInsNum ("loongarch-materialize-float-imm", cl::Hidden, cl::desc("Maximum number of instructions used (including code sequence " "to generate the value and moving the value to FPR) when " "materializing floating-point immediates (default = 3)"), cl::init(MaterializeFPImm3Ins), cl::values(clEnumValN(NoMaterializeFPImm, "0", "Use constant pool"), clEnumValN(MaterializeFPImm2Ins, "2", "Materialize FP immediate within 2 instructions"), clEnumValN(MaterializeFPImm3Ins, "3", "Materialize FP immediate within 3 instructions"), clEnumValN(MaterializeFPImm4Ins, "4", "Materialize FP immediate within 4 instructions"), clEnumValN(MaterializeFPImm5Ins, "5", "Materialize FP immediate within 5 instructions"), clEnumValN(MaterializeFPImm6Ins, "6", "Materialize FP immediate within 6 instructions " "(behaves same as 5 on loongarch64)")))
static cl::opt< bool >	ZeroDivCheck ("loongarch-check-zero-division", cl::Hidden, cl::desc("Trap on integer division by zero."), cl::init(false))
const MCPhysReg	ArgGPRs []
const MCPhysReg	ArgFPR32s []
const MCPhysReg	ArgFPR64s []
const MCPhysReg	ArgVRs []
const MCPhysReg	ArgXRs []

Macro Definition Documentation

ASRT_LE_GT_CASE

#define ASRT_LE_GT_CASE

(

NAME

)

Value:

  case Intrinsic::loongarch_##NAME: {                                          \
    return !Subtarget.is64Bit()                                                \
               ? emitIntrinsicErrorMessage(Op, ErrorMsgReqLA64, DAG)           \
               : Op;                                                           \
  }

CRC_CASE_EXT_BINARYOP

#define CRC_CASE_EXT_BINARYOP	(		NAME,
			NODE )

Value:

  case Intrinsic::loongarch_##NAME: {                                          \
    SDValue NODE = DAG.getNode(                                                \
        LoongArchISD::NODE, DL, {MVT::i64, MVT::Other},                        \
        {Chain, DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op2),               \
         DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(3))});       \
    Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, VT, NODE.getValue(0)));   \
    Results.push_back(NODE.getValue(1));                                       \
    break;                                                                     \
  }

Referenced by llvm::LoongArchTargetLowering::ReplaceNodeResults().

CRC_CASE_EXT_UNARYOP

#define CRC_CASE_EXT_UNARYOP	(		NAME,
			NODE )

Value:

  case Intrinsic::loongarch_##NAME: {                                          \
    SDValue NODE = DAG.getNode(                                                \
        LoongArchISD::NODE, DL, {MVT::i64, MVT::Other},                        \
        {Chain, Op2,                                                           \
         DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(3))});       \
    Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, VT, NODE.getValue(0)));   \
    Results.push_back(NODE.getValue(1));                                       \
    break;                                                                     \
  }

Referenced by llvm::LoongArchTargetLowering::ReplaceNodeResults().

CSR_CASE

#define CSR_CASE

(

ID

)

Value:

  case Intrinsic::loongarch_##ID: {                                            \
    if (!Subtarget.is64Bit())                                                  \
      emitErrorAndReplaceIntrinsicResults(N, Results, DAG, ErrorMsgReqLA64);   \
    break;                                                                     \
  }

Referenced by llvm::LoongArchTargetLowering::ReplaceNodeResults().

DEBUG_TYPE

#define DEBUG_TYPE   "loongarch-isel-lowering"

Definition at line 42 of file LoongArchISelLowering.cpp.

GET_REGISTER_MATCHER

#define GET_REGISTER_MATCHER

Definition at line 9544 of file LoongArchISelLowering.cpp.

IOCSRRD_CASE [1/2]

#define IOCSRRD_CASE	(		NAME,
			NODE )

Value:

  case Intrinsic::loongarch_##NAME: {                                          \
    return DAG.getNode(LoongArchISD::NODE, DL, {GRLenVT, MVT::Other},          \
                       {Chain, Op.getOperand(2)});                             \
  }

Referenced by llvm::LoongArchTargetLowering::ReplaceNodeResults().

IOCSRRD_CASE [2/2]

#define IOCSRRD_CASE	(		NAME,
			NODE )

Value:

  case Intrinsic::loongarch_##NAME: {                                          \
    SDValue IOCSRRDResults =                                                   \
        DAG.getNode(LoongArchISD::NODE, DL, {MVT::i64, MVT::Other},            \
                    {Chain, DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op2)}); \
    Results.push_back(                                                         \
        DAG.getNode(ISD::TRUNCATE, DL, VT, IOCSRRDResults.getValue(0)));       \
    Results.push_back(IOCSRRDResults.getValue(1));                             \
    break;                                                                     \
  }

IOCSRWR_CASE

#define IOCSRWR_CASE	(		NAME,
			NODE )

Value:

  case Intrinsic::loongarch_##NAME: {                                          \
    SDValue Op3 = Op.getOperand(3);                                            \
    return Subtarget.is64Bit()                                                 \
               ? DAG.getNode(LoongArchISD::NODE, DL, MVT::Other, Chain,        \
                             DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op2),  \
                             DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op3))  \
               : DAG.getNode(LoongArchISD::NODE, DL, MVT::Other, Chain, Op2,   \
                             Op3);                                             \
  }

Enumeration Type Documentation

MaterializeFPImm

enum MaterializeFPImm

Enumerator
NoMaterializeFPImm
MaterializeFPImm2Ins
MaterializeFPImm3Ins
MaterializeFPImm4Ins
MaterializeFPImm5Ins
MaterializeFPImm6Ins

Definition at line 46 of file LoongArchISelLowering.cpp.

Function Documentation

canonicalizeShuffleVectorByLane()

bool canonicalizeShuffleVectorByLane ( const SDLoc & DL, MutableArrayRef< int > Mask, MVT VT, SDValue & V1, SDValue & V2, SelectionDAG & DAG, const LoongArchSubtarget & Subtarget )

static

Shuffle vectors by lane to generate more optimized instructions.

256-bit shuffles are always considered as 2-lane 128-bit shuffles.

Therefore, except for the following four cases, other cases are regarded as cross-lane shuffles, where optimization is relatively limited.

• Shuffle high, low lanes of two inputs vector <0, 1, 2, 3> + <4, 5, 6, 7> — <0, 5, 3, 6>
• Shuffle low, high lanes of two inputs vector <0, 1, 2, 3> + <4, 5, 6, 7> — <3, 6, 0, 5>
• Shuffle low, low lanes of two inputs vector <0, 1, 2, 3> + <4, 5, 6, 7> — <3, 6, 3, 6>
• Shuffle high, high lanes of two inputs vector <0, 1, 2, 3> + <4, 5, 6, 7> — <0, 5, 0, 5>

The first case is the closest to LoongArch instructions and the other cases need to be converted to it for processing.

This function will return true for the last three cases above and will modify V1, V2 and Mask. Otherwise, return false for the first case and cross-lane shuffle cases.

Definition at line 2611 of file LoongArchISelLowering.cpp.

References DL, llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getConstant(), llvm::LoongArchSubtarget::getGRLenVT(), llvm::SelectionDAG::getNode(), llvm::SDValue::isUndef(), and llvm::None.

Referenced by lower256BitShuffle().

CC_LoongArch()

bool CC_LoongArch ( const DataLayout & DL, LoongArchABI::ABI ABI, unsigned ValNo, MVT ValVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState & State, bool IsRet, Type * OrigTy )

static

Definition at line 7814 of file LoongArchISelLowering.cpp.

References llvm::LoongArchABI::ABI_ILP32D, llvm::LoongArchABI::ABI_ILP32F, llvm::LoongArchABI::ABI_ILP32S, llvm::LoongArchABI::ABI_LP64D, llvm::LoongArchABI::ABI_LP64F, llvm::LoongArchABI::ABI_LP64S, ArgFPR32s, ArgFPR64s, ArgGPRs, ArgVRs, ArgXRs, assert(), llvm::CCValAssign::BCvt, CC_LoongArchAssign2GRLen(), llvm::SmallVectorImpl< T >::clear(), DL, llvm::SmallVectorTemplateCommon< T, typename >::empty(), llvm::CCValAssign::Full, llvm::CCValAssign::getCustomMem(), llvm::CCValAssign::getCustomReg(), llvm::CCValAssign::getMem(), llvm::ISD::ArgFlagsTy::getNonZeroOrigAlign(), llvm::CCValAssign::getPending(), llvm::CCValAssign::getReg(), llvm::CCValAssign::Indirect, llvm::MVT::is128BitVector(), llvm::MVT::is256BitVector(), llvm::MVT::isFloatingPoint(), llvm::MVT::isScalarInteger(), llvm::ISD::ArgFlagsTy::isSplit(), llvm::ISD::ArgFlagsTy::isSplitEnd(), llvm::ISD::ArgFlagsTy::isVarArg(), llvm_unreachable, llvm::SmallVectorTemplateBase< T, bool >::push_back(), Reg, and llvm::SmallVectorTemplateCommon< T, typename >::size().

Referenced by llvm::LoongArchTargetLowering::CanLowerReturn(), llvm::LoongArchTargetLowering::LowerCall(), llvm::LoongArchTargetLowering::LowerFormalArguments(), and llvm::LoongArchTargetLowering::LowerReturn().

CC_LoongArch_GHC()

bool CC_LoongArch_GHC ( unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, Type * OrigTy, CCState & State )

static

Definition at line 8166 of file LoongArchISelLowering.cpp.

References llvm::CCValAssign::getReg(), Reg, and llvm::report_fatal_error().

Referenced by llvm::LoongArchTargetLowering::LowerCall(), and llvm::LoongArchTargetLowering::LowerFormalArguments().

CC_LoongArchAssign2GRLen()

bool CC_LoongArchAssign2GRLen ( unsigned GRLen, CCState & State, CCValAssign VA1, ISD::ArgFlagsTy ArgFlags1, unsigned ValNo2, MVT ValVT2, MVT LocVT2, ISD::ArgFlagsTy ArgFlags2 )

static

Definition at line 7778 of file LoongArchISelLowering.cpp.

References ArgGPRs, llvm::CCValAssign::Full, llvm::CCValAssign::getLocVT(), llvm::CCValAssign::getMem(), llvm::ISD::ArgFlagsTy::getNonZeroOrigAlign(), llvm::CCValAssign::getReg(), llvm::CCValAssign::getValNo(), llvm::CCValAssign::getValVT(), and Reg.

Referenced by CC_LoongArch().

checkBitcastSrcVectorSize()

bool checkBitcastSrcVectorSize ( SDValue Src, unsigned Size, unsigned Depth )

static

Definition at line 5349 of file LoongArchISelLowering.cpp.

References llvm::ISD::AND, llvm::ISD::BUILD_VECTOR, checkBitcastSrcVectorSize(), llvm::Depth, llvm::ISD::FREEZE, llvm::ISD::isBuildVectorAllOnes(), llvm::ISD::isBuildVectorAllZeros(), llvm::SelectionDAG::MaxRecursionDepth, llvm::ISD::OR, llvm::ISD::SELECT, llvm::ISD::SETCC, Size, llvm::ISD::TRUNCATE, llvm::ISD::VSELECT, and llvm::ISD::XOR.

Referenced by checkBitcastSrcVectorSize(), checkBitcastSrcVectorSize(), combineBitcastvxi1(), and performBITCASTCombine().

checkIntrinsicImmArg()

template<unsigned N>

SDValue checkIntrinsicImmArg ( SDValue Op, unsigned ImmOp, SelectionDAG & DAG, bool IsSigned = false )

static

Definition at line 3902 of file LoongArchISelLowering.cpp.

References llvm::cast(), llvm::LLVMContext::emitError(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getNode(), llvm::isInt(), llvm::isUInt(), SDValue(), and llvm::ISD::UNDEF.

checkValueWidth()

bool checkValueWidth ( SDValue V, ISD::LoadExtType & ExtType )

static

Definition at line 5796 of file LoongArchISelLowering.cpp.

References llvm::ISD::AssertSext, llvm::ISD::AssertZext, llvm::cast(), llvm::LoadSDNode::getExtensionType(), llvm::MemSDNode::getMemoryVT(), llvm::VTSDNode::getVT(), llvm::ISD::LOAD, llvm::ISD::NON_EXTLOAD, llvm::ISD::SEXTLOAD, and llvm::ISD::ZEXTLOAD.

combine_CC()

bool combine_CC ( SDValue & LHS, SDValue & RHS, SDValue & CC, const SDLoc & DL, SelectionDAG & DAG, const LoongArchSubtarget & Subtarget )

static

Definition at line 5975 of file LoongArchISelLowering.cpp.

References llvm::ISD::AND, llvm::cast(), llvm::ISD::Constant, DL, llvm::APInt::getBitsSetFrom(), llvm::SelectionDAG::getCondCode(), llvm::SelectionDAG::getConstant(), llvm::SDValue::getConstantOperandVal(), llvm::LoongArchSubtarget::getGRLenVT(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::ISD::getSetCCInverse(), llvm::ISD::isIntEqualitySetCC(), llvm::isNullConstant(), llvm::isOneConstant(), llvm::isPowerOf2_64(), LHS, llvm::Log2_64(), llvm::SelectionDAG::MaskedValueIsZero(), RHS, llvm::ISD::SETCC, llvm::ISD::SETEQ, llvm::ISD::SETGE, llvm::ISD::SETLT, llvm::ISD::SHL, llvm::ISD::SRA, llvm::ISD::SRL, and translateSetCCForBranch().

Referenced by performBR_CCCombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), and performSELECT_CCCombine().

combineAndNotIntoVANDN()

SDValue combineAndNotIntoVANDN ( SDNode * N, const SDLoc & DL, SelectionDAG & DAG )

static

Try to fold: (and (xor X, -1), Y) -> (vandn X, Y).

Definition at line 5183 of file LoongArchISelLowering.cpp.

References llvm::ISD::AND, assert(), DL, llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getNode(), llvm::MVT::is128BitVector(), llvm::MVT::is256BitVector(), isNOT(), N, SDValue(), X, and Y.

Referenced by performANDCombine().

combineSelectToBinOp()

SDValue combineSelectToBinOp ( SDNode * N, SelectionDAG & DAG, const LoongArchSubtarget & Subtarget )

static

Definition at line 915 of file LoongArchISelLowering.cpp.

References llvm::ISD::ADD, llvm::ISD::AND, llvm::cast(), DL, llvm::SelectionDAG::getAllOnesConstant(), llvm::SDNode::getAsAPIntVal(), llvm::SelectionDAG::getFreeze(), llvm::SelectionDAG::getNegative(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::isa(), llvm::isAllOnesConstant(), llvm::isNullConstant(), LHS, matchSetCC(), N, llvm::ISD::OR, RHS, SDValue(), llvm::ISD::SETCC, and llvm::ISD::XOR.

computeZeroableShuffleElements()

void computeZeroableShuffleElements ( ArrayRef< int > Mask, SDValue V1, SDValue V2, APInt & KnownUndef, APInt & KnownZero )

static

Compute whether each element of a shuffle is zeroable.

A "zeroable" vector shuffle element is one which can be lowered to zero.

Definition at line 1472 of file LoongArchISelLowering.cpp.

References assert(), llvm::SDValue::getNode(), llvm::SDValue::getValueSizeInBits(), llvm::APInt::getZero(), llvm::ISD::isBuildVectorAllZeros(), llvm::peekThroughBitcasts(), llvm::APInt::setBit(), and Size.

Referenced by lower128BitShuffle(), lower256BitShuffle(), and lowerVECTOR_SHUFFLE().

convertLocVTToValVT()

SDValue convertLocVTToValVT ( SelectionDAG & DAG, SDValue Val, const CCValAssign & VA, const SDLoc & DL )

static

Definition at line 8039 of file LoongArchISelLowering.cpp.

References llvm::CCValAssign::BCvt, llvm::ISD::BITCAST, DL, llvm::CCValAssign::Full, llvm::CCValAssign::getLocInfo(), llvm::CCValAssign::getLocVT(), llvm::SelectionDAG::getNode(), llvm::CCValAssign::getValVT(), llvm::CCValAssign::Indirect, and llvm_unreachable.

convertValVTToLocVT()

SDValue convertValVTToLocVT ( SelectionDAG & DAG, SDValue Val, const CCValAssign & VA, const SDLoc & DL )

static

Definition at line 8147 of file LoongArchISelLowering.cpp.

References llvm::CCValAssign::BCvt, llvm::ISD::BITCAST, DL, llvm::CCValAssign::Full, llvm::CCValAssign::getLocInfo(), llvm::CCValAssign::getLocVT(), llvm::SelectionDAG::getNode(), llvm::CCValAssign::getValVT(), and llvm_unreachable.

customLegalizeToWOp()

SDValue customLegalizeToWOp ( SDNode * N, SelectionDAG & DAG, int NumOp, unsigned ExtOpc = ISD::ANY_EXTEND )

static

Definition at line 4620 of file LoongArchISelLowering.cpp.

References llvm::ISD::ANY_EXTEND, DL, llvm::SelectionDAG::getConstant(), getLoongArchWOpcode(), llvm::SelectionDAG::getNode(), llvm_unreachable, N, llvm::ISD::ROTL, llvm::ISD::SUB, and llvm::ISD::TRUNCATE.

Referenced by llvm::LoongArchTargetLowering::ReplaceNodeResults(), and llvm::RISCVTargetLowering::ReplaceNodeResults().

customLegalizeToWOpWithSExt()

SDValue customLegalizeToWOpWithSExt ( SDNode * N, SelectionDAG & DAG )

static

Definition at line 4654 of file LoongArchISelLowering.cpp.

References llvm::ISD::ANY_EXTEND, DL, llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getValueType(), N, llvm::ISD::SIGN_EXTEND_INREG, and llvm::ISD::TRUNCATE.

Referenced by llvm::LoongArchTargetLowering::ReplaceNodeResults(), and llvm::RISCVTargetLowering::ReplaceNodeResults().

emitBuildPairF64Pseudo()

MachineBasicBlock * emitBuildPairF64Pseudo ( MachineInstr & MI, MachineBasicBlock * BB, const LoongArchSubtarget & Subtarget )

static

Definition at line 7470 of file LoongArchISelLowering.cpp.

References llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), DL, llvm::TargetSubtargetInfo::getInstrInfo(), llvm::getKillRegState(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), llvm::MachineFunction::getSubtarget(), llvm::RegState::Kill, MI, MRI, and TII.

Referenced by llvm::RISCVTargetLowering::EmitInstrWithCustomInserter().

emitErrorAndReplaceIntrinsicResults()

void emitErrorAndReplaceIntrinsicResults ( SDNode * N, SmallVectorImpl< SDValue > & Results, SelectionDAG & DAG, StringRef ErrorMsg, bool WithChain = true )

static

Definition at line 4666 of file LoongArchISelLowering.cpp.

References llvm::LLVMContext::emitError(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getUNDEF(), N, and Results.

Referenced by llvm::LoongArchTargetLowering::ReplaceNodeResults(), and replaceVPICKVE2GRResults().

emitIntrinsicErrorMessage()

SDValue emitIntrinsicErrorMessage ( SDValue Op, StringRef ErrorMsg, SelectionDAG & DAG )

static

Definition at line 4318 of file LoongArchISelLowering.cpp.

References llvm::LLVMContext::emitError(), and llvm::SelectionDAG::getContext().

emitIntrinsicWithChainErrorMessage()

SDValue emitIntrinsicWithChainErrorMessage ( SDValue Op, StringRef ErrorMsg, SelectionDAG & DAG )

static

Definition at line 4195 of file LoongArchISelLowering.cpp.

References llvm::LLVMContext::emitError(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getMergeValues(), and llvm::SelectionDAG::getUNDEF().

emitPseudoCTPOP()

MachineBasicBlock * emitPseudoCTPOP ( MachineInstr & MI, MachineBasicBlock * BB, const LoongArchSubtarget & Subtarget )

static

Definition at line 7297 of file LoongArchISelLowering.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), DL, llvm::LoongArchSubtarget::getInstrInfo(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), llvm::LoongArchSubtarget::is64Bit(), MI, MRI, and TII.

emitPseudoVMSKCOND()

MachineBasicBlock * emitPseudoVMSKCOND ( MachineInstr & MI, MachineBasicBlock * BB, const LoongArchSubtarget & Subtarget )

static

Definition at line 7336 of file LoongArchISelLowering.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), DL, llvm::LoongArchSubtarget::getInstrInfo(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), llvm::LoongArchSubtarget::getRegisterInfo(), llvm::Hi, llvm::LoongArchSubtarget::is64Bit(), llvm::RegState::Kill, llvm_unreachable, llvm::Lo, MI, MRI, TII, and TRI.

emitPseudoXVINSGR2VR()

MachineBasicBlock * emitPseudoXVINSGR2VR ( MachineInstr & MI, MachineBasicBlock * BB, const LoongArchSubtarget & Subtarget )

static

Definition at line 7227 of file LoongArchISelLowering.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), DL, llvm::LoongArchSubtarget::getInstrInfo(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), llvm::Register::isVirtual(), llvm_unreachable, MI, MRI, and TII.

emitSelectPseudo()

MachineBasicBlock * emitSelectPseudo ( MachineInstr & MI, MachineBasicBlock * BB, const LoongArchSubtarget & Subtarget )

static

Definition at line 7503 of file LoongArchISelLowering.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMBB(), llvm::MachineInstrBuilder::addReg(), llvm::MachineBasicBlock::addSuccessor(), llvm::any_of(), llvm::MachineBasicBlock::begin(), llvm::BuildMI(), llvm::MachineInstr::collectDebugValues(), llvm::SmallSet< T, N, C >::count(), DL, E(), llvm::MachineBasicBlock::end(), llvm::MachineInstr::eraseFromParent(), F, llvm::MachineBasicBlock::getBasicBlock(), llvm::getImm(), llvm::LoongArchSubtarget::getInstrInfo(), llvm::ilist_node_impl< OptionsT >::getIterator(), llvm::MachineBasicBlock::getParent(), I, llvm::SmallSet< T, N, C >::insert(), isSelectPseudo(), LHS, MI, llvm::Next, llvm::MachineBasicBlock::push_back(), RHS, llvm::MachineBasicBlock::setCallFrameSize(), llvm::MachineBasicBlock::splice(), TII, and llvm::MachineBasicBlock::transferSuccessorsAndUpdatePHIs().

emitSplitPairF64Pseudo()

MachineBasicBlock * emitSplitPairF64Pseudo ( MachineInstr & MI, MachineBasicBlock * BB, const LoongArchSubtarget & Subtarget )

static

Definition at line 7450 of file LoongArchISelLowering.cpp.

References llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), DL, llvm::TargetSubtargetInfo::getInstrInfo(), llvm::getKillRegState(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getSubtarget(), MI, and TII.

emitVecCondBranchPseudo()

MachineBasicBlock * emitVecCondBranchPseudo ( MachineInstr & MI, MachineBasicBlock * BB, const LoongArchSubtarget & Subtarget )

static

Definition at line 7102 of file LoongArchISelLowering.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMBB(), llvm::MachineInstrBuilder::addReg(), llvm::MachineBasicBlock::addSuccessor(), llvm::MachineBasicBlock::begin(), llvm::BuildMI(), DL, llvm::MachineBasicBlock::end(), F, llvm::MachineBasicBlock::getBasicBlock(), llvm::LoongArchSubtarget::getInstrInfo(), llvm::ilist_node_impl< OptionsT >::getIterator(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), llvm_unreachable, MI, MRI, llvm::MachineBasicBlock::splice(), TII, and llvm::MachineBasicBlock::transferSuccessorsAndUpdatePHIs().

fillSubVectorFromBuildVector()

SDValue fillSubVectorFromBuildVector ( BuildVectorSDNode * Node, SelectionDAG & DAG, SDLoc DL, const LoongArchSubtarget & Subtarget, EVT ResTy, unsigned first )

static

Definition at line 3036 of file LoongArchISelLowering.cpp.

References AbstractManglingParser< Derived, Alloc >::Ops, assert(), DL, fillVector(), llvm::SelectionDAG::getUNDEF(), llvm::EVT::getVectorNumElements(), and llvm::Vector.

fillVector()

void fillVector ( ArrayRef< SDValue > Ops, SelectionDAG & DAG, SDLoc DL, const LoongArchSubtarget & Subtarget, SDValue & Vector, EVT ResTy )

static

Definition at line 3017 of file LoongArchISelLowering.cpp.

References AbstractManglingParser< Derived, Alloc >::Ops, assert(), DL, llvm::SelectionDAG::getConstant(), llvm::LoongArchSubtarget::getGRLenVT(), llvm::SelectionDAG::getNode(), llvm::EVT::getVectorNumElements(), llvm::ISD::INSERT_VECTOR_ELT, llvm::SDValue::isUndef(), llvm::ISD::SCALAR_TO_VECTOR, and llvm::Vector.

Referenced by fillSubVectorFromBuildVector().

fitsRegularPattern()

template<typename ValType>

bool fitsRegularPattern ( typename SmallVectorImpl< ValType >::const_iterator Begin, unsigned CheckStride, typename SmallVectorImpl< ValType >::const_iterator End, ValType ExpectedIndex, unsigned ExpectedIndexStride )

static

Determine whether a range fits a regular pattern of values.

This function accounts for the possibility of jumping over the End iterator.

Definition at line 1450 of file LoongArchISelLowering.cpp.

References I.

Referenced by isVECTOR_SHUFFLE_SPLATI(), lowerVECTOR_SHUFFLE_ILVEV(), lowerVECTOR_SHUFFLE_ILVL(), lowerVECTOR_SHUFFLE_ILVOD(), lowerVECTOR_SHUFFLE_ILVR(), lowerVECTOR_SHUFFLE_PCKEV(), lowerVECTOR_SHUFFLE_PCKOD(), lowerVECTOR_SHUFFLE_VILVH(), lowerVECTOR_SHUFFLE_VILVL(), lowerVECTOR_SHUFFLE_VPACKEV(), lowerVECTOR_SHUFFLE_VPACKOD(), lowerVECTOR_SHUFFLE_VPICKEV(), lowerVECTOR_SHUFFLE_VPICKOD(), lowerVECTOR_SHUFFLE_VREPLVEI(), lowerVECTOR_SHUFFLE_XVILVH(), lowerVECTOR_SHUFFLE_XVILVL(), lowerVECTOR_SHUFFLE_XVPICKEV(), lowerVECTOR_SHUFFLE_XVPICKOD(), and lowerVECTOR_SHUFFLE_XVREPLVEI().

foldBinOpIntoSelectIfProfitable()

SDValue foldBinOpIntoSelectIfProfitable ( SDNode * BO, SelectionDAG & DAG, const LoongArchSubtarget & Subtarget )

static

Definition at line 989 of file LoongArchISelLowering.cpp.

References DL, llvm::dyn_cast(), llvm::SelectionDAG::FoldConstantArithmetic(), llvm::SDNode::getAsAPIntVal(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOperand(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getSelect(), llvm::SDNode::getValueType(), llvm::SDValue::hasOneUse(), llvm::isa(), llvm::APInt::isAllOnes(), llvm::ConstantSDNode::isOpaque(), llvm::APInt::isZero(), SDValue(), llvm::ISD::SELECT, and std::swap().

getEstimateRefinementSteps()

int getEstimateRefinementSteps ( EVT VT, const LoongArchSubtarget & Subtarget )

static

Definition at line 9313 of file LoongArchISelLowering.cpp.

References llvm::EVT::getScalarType().

Referenced by llvm::LoongArchTargetLowering::getRecipEstimate(), and llvm::LoongArchTargetLowering::getSqrtEstimate().

getIntrinsicForMaskedAtomicRMWBinOp()

Intrinsic::ID getIntrinsicForMaskedAtomicRMWBinOp ( unsigned GRLen, AtomicRMWInst::BinOp BinOp )

static

Definition at line 9134 of file LoongArchISelLowering.cpp.

References llvm::AtomicRMWInst::Add, llvm_unreachable, llvm::AtomicRMWInst::Max, llvm::AtomicRMWInst::Min, llvm::AtomicRMWInst::Nand, llvm::AtomicRMWInst::Sub, llvm::AtomicRMWInst::UMax, llvm::AtomicRMWInst::UMin, and llvm::AtomicRMWInst::Xchg.

Referenced by llvm::LoongArchTargetLowering::emitMaskedAtomicRMWIntrinsic(), and llvm::RISCVTargetLowering::emitMaskedAtomicRMWIntrinsic().

getLoongArchWOpcode()

unsigned getLoongArchWOpcode ( unsigned Opcode )

static

Definition at line 4587 of file LoongArchISelLowering.cpp.

References llvm::ISD::CTLZ, llvm::ISD::CTTZ, llvm_unreachable, llvm::ISD::ROTL, llvm::ISD::ROTR, llvm::ISD::SDIV, llvm::ISD::SHL, llvm::ISD::SRA, llvm::ISD::SREM, llvm::ISD::SRL, llvm::ISD::UDIV, and llvm::ISD::UREM.

Referenced by customLegalizeToWOp().

getPrefTypeAlign()

Align getPrefTypeAlign ( EVT VT, SelectionDAG & DAG )

static

Definition at line 8445 of file LoongArchISelLowering.cpp.

References llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getDataLayout(), llvm::DataLayout::getPrefTypeAlign(), and llvm::EVT::getTypeForEVT().

Referenced by llvm::SelectionDAG::CreateStackTemporary(), llvm::LoongArchTargetLowering::LowerCall(), and llvm::RISCVTargetLowering::LowerCall().

getTargetNode() [1/4]

SDValue getTargetNode ( BlockAddressSDNode * N, SDLoc DL, EVT Ty, SelectionDAG & DAG, unsigned Flags )

static

Definition at line 3629 of file LoongArchISelLowering.cpp.

References DL, llvm::SelectionDAG::getTargetBlockAddress(), and N.

getTargetNode() [2/4]

SDValue getTargetNode ( ConstantPoolSDNode * N, SDLoc DL, EVT Ty, SelectionDAG & DAG, unsigned Flags )

static

Definition at line 3635 of file LoongArchISelLowering.cpp.

References DL, llvm::SelectionDAG::getTargetConstantPool(), and N.

getTargetNode() [3/4]

SDValue getTargetNode ( GlobalAddressSDNode * N, SDLoc DL, EVT Ty, SelectionDAG & DAG, unsigned Flags )

static

Definition at line 3624 of file LoongArchISelLowering.cpp.

References DL, llvm::SelectionDAG::getTargetGlobalAddress(), and N.

getTargetNode() [4/4]

SDValue getTargetNode ( JumpTableSDNode * N, SDLoc DL, EVT Ty, SelectionDAG & DAG, unsigned Flags )

static

Definition at line 3641 of file LoongArchISelLowering.cpp.

References DL, llvm::SelectionDAG::getTargetJumpTable(), and N.

insertDivByZeroTrap()

MachineBasicBlock * insertDivByZeroTrap ( MachineInstr & MI, MachineBasicBlock * MBB )

static

Definition at line 7051 of file LoongArchISelLowering.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMBB(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::MachineFunction::CreateMachineBasicBlock(), DL, llvm::TargetSubtargetInfo::getInstrInfo(), llvm::getKillRegState(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getSubtarget(), llvm::MachineFunction::insert(), llvm::MachineOperand::isKill(), MBB, MI, llvm::MachineOperand::setIsKill(), TII, and ZeroDivCheck.

Referenced by llvm::MipsTargetLowering::EmitInstrWithCustomInserter().

isNOT()

SDValue isNOT ( SDValue V, SelectionDAG & DAG )

static

Definition at line 626 of file LoongArchISelLowering.cpp.

References llvm::ISD::AND, llvm::ISD::BUILD_VECTOR, llvm::cast(), llvm::ISD::EXTRACT_SUBVECTOR, llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getSplat(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::isAllOnesConstant(), llvm::ISD::isBuildVectorAllOnes(), isNOT(), llvm::isNullConstant(), llvm::TargetLoweringBase::isTypeLegal(), llvm::ISD::OR, llvm::peekThroughBitcasts(), SDValue(), and llvm::ISD::XOR.

Referenced by combineAndNotIntoVANDN(), llvm::X86InstrInfo::isDataInvariant(), isNOT(), and performVANDNCombine().

isRepeatedShuffleMask()

bool isRepeatedShuffleMask ( unsigned LaneSizeInBits, MVT VT, ArrayRef< int > Mask, SmallVectorImpl< int > & RepeatedMask )

static

Test whether a shuffle mask is equivalent within each sub-lane.

The specific repeated shuffle mask is populated in RepeatedMask, as it is non-trivial to compute in the face of undef lanes. The representation is suitable for use with existing 128-bit shuffles as entries from the second vector have been remapped to [LaneSize, 2*LaneSize).

Definition at line 1508 of file LoongArchISelLowering.cpp.

References assert(), llvm::SmallVectorImpl< T >::assign(), llvm::MVT::getScalarSizeInBits(), and Size.

Referenced by is128BitLaneRepeatedShuffleMask(), is128BitLaneRepeatedShuffleMask(), is256BitLaneRepeatedShuffleMask(), and matchShuffleAsByteRotate().

isSelectPseudo()

bool isSelectPseudo ( MachineInstr & MI )

static

Definition at line 7493 of file LoongArchISelLowering.cpp.

References MI.

Referenced by emitSelectPseudo().

legalizeIntrinsicImmArg()

template<unsigned N>

SDValue legalizeIntrinsicImmArg ( SDNode * Node, unsigned ImmOp, SelectionDAG & DAG, const LoongArchSubtarget & Subtarget, bool IsSigned = false )

static

Definition at line 6114 of file LoongArchISelLowering.cpp.

References llvm::cast(), DL, llvm::LLVMContext::emitError(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::LoongArchSubtarget::getGRLenVT(), llvm::SelectionDAG::getNode(), llvm::isInt(), llvm::isUInt(), and llvm::ISD::UNDEF.

Referenced by performINTRINSIC_WO_CHAINCombine().

lower128BitShuffle()

SDValue lower128BitShuffle ( const SDLoc & DL, ArrayRef< int > Mask, MVT VT, SDValue V1, SDValue V2, SelectionDAG & DAG, const LoongArchSubtarget & Subtarget )

static

Dispatching routine to lower various 128-bit LoongArch vector shuffles.

This routine breaks down the specific type of 128-bit shuffle and dispatches to the lowering routines accordingly.

Definition at line 2149 of file LoongArchISelLowering.cpp.

References assert(), computeZeroableShuffleElements(), DL, llvm::SDValue::getSimpleValueType(), llvm::MVT::getVectorNumElements(), llvm::SDValue::isUndef(), lowerVECTOR_SHUFFLE_IsReverse(), lowerVECTOR_SHUFFLE_VILVH(), lowerVECTOR_SHUFFLE_VILVL(), lowerVECTOR_SHUFFLE_VPACKEV(), lowerVECTOR_SHUFFLE_VPACKOD(), lowerVECTOR_SHUFFLE_VPICKEV(), lowerVECTOR_SHUFFLE_VPICKOD(), lowerVECTOR_SHUFFLE_VREPLVEI(), lowerVECTOR_SHUFFLE_VSHUF(), lowerVECTOR_SHUFFLE_VSHUF4I(), lowerVECTOR_SHUFFLEAsByteRotate(), lowerVECTOR_SHUFFLEAsShift(), lowerVECTOR_SHUFFLEAsZeroOrAnyExtend(), SDValue(), llvm::MVT::SimpleTy, and widenShuffleMask().

Referenced by lowerVECTOR_SHUFFLE().

lower256BitShuffle()

SDValue lower256BitShuffle ( const SDLoc & DL, ArrayRef< int > Mask, MVT VT, SDValue V1, SDValue V2, SelectionDAG & DAG, const LoongArchSubtarget & Subtarget )

static

Dispatching routine to lower various 256-bit LoongArch vector shuffles.

This routine breaks down the specific type of 256-bit shuffle and dispatches to the lowering routines accordingly.

Definition at line 2761 of file LoongArchISelLowering.cpp.

References assert(), canonicalizeShuffleVectorByLane(), computeZeroableShuffleElements(), DL, llvm::SDValue::getSimpleValueType(), llvm::MVT::getVectorNumElements(), llvm::SDValue::isUndef(), lower256BitShuffle(), lowerVECTOR_SHUFFLE_IsReverse(), lowerVECTOR_SHUFFLE_XVILVH(), lowerVECTOR_SHUFFLE_XVILVL(), lowerVECTOR_SHUFFLE_XVINSVE0(), lowerVECTOR_SHUFFLE_XVPACKEV(), lowerVECTOR_SHUFFLE_XVPACKOD(), lowerVECTOR_SHUFFLE_XVPERM(), lowerVECTOR_SHUFFLE_XVPERMI(), lowerVECTOR_SHUFFLE_XVPICKEV(), lowerVECTOR_SHUFFLE_XVPICKOD(), lowerVECTOR_SHUFFLE_XVREPLVEI(), lowerVECTOR_SHUFFLE_XVSHUF(), lowerVECTOR_SHUFFLE_XVSHUF4I(), lowerVECTOR_SHUFFLEAsByteRotate(), lowerVECTOR_SHUFFLEAsLanePermuteAndShuffle(), lowerVECTOR_SHUFFLEAsShift(), SDValue(), llvm::MVT::SimpleTy, and widenShuffleMask().

Referenced by lower256BitShuffle(), and lowerVECTOR_SHUFFLE().

lowerBUILD_VECTORAsBroadCastLoad()

SDValue lowerBUILD_VECTORAsBroadCastLoad ( BuildVectorSDNode * BVOp, const SDLoc & DL, SelectionDAG & DAG )

static

Definition at line 2971 of file LoongArchISelLowering.cpp.

References AbstractManglingParser< Derived, Alloc >::NumOps, AbstractManglingParser< Derived, Alloc >::Ops, assert(), llvm::cast(), DL, llvm::ISD::EXTLOAD, llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getNumOperands(), llvm::SDNode::getOperand(), llvm::MVT::getScalarSizeInBits(), llvm::SDNode::getSimpleValueType(), llvm::SDValue::getValue(), llvm::SelectionDAG::getVTList(), llvm::MVT::is128BitVector(), llvm::MVT::is256BitVector(), llvm::SDNode::isOnlyUserOf(), llvm::ISD::LOAD, llvm::ISD::NON_EXTLOAD, llvm::SelectionDAG::ReplaceAllUsesOfValueWith(), and SDValue().

lowerVECTOR_SHUFFLE_IsReverse()

SDValue lowerVECTOR_SHUFFLE_IsReverse ( const SDLoc & DL, ArrayRef< int > Mask, MVT VT, SDValue V1, SelectionDAG & DAG, const LoongArchSubtarget & Subtarget )

static

Lower VECTOR_SHUFFLE whose result is the reversed source vector.

It is possible to do optimization for VECTOR_SHUFFLE performing vector reverse whose mask likes: <7, 6, 5, 4, 3, 2, 1, 0>

When undef's appear in the mask they are treated as if they were whatever value is necessary in order to fit the above forms.

Definition at line 1844 of file LoongArchISelLowering.cpp.

References DL, llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getConstant(), llvm::LoongArchSubtarget::getGRLenVT(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getUNDEF(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorNumElements(), llvm::SelectionDAG::getVectorShuffle(), llvm::MVT::getVectorVT(), llvm::ShuffleVectorInst::isReverseMask(), and SDValue().

Referenced by lower128BitShuffle(), and lower256BitShuffle().

lowerVECTOR_SHUFFLE_VILVH()

SDValue lowerVECTOR_SHUFFLE_VILVH ( const SDLoc & DL, ArrayRef< int > Mask, MVT VT, SDValue V1, SDValue V2, SelectionDAG & DAG )

static

Lower VECTOR_SHUFFLE into VILVH (if possible).

VILVH interleaves consecutive elements from the left (highest-indexed) half of each vector.

It is possible to lower into VILVH when the mask consists of two of the following forms interleaved: <x, x+1, x+2, ...> <n+x, n+x+1, n+x+2, ...> where n is the number of elements in the vector and x is half n. For example: <x, x, x+1, x+1, x+2, x+2, ...> <x, n+x, x+1, n+x+1, x+2, n+x+2, ...>

When undef's appear in the mask they are treated as if they were whatever value is necessary in order to fit the above forms.

Definition at line 1968 of file LoongArchISelLowering.cpp.

References DL, fitsRegularPattern(), llvm::SelectionDAG::getNode(), and SDValue().

Referenced by lower128BitShuffle().

lowerVECTOR_SHUFFLE_VILVL()

SDValue lowerVECTOR_SHUFFLE_VILVL ( const SDLoc & DL, ArrayRef< int > Mask, MVT VT, SDValue V1, SDValue V2, SelectionDAG & DAG )

static

Lower VECTOR_SHUFFLE into VILVL (if possible).

VILVL interleaves consecutive elements from the right (lowest-indexed) half of each vector.

It is possible to lower into VILVL when the mask consists of two of the following forms interleaved: <0, 1, 2, ...> <n, n+1, n+2, ...> where n is the number of elements in the vector. For example: <0, 0, 1, 1, 2, 2, ...> <0, n, 1, n+1, 2, n+2, ...>

When undef's appear in the mask they are treated as if they were whatever value is necessary in order to fit the above forms.

Definition at line 2011 of file LoongArchISelLowering.cpp.

References DL, fitsRegularPattern(), llvm::SelectionDAG::getNode(), and SDValue().

Referenced by lower128BitShuffle().

lowerVECTOR_SHUFFLE_VPACKEV()

SDValue lowerVECTOR_SHUFFLE_VPACKEV ( const SDLoc & DL, ArrayRef< int > Mask, MVT VT, SDValue V1, SDValue V2, SelectionDAG & DAG )

static

Lower VECTOR_SHUFFLE into VPACKEV (if possible).

VPACKEV interleaves the even elements from each vector.

It is possible to lower into VPACKEV when the mask consists of two of the following forms interleaved: <0, 2, 4, ...> <n, n+2, n+4, ...> where n is the number of elements in the vector. For example: <0, 0, 2, 2, 4, 4, ...> <0, n, 2, n+2, 4, n+4, ...>

When undef's appear in the mask they are treated as if they were whatever value is necessary in order to fit the above forms.

Definition at line 1887 of file LoongArchISelLowering.cpp.

References DL, fitsRegularPattern(), llvm::SelectionDAG::getNode(), and SDValue().

Referenced by lower128BitShuffle(), and lowerVECTOR_SHUFFLE_XVPACKEV().

lowerVECTOR_SHUFFLE_VPACKOD()

SDValue lowerVECTOR_SHUFFLE_VPACKOD ( const SDLoc & DL, ArrayRef< int > Mask, MVT VT, SDValue V1, SDValue V2, SelectionDAG & DAG )

static

Lower VECTOR_SHUFFLE into VPACKOD (if possible).

VPACKOD interleaves the odd elements from each vector.

It is possible to lower into VPACKOD when the mask consists of two of the following forms interleaved: <1, 3, 5, ...> <n+1, n+3, n+5, ...> where n is the number of elements in the vector. For example: <1, 1, 3, 3, 5, 5, ...> <1, n+1, 3, n+3, 5, n+5, ...>

When undef's appear in the mask they are treated as if they were whatever value is necessary in order to fit the above forms.

Definition at line 1927 of file LoongArchISelLowering.cpp.

References DL, fitsRegularPattern(), llvm::SelectionDAG::getNode(), and SDValue().

Referenced by lower128BitShuffle(), and lowerVECTOR_SHUFFLE_XVPACKOD().

lowerVECTOR_SHUFFLE_VPICKEV()

SDValue lowerVECTOR_SHUFFLE_VPICKEV ( const SDLoc & DL, ArrayRef< int > Mask, MVT VT, SDValue V1, SDValue V2, SelectionDAG & DAG )

static

Lower VECTOR_SHUFFLE into VPICKEV (if possible).

VPICKEV copies the even elements of each vector into the result vector.

It is possible to lower into VPICKEV when the mask consists of two of the following forms concatenated: <0, 2, 4, ...> <n, n+2, n+4, ...> where n is the number of elements in the vector. For example: <0, 2, 4, ..., 0, 2, 4, ...> <0, 2, 4, ..., n, n+2, n+4, ...>

When undef's appear in the mask they are treated as if they were whatever value is necessary in order to fit the above forms.

Definition at line 2051 of file LoongArchISelLowering.cpp.

References DL, fitsRegularPattern(), llvm::SelectionDAG::getNode(), and SDValue().

Referenced by lower128BitShuffle().

lowerVECTOR_SHUFFLE_VPICKOD()

SDValue lowerVECTOR_SHUFFLE_VPICKOD ( const SDLoc & DL, ArrayRef< int > Mask, MVT VT, SDValue V1, SDValue V2, SelectionDAG & DAG )

static

Lower VECTOR_SHUFFLE into VPICKOD (if possible).

VPICKOD copies the odd elements of each vector into the result vector.

It is possible to lower into VPICKOD when the mask consists of two of the following forms concatenated: <1, 3, 5, ...> <n+1, n+3, n+5, ...> where n is the number of elements in the vector. For example: <1, 3, 5, ..., 1, 3, 5, ...> <1, 3, 5, ..., n+1, n+3, n+5, ...>

When undef's appear in the mask they are treated as if they were whatever value is necessary in order to fit the above forms.

Definition at line 2093 of file LoongArchISelLowering.cpp.

References DL, fitsRegularPattern(), llvm::SelectionDAG::getNode(), and SDValue().

Referenced by lower128BitShuffle().

lowerVECTOR_SHUFFLE_VREPLVEI()

SDValue lowerVECTOR_SHUFFLE_VREPLVEI ( const SDLoc & DL, ArrayRef< int > Mask, MVT VT, SDValue V1, SelectionDAG & DAG, const LoongArchSubtarget & Subtarget )

static

Lower VECTOR_SHUFFLE into VREPLVEI (if possible).

VREPLVEI performs vector broadcast based on an element specified by an integer immediate, with its mask being similar to: <x, x, x, ...> where x is any valid index.

When undef's appear in the mask they are treated as if they were whatever value is necessary in order to fit the above form.

Definition at line 1738 of file LoongArchISelLowering.cpp.

References assert(), DL, fitsRegularPattern(), llvm::SelectionDAG::getConstant(), llvm::LoongArchSubtarget::getGRLenVT(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getUNDEF(), and SDValue().

Referenced by lower128BitShuffle().

lowerVECTOR_SHUFFLE_VSHUF()

SDValue lowerVECTOR_SHUFFLE_VSHUF ( const SDLoc & DL, ArrayRef< int > Mask, MVT VT, SDValue V1, SDValue V2, SelectionDAG & DAG, const LoongArchSubtarget & Subtarget )

static

Lower VECTOR_SHUFFLE into VSHUF.

This mostly consists of converting the shuffle mask into a BUILD_VECTOR and adding it as an operand to the resulting VSHUF.

Definition at line 2123 of file LoongArchISelLowering.cpp.

References AbstractManglingParser< Derived, Alloc >::Ops, llvm::MVT::changeVectorElementTypeToInteger(), DL, llvm::SelectionDAG::getBuildVector(), llvm::LoongArchSubtarget::getGRLenVT(), llvm::SelectionDAG::getNode(), and llvm::SelectionDAG::getSignedConstant().

Referenced by lower128BitShuffle().

lowerVECTOR_SHUFFLE_VSHUF4I()

SDValue lowerVECTOR_SHUFFLE_VSHUF4I ( const SDLoc & DL, ArrayRef< int > Mask, MVT VT, SDValue V1, SDValue V2, SelectionDAG & DAG, const LoongArchSubtarget & Subtarget )

static

Lower VECTOR_SHUFFLE into VSHUF4I (if possible).

VSHUF4I splits the vector into blocks of four elements, then shuffles these elements according to a <4 x i2> constant (encoded as an integer immediate).

It is therefore possible to lower into VSHUF4I when the mask takes the form: <a, b, c, d, a+4, b+4, c+4, d+4, a+8, b+8, c+8, d+8, ...> When undef's appear they are treated as if they were whatever value is necessary in order to fit the above forms.

For example: %2 = shufflevector <8 x i16> %0, <8 x i16> undef, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4> is lowered to: (VSHUF4I_H $v0, $v1, 27) where the 27 comes from: 3 + (2 << 2) + (1 << 4) + (0 << 6)

Definition at line 1780 of file LoongArchISelLowering.cpp.

References DL, llvm::SelectionDAG::getConstant(), llvm::LoongArchSubtarget::getGRLenVT(), llvm::SelectionDAG::getNode(), and SDValue().

Referenced by lower128BitShuffle(), and lowerVECTOR_SHUFFLE_XVSHUF4I().

lowerVECTOR_SHUFFLE_XVILVH()

SDValue lowerVECTOR_SHUFFLE_XVILVH ( const SDLoc & DL, ArrayRef< int > Mask, MVT VT, SDValue V1, SDValue V2, SelectionDAG & DAG )

static

Lower VECTOR_SHUFFLE into XVILVH (if possible).

Definition at line 2350 of file LoongArchISelLowering.cpp.

References DL, fitsRegularPattern(), llvm::SelectionDAG::getNode(), and SDValue().

Referenced by lower256BitShuffle().

lowerVECTOR_SHUFFLE_XVILVL()

SDValue lowerVECTOR_SHUFFLE_XVILVL ( const SDLoc & DL, ArrayRef< int > Mask, MVT VT, SDValue V1, SDValue V2, SelectionDAG & DAG )

static

Lower VECTOR_SHUFFLE into XVILVL (if possible).

Definition at line 2389 of file LoongArchISelLowering.cpp.

References DL, fitsRegularPattern(), llvm::SelectionDAG::getNode(), and SDValue().

Referenced by lower256BitShuffle().

lowerVECTOR_SHUFFLE_XVINSVE0()

SDValue lowerVECTOR_SHUFFLE_XVINSVE0 ( const SDLoc & DL, ArrayRef< int > Mask, MVT VT, SDValue V1, SDValue V2, SelectionDAG & DAG, const LoongArchSubtarget & Subtarget )

static

Lower VECTOR_SHUFFLE into XVINSVE0 (if possible).

Definition at line 2495 of file LoongArchISelLowering.cpp.

References assert(), llvm::sampleprof::Base, DL, llvm::SelectionDAG::getConstant(), llvm::LoongArchSubtarget::getGRLenVT(), llvm::SelectionDAG::getNode(), llvm::MVT::getVectorNumElements(), and SDValue().

Referenced by lower256BitShuffle().

lowerVECTOR_SHUFFLE_XVPACKEV()

SDValue lowerVECTOR_SHUFFLE_XVPACKEV ( const SDLoc & DL, ArrayRef< int > Mask, MVT VT, SDValue V1, SDValue V2, SelectionDAG & DAG )

static

Lower VECTOR_SHUFFLE into XVPACKEV (if possible).

Definition at line 2336 of file LoongArchISelLowering.cpp.

References DL, and lowerVECTOR_SHUFFLE_VPACKEV().

Referenced by lower256BitShuffle().

lowerVECTOR_SHUFFLE_XVPACKOD()

SDValue lowerVECTOR_SHUFFLE_XVPACKOD ( const SDLoc & DL, ArrayRef< int > Mask, MVT VT, SDValue V1, SDValue V2, SelectionDAG & DAG )

static

Lower VECTOR_SHUFFLE into XVPACKOD (if possible).

Definition at line 2343 of file LoongArchISelLowering.cpp.

References DL, and lowerVECTOR_SHUFFLE_VPACKOD().

Referenced by lower256BitShuffle().

lowerVECTOR_SHUFFLE_XVPERM()

SDValue lowerVECTOR_SHUFFLE_XVPERM ( const SDLoc & DL, ArrayRef< int > Mask, MVT VT, SDValue V1, SelectionDAG & DAG, const LoongArchSubtarget & Subtarget )

static

Lower VECTOR_SHUFFLE into XVPERM (if possible).

Definition at line 2293 of file LoongArchISelLowering.cpp.

References DL, llvm::SelectionDAG::getBuildVector(), llvm::SelectionDAG::getConstant(), llvm::LoongArchSubtarget::getGRLenVT(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getUNDEF(), llvm::MVT::getVectorNumElements(), inRange(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), and SDValue().

Referenced by lower256BitShuffle().

lowerVECTOR_SHUFFLE_XVPERMI()

SDValue lowerVECTOR_SHUFFLE_XVPERMI ( const SDLoc & DL, ArrayRef< int > Mask, MVT VT, SDValue V1, SelectionDAG & DAG, const LoongArchSubtarget & Subtarget )

static

Lower VECTOR_SHUFFLE into XVPERMI (if possible).

Definition at line 2274 of file LoongArchISelLowering.cpp.

References DL, llvm::SelectionDAG::getConstant(), llvm::LoongArchSubtarget::getGRLenVT(), llvm::SelectionDAG::getNode(), and SDValue().

Referenced by lower256BitShuffle().

lowerVECTOR_SHUFFLE_XVPICKEV()

SDValue lowerVECTOR_SHUFFLE_XVPICKEV ( const SDLoc & DL, ArrayRef< int > Mask, MVT VT, SDValue V1, SDValue V2, SelectionDAG & DAG )

static

Lower VECTOR_SHUFFLE into XVPICKEV (if possible).

Definition at line 2423 of file LoongArchISelLowering.cpp.

References DL, fitsRegularPattern(), llvm::SelectionDAG::getNode(), and SDValue().

Referenced by lower256BitShuffle().

lowerVECTOR_SHUFFLE_XVPICKOD()

SDValue lowerVECTOR_SHUFFLE_XVPICKOD ( const SDLoc & DL, ArrayRef< int > Mask, MVT VT, SDValue V1, SDValue V2, SelectionDAG & DAG )

static

Lower VECTOR_SHUFFLE into XVPICKOD (if possible).

Definition at line 2458 of file LoongArchISelLowering.cpp.

References DL, fitsRegularPattern(), llvm::SelectionDAG::getNode(), and SDValue().

Referenced by lower256BitShuffle().

lowerVECTOR_SHUFFLE_XVREPLVEI()

SDValue lowerVECTOR_SHUFFLE_XVREPLVEI ( const SDLoc & DL, ArrayRef< int > Mask, MVT VT, SDValue V1, SelectionDAG & DAG, const LoongArchSubtarget & Subtarget )

static

Lower VECTOR_SHUFFLE into XVREPLVEI (if possible).

It is a XVREPLVEI when the mask is: <x, x, x, ..., x+n, x+n, x+n, ...> where the number of x is equal to n and n is half the length of vector.

When undef's appear in the mask they are treated as if they were whatever value is necessary in order to fit the above form.

Definition at line 2228 of file LoongArchISelLowering.cpp.

References assert(), DL, fitsRegularPattern(), llvm::SelectionDAG::getConstant(), llvm::LoongArchSubtarget::getGRLenVT(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getUNDEF(), and SDValue().

Referenced by lower256BitShuffle().

lowerVECTOR_SHUFFLE_XVSHUF()

SDValue lowerVECTOR_SHUFFLE_XVSHUF ( const SDLoc & DL, ArrayRef< int > Mask, MVT VT, SDValue V1, SDValue V2, SelectionDAG & DAG )

static

Lower VECTOR_SHUFFLE into XVSHUF (if possible).

Definition at line 2541 of file LoongArchISelLowering.cpp.

References assert(), llvm::MVT::changeVectorElementTypeToInteger(), DL, llvm::SelectionDAG::getBuildVector(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getTargetConstant(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), SDValue(), and llvm::SmallVectorTemplateCommon< T, typename >::size().

Referenced by lower256BitShuffle().

lowerVECTOR_SHUFFLE_XVSHUF4I()

SDValue lowerVECTOR_SHUFFLE_XVSHUF4I ( const SDLoc & DL, ArrayRef< int > Mask, MVT VT, SDValue V1, SDValue V2, SelectionDAG & DAG, const LoongArchSubtarget & Subtarget )

static

Lower VECTOR_SHUFFLE into XVSHUF4I (if possible).

Definition at line 2262 of file LoongArchISelLowering.cpp.

References DL, lowerVECTOR_SHUFFLE_VSHUF4I(), and SDValue().

Referenced by lower256BitShuffle().

lowerVECTOR_SHUFFLEAsByteRotate()

SDValue lowerVECTOR_SHUFFLEAsByteRotate ( const SDLoc & DL, ArrayRef< int > Mask, MVT VT, SDValue V1, SDValue V2, SelectionDAG & DAG, const LoongArchSubtarget & Subtarget )

static

Lower VECTOR_SHUFFLE as byte rotate (if possible).

For example: shuffle = shufflevector <2 x i64> a, <2 x i64> b, <2 x i32> <i32 3, i32 0> is lowered to: (VBSRL_V $v1, $v1, 8) (VBSLL_V $v0, $v0, 8) (VOR_V $v0, $V0, $v1)

Definition at line 1612 of file LoongArchISelLowering.cpp.

References DL, llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getConstant(), llvm::LoongArchSubtarget::getGRLenVT(), llvm::SelectionDAG::getNode(), llvm::MVT::getSizeInBits(), llvm::MVT::getVectorVT(), llvm::Hi, llvm::Lo, matchShuffleAsByteRotate(), llvm::ISD::OR, and SDValue().

Referenced by lower128BitShuffle(), and lower256BitShuffle().

lowerVECTOR_SHUFFLEAsLanePermuteAndShuffle()

SDValue lowerVECTOR_SHUFFLEAsLanePermuteAndShuffle ( const SDLoc & DL, ArrayRef< int > Mask, MVT VT, SDValue V1, SDValue V2, SelectionDAG & DAG )

static

Lower VECTOR_SHUFFLE as lane permute and then shuffle (if possible).

Only for 256-bit vector.

For example: %2 = shufflevector <4 x i64> %0, <4 x i64> posion, <4 x i64> <i32 0, i32 3, i32 2, i32 0> is lowerded to: (XVPERMI $xr2, $xr0, 78) (XVSHUF $xr1, $xr2, $xr0) (XVORI $xr0, $xr1, 0)

Definition at line 2722 of file LoongArchISelLowering.cpp.

References assert(), llvm::SmallVectorImpl< T >::assign(), DL, llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getUNDEF(), llvm::SelectionDAG::getVectorShuffle(), llvm::MVT::is256BitVector(), SDValue(), and Size.

Referenced by lower256BitShuffle().

lowerVECTOR_SHUFFLEAsShift()

SDValue lowerVECTOR_SHUFFLEAsShift ( const SDLoc & DL, ArrayRef< int > Mask, MVT VT, SDValue V1, SDValue V2, SelectionDAG & DAG, const LoongArchSubtarget & Subtarget, const APInt & Zeroable )

static

Lower VECTOR_SHUFFLE as shift (if possible).

For example: %2 = shufflevector <4 x i32> %0, <4 x i32> zeroinitializer, <4 x i32> <i32 4, i32 0, i32 1, i32 2> is lowered to: (VBSLL_V $v0, $v0, 4)

%2 = shufflevector <4 x i32> %0, <4 x i32> zeroinitializer, <4 x i32> <i32 4, i32 0, i32 4, i32 2> is lowered to: (VSLLI_D $v0, $v0, 32)

Definition at line 1412 of file LoongArchISelLowering.cpp.

References assert(), DL, llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getConstant(), llvm::LoongArchSubtarget::getGRLenVT(), llvm::SelectionDAG::getNode(), llvm::MVT::getScalarSizeInBits(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::MVT::getVectorNumElements(), llvm::TargetLoweringBase::isTypeLegal(), matchShuffleAsShift(), SDValue(), and Size.

Referenced by lower128BitShuffle(), and lower256BitShuffle().

lowerVECTOR_SHUFFLEAsZeroOrAnyExtend()

SDValue lowerVECTOR_SHUFFLEAsZeroOrAnyExtend ( const SDLoc & DL, ArrayRef< int > Mask, MVT VT, SDValue V1, SDValue V2, SelectionDAG & DAG, const APInt & Zeroable )

static

Lower VECTOR_SHUFFLE as ZERO_EXTEND Or ANY_EXTEND (if possible).

For example: %2 = shufflevector <4 x i32> %0, <4 x i32> zeroinitializer, <4 x i32> <i32 0, i32 4, i32 1, i32 4> %3 = bitcast <4 x i32> %2 to <2 x i64> is lowered to: (VREPLI $v1, 0) (VILVL $v0, $v1, $v0)

Definition at line 1645 of file LoongArchISelLowering.cpp.

References DL, llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getFreeze(), llvm::MVT::getIntegerVT(), llvm::SelectionDAG::getNode(), llvm::MVT::getScalarSizeInBits(), llvm::MVT::getSizeInBits(), llvm::MVT::getVectorNumElements(), llvm::MVT::getVectorVT(), llvm::APInt::isAllOnes(), llvm::Lower, llvm::Offset, and SDValue().

Referenced by lower128BitShuffle().

lowerVectorBitClear()

SDValue lowerVectorBitClear ( SDNode * Node, SelectionDAG & DAG )

static

Definition at line 6158 of file LoongArchISelLowering.cpp.

References llvm::ISD::AND, DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getNOT(), llvm::ISD::SHL, and truncateVecElts().

Referenced by performINTRINSIC_WO_CHAINCombine().

lowerVectorBitClearImm()

template<unsigned N>

SDValue lowerVectorBitClearImm ( SDNode * Node, SelectionDAG & DAG )

static

Definition at line 6170 of file LoongArchISelLowering.cpp.

References llvm::ISD::AND, llvm::cast(), DL, llvm::LLVMContext::emitError(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getNode(), llvm::EVT::getScalarSizeInBits(), llvm::isUInt(), and llvm::ISD::UNDEF.

Referenced by performINTRINSIC_WO_CHAINCombine().

lowerVectorBitRevImm()

template<unsigned N>

SDValue lowerVectorBitRevImm ( SDNode * Node, SelectionDAG & DAG )

static

Definition at line 6205 of file LoongArchISelLowering.cpp.

References llvm::cast(), DL, llvm::LLVMContext::emitError(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getNode(), llvm::EVT::getScalarSizeInBits(), llvm::isUInt(), llvm::ISD::UNDEF, and llvm::ISD::XOR.

Referenced by performINTRINSIC_WO_CHAINCombine().

lowerVectorBitSetImm()

template<unsigned N>

SDValue lowerVectorBitSetImm ( SDNode * Node, SelectionDAG & DAG )

static

Definition at line 6188 of file LoongArchISelLowering.cpp.

References llvm::cast(), DL, llvm::LLVMContext::emitError(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getNode(), llvm::EVT::getScalarSizeInBits(), llvm::isUInt(), llvm::ISD::OR, and llvm::ISD::UNDEF.

Referenced by performINTRINSIC_WO_CHAINCombine().

lowerVectorPickVE2GR()

template<unsigned W>

SDValue lowerVectorPickVE2GR ( SDNode * N, SelectionDAG & DAG, unsigned ResOp )

static

Definition at line 6222 of file LoongArchISelLowering.cpp.

References DL, llvm::LLVMContext::emitError(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueType(), llvm::SelectionDAG::getValueType(), llvm::EVT::getVectorElementType(), llvm::isUInt(), and N.

Referenced by performINTRINSIC_WO_CHAINCombine().

lowerVectorSplatImm()

template<unsigned N>

SDValue lowerVectorSplatImm ( SDNode * Node, unsigned ImmOp, SelectionDAG & DAG, bool IsSigned = false )

static

Definition at line 6131 of file LoongArchISelLowering.cpp.

References llvm::cast(), DL, llvm::LLVMContext::emitError(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getNode(), llvm::EVT::getScalarType(), llvm::EVT::getSizeInBits(), llvm::isInt(), llvm::isUInt(), and llvm::ISD::UNDEF.

Referenced by performINTRINSIC_WO_CHAINCombine().

matchSetCC()

std::optional< bool > matchSetCC ( SDValue LHS, SDValue RHS, ISD::CondCode CC, SDValue Val )

static

Definition at line 892 of file LoongArchISelLowering.cpp.

References assert(), llvm::cast(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::ISD::getSetCCInverse(), llvm::ISD::getSetCCSwappedOperands(), llvm::SDValue::getValueType(), LHS, RHS, and llvm::ISD::SETCC.

Referenced by combineSelectToBinOp(), and lowerSelectToBinOp().

matchShuffleAsByteRotate()

int matchShuffleAsByteRotate ( MVT VT, SDValue & V1, SDValue & V2, ArrayRef< int > Mask )

static

Attempts to match vector shuffle as byte rotation.

Definition at line 1537 of file LoongArchISelLowering.cpp.

References assert(), llvm::Hi, isRepeatedShuffleMask(), llvm::Lo, and llvm::SmallVectorTemplateCommon< T, typename >::size().

Referenced by lowerShuffleAsByteRotate(), lowerVECTOR_SHUFFLEAsByteRotate(), and matchBinaryPermuteShuffle().

matchShuffleAsShift()

int matchShuffleAsShift ( MVT & ShiftVT, unsigned & Opcode, unsigned ScalarSizeInBits, ArrayRef< int > Mask, int MaskOffset, const APInt & Zeroable )

static

Attempts to match a shuffle mask against the VBSLL, VBSRL, VSLLI and VSRLI instruction.

Definition at line 1337 of file LoongArchISelLowering.cpp.

References llvm::MVT::getIntegerVT(), llvm::MVT::getVectorVT(), isSequentialOrUndefInRange(), llvm::Left, llvm::Low, and Size.

Referenced by lowerShuffleAsShift(), lowerVECTOR_SHUFFLEAsShift(), and matchUnaryPermuteShuffle().

performANDCombine()

SDValue performANDCombine ( SDNode * N, SelectionDAG & DAG, TargetLowering::DAGCombinerInfo & DCI, const LoongArchSubtarget & Subtarget )

static

Definition at line 5209 of file LoongArchISelLowering.cpp.

References combineAndNotIntoVANDN(), DL, llvm::dyn_cast(), llvm::SelectionDAG::getConstant(), llvm::LoongArchSubtarget::getGRLenVT(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::ConstantSDNode::getSExtValue(), llvm::ConstantSDNode::getZExtValue(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalizeOps(), llvm::isShiftedMask_64(), N, SDValue(), llvm::ISD::SHL, llvm::ISD::SRA, llvm::ISD::SRL, and llvm::SDNode::use_size().

performBITCASTCombine()

SDValue performBITCASTCombine ( SDNode * N, SelectionDAG & DAG, TargetLowering::DAGCombinerInfo & DCI, const LoongArchSubtarget & Subtarget )

static

Definition at line 5477 of file LoongArchISelLowering.cpp.

References checkBitcastSrcVectorSize(), DL, llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getContext(), llvm::LoongArchSubtarget::getGRLenVT(), llvm::EVT::getIntegerVT(), llvm::SelectionDAG::getNode(), llvm::EVT::getScalarType(), llvm::SelectionDAG::getShiftAmountConstant(), llvm::EVT::getSimpleVT(), llvm::EVT::getSizeInBits(), llvm::EVT::getVectorNumElements(), llvm::SelectionDAG::getZExtOrTrunc(), llvm::Hi, llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalizeOps(), llvm::EVT::isSimple(), llvm::Lo, N, Opc, llvm::ISD::OR, performSETCC_BITCASTCombine(), SDValue(), llvm::ISD::SETCC, llvm::ISD::SHL, llvm::ISD::SIGN_EXTEND, signExtendBitcastSrcVector(), llvm::MVT::SimpleTy, llvm::SelectionDAG::SplitVector(), and T.

Referenced by llvm::LoongArchTargetLowering::PerformDAGCombine().

performBITREV_WCombine()

SDValue performBITREV_WCombine ( SDNode * N, SelectionDAG & DAG, TargetLowering::DAGCombinerInfo & DCI, const LoongArchSubtarget & Subtarget )

static

Definition at line 5960 of file LoongArchISelLowering.cpp.

References llvm::SelectionDAG::getNode(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalizeOps(), N, and SDValue().

Referenced by llvm::LoongArchTargetLowering::PerformDAGCombine().

performBR_CCCombine()

SDValue performBR_CCCombine ( SDNode * N, SelectionDAG & DAG, TargetLowering::DAGCombinerInfo & DCI, const LoongArchSubtarget & Subtarget )

static

Definition at line 6047 of file LoongArchISelLowering.cpp.

References combine_CC(), DL, llvm::SelectionDAG::getNode(), LHS, N, RHS, and SDValue().

Referenced by llvm::LoongArchTargetLowering::PerformDAGCombine().

performEXTRACT_VECTOR_ELTCombine()

SDValue performEXTRACT_VECTOR_ELTCombine ( SDNode * N, SelectionDAG & DAG, TargetLowering::DAGCombinerInfo & DCI, const LoongArchSubtarget & Subtarget )

static

Definition at line 6871 of file LoongArchISelLowering.cpp.

References llvm::ISD::ANY_EXTEND, DL, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getValueType(), llvm::EVT::is256BitVector(), llvm::isa(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalize(), N, SDValue(), llvm::ISD::SIGN_EXTEND, llvm::ISD::TRUNCATE, and llvm::ISD::ZERO_EXTEND.

Referenced by llvm::LoongArchTargetLowering::PerformDAGCombine().

performINTRINSIC_WO_CHAINCombine()

SDValue performINTRINSIC_WO_CHAINCombine ( SDNode * N, SelectionDAG & DAG, TargetLowering::DAGCombinerInfo & DCI, const LoongArchSubtarget & Subtarget )

static

Definition at line 6238 of file LoongArchISelLowering.cpp.

References llvm::ISD::ADD, llvm::ISD::AND, llvm::ISD::ANY_EXTEND, llvm::ISD::CONCAT_VECTORS, llvm::ISD::CTLZ, llvm::ISD::CTPOP, DL, llvm::ISD::FADD, llvm::ISD::FDIV, llvm::ISD::FMA, llvm::ISD::FMUL, llvm::ISD::FSUB, llvm::SelectionDAG::getConstant(), llvm::LoongArchSubtarget::getGRLenVT(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getNOT(), llvm::SDNode::getValueType(), llvm::ISD::INSERT_VECTOR_ELT, llvm::LoongArchSubtarget::is64Bit(), legalizeIntrinsicImmArg(), lowerVectorBitClear(), lowerVectorBitClearImm(), lowerVectorBitRevImm(), lowerVectorBitSetImm(), lowerVectorPickVE2GR(), lowerVectorSplatImm(), llvm::ISD::MUL, N, llvm::ISD::OR, llvm::ISD::SDIV, SDValue(), llvm::ISD::SHL, llvm::ISD::SMAX, llvm::ISD::SMIN, llvm::ISD::SRA, llvm::ISD::SREM, llvm::ISD::SRL, llvm::ISD::SUB, truncateVecElts(), llvm::ISD::UDIV, llvm::ISD::UMAX, llvm::ISD::UMIN, llvm::ISD::UREM, and llvm::ISD::XOR.

Referenced by llvm::LoongArchTargetLowering::PerformDAGCombine().

performMOVFR2GR_SCombine()

SDValue performMOVFR2GR_SCombine ( SDNode * N, SelectionDAG & DAG, TargetLowering::DAGCombinerInfo & DCI, const LoongArchSubtarget & Subtarget )

static

Definition at line 6809 of file LoongArchISelLowering.cpp.

References assert(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getValueType(), N, and SDValue().

Referenced by llvm::LoongArchTargetLowering::PerformDAGCombine().

performMOVGR2FR_WCombine()

SDValue performMOVGR2FR_WCombine ( SDNode * N, SelectionDAG & DAG, TargetLowering::DAGCombinerInfo & DCI, const LoongArchSubtarget & Subtarget )

static

Definition at line 6797 of file LoongArchISelLowering.cpp.

References llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), N, and SDValue().

Referenced by llvm::LoongArchTargetLowering::PerformDAGCombine().

performORCombine()

SDValue performORCombine ( SDNode * N, SelectionDAG & DAG, TargetLowering::DAGCombinerInfo & DCI, const LoongArchSubtarget & Subtarget )

static

Definition at line 5572 of file LoongArchISelLowering.cpp.

References llvm::ISD::AND, llvm::SelectionDAG::computeKnownBits(), llvm::dbgs(), DL, llvm::dyn_cast(), llvm::SelectionDAG::getConstant(), llvm::LoongArchSubtarget::getGRLenVT(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::ConstantSDNode::getSExtValue(), llvm::SelectionDAG::getSignedConstant(), llvm::ConstantSDNode::getZExtValue(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalizeOps(), llvm::isShiftedMask_64(), llvm::APInt::isSubsetOf(), LLVM_DEBUG, N, SDValue(), llvm::ISD::SHL, llvm::ISD::SRL, std::swap(), and llvm::KnownBits::Zero.

performSELECT_CCCombine()

SDValue performSELECT_CCCombine ( SDNode * N, SelectionDAG & DAG, TargetLowering::DAGCombinerInfo & DCI, const LoongArchSubtarget & Subtarget )

static

Definition at line 6062 of file LoongArchISelLowering.cpp.

References llvm::ISD::ADD, llvm::ISD::AND, llvm::cast(), combine_CC(), DL, llvm::SelectionDAG::getConstant(), llvm::LoongArchSubtarget::getGRLen(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getSignedConstant(), llvm::isa(), llvm::isInt(), llvm::isNullConstant(), LHS, N, RHS, SDValue(), llvm::ISD::SETGE, llvm::ISD::SETLT, llvm::ISD::SRA, and std::swap().

Referenced by llvm::LoongArchTargetLowering::PerformDAGCombine().

performSETCC_BITCASTCombine()

SDValue performSETCC_BITCASTCombine ( SDNode * N, SelectionDAG & DAG, TargetLowering::DAGCombinerInfo & DCI, const LoongArchSubtarget & Subtarget )

static

Definition at line 5404 of file LoongArchISelLowering.cpp.

References llvm::cast(), llvm::ISD::DELETED_NODE, DL, llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getContext(), llvm::LoongArchSubtarget::getGRLenVT(), llvm::EVT::getIntegerVT(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOperand(), llvm::EVT::getSizeInBits(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::SelectionDAG::getZExtOrTrunc(), llvm::ISD::isBuildVectorAllOnes(), llvm::ISD::isBuildVectorAllZeros(), N, Opc, SDValue(), llvm::ISD::SETCC, llvm::ISD::SETEQ, llvm::ISD::SETGE, llvm::ISD::SETGT, llvm::ISD::SETLE, llvm::ISD::SETLT, llvm::ISD::SETNE, and T.

Referenced by performBITCASTCombine().

performSETCCCombine()

SDValue performSETCCCombine ( SDNode * N, SelectionDAG & DAG, TargetLowering::DAGCombinerInfo & DCI, const LoongArchSubtarget & Subtarget )

static

Definition at line 5891 of file LoongArchISelLowering.cpp.

References llvm::ISD::AND, llvm::cast(), checkValueWidth(), llvm::dyn_cast(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOperand(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getSetCC(), llvm::SDNode::getValueType(), llvm::ConstantSDNode::isAllOnes(), llvm::ConstantSDNode::isZero(), N, llvm::SelectionDAG::ReplaceAllUsesWith(), SDValue(), llvm::ISD::SETEQ, llvm::ISD::SETNE, llvm::ISD::SEXTLOAD, llvm::ISD::TRUNCATE, llvm::ISD::XOR, llvm::ISD::ZERO_EXTEND, and llvm::ISD::ZEXTLOAD.

performSINT_TO_FPCombine()

SDValue performSINT_TO_FPCombine ( SDNode * N, SelectionDAG & DAG, TargetLowering::DAGCombinerInfo & DCI, const LoongArchSubtarget & Subtarget )

static

Definition at line 6969 of file LoongArchISelLowering.cpp.

References llvm::cast(), DL, llvm::MemSDNode::getAlign(), llvm::LoadSDNode::getBasePtr(), llvm::MemSDNode::getChain(), llvm::MachineMemOperand::getFlags(), llvm::SelectionDAG::getLoad(), llvm::MemSDNode::getMemOperand(), llvm::SelectionDAG::getNode(), llvm::MemSDNode::getPointerInfo(), llvm::EVT::getSizeInBits(), llvm::ISD::isNormalLoad(), N, llvm::SelectionDAG::ReplaceAllUsesOfValueWith(), and SDValue().

Referenced by llvm::LoongArchTargetLowering::PerformDAGCombine().

performSPLIT_PAIR_F64Combine()

SDValue performSPLIT_PAIR_F64Combine ( SDNode * N, SelectionDAG & DAG, TargetLowering::DAGCombinerInfo & DCI, const LoongArchSubtarget & Subtarget )

static

Definition at line 6840 of file LoongArchISelLowering.cpp.

References llvm::CallingConv::C, llvm::TargetLowering::DAGCombinerInfo::CombineTo(), DL, llvm::dyn_cast(), llvm::SelectionDAG::getConstant(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getUNDEF(), llvm::Hi, llvm::SDNode::isUndef(), llvm::Lo, N, and SDValue().

Referenced by llvm::LoongArchTargetLowering::PerformDAGCombine().

performSRLCombine()

SDValue performSRLCombine ( SDNode * N, SelectionDAG & DAG, TargetLowering::DAGCombinerInfo & DCI, const LoongArchSubtarget & Subtarget )

static

Definition at line 5302 of file LoongArchISelLowering.cpp.

References llvm::ISD::AND, DL, llvm::dyn_cast(), llvm::SelectionDAG::getConstant(), llvm::LoongArchSubtarget::getGRLenVT(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOperand(), llvm::SDValue::getOperand(), llvm::ConstantSDNode::getZExtValue(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalizeOps(), llvm::isShiftedMask_64(), N, and SDValue().

Referenced by llvm::LoongArchTargetLowering::PerformDAGCombine(), and llvm::MipsSETargetLowering::PerformDAGCombine().

performVANDNCombine()

SDValue performVANDNCombine ( SDNode * N, SelectionDAG & DAG, TargetLowering::DAGCombinerInfo & DCI, const LoongArchSubtarget & Subtarget )

static

Do target-specific dag combines on LoongArchISD::VANDN nodes.

Definition at line 6907 of file LoongArchISelLowering.cpp.

References llvm::ISD::AND, llvm::ISD::BUILD_VECTOR, llvm::CallingConv::C, llvm::cast(), DL, llvm::dyn_cast(), llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getConstant(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getNOT(), llvm::SDValue::getOpcode(), llvm::SelectionDAG::getSplat(), llvm::SelectionDAG::getTargetConstant(), llvm::SDNode::hasOneUse(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalizeOps(), llvm::ISD::isBuildVectorAllOnes(), llvm::ISD::isBuildVectorAllZeros(), isNOT(), llvm::SDNode::isOnlyUserOf(), llvm::SDValue::isUndef(), N, llvm::ISD::OR, and SDValue().

Referenced by llvm::LoongArchTargetLowering::PerformDAGCombine().

performVMSKLTZCombine()

SDValue performVMSKLTZCombine ( SDNode * N, SelectionDAG & DAG, TargetLowering::DAGCombinerInfo & DCI, const LoongArchSubtarget & Subtarget )

static

Definition at line 6824 of file LoongArchISelLowering.cpp.

References llvm::APInt::getAllOnes(), llvm::MVT::getScalarSizeInBits(), llvm::SelectionDAG::getTargetLoweringInfo(), N, SDValue(), and llvm::TargetLowering::SimplifyDemandedBits().

Referenced by llvm::LoongArchTargetLowering::PerformDAGCombine().

replaceCMP_XCHG_128Results()

void replaceCMP_XCHG_128Results ( SDNode * N, SmallVectorImpl< SDValue > & Results, SelectionDAG & DAG )

static

Definition at line 4780 of file LoongArchISelLowering.cpp.

References AbstractManglingParser< Derived, Alloc >::Ops, llvm::Acquire, llvm::AcquireRelease, assert(), llvm::ISD::BUILD_PAIR, llvm::cast(), DL, llvm::SelectionDAG::getMachineNode(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getVTList(), llvm_unreachable, llvm::Monotonic, N, llvm::Release, Results, SDValue(), llvm::SequentiallyConsistent, llvm::SelectionDAG::setNodeMemRefs(), and llvm::SelectionDAG::SplitScalar().

Referenced by llvm::LoongArchTargetLowering::ReplaceNodeResults().

replaceINTRINSIC_WO_CHAINResults()

void replaceINTRINSIC_WO_CHAINResults ( SDNode * N, SmallVectorImpl< SDValue > & Results, SelectionDAG & DAG, const LoongArchSubtarget & Subtarget )

static

Definition at line 4713 of file LoongArchISelLowering.cpp.

References llvm_unreachable, N, replaceVecCondBranchResults(), replaceVPICKVE2GRResults(), and Results.

Referenced by llvm::LoongArchTargetLowering::ReplaceNodeResults().

replaceVecCondBranchResults()

void replaceVecCondBranchResults ( SDNode * N, SmallVectorImpl< SDValue > & Results, SelectionDAG & DAG, const LoongArchSubtarget & Subtarget, unsigned ResOp )

static

Definition at line 4699 of file LoongArchISelLowering.cpp.

References DL, llvm::LoongArchSubtarget::getGRLenVT(), llvm::SelectionDAG::getNode(), llvm::SDValue::getValue(), N, Results, and llvm::ISD::TRUNCATE.

Referenced by replaceINTRINSIC_WO_CHAINResults().

replaceVPICKVE2GRResults()

template<unsigned N>

void replaceVPICKVE2GRResults ( SDNode * Node, SmallVectorImpl< SDValue > & Results, SelectionDAG & DAG, const LoongArchSubtarget & Subtarget, unsigned ResOp )

static

Definition at line 4678 of file LoongArchISelLowering.cpp.

References DL, emitErrorAndReplaceIntrinsicResults(), llvm::SelectionDAG::getConstant(), llvm::LoongArchSubtarget::getGRLenVT(), llvm::SelectionDAG::getNode(), llvm::SDValue::getValue(), llvm::SDValue::getValueType(), llvm::SelectionDAG::getValueType(), llvm::EVT::getVectorElementType(), llvm::isUInt(), Results, and llvm::ISD::TRUNCATE.

Referenced by replaceINTRINSIC_WO_CHAINResults().

signExtendBitcastSrcVector()

SDValue signExtendBitcastSrcVector ( SelectionDAG & DAG, EVT SExtVT, SDValue Src, const SDLoc & DL )

static

Definition at line 5378 of file LoongArchISelLowering.cpp.

References llvm::ISD::AND, llvm::ISD::BUILD_VECTOR, DL, llvm::ISD::FREEZE, llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getSelect(), llvm_unreachable, llvm::ISD::OR, llvm::ISD::SELECT, llvm::ISD::SETCC, llvm::ISD::SIGN_EXTEND, signExtendBitcastSrcVector(), llvm::ISD::TRUNCATE, llvm::ISD::VSELECT, and llvm::ISD::XOR.

Referenced by combineBitcastvxi1(), performBITCASTCombine(), signExtendBitcastSrcVector(), and signExtendBitcastSrcVector().

STATISTIC()

STATISTIC	(	NumTailCalls	,
		"Number of tail calls"	)

translateSetCCForBranch()

void translateSetCCForBranch ( const SDLoc & DL, SDValue & LHS, SDValue & RHS, ISD::CondCode & CC, SelectionDAG & DAG )

static

Definition at line 1048 of file LoongArchISelLowering.cpp.

References llvm::ISD::AND, llvm::bit_width(), llvm::CallingConv::C, DL, llvm::dyn_cast(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::ISD::getSetCCSwappedOperands(), llvm::isa(), llvm::isInt(), llvm::isMask_64(), llvm::isNullConstant(), llvm::isPowerOf2_64(), LHS, llvm::Log2_64(), RHS, llvm::ISD::SETEQ, llvm::ISD::SETGE, llvm::ISD::SETGT, llvm::ISD::SETLE, llvm::ISD::SETLT, llvm::ISD::SETUGT, llvm::ISD::SETULE, llvm::ISD::SHL, and std::swap().

Referenced by combine_CC(), and combine_CC().

truncateVecElts()

SDValue truncateVecElts ( SDNode * Node, SelectionDAG & DAG )

static

Definition at line 6150 of file LoongArchISelLowering.cpp.

References llvm::ISD::AND, DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), and llvm::SDValue::getScalarValueSizeInBits().

Referenced by lowerMSABitClear(), lowerVectorBitClear(), and performINTRINSIC_WO_CHAINCombine().

unpackF64OnLA32DSoftABI()

SDValue unpackF64OnLA32DSoftABI ( SelectionDAG & DAG, SDValue Chain, const CCValAssign & VA, const CCValAssign & HiVA, const SDLoc & DL )

static

Definition at line 8115 of file LoongArchISelLowering.cpp.

References assert(), llvm::MachineFrameInfo::CreateFixedObject(), DL, llvm::SelectionDAG::getCopyFromReg(), llvm::MachinePointerInfo::getFixedStack(), llvm::SelectionDAG::getFrameIndex(), llvm::MachineFunction::getFrameInfo(), llvm::SelectionDAG::getLoad(), llvm::CCValAssign::getLocMemOffset(), llvm::CCValAssign::getLocReg(), llvm::CCValAssign::getLocVT(), llvm::SelectionDAG::getMachineFunction(), llvm::SelectionDAG::getNode(), llvm::MachineFunction::getRegInfo(), llvm::CCValAssign::getValVT(), llvm::Hi, llvm::CCValAssign::isMemLoc(), llvm::CCValAssign::isRegLoc(), and llvm::Lo.

Referenced by llvm::LoongArchTargetLowering::LowerFormalArguments().

unpackFromMemLoc()

SDValue unpackFromMemLoc ( SelectionDAG & DAG, SDValue Chain, const CCValAssign & VA, const SDLoc & DL )

static

Definition at line 8090 of file LoongArchISelLowering.cpp.

References llvm::CCValAssign::BCvt, llvm::MachineFrameInfo::CreateFixedObject(), DL, llvm::CCValAssign::Full, llvm::SelectionDAG::getDataLayout(), llvm::SelectionDAG::getExtLoad(), llvm::MachinePointerInfo::getFixedStack(), llvm::SelectionDAG::getFrameIndex(), llvm::MachineFunction::getFrameInfo(), llvm::MVT::getIntegerVT(), llvm::CCValAssign::getLocInfo(), llvm::CCValAssign::getLocMemOffset(), llvm::CCValAssign::getLocVT(), llvm::SelectionDAG::getMachineFunction(), llvm::DataLayout::getPointerSizeInBits(), llvm::EVT::getStoreSize(), llvm::CCValAssign::getValVT(), llvm::CCValAssign::Indirect, llvm_unreachable, and llvm::ISD::NON_EXTLOAD.

unpackFromRegLoc()

SDValue unpackFromRegLoc ( SelectionDAG & DAG, SDValue Chain, const CCValAssign & VA, const SDLoc & DL, const ISD::InputArg & In, const LoongArchTargetLowering & TLI )

static

Definition at line 8057 of file LoongArchISelLowering.cpp.

References llvm::LoongArchMachineFunctionInfo::addSExt32Register(), llvm::BitWidth, convertLocVTToValVT(), DL, llvm::Function::getArg(), llvm::SelectionDAG::getCopyFromReg(), llvm::MachineFunction::getFunction(), llvm::MachineFunction::getInfo(), llvm::Type::getIntegerBitWidth(), llvm::CCValAssign::getLocReg(), llvm::CCValAssign::getLocVT(), llvm::SelectionDAG::getMachineFunction(), llvm::TargetLoweringBase::getRegClassFor(), llvm::MachineFunction::getRegInfo(), llvm::EVT::getSimpleVT(), llvm::Value::getType(), and llvm::Type::isIntegerTy().

widenShuffleMask()

SDValue widenShuffleMask ( const SDLoc & DL, ArrayRef< int > Mask, MVT VT, SDValue V1, SDValue V2, SelectionDAG & DAG )

static

Definition at line 1307 of file LoongArchISelLowering.cpp.

References DL, llvm::SelectionDAG::getBitcast(), llvm::MVT::getFloatingPointVT(), llvm::MVT::getIntegerVT(), llvm::MVT::getScalarSizeInBits(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::MVT::getVectorNumElements(), llvm::SelectionDAG::getVectorShuffle(), llvm::MVT::getVectorVT(), llvm::MVT::isFloatingPoint(), llvm::TargetLoweringBase::isTypeLegal(), SDValue(), and llvm::widenShuffleMaskElts().

Referenced by lower128BitShuffle(), and lower256BitShuffle().

Variable Documentation

ArgFPR32s

const MCPhysReg ArgFPR32s[]

Initial value:

= {LoongArch::F0, LoongArch::F1, LoongArch::F2,
                               LoongArch::F3, LoongArch::F4, LoongArch::F5,
                               LoongArch::F6, LoongArch::F7}

Definition at line 7760 of file LoongArchISelLowering.cpp.

Referenced by CC_LoongArch(), and llvm::CC_RISCV().

ArgFPR64s

const MCPhysReg ArgFPR64s[]

Initial value:

= {
    LoongArch::F0_64, LoongArch::F1_64, LoongArch::F2_64, LoongArch::F3_64,
    LoongArch::F4_64, LoongArch::F5_64, LoongArch::F6_64, LoongArch::F7_64}

Definition at line 7764 of file LoongArchISelLowering.cpp.

Referenced by CC_LoongArch(), and llvm::CC_RISCV().

ArgGPRs

const MCPhysReg ArgGPRs[]

Initial value:

= {LoongArch::R4,  LoongArch::R5, LoongArch::R6,
                             LoongArch::R7,  LoongArch::R8, LoongArch::R9,
                             LoongArch::R10, LoongArch::R11}

Definition at line 7755 of file LoongArchISelLowering.cpp.

Referenced by llvm::CC_CSKY_ABIV2_SOFT_64(), CC_LoongArch(), CC_LoongArchAssign2GRLen(), llvm::CC_RISCV(), llvm::CC_RISCV_FastCC(), CC_RISCVAssign2XLen(), llvm::LoongArchTargetLowering::LowerFormalArguments(), and llvm::Ret_CSKY_ABIV2_SOFT_64().

ArgVRs

const MCPhysReg ArgVRs[]

Initial value:

= {LoongArch::VR0, LoongArch::VR1, LoongArch::VR2,
                            LoongArch::VR3, LoongArch::VR4, LoongArch::VR5,
                            LoongArch::VR6, LoongArch::VR7}

Definition at line 7768 of file LoongArchISelLowering.cpp.

Referenced by allocateRVVReg(), and CC_LoongArch().

ArgXRs

const MCPhysReg ArgXRs[]

Initial value:

= {LoongArch::XR0, LoongArch::XR1, LoongArch::XR2,
                            LoongArch::XR3, LoongArch::XR4, LoongArch::XR5,
                            LoongArch::XR6, LoongArch::XR7}

Definition at line 7772 of file LoongArchISelLowering.cpp.

Referenced by CC_LoongArch().

MaterializeFPImmInsNum

cl::opt< MaterializeFPImm > MaterializeFPImmInsNum("loongarch-materialize-float-imm", cl::Hidden, cl::desc("Maximum number of instructions used (including code sequence " "to generate the value and moving the value to FPR) when " "materializing floating-point immediates (default = 3)"), cl::init(MaterializeFPImm3Ins), cl::values(clEnumValN(NoMaterializeFPImm, "0", "Use constant pool"), clEnumValN(MaterializeFPImm2Ins, "2", "Materialize FP immediate within 2 instructions"), clEnumValN(MaterializeFPImm3Ins, "3", "Materialize FP immediate within 3 instructions"), clEnumValN(MaterializeFPImm4Ins, "4", "Materialize FP immediate within 4 instructions"), clEnumValN(MaterializeFPImm5Ins, "5", "Materialize FP immediate within 5 instructions"), clEnumValN(MaterializeFPImm6Ins, "6", "Materialize FP immediate within 6 instructions " "(behaves same as 5 on loongarch64)"))) ( "loongarch-materialize-float-imm" , cl::Hidden , cl::desc("Maximum number of instructions used (including code sequence " "to generate the value and moving the value to FPR) when " "materializing floating-point immediates (default = 3)") , cl::init(MaterializeFPImm3Ins) , cl::values(clEnumValN(NoMaterializeFPImm, "0", "Use constant pool"), clEnumValN(MaterializeFPImm2Ins, "2", "Materialize FP immediate within 2 instructions"), clEnumValN(MaterializeFPImm3Ins, "3", "Materialize FP immediate within 3 instructions"), clEnumValN(MaterializeFPImm4Ins, "4", "Materialize FP immediate within 4 instructions"), clEnumValN(MaterializeFPImm5Ins, "5", "Materialize FP immediate within 5 instructions"), clEnumValN(MaterializeFPImm6Ins, "6", "Materialize FP immediate within 6 instructions " "(behaves same as 5 on loongarch64)"))  )

static

ZeroDivCheck

cl::opt< bool > ZeroDivCheck("loongarch-check-zero-division", cl::Hidden, cl::desc("Trap on integer division by zero."), cl::init(false)) ( "loongarch-check-zero-division" , cl::Hidden , cl::desc("Trap on integer division by zero.") , cl::init(false)  )

static

Referenced by insertDivByZeroTrap().