LLVM 22.0.0git
llvm::TargetLowering::DAGCombinerInfo Struct Reference

#include "llvm/CodeGen/TargetLowering.h"

Public Member Functions

 DAGCombinerInfo (SelectionDAG &dag, CombineLevel level, bool cl, void *dc)
bool isBeforeLegalize () const
bool isBeforeLegalizeOps () const
bool isAfterLegalizeDAG () const
CombineLevel getDAGCombineLevel ()
bool isCalledByLegalizer () const
LLVM_ABI void AddToWorklist (SDNode *N)
LLVM_ABI SDValue CombineTo (SDNode *N, ArrayRef< SDValue > To, bool AddTo=true)
LLVM_ABI SDValue CombineTo (SDNode *N, SDValue Res, bool AddTo=true)
LLVM_ABI SDValue CombineTo (SDNode *N, SDValue Res0, SDValue Res1, bool AddTo=true)
LLVM_ABI bool recursivelyDeleteUnusedNodes (SDNode *N)
LLVM_ABI void CommitTargetLoweringOpt (const TargetLoweringOpt &TLO)

Public Attributes

void * DC
CombineLevel Level
bool CalledByLegalizer
SelectionDAGDAG

Detailed Description

Definition at line 4398 of file TargetLowering.h.

Constructor & Destructor Documentation

◆ DAGCombinerInfo()

llvm::TargetLowering::DAGCombinerInfo::DAGCombinerInfo ( SelectionDAG & dag,
CombineLevel level,
bool cl,
void * dc )
inline

Definition at line 4406 of file TargetLowering.h.

References CalledByLegalizer, DAG, DC, and Level.

Member Function Documentation

◆ AddToWorklist()

◆ CombineTo() [1/3]

◆ CombineTo() [2/3]

SDValue TargetLowering::DAGCombinerInfo::CombineTo ( SDNode * N,
SDValue Res,
bool AddTo = true )

Definition at line 943 of file DAGCombiner.cpp.

References DC, and N.

◆ CombineTo() [3/3]

SDValue TargetLowering::DAGCombinerInfo::CombineTo ( SDNode * N,
SDValue Res0,
SDValue Res1,
bool AddTo = true )

Definition at line 948 of file DAGCombiner.cpp.

References DC, and N.

◆ CommitTargetLoweringOpt()

◆ getDAGCombineLevel()

CombineLevel llvm::TargetLowering::DAGCombinerInfo::getDAGCombineLevel ( )
inline

◆ isAfterLegalizeDAG()

◆ isBeforeLegalize()

bool llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalize ( ) const
inline

Definition at line 4409 of file TargetLowering.h.

References llvm::BeforeLegalizeTypes, and Level.

Referenced by AddCombineBUILD_VECTORToVPADDL(), CombineANDShift(), combineBitcast(), combineBITREVERSE(), combineCMov(), combineExtractVectorElt(), combineGatherScatter(), combineINTRINSIC_VOID(), combineINTRINSIC_W_CHAIN(), combineINTRINSIC_WO_CHAIN(), combineLOAD(), combineLoad(), combineMul(), combineOp_VLToVWOp_VL(), combineOrCmpEqZeroToCtlzSrl(), combineSelect(), combineSetCC(), combineSIntToFP(), combineSTORE(), combineStore(), combineVSelectToBLENDV(), expandMul(), legalizeScatterGatherIndexType(), performActiveLaneMaskCombine(), performADDCombine(), PerformADDECombine(), performANDSETCCCombine(), performBitcastCombine(), llvm::AMDGPUTargetLowering::PerformDAGCombine(), llvm::PPCTargetLowering::PerformDAGCombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), llvm::SITargetLowering::PerformDAGCombine(), performEXTRACT_VECTOR_ELTCombine(), performExtractLastActiveCombine(), performFirstTrueTestVectorCombine(), performLastTrueTestVectorCombine(), llvm::AMDGPUTargetLowering::performLoadCombine(), performMaskedGatherScatterCombine(), PerformMULCombine(), performMulCombine(), PerformMVEVLDCombine(), performNEONPostLDSTCombine(), performSelectCombine(), performSETCCCombine(), performSETCCCombine(), PerformShiftCombine(), PerformSHLSimplify(), llvm::AMDGPUTargetLowering::performStoreCombine(), performVecReduceBitwiseCombine(), performVectorDeinterleaveCombine(), PerformVLDCombine(), scalarizeExtEltFP(), llvm::TargetLowering::SimplifyDemandedBits(), llvm::TargetLowering::SimplifyDemandedBits(), llvm::TargetLowering::SimplifyDemandedVectorElts(), llvm::TargetLowering::SimplifySetCC(), sinkProxyReg(), and tryConvertSVEWideCompare().

◆ isBeforeLegalizeOps()

bool llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalizeOps ( ) const
inline

Definition at line 4410 of file TargetLowering.h.

References llvm::AfterLegalizeVectorOps, and Level.

Referenced by combineAnd(), combineCastedMaskArithmetic(), combineCMov(), combineEXTEND_VECTOR_INREG(), combineEXTRACT_SUBVECTOR(), combineExtractWithShuffle(), combineFMA(), combineFMADDSUB(), combineFneg(), combineGatherScatter(), combineINSERT_SUBVECTOR(), combineLoad(), combineOr(), combineSelect(), combineSext(), combineStore(), combineTargetShuffle(), combineToExtendBoolVectorInReg(), combineVSelectToBLENDV(), combineXor(), combineZext(), convertIntLogicToFPLogic(), llvm::PPCTargetLowering::expandVSXLoadForLE(), llvm::PPCTargetLowering::expandVSXStoreForLE(), performADDCombine(), performAddSubLongCombine(), performANDCombine(), performANDCombine(), performBITCASTCombine(), performBITREV_WCombine(), performCMovFPCombine(), performConcatVectorsCombine(), llvm::AMDGPUTargetLowering::PerformDAGCombine(), llvm::HexagonTargetLowering::PerformDAGCombine(), llvm::R600TargetLowering::PerformDAGCombine(), performDivRemCombine(), performExtendCombine(), performExtractSubvectorCombine(), performFPExtendCombine(), performMulCombine(), performORCombine(), performORCombine(), performPostLD1Combine(), performScalarToVectorCombine(), performSELECTCombine(), performSHLCombine(), performSHLCombine(), performSignExtendInRegCombine(), performSRLCombine(), performSUBCombine(), performSVEAndCombine(), performXorCombine(), llvm::TargetLowering::SimplifyDemandedBits(), llvm::TargetLowering::SimplifyDemandedBits(), llvm::TargetLowering::SimplifyDemandedVectorElts(), llvm::TargetLowering::SimplifySetCC(), tryCombineFixedPointConvert(), tryCombineLongOpWithDup(), tryCombineMULLWithUZP1(), and tryToReplaceScalarFPConversionWithSVE().

◆ isCalledByLegalizer()

◆ recursivelyDeleteUnusedNodes()

bool TargetLowering::DAGCombinerInfo::recursivelyDeleteUnusedNodes ( SDNode * N)

Member Data Documentation

◆ CalledByLegalizer

bool llvm::TargetLowering::DAGCombinerInfo::CalledByLegalizer

Definition at line 4401 of file TargetLowering.h.

Referenced by DAGCombinerInfo(), and isCalledByLegalizer().

◆ DAG

SelectionDAG& llvm::TargetLowering::DAGCombinerInfo::DAG

Definition at line 4404 of file TargetLowering.h.

Referenced by AddCombineBUILD_VECTORToVPADDL(), AddCombineTo64bitMLAL(), AddCombineTo64BitSMLAL16(), AddCombineTo64bitUMAAL(), AddCombineToVPADD(), AddCombineVUZPToVPADDL(), CombineANDShift(), CombineBaseUpdate(), llvm::AMDGPUTargetLowering::combineFMinMaxLegacy(), llvm::AMDGPUTargetLowering::combineFMinMaxLegacyImpl(), combineLOAD(), combineMADConstOne(), combineMulSelectConstOne(), combineMulWide(), combineOp_VLToVWOp_VL(), combinePackingMovIntoStore(), combinePRMT(), llvm::VETargetLowering::combineSelect(), combineSelectAndUse(), combineSelectAndUse(), llvm::VETargetLowering::combineSelectCC(), combineSTORE(), llvm::VETargetLowering::combineTRUNCATE(), combineVectorSizedSetCCEquality(), CombineVLDDUP(), DAGCombinerInfo(), distributeOpThroughSelect(), llvm::PPCTargetLowering::expandVSXLoadForLE(), llvm::PPCTargetLowering::expandVSXStoreForLE(), llvm::AMDGPUTargetLowering::foldFreeOpFromSelect(), legalizeScatterGatherIndexType(), matchPERM(), performActiveLaneMaskCombine(), PerformADDCombine(), performADDCombine(), PerformADDCombineWithOperands(), PerformAddcSubcCombine(), PerformAddeSubeCombine(), performAddSubCombine(), performAddSubLongCombine(), PerformANDCombine(), performANDCombine(), performANDCombine(), performANDSETCCCombine(), PerformARMBUILD_VECTORCombine(), llvm::AMDGPUTargetLowering::performAssertSZExtCombine(), llvm::SparcTargetLowering::PerformBITCASTCombine(), PerformBITCASTCombine(), performBitcastCombine(), PerformBUILD_VECTORCombine(), PerformBUILD_VECTORCombine(), performConcatVectorsCombine(), llvm::AMDGPUTargetLowering::performCtlz_CttzCombine(), llvm::AArch64TargetLowering::PerformDAGCombine(), llvm::AMDGPUTargetLowering::PerformDAGCombine(), llvm::ARMTargetLowering::PerformDAGCombine(), llvm::HexagonTargetLowering::PerformDAGCombine(), llvm::LoongArchTargetLowering::PerformDAGCombine(), llvm::MipsSETargetLowering::PerformDAGCombine(), llvm::MipsTargetLowering::PerformDAGCombine(), llvm::PPCTargetLowering::PerformDAGCombine(), llvm::R600TargetLowering::PerformDAGCombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), llvm::SITargetLowering::PerformDAGCombine(), llvm::X86TargetLowering::PerformDAGCombine(), performDUPCombine(), PerformEXTRACTCombine(), PerformExtractEltCombine(), PerformExtractEltToVMOVRRD(), performExtractLastActiveCombine(), performExtractVectorEltCombine(), llvm::AMDGPUTargetLowering::performFAbsCombine(), performFADDCombine(), PerformFADDCombineWithOperands(), performFirstTrueTestVectorCombine(), performFlagSettingCombine(), llvm::AMDGPUTargetLowering::performFNegCombine(), performFP_TO_INT_SATCombine(), performFP_TO_INTCombine(), PerformHWLoopCombine(), PerformInsertEltCombine(), PerformInsertSubvectorCombine(), llvm::ARMTargetLowering::PerformIntrinsicCombine(), performIntrinsicCombine(), llvm::AMDGPUTargetLowering::performIntrinsicWOChainCombine(), performLastTrueTestVectorCombine(), PerformLOADCombine(), llvm::AMDGPUTargetLowering::performLoadCombine(), performMemPairCombine(), PerformMULCombine(), llvm::AMDGPUTargetLowering::performMulCombine(), performMulCombine(), llvm::AMDGPUTargetLowering::performMulhsCombine(), llvm::AMDGPUTargetLowering::performMulhuCombine(), llvm::AMDGPUTargetLowering::performMulLoHiCombine(), llvm::ARMTargetLowering::PerformMVEExtCombine(), llvm::ARMTargetLowering::PerformMVETruncCombine(), PerformMVEVLDCombine(), PerformORCombine(), performORCombine(), performORCombine(), PerformORCombineToBFI(), PerformORCombineToSMULWBT(), performPostLD1Combine(), PerformPREDICATE_CASTCombine(), llvm::AMDGPUTargetLowering::performRcpCombine(), PerformREMCombine(), PerformSELECTCombine(), llvm::AMDGPUTargetLowering::performSelectCombine(), performSelectCombine(), PerformSETCCCombine(), performSETCCCombine(), performSETCCCombine(), performSetccMergeZeroCombine(), PerformShiftCombine(), performSHLCombine(), llvm::AMDGPUTargetLowering::performShlCombine(), PerformSHLSimplify(), performSIGN_EXTEND_INREGCombine(), llvm::AMDGPUTargetLowering::performSraCombine(), llvm::AMDGPUTargetLowering::performSrlCombine(), PerformSTORECombine(), llvm::AMDGPUTargetLowering::performStoreCombine(), PerformSUBCombine(), performSVEAndCombine(), performSVEMulAddSubCombine(), llvm::AMDGPUTargetLowering::performTruncateCombine(), performTruncateCombine(), PerformVDUPLANECombine(), performVECTOR_SHUFFLECombine(), performVectorExtendCombine(), performVectorExtendToFPCombine(), performVectorNonNegToFPCombine(), performVectorShiftCombine(), performVectorTruncZeroCombine(), performVFMADD_VLCombine(), PerformVMOVhrCombine(), PerformVMOVNCombine(), PerformVMOVRRDCombine(), PerformVMULCombine(), PerformVQDMULHCombine(), PerformVQMOVNCombine(), PerformVSELECTCombine(), PerformVSELECTCombine(), PerformVSetCCToVCTPCombine(), performVWADDSUBW_VLCombine(), PerformXORCombine(), reduceANDOfAtomicLoad(), llvm::TargetLowering::SimplifyDemandedBits(), llvm::TargetLowering::SimplifyDemandedBits(), llvm::TargetLowering::SimplifyDemandedVectorElts(), simplifyMul24(), llvm::TargetLowering::SimplifySetCC(), sinkProxyReg(), llvm::AMDGPUTargetLowering::splitBinaryBitConstantOpImpl(), TryCombineBaseUpdate(), and TryMULWIDECombine().

◆ DC

void* llvm::TargetLowering::DAGCombinerInfo::DC

◆ Level

CombineLevel llvm::TargetLowering::DAGCombinerInfo::Level

The documentation for this struct was generated from the following files: