46#include "llvm/IR/IntrinsicsHexagon.h"
66#define DEBUG_TYPE "hexagon-lowering"
70 cl::desc(
"Control jump table emission on Hexagon target"));
74 cl::desc(
"Enable Hexagon SDNode scheduling"));
77 cl::desc(
"Enable Fast Math processing"));
81 cl::desc(
"Set minimum jump tables"));
85 cl::desc(
"Max #stores to inline memcpy"));
89 cl::desc(
"Max #stores to inline memcpy"));
93 cl::desc(
"Max #stores to inline memmove"));
98 cl::desc(
"Max #stores to inline memmove"));
102 cl::desc(
"Max #stores to inline memset"));
106 cl::desc(
"Max #stores to inline memset"));
110 cl::desc(
"Rewrite unaligned loads as a pair of aligned loads"));
115 cl::desc(
"Disable minimum alignment of 1 for "
116 "arguments passed by value on stack"));
120 class HexagonCCState :
public CCState {
121 unsigned NumNamedVarArgParams = 0;
126 unsigned NumNamedArgs)
128 NumNamedVarArgParams(NumNamedArgs) {}
129 unsigned getNumNamedVarArgParams()
const {
return NumNamedVarArgParams; }
141 Hexagon::R0, Hexagon::R1, Hexagon::R2,
142 Hexagon::R3, Hexagon::R4, Hexagon::R5
144 const unsigned NumArgRegs = std::size(ArgRegs);
148 if (RegNum != NumArgRegs && RegNum % 2 == 1)
157#include "HexagonGenCallingConv.inc"
176 Chain, dl, Dst, Src, SizeNode, Flags.getNonZeroByValAlign(),
187 CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);
190 return CCInfo.
CheckReturn(Outs, RetCC_Hexagon_HVX);
220 for (
unsigned i = 0; i != RVLocs.
size(); ++i) {
269 .
Case(
"r0", Hexagon::R0)
270 .
Case(
"r1", Hexagon::R1)
271 .
Case(
"r2", Hexagon::R2)
272 .
Case(
"r3", Hexagon::R3)
273 .
Case(
"r4", Hexagon::R4)
274 .
Case(
"r5", Hexagon::R5)
275 .
Case(
"r6", Hexagon::R6)
276 .
Case(
"r7", Hexagon::R7)
277 .
Case(
"r8", Hexagon::R8)
278 .
Case(
"r9", Hexagon::R9)
279 .
Case(
"r10", Hexagon::R10)
280 .
Case(
"r11", Hexagon::R11)
281 .
Case(
"r12", Hexagon::R12)
282 .
Case(
"r13", Hexagon::R13)
283 .
Case(
"r14", Hexagon::R14)
284 .
Case(
"r15", Hexagon::R15)
285 .
Case(
"r16", Hexagon::R16)
286 .
Case(
"r17", Hexagon::R17)
287 .
Case(
"r18", Hexagon::R18)
288 .
Case(
"r19", Hexagon::R19)
289 .
Case(
"r20", Hexagon::R20)
290 .
Case(
"r21", Hexagon::R21)
291 .
Case(
"r22", Hexagon::R22)
292 .
Case(
"r23", Hexagon::R23)
293 .
Case(
"r24", Hexagon::R24)
294 .
Case(
"r25", Hexagon::R25)
295 .
Case(
"r26", Hexagon::R26)
296 .
Case(
"r27", Hexagon::R27)
297 .
Case(
"r28", Hexagon::R28)
298 .
Case(
"r29", Hexagon::R29)
299 .
Case(
"r30", Hexagon::R30)
300 .
Case(
"r31", Hexagon::R31)
301 .
Case(
"r1:0", Hexagon::D0)
302 .
Case(
"r3:2", Hexagon::D1)
303 .
Case(
"r5:4", Hexagon::D2)
304 .
Case(
"r7:6", Hexagon::D3)
305 .
Case(
"r9:8", Hexagon::D4)
306 .
Case(
"r11:10", Hexagon::D5)
307 .
Case(
"r13:12", Hexagon::D6)
308 .
Case(
"r15:14", Hexagon::D7)
309 .
Case(
"r17:16", Hexagon::D8)
310 .
Case(
"r19:18", Hexagon::D9)
311 .
Case(
"r21:20", Hexagon::D10)
312 .
Case(
"r23:22", Hexagon::D11)
313 .
Case(
"r25:24", Hexagon::D12)
314 .
Case(
"r27:26", Hexagon::D13)
315 .
Case(
"r29:28", Hexagon::D14)
316 .
Case(
"r31:30", Hexagon::D15)
317 .
Case(
"sp", Hexagon::R29)
318 .
Case(
"fp", Hexagon::R30)
319 .
Case(
"lr", Hexagon::R31)
320 .
Case(
"p0", Hexagon::P0)
321 .
Case(
"p1", Hexagon::P1)
322 .
Case(
"p2", Hexagon::P2)
323 .
Case(
"p3", Hexagon::P3)
324 .
Case(
"sa0", Hexagon::SA0)
325 .
Case(
"lc0", Hexagon::LC0)
326 .
Case(
"sa1", Hexagon::SA1)
327 .
Case(
"lc1", Hexagon::LC1)
328 .
Case(
"m0", Hexagon::M0)
329 .
Case(
"m1", Hexagon::M1)
330 .
Case(
"usr", Hexagon::USR)
331 .
Case(
"ugp", Hexagon::UGP)
332 .
Case(
"cs0", Hexagon::CS0)
333 .
Case(
"cs1", Hexagon::CS1)
363 for (
unsigned i = 0; i != RVLocs.
size(); ++i) {
365 if (RVLocs[i].getValVT() == MVT::i1) {
375 Register PredR =
MRI.createVirtualRegister(&Hexagon::PredRegsRegClass);
387 RVLocs[i].getValVT(), Glue);
413 bool IsStructRet = Outs.
empty() ?
false : Outs[0].Flags.isSRet();
427 HexagonCCState CCInfo(CallConv, TreatAsVarArg, MF, ArgLocs, *DAG.
getContext(),
431 CCInfo.AnalyzeCallOperands(Outs, CC_Hexagon_HVX);
433 CCInfo.AnalyzeCallOperands(Outs, CC_Hexagon_Legacy);
435 CCInfo.AnalyzeCallOperands(Outs, CC_Hexagon);
440 IsVarArg, IsStructRet, StructAttrFlag, Outs,
449 :
"Argument must be passed on stack. "
450 "Not eligible for Tail Call\n"));
453 unsigned NumBytes = CCInfo.getStackSize();
461 bool NeedsArgAlign =
false;
462 Align LargestAlignSeen;
464 for (
unsigned i = 0, e = ArgLocs.
size(); i != e; ++i) {
470 NeedsArgAlign |= ArgAlign;
496 StackPtr.getValueType());
499 LargestAlignSeen = std::max(
501 if (Flags.isByVal()) {
521 if (NeedsArgAlign && Subtarget.
hasV60Ops()) {
522 LLVM_DEBUG(
dbgs() <<
"Function needs byte stack align due to call args\n");
523 Align VecAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass);
524 LargestAlignSeen = std::max(LargestAlignSeen, VecAlign);
529 if (!MemOpChains.
empty())
543 for (
const auto &R : RegsToPass) {
544 Chain = DAG.
getCopyToReg(Chain, dl, R.first, R.second, Glue);
559 for (
const auto &R : RegsToPass) {
560 Chain = DAG.
getCopyToReg(Chain, dl, R.first, R.second, Glue);
575 dyn_cast<ExternalSymbolSDNode>(Callee)) {
586 for (
const auto &R : RegsToPass)
590 assert(Mask &&
"Missing call preserved mask for calling convention");
607 Chain = DAG.
getNode(OpCode, dl, {MVT::Other, MVT::Glue}, Ops);
617 InVals, OutVals, Callee);
632 bool IsLegalType = VT == MVT::i8 || VT == MVT::i16 || VT == MVT::i32 ||
633 VT == MVT::i64 || VT == MVT::f32 || VT == MVT::f64 ||
634 VT == MVT::v2i16 || VT == MVT::v2i32 || VT == MVT::v4i8 ||
635 VT == MVT::v4i16 || VT == MVT::v8i8 ||
644 if (!isa<ConstantSDNode>(
Offset.getNode()))
648 int32_t V = cast<ConstantSDNode>(
Offset.getNode())->getSExtValue();
664 unsigned LR = HRI.getRARegister();
671 if (
Op.getOperand(NumOps-1).getValueType() == MVT::Glue)
676 unsigned NumVals = Flags.getNumOperandRegisters();
679 switch (Flags.getKind()) {
690 for (; NumVals; --NumVals, ++i) {
691 Register Reg = cast<RegisterSDNode>(
Op.getOperand(i))->getReg();
694 HMFI.setHasClobberLR(
true);
746 unsigned IntNo =
Op.getConstantOperandVal(1);
748 if (IntNo == Intrinsic::hexagon_prefetch) {
766 assert(AlignConst &&
"Non-constant Align in LowerDYNAMIC_STACKALLOC");
772 A = HFI.getStackAlign().value();
775 dbgs () << __func__ <<
" Align: " <<
A <<
" Size: ";
776 Size.getNode()->dump(&DAG);
801 HexagonCCState CCInfo(CallConv, TreatAsVarArg, MF, ArgLocs,
806 CCInfo.AnalyzeFormalArguments(Ins, CC_Hexagon_HVX);
808 CCInfo.AnalyzeFormalArguments(Ins, CC_Hexagon_Legacy);
810 CCInfo.AnalyzeFormalArguments(Ins, CC_Hexagon);
819 switch (RC.
getID()) {
820 case Hexagon::IntRegsRegClassID:
821 return Reg - Hexagon::R0 + 1;
822 case Hexagon::DoubleRegsRegClassID:
823 return (Reg - Hexagon::D0 + 1) * 2;
824 case Hexagon::HvxVRRegClassID:
825 return Reg - Hexagon::V0 + 1;
826 case Hexagon::HvxWRRegClassID:
827 return (Reg - Hexagon::W0 + 1) * 2;
834 HFL.FirstVarArgSavedReg = 0;
837 for (
unsigned i = 0, e = ArgLocs.
size(); i != e; ++i) {
840 bool ByVal = Flags.isByVal();
846 if (VA.
isRegLoc() && ByVal && Flags.getByValSize() <= 8)
850 (!ByVal || (ByVal && Flags.getByValSize() > 8));
879 HFL.FirstVarArgSavedReg = NextSingleReg(*RC, VA.
getLocReg());
885 unsigned ObjSize = Flags.isByVal()
886 ? Flags.getByValSize()
894 if (Flags.isByVal()) {
908 for (
int i = HFL.FirstVarArgSavedReg; i < 6; i++)
909 MRI.addLiveIn(Hexagon::R0+i);
913 HMFI.setFirstNamedArgFrameIndex(HMFI.getFirstNamedArgFrameIndex() - 1);
917 int NumVarArgRegs = 6 - HFL.FirstVarArgSavedReg;
918 bool RequiresPadding = (NumVarArgRegs & 1);
919 int RegSaveAreaSizePlusPadding = RequiresPadding
920 ? (NumVarArgRegs + 1) * 4
923 if (RegSaveAreaSizePlusPadding > 0) {
926 if (!(RegAreaStart % 8))
927 RegAreaStart = (RegAreaStart + 7) & -8;
929 int RegSaveAreaFrameIndex =
931 HMFI.setRegSavedAreaStartFrameIndex(RegSaveAreaFrameIndex);
934 int Offset = RegAreaStart + RegSaveAreaSizePlusPadding;
936 HMFI.setVarArgsFrameIndex(FI);
942 HMFI.setRegSavedAreaStartFrameIndex(FI);
943 HMFI.setVarArgsFrameIndex(FI);
952 HMFI.setVarArgsFrameIndex(FI);
965 const Value *SV = cast<SrcValueSDNode>(
Op.getOperand(2))->getValue();
985 SDValue SavedRegAreaStartFrameIndex =
986 DAG.
getFrameIndex(FuncInfo.getRegSavedAreaStartFrameIndex(), MVT::i32);
990 if (HFL.FirstVarArgSavedReg & 1)
991 SavedRegAreaStartFrameIndex =
1000 SavedRegAreaStartFrameIndex,
1032 const Value *DestSV = cast<SrcValueSDNode>(
Op.getOperand(3))->getValue();
1033 const Value *SrcSV = cast<SrcValueSDNode>(
Op.getOperand(4))->getValue();
1039 false,
false,
nullptr, std::nullopt,
1051 if (OpTy == MVT::v2i16 || OpTy == MVT::v4i8) {
1068 auto isSExtFree = [
this](
SDValue N) {
1069 switch (
N.getOpcode()) {
1075 EVT OrigTy = cast<VTSDNode>(
Op.getOperand(1))->getVT();
1081 return ThisBW >= OrigBW;
1090 if (OpTy == MVT::i8 || OpTy == MVT::i16) {
1092 bool IsNegative =
C &&
C->getAPIntValue().isNegative();
1093 if (IsNegative || isSExtFree(
LHS) || isSExtFree(
RHS))
1105 SDValue Op1 =
Op.getOperand(1), Op2 =
Op.getOperand(2);
1109 if (OpTy == MVT::v2i16 || OpTy == MVT::v4i8) {
1127 EVT ValTy =
Op.getValueType();
1130 bool isVTi1Type =
false;
1131 if (
auto *CV = dyn_cast<ConstantVector>(CPN->
getConstVal())) {
1132 if (cast<VectorType>(CV->getType())->getElementType()->isIntegerTy(1)) {
1135 unsigned VecLen = CV->getNumOperands();
1137 "conversion only supported for pow2 VectorSize");
1138 for (
unsigned i = 0; i < VecLen; ++i)
1154 else if (isVTi1Type)
1160 assert(cast<ConstantPoolSDNode>(
T)->getTargetFlags() == TF &&
1161 "Inconsistent target flag encountered");
1163 if (IsPositionIndependent)
1170 EVT VT =
Op.getValueType();
1171 int Idx = cast<JumpTableSDNode>(
Op)->getIndex();
1191 EVT VT =
Op.getValueType();
1193 unsigned Depth =
Op.getConstantOperandVal(0);
1213 EVT VT =
Op.getValueType();
1215 unsigned Depth =
Op.getConstantOperandVal(0);
1233 auto *GAN = cast<GlobalAddressSDNode>(
Op);
1235 auto *GV = GAN->getGlobal();
1236 int64_t
Offset = GAN->getOffset();
1244 if (GO && Subtarget.
useSmallData() && HLOF.isGlobalInSmallSection(GO, HTM))
1266 const BlockAddress *BA = cast<BlockAddressSDNode>(
Op)->getBlockAddress();
1292 unsigned char OperandFlags)
const {
1311 assert(Mask &&
"Missing call preserved mask for calling convention");
1346 if (IsPositionIndependent) {
1418 Hexagon::R0, Flags);
1556 for (
unsigned LegalIntOp :
1596 for (
unsigned IntExpOp :
1605 for (
unsigned FPExpOp :
1641 static const unsigned VectExpOps[] = {
1667 for (
unsigned VectExpOp : VectExpOps)
1681 if (VT.getVectorElementType() != MVT::i32) {
1705 for (
MVT NativeVT : {MVT::v8i1, MVT::v4i1, MVT::v2i1, MVT::v4i8,
1706 MVT::v8i8, MVT::v2i16, MVT::v4i16, MVT::v2i32}) {
1721 if (NativeVT.getVectorElementType() != MVT::i1) {
1728 for (
MVT VT : {MVT::v8i8, MVT::v4i16, MVT::v2i32}) {
1739 for (
MVT VT : {MVT::i16, MVT::i32, MVT::v4i8, MVT::i64, MVT::v8i8,
1740 MVT::v2i16, MVT::v4i16, MVT::v2i32}) {
1746 for (
MVT VT : {MVT::v2i1, MVT::v4i1, MVT::v8i1}) {
1752 for (
MVT VT : {MVT::v2i16, MVT::v4i8, MVT::v8i8, MVT::v2i32, MVT::v4i16,
1764 for (
MVT VT : {MVT::i1, MVT::v2i1, MVT::v4i1, MVT::v8i1}) {
1817 for (
MVT VT : {MVT::i8, MVT::i16, MVT::i32, MVT::i64, MVT::f32, MVT::f64,
1818 MVT::v2i16, MVT::v2i32, MVT::v4i8, MVT::v4i16, MVT::v8i8}) {
1846 initializeHVXLowering();
1866 setLibcallName(RTLIB::FPTOUINT_F32_I128,
"__hexagon_fixunssfti");
1867 setLibcallName(RTLIB::FPTOUINT_F64_I128,
"__hexagon_fixunsdfti");
1962HexagonTargetLowering::validateConstPtrAlignment(
SDValue Ptr,
Align NeedAlign,
1964 auto *CA = dyn_cast<ConstantSDNode>(
Ptr);
1967 unsigned Addr = CA->getZExtValue();
1970 if (HaveAlign >= NeedAlign)
1976 DiagnosticInfoMisalignedTrap(
StringRef M)
1982 return DI->
getKind() == DK_MisalignedTrap;
1990 <<
" has alignment " << HaveAlign.
value()
1991 <<
", but the memory access requires " << NeedAlign.
value();
1994 O <<
". The instruction has been replaced with a trap.";
2004 auto *
LS = cast<LSBaseSDNode>(
Op.getNode());
2005 assert(!
LS->isIndexed() &&
"Not expecting indexed ops on constant address");
2017 unsigned ID = cast<IntrinsicInst>(Inst)->getIntrinsicID();
2018 return (
ID == Intrinsic::hexagon_L2_loadrd_pbr ||
2019 ID == Intrinsic::hexagon_L2_loadri_pbr ||
2020 ID == Intrinsic::hexagon_L2_loadrh_pbr ||
2021 ID == Intrinsic::hexagon_L2_loadruh_pbr ||
2022 ID == Intrinsic::hexagon_L2_loadrb_pbr ||
2023 ID == Intrinsic::hexagon_L2_loadrub_pbr);
2032 V = cast<Operator>(V)->getOperand(0);
2034 V = cast<Instruction>(V)->getOperand(0);
2047 if (Blk == Parent) {
2052 BaseVal = BackEdgeVal;
2054 }
while ((BaseVal != BackEdgeVal) && (IntrBaseVal != BackEdgeVal));
2057 if (IntrBaseVal == BackEdgeVal)
2064 assert(
Idx >= 0 &&
"Unexpected index to incoming argument in PHI");
2072 Value *IntrBaseVal = V;
2079 }
while (BaseVal != V);
2082 if (
const PHINode *PN = dyn_cast<PHINode>(V))
2096 unsigned Intrinsic)
const {
2097 switch (Intrinsic) {
2098 case Intrinsic::hexagon_L2_loadrd_pbr:
2099 case Intrinsic::hexagon_L2_loadri_pbr:
2100 case Intrinsic::hexagon_L2_loadrh_pbr:
2101 case Intrinsic::hexagon_L2_loadruh_pbr:
2102 case Intrinsic::hexagon_L2_loadrb_pbr:
2103 case Intrinsic::hexagon_L2_loadrub_pbr: {
2105 auto &
DL =
I.getDataLayout();
2106 auto &Cont =
I.getCalledFunction()->getParent()->getContext();
2110 Type *ElTy =
I.getCalledFunction()->getReturnType()->getStructElementType(0);
2117 Info.align =
DL.getABITypeAlign(
Info.memVT.getTypeForEVT(Cont));
2121 case Intrinsic::hexagon_V6_vgathermw:
2122 case Intrinsic::hexagon_V6_vgathermw_128B:
2123 case Intrinsic::hexagon_V6_vgathermh:
2124 case Intrinsic::hexagon_V6_vgathermh_128B:
2125 case Intrinsic::hexagon_V6_vgathermhw:
2126 case Intrinsic::hexagon_V6_vgathermhw_128B:
2127 case Intrinsic::hexagon_V6_vgathermwq:
2128 case Intrinsic::hexagon_V6_vgathermwq_128B:
2129 case Intrinsic::hexagon_V6_vgathermhq:
2130 case Intrinsic::hexagon_V6_vgathermhq_128B:
2131 case Intrinsic::hexagon_V6_vgathermhwq:
2132 case Intrinsic::hexagon_V6_vgathermhwq_128B: {
2133 const Module &M = *
I.getParent()->getParent()->getParent();
2135 Type *VecTy =
I.getArgOperand(1)->getType();
2137 Info.ptrVal =
I.getArgOperand(0);
2140 MaybeAlign(M.getDataLayout().getTypeAllocSizeInBits(VecTy) / 8);
2153 return X.getValueType().isScalarInteger();
2173 unsigned DefinedValues)
const {
2178 unsigned Index)
const {
2210 unsigned Action = getPreferredHvxVectorAction(VT);
2216 if (ElemTy == MVT::i1)
2230 unsigned Action = getCustomHvxOperationAction(
Op);
2237std::pair<SDValue, int>
2238HexagonTargetLowering::getBaseAndOffset(
SDValue Addr)
const {
2241 if (
auto *CN = dyn_cast<const ConstantSDNode>(Op1.
getNode()))
2242 return {
Addr.getOperand(0), CN->getSExtValue() };
2252 const auto *SVN = cast<ShuffleVectorSDNode>(
Op);
2254 assert(AM.
size() <= 8 &&
"Unexpected shuffle mask");
2255 unsigned VecLen = AM.
size();
2259 "HVX shuffles should be legal");
2269 if (ty(Op0) != VecTy || ty(Op1) != VecTy)
2278 if (AM[
F] >=
int(VecLen)) {
2286 for (
int M : Mask) {
2288 for (
unsigned j = 0; j != ElemBytes; ++j)
2291 for (
unsigned j = 0; j != ElemBytes; ++j)
2304 for (
unsigned i = 0, e = ByteMask.
size(); i != e; ++i) {
2312 if (ByteMask.
size() == 4) {
2314 if (MaskIdx == (0x03020100 | MaskUnd))
2317 if (MaskIdx == (0x00010203 | MaskUnd)) {
2325 getCombine(Op1, Op0, dl, typeJoin({ty(Op1), ty(Op0)}), DAG);
2326 if (MaskIdx == (0x06040200 | MaskUnd))
2327 return getInstr(Hexagon::S2_vtrunehb, dl, VecTy, {Concat10}, DAG);
2328 if (MaskIdx == (0x07050301 | MaskUnd))
2329 return getInstr(Hexagon::S2_vtrunohb, dl, VecTy, {Concat10}, DAG);
2332 getCombine(Op0, Op1, dl, typeJoin({ty(Op0), ty(Op1)}), DAG);
2333 if (MaskIdx == (0x02000604 | MaskUnd))
2334 return getInstr(Hexagon::S2_vtrunehb, dl, VecTy, {Concat01}, DAG);
2335 if (MaskIdx == (0x03010705 | MaskUnd))
2336 return getInstr(Hexagon::S2_vtrunohb, dl, VecTy, {Concat01}, DAG);
2339 if (ByteMask.
size() == 8) {
2341 if (MaskIdx == (0x0706050403020100ull | MaskUnd))
2344 if (MaskIdx == (0x0001020304050607ull | MaskUnd)) {
2351 if (MaskIdx == (0x0d0c050409080100ull | MaskUnd))
2352 return getInstr(Hexagon::S2_shuffeh, dl, VecTy, {Op1, Op0}, DAG);
2353 if (MaskIdx == (0x0f0e07060b0a0302ull | MaskUnd))
2354 return getInstr(Hexagon::S2_shuffoh, dl, VecTy, {Op1, Op0}, DAG);
2355 if (MaskIdx == (0x0d0c090805040100ull | MaskUnd))
2356 return getInstr(Hexagon::S2_vtrunewh, dl, VecTy, {Op1, Op0}, DAG);
2357 if (MaskIdx == (0x0f0e0b0a07060302ull | MaskUnd))
2358 return getInstr(Hexagon::S2_vtrunowh, dl, VecTy, {Op1, Op0}, DAG);
2359 if (MaskIdx == (0x0706030205040100ull | MaskUnd)) {
2360 VectorPair
P = opSplit(Op0, dl, DAG);
2361 return getInstr(Hexagon::S2_packhl, dl, VecTy, {
P.second,
P.first}, DAG);
2365 if (MaskIdx == (0x0e060c040a020800ull | MaskUnd))
2366 return getInstr(Hexagon::S2_shuffeb, dl, VecTy, {Op1, Op0}, DAG);
2367 if (MaskIdx == (0x0f070d050b030901ull | MaskUnd))
2368 return getInstr(Hexagon::S2_shuffob, dl, VecTy, {Op1, Op0}, DAG);
2376 switch (
Op.getOpcode()) {
2378 if (
SDValue S = cast<BuildVectorSDNode>(
Op)->getSplatValue())
2382 return Op.getOperand(0);
2392 switch (
Op.getOpcode()) {
2406 if (
SDValue Sp = getSplatValue(
Op.getOperand(1), DAG))
2419 if (
SDValue S = getVectorShiftByInt(
Op, DAG))
2433 MVT ResTy = ty(Res);
2441 auto ShiftPartI8 = [&dl, &DAG,
this](
unsigned Opc,
SDValue V,
SDValue A) {
2451 return ShiftPartI8(Opc, Val, Amt);
2453 auto [LoV, HiV] = opSplit(Val, dl, DAG);
2455 {ShiftPartI8(Opc, LoV, Amt), ShiftPartI8(Opc, HiV, Amt)});
2460 if (isa<ConstantSDNode>(
Op.getOperand(1).getNode()))
2469 MVT InpTy = ty(InpV);
2474 if (InpTy == MVT::i8) {
2475 if (ResTy == MVT::v8i1) {
2478 return getInstr(Hexagon::C2_tfrrp, dl, ResTy, Ext, DAG);
2493 bool AllConst =
true;
2495 for (
unsigned i = 0, e = Values.
size(); i != e; ++i) {
2498 Consts[i] = ConstantInt::get(IntTy, 0);
2502 if (
auto *CN = dyn_cast<ConstantSDNode>(V.getNode())) {
2503 const ConstantInt *CI = CN->getConstantIntValue();
2505 }
else if (
auto *CN = dyn_cast<ConstantFPSDNode>(
V.getNode())) {
2506 const ConstantFP *CF = CN->getConstantFPValue();
2508 Consts[i] = ConstantInt::get(IntTy,
A.getZExtValue());
2523 bool AllConst = getBuildVectorConstInts(Elem, VecTy, DAG, Consts);
2527 if (!isUndef(Elem[
First]))
2535 return getZero(dl, VecTy, DAG);
2537 if (ElemTy == MVT::i16 || ElemTy == MVT::f16) {
2542 uint32_t V = (Consts[0]->getZExtValue() & 0xFFFF) |
2543 Consts[1]->getZExtValue() << 16;
2547 if (ElemTy == MVT::f16) {
2554 SDValue N = getInstr(Hexagon::A2_combine_ll, dl, MVT::i32, {E1, E0}, DAG);
2558 if (ElemTy == MVT::i8) {
2561 uint32_t V = (Consts[0]->getZExtValue() & 0xFF) |
2562 (Consts[1]->getZExtValue() & 0xFF) << 8 |
2563 (Consts[2]->getZExtValue() & 0xFF) << 16 |
2564 Consts[3]->getZExtValue() << 24;
2569 bool IsSplat =
true;
2570 for (
unsigned i =
First+1; i != Num; ++i) {
2571 if (Elem[i] == Elem[
First] || isUndef(Elem[i]))
2587 for (
unsigned i = 0; i != 4; ++i) {
2597 SDValue R = getInstr(Hexagon::A2_combine_ll, dl, MVT::i32, {B1, B0}, DAG);
2602 dbgs() <<
"VecTy: " << VecTy <<
'\n';
2614 bool AllConst = getBuildVectorConstInts(Elem, VecTy, DAG, Consts);
2618 if (!isUndef(Elem[
First]))
2626 return getZero(dl, VecTy, DAG);
2629 if (ElemTy == MVT::i16 || ElemTy == MVT::f16) {
2630 bool IsSplat =
true;
2631 for (
unsigned i =
First+1; i != Num; ++i) {
2632 if (Elem[i] == Elem[
First] || isUndef(Elem[i]))
2651 for (
unsigned i = 0; i != Num; ++i)
2652 Val = (Val << W) | (Consts[Num-1-i]->getZExtValue() &
Mask);
2661 : buildVector32(Elem.
take_front(Num/2), dl, HalfTy, DAG);
2664 : buildVector32(Elem.
drop_front(Num/2), dl, HalfTy, DAG);
2665 return getCombine(
H, L, dl, VecTy, DAG);
2672 MVT VecTy = ty(VecV);
2676 return extractVectorPred(VecV, IdxV, dl, ValTy, ResTy, DAG);
2681 assert((VecWidth % ElemWidth) == 0);
2682 assert(VecWidth == 32 || VecWidth == 64);
2685 MVT ScalarTy = tyScalar(VecTy);
2691 if (
auto *IdxN = dyn_cast<ConstantSDNode>(IdxV)) {
2692 unsigned Off = IdxN->getZExtValue() * ElemWidth;
2693 if (VecWidth == 64 && ValWidth == 32) {
2694 assert(Off == 0 || Off == 32);
2695 ExtV =
Off == 0 ? LoHalf(VecV, DAG) : HiHalf(VecV, DAG);
2696 }
else if (Off == 0 && (ValWidth % 8) == 0) {
2703 {VecV, WidthV, OffV});
2706 if (ty(IdxV) != MVT::i32)
2711 {VecV, WidthV, OffV});
2721HexagonTargetLowering::extractVectorPred(
SDValue VecV,
SDValue IdxV,
2726 MVT VecTy = ty(VecV);
2730 "Vector elements should equal vector width size");
2731 assert(VecWidth == 8 || VecWidth == 4 || VecWidth == 2);
2742 if (ValWidth == 1) {
2743 SDValue A0 = getInstr(Hexagon::C2_tfrpr, dl, MVT::i32, {VecV}, DAG);
2753 unsigned Scale = VecWidth / ValWidth;
2757 assert(ty(IdxV) == MVT::i32);
2758 unsigned VecRep = 8 / VecWidth;
2766 T1 = LoHalf(T1, DAG);
2767 T1 = expandPredicate(T1, dl, DAG);
2778 MVT VecTy = ty(VecV);
2780 return insertVectorPred(VecV, ValV, IdxV, dl, ValTy, DAG);
2784 assert(VecWidth == 32 || VecWidth == 64);
2785 assert((VecWidth % ValWidth) == 0);
2801 unsigned W =
C->getZExtValue() * ValWidth;
2804 {VecV, ValV, WidthV, OffV});
2806 if (ty(IdxV) != MVT::i32)
2810 {VecV, ValV, WidthV, OffV});
2817HexagonTargetLowering::insertVectorPred(
SDValue VecV,
SDValue ValV,
2820 MVT VecTy = ty(VecV);
2823 if (ValTy == MVT::i1) {
2824 SDValue ToReg = getInstr(Hexagon::C2_tfrpr, dl, MVT::i32, {VecV}, DAG);
2830 return getInstr(Hexagon::C2_tfrrp, dl, VecTy, {
Ins}, DAG);
2841 for (
unsigned R = Scale;
R > 1;
R /= 2) {
2842 ValR = contractPredicate(ValR, dl, DAG);
2843 ValR = getCombine(DAG.
getUNDEF(MVT::i32), ValR, dl, MVT::i64, DAG);
2855HexagonTargetLowering::expandPredicate(
SDValue Vec32,
const SDLoc &dl,
2857 assert(ty(Vec32).getSizeInBits() == 32);
2866HexagonTargetLowering::contractPredicate(
SDValue Vec64,
const SDLoc &dl,
2868 assert(ty(Vec64).getSizeInBits() == 64);
2874 {0, 2, 4, 6, 1, 3, 5, 7});
2875 return extractVector(S, DAG.
getConstant(0, dl, MVT::i32), dl, MVT::v4i8,
2899 MVT ValTy = ty(Val);
2904 if (ValLen == ResLen)
2907 const SDLoc &dl(Val);
2909 assert(ResLen % ValLen == 0);
2912 for (
unsigned i = 1, e = ResLen / ValLen; i <
e; ++i)
2921 MVT ElemTy = ty(
Hi);
2950 return buildVector32(Ops, dl, VecTy, DAG);
2952 return buildVector64(Ops, dl, VecTy, DAG);
2954 if (VecTy == MVT::v8i1 || VecTy == MVT::v4i1 || VecTy == MVT::v2i1) {
2956 bool All0 =
true, All1 =
true;
2958 auto *CN = dyn_cast<ConstantSDNode>(
P.getNode());
2959 if (CN ==
nullptr) {
2960 All0 = All1 =
false;
2976 SDValue Z = getZero(dl, MVT::i32, DAG);
2979 for (
unsigned i = 0; i != 8; ++i) {
2981 Rs[i] = DAG.
getSelect(dl, MVT::i32, Ops[i/Rep], S, Z);
2984 for (
unsigned i = 0, e =
A.size()/2; i != e; ++i)
2988 return getInstr(Hexagon::C2_tfrrp, dl, VecTy, {Rs[0]}, DAG);
3001 return getCombine(
Op.getOperand(1),
Op.getOperand(0), dl, VecTy, DAG);
3005 if (ElemTy == MVT::i1) {
3006 assert(VecTy == MVT::v2i1 || VecTy == MVT::v4i1 || VecTy == MVT::v8i1);
3007 MVT OpTy = ty(
Op.getOperand(0));
3020 for (
SDValue P :
Op.getNode()->op_values()) {
3022 for (
unsigned R = Scale; R > 1; R /= 2) {
3023 W = contractPredicate(W, dl, DAG);
3024 W = getCombine(DAG.
getUNDEF(MVT::i32), W, dl, MVT::i64, DAG);
3032 Words[IdxW ^ 1].
clear();
3034 for (
unsigned i = 0, e = Words[IdxW].
size(); i != e; i += 2) {
3035 SDValue W0 = Words[IdxW][i], W1 = Words[IdxW][i+1];
3038 {W0, W1, WidthV, WidthV});
3046 assert(Scale == 2 && Words[IdxW].
size() == 2);
3048 SDValue WW = getCombine(Words[IdxW][1], Words[IdxW][0], dl, MVT::i64, DAG);
3060 return extractVector(Vec,
Op.getOperand(1),
SDLoc(
Op), ElemTy, ty(
Op), DAG);
3066 return extractVector(
Op.getOperand(0),
Op.getOperand(1),
SDLoc(
Op),
3067 ty(
Op), ty(
Op), DAG);
3073 return insertVector(
Op.getOperand(0),
Op.getOperand(1),
Op.getOperand(2),
3081 return insertVector(
Op.getOperand(0), ValV,
Op.getOperand(2),
3106 bool LoadPred = MemTy == MVT::v2i1 || MemTy == MVT::v4i1 || MemTy == MVT::v8i1;
3113 LN = cast<LoadSDNode>(NL.
getNode());
3117 if (!validateConstPtrAlignment(LN->
getBasePtr(), ClaimAlign, dl, DAG))
3118 return replaceMemWithUndef(
Op, DAG);
3124 SDValue TP = getInstr(Hexagon::C2_tfrrp, dl, MemTy, {LU}, DAG);
3143 if (Ty == MVT::v2i1 || Ty == MVT::v4i1 || Ty == MVT::v8i1) {
3145 SDValue TR = getInstr(Hexagon::C2_tfrpr, dl, MVT::i32, {Val}, DAG);
3152 SN = cast<StoreSDNode>(NS.getNode());
3156 if (!validateConstPtrAlignment(SN->
getBasePtr(), ClaimAlign, dl, DAG))
3157 return replaceMemWithUndef(
Op, DAG);
3161 if (ClaimAlign < NeedAlign)
3170 MVT LoadTy = ty(
Op);
3173 if (HaveAlign >= NeedAlign)
3182 bool DoDefault =
false;
3193 if (!DoDefault && (2 * HaveAlign) == NeedAlign) {
3212 unsigned LoadLen = NeedAlign;
3215 auto BO = getBaseAndOffset(
Base);
3216 unsigned BaseOpc = BO.first.getOpcode();
3220 if (BO.second % LoadLen != 0) {
3222 DAG.
getConstant(BO.second % LoadLen, dl, MVT::i32));
3223 BO.second -= BO.second % LoadLen;
3238 MMO->getPointerInfo(), MMO->getFlags(), 2 * LoadLen,
Align(LoadLen),
3239 MMO->getAAInfo(), MMO->getRanges(), MMO->getSyncScopeID(),
3240 MMO->getSuccessOrdering(), MMO->getFailureOrdering());
3257 auto *CY = dyn_cast<ConstantSDNode>(
Y);
3265 unsigned Opc =
Op.getOpcode();
3269 assert(VY != 0 &&
"This should have been folded");
3294 unsigned Opc =
Op.getOpcode();
3301 EVT CarryTy =
C.getValueType();
3303 { X, Y, DAG.getLogicalNOT(dl, C, CarryTy) });
3322 unsigned OffsetReg = Hexagon::R28;
3338 unsigned Opc =
Op.getOpcode();
3344 if (isHvxOperation(
Op.getNode(), DAG)) {
3346 if (
SDValue V = LowerHvxOperation(
Op, DAG))
3353 Op.getNode()->dumpr(&DAG);
3355 errs() <<
"Error: check for a non-legal type in this operation\n";
3409 if (isHvxOperation(
N, DAG)) {
3410 LowerHvxOperationWrapper(
N,
Results, DAG);
3416 unsigned Opc =
N->getOpcode();
3440 if (isHvxOperation(
N, DAG)) {
3441 ReplaceHvxNodeResults(
N,
Results, DAG);
3447 switch (
N->getOpcode()) {
3454 if (
N->getValueType(0) == MVT::i8) {
3455 if (
N->getOperand(0).getValueType() == MVT::v8i1) {
3456 SDValue P = getInstr(Hexagon::C2_tfrpr, dl, MVT::i32,
3457 N->getOperand(0), DAG);
3469 if (isHvxOperation(
N, DCI.
DAG)) {
3470 if (
SDValue V = PerformHvxDAGCombine(
N, DCI))
3477 unsigned Opc =
Op.getOpcode();
3483 EVT TruncTy =
Op.getValueType();
3499 switch (
P.getOpcode()) {
3503 return getZero(dl, ty(
Op), DCI.
DAG);
3516 Op.getOperand(2),
Op.getOperand(1));
3524 MVT TruncTy = ty(
Op);
3527 if (ty(Elem0) == TruncTy)
3530 if (ty(Elem0).bitsGT(TruncTy))
3537 if (ty(
Op) != MVT::i64)
3548 auto *Amt = dyn_cast<ConstantSDNode>(Shl.
getOperand(1));
3549 if (Amt && Amt->getZExtValue() >= 32 && ty(Z).getSizeInBits() <= 32) {
3550 unsigned A = Amt->getZExtValue();
3572 int Idx = cast<JumpTableSDNode>(Table)->getIndex();
3584 if (Constraint.
size() == 1) {
3585 switch (Constraint[0]) {
3600std::pair<unsigned, const TargetRegisterClass*>
3604 if (Constraint.
size() == 1) {
3605 switch (Constraint[0]) {
3609 return {0u,
nullptr};
3615 return {0u, &Hexagon::IntRegsRegClass};
3618 return {0u, &Hexagon::DoubleRegsRegClass};
3623 return {0u,
nullptr};
3624 return {0u, &Hexagon::ModRegsRegClass};
3628 return {0u,
nullptr};
3631 return {0u, &Hexagon::HvxQRRegClass};
3637 return {0u,
nullptr};
3639 return {0u, &Hexagon::HvxVRRegClass};
3642 return {0u, &Hexagon::HvxVRRegClass};
3643 return {0u, &Hexagon::HvxWRRegClass};
3645 return {0u, &Hexagon::HvxWRRegClass};
3649 return {0u,
nullptr};
3660 bool ForCodeSize)
const {
3690 int Scale = AM.
Scale;
3714 return Imm >= -512 && Imm <= 511;
3724 bool IsCalleeStructRet,
3725 bool IsCallerStructRet,
3732 bool CCMatch = CallerCC == CalleeCC;
3740 if (!isa<GlobalAddressSDNode>(Callee) &&
3741 !isa<ExternalSymbolSDNode>(Callee)) {
3761 if (IsCalleeStructRet || IsCallerStructRet)
3784 if (
Op.size() >= 8 &&
Op.isAligned(
Align(8)))
3786 if (
Op.size() >= 4 &&
Op.isAligned(
Align(4)))
3788 if (
Op.size() >= 2 &&
Op.isAligned(
Align(2)))
3798 return allowsHvxMemoryAccess(SVT, Flags,
Fast);
3800 Context,
DL, VT, AddrSpace, Alignment, Flags,
Fast);
3805 unsigned *
Fast)
const {
3808 return allowsHvxMisalignedMemoryAccesses(SVT, Flags,
Fast);
3814std::pair<const TargetRegisterClass*, uint8_t>
3822 return std::make_pair(&Hexagon::HvxQRRegClass, 1);
3824 return std::make_pair(&Hexagon::HvxVRRegClass, 1);
3826 return std::make_pair(&Hexagon::HvxWRRegClass, 1);
3838 auto *L = cast<LoadSDNode>(Load);
3839 std::pair<SDValue,int> BO = getBaseAndOffset(L->getBasePtr());
3845 const auto *GO = dyn_cast_or_null<const GlobalObject>(GA->getGlobal());
3853 AdjustHvxInstrPostInstrSelection(
MI, Node);
3860 assert((SZ == 32 || SZ == 64) &&
"Only 32/64-bit atomic loads supported");
3861 Intrinsic::ID IntID = (SZ == 32) ? Intrinsic::hexagon_L2_loadw_locked
3862 : Intrinsic::hexagon_L4_loadd_locked;
3881 assert((SZ == 32 || SZ == 64) &&
"Only 32/64-bit atomic stores supported");
3882 Intrinsic::ID IntID = (SZ == 32) ? Intrinsic::hexagon_S2_storew_locked
3883 : Intrinsic::hexagon_S4_stored_locked;
3905 return SI->getValueOperand()->getType()->getPrimitiveSizeInBits() > 64
unsigned const MachineRegisterInfo * MRI
This file implements a class to represent arbitrary precision integral constant values and operations...
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Function Alias Analysis Results
static void print(raw_ostream &Out, object::Archive::Kind Kind, T Val)
static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")
Analysis containing CSE Info
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
static cl::opt< int > MaxStoresPerMemcpyCL("max-store-memcpy", cl::Hidden, cl::init(6), cl::desc("Max #stores to inline memcpy"))
static Value * getUnderLyingObjectForBrevLdIntr(Value *V)
static bool CC_SkipOdd(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State)
static cl::opt< bool > AlignLoads("hexagon-align-loads", cl::Hidden, cl::init(false), cl::desc("Rewrite unaligned loads as a pair of aligned loads"))
static bool isBrevLdIntrinsic(const Value *Inst)
static cl::opt< int > MaxStoresPerMemmoveOptSizeCL("max-store-memmove-Os", cl::Hidden, cl::init(4), cl::desc("Max #stores to inline memmove"))
static cl::opt< int > MaxStoresPerMemmoveCL("max-store-memmove", cl::Hidden, cl::init(6), cl::desc("Max #stores to inline memmove"))
static Value * getBrevLdObject(Value *V)
static cl::opt< int > MaxStoresPerMemsetCL("max-store-memset", cl::Hidden, cl::init(8), cl::desc("Max #stores to inline memset"))
static cl::opt< bool > DisableArgsMinAlignment("hexagon-disable-args-min-alignment", cl::Hidden, cl::init(false), cl::desc("Disable minimum alignment of 1 for " "arguments passed by value on stack"))
static Value * returnEdge(const PHINode *PN, Value *IntrBaseVal)
static cl::opt< int > MaxStoresPerMemcpyOptSizeCL("max-store-memcpy-Os", cl::Hidden, cl::init(4), cl::desc("Max #stores to inline memcpy"))
static SDValue CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain, ISD::ArgFlagsTy Flags, SelectionDAG &DAG, const SDLoc &dl)
CreateCopyOfByValArgument - Make a copy of an aggregate at address specified by "Src" to address "Dst...
static cl::opt< int > MaxStoresPerMemsetOptSizeCL("max-store-memset-Os", cl::Hidden, cl::init(4), cl::desc("Max #stores to inline memset"))
static cl::opt< bool > EmitJumpTables("hexagon-emit-jump-tables", cl::init(true), cl::Hidden, cl::desc("Control jump table emission on Hexagon target"))
static cl::opt< int > MinimumJumpTables("minimum-jump-tables", cl::Hidden, cl::init(5), cl::desc("Set minimum jump tables"))
static cl::opt< bool > EnableHexSDNodeSched("enable-hexagon-sdnode-sched", cl::Hidden, cl::desc("Enable Hexagon SDNode scheduling"))
static cl::opt< bool > EnableFastMath("ffast-math", cl::Hidden, cl::desc("Enable Fast Math processing"))
#define Hexagon_PointerSize
#define HEXAGON_LRFP_SIZE
#define HEXAGON_GOT_SYM_NAME
Module.h This file contains the declarations for the Module class.
std::pair< MCSymbol *, MachineModuleInfoImpl::StubValueTy > PairTy
unsigned const TargetRegisterInfo * TRI
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
const SmallVectorImpl< MachineOperand > & Cond
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file defines the SmallVector class.
This file implements the StringSwitch template, which mimics a switch() statement whose cases are str...
APInt bitcastToAPInt() const
Class for arbitrary precision integers.
int64_t getSExtValue() const
Get sign extended value.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
ArrayRef< T > take_front(size_t N=1) const
Return a copy of *this with only the first N elements.
ArrayRef< T > drop_front(size_t N=1) const
Drop the first N elements of the array.
size_t size() const
size - Get the array size.
An instruction that atomically checks whether a specified value is in a memory location,...
LLVM Basic Block Representation.
const Function * getParent() const
Return the enclosing method, or null if none.
The address of a basic block.
CCState - This class holds information needed while lowering arguments and return values.
unsigned getFirstUnallocated(ArrayRef< MCPhysReg > Regs) const
getFirstUnallocated - Return the index of the first unallocated register in the set,...
void AnalyzeCallResult(const SmallVectorImpl< ISD::InputArg > &Ins, CCAssignFn Fn)
AnalyzeCallResult - Analyze the return values of a call, incorporating info about the passed values i...
MCRegister AllocateReg(MCPhysReg Reg)
AllocateReg - Attempt to allocate one register.
bool CheckReturn(const SmallVectorImpl< ISD::OutputArg > &Outs, CCAssignFn Fn)
CheckReturn - Analyze the return values of a function, returning true if the return can be performed ...
void AnalyzeReturn(const SmallVectorImpl< ISD::OutputArg > &Outs, CCAssignFn Fn)
AnalyzeReturn - Analyze the returned values of a return, incorporating info about the result values i...
CCValAssign - Represent assignment of one arg/retval to a location.
Register getLocReg() const
LocInfo getLocInfo() const
int64_t getLocMemOffset() const
FunctionType * getFunctionType() const
This class represents a function call, abstracting a target machine's calling convention.
ConstantFP - Floating Point Values [float, double].
const APFloat & getValueAPF() const
This is the shared class of boolean and integer constants.
bool isZero() const
This is just a convenience method to make client code smaller for a common code.
const APInt & getValue() const
Return the constant as an APInt value reference.
MachineConstantPoolValue * getMachineCPVal() const
bool isMachineConstantPoolEntry() const
const Constant * getConstVal() const
int64_t getSExtValue() const
static Constant * get(ArrayRef< Constant * > V)
This is an important base class in LLVM.
This class represents an Operation in the Expression.
uint64_t getNumOperands() const
A parsed version of the target data layout string in and methods for querying it.
This is the base abstract class for diagnostic reporting in the backend.
Interface for custom diagnostic printing.
unsigned getNumParams() const
Return the number of fixed parameters this function type requires.
bool hasOptSize() const
Optimize this function for size (-Os) or minimum size (-Oz).
FunctionType * getFunctionType() const
Returns the FunctionType for me.
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
bool hasStructRetAttr() const
Determine if the function returns a structure through first or second pointer argument.
int64_t getOffset() const
const GlobalValue * getGlobal() const
Module * getParent()
Get the module that this global value is contained inside of...
const GlobalObject * getAliaseeObject() const
bool isValidAutoIncImm(const EVT VT, const int Offset) const
Hexagon target-specific information for each MachineFunction.
int getVarArgsFrameIndex()
void setFirstNamedArgFrameIndex(int v)
void setHasEHReturn(bool H=true)
Register getStackRegister() const
Register getFrameRegister(const MachineFunction &MF) const override
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const override
const HexagonInstrInfo * getInstrInfo() const override
const HexagonFrameLowering * getFrameLowering() const override
bool useSmallData() const
const HexagonRegisterInfo * getRegisterInfo() const override
bool isHVXVectorType(EVT VecTy, bool IncludeBool=false) const
Align getTypeAlignment(MVT Ty) const
unsigned getVectorLength() const
bool useHVX128BOps() const
bool isEnvironmentMusl() const
SDValue getPICJumpTableRelocBase(SDValue Table, SelectionDAG &DAG) const override
Returns relocation base for the given PIC jumptable.
SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const
SDValue LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG) const
bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, LLVMContext &Context) const override
This hook should be implemented to check whether the return values described by the Outs array can fi...
SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const
void AdjustInstrPostInstrSelection(MachineInstr &MI, SDNode *Node) const override
This method should be implemented by targets that mark instructions with the 'hasPostISelHook' flag.
bool isTargetCanonicalConstantNode(SDValue Op) const override
Returns true if the given Opc is considered a canonical constant for the target, which should not be ...
ConstraintType getConstraintType(StringRef Constraint) const override
Given a constraint, return the type of constraint it is for this target.
bool isTruncateFree(Type *Ty1, Type *Ty2) const override
Return true if it's free to truncate a value of type FromTy to type ToTy.
SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const
EVT getOptimalMemOpType(const MemOp &Op, const AttributeList &FuncAttributes) const override
Returns the target specific optimal type for load and store operations as a result of memset,...
SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const
SDValue LowerUAddSubO(SDValue Op, SelectionDAG &DAG) const
Value * emitLoadLinked(IRBuilderBase &Builder, Type *ValueTy, Value *Addr, AtomicOrdering Ord) const override
Perform a load-linked operation on Addr, returning a "Value *" with the corresponding pointee type.
bool isLegalICmpImmediate(int64_t Imm) const override
isLegalICmpImmediate - Return true if the specified immediate is legal icmp immediate,...
bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS, Instruction *I=nullptr) const override
isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target...
SDValue LowerINLINEASM(SDValue Op, SelectionDAG &DAG) const
AtomicExpansionKind shouldExpandAtomicStoreInIR(StoreInst *SI) const override
Returns how the given (atomic) store should be expanded by the IR-level AtomicExpand pass into.
SDValue GetDynamicTLSAddr(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA, SDValue InGlue, EVT PtrVT, unsigned ReturnReg, unsigned char OperandGlues) const
SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SDLoc &dl, SelectionDAG &DAG) const override
This hook must be implemented to lower outgoing return values, described by the Outs array,...
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const
bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) const override
Returns true by value, base pointer and offset pointer and addressing mode by reference if this node ...
SDValue LowerUnalignedLoad(SDValue Op, SelectionDAG &DAG) const
SDValue LowerFDIV(SDValue Op, SelectionDAG &DAG) const
SDValue LowerVACOPY(SDValue Op, SelectionDAG &DAG) const
SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower the incoming (formal) arguments, described by the Ins array,...
bool isFPImmLegal(const APFloat &Imm, EVT VT, bool ForCodeSize) const override
isFPImmLegal - Returns true if the target can instruction select the specified FP immediate natively.
bool mayBeEmittedAsTailCall(const CallInst *CI) const override
Return true if the target may be able emit the call instruction as a tail call.
AtomicExpansionKind shouldExpandAtomicLoadInIR(LoadInst *LI) const override
Returns how the given (atomic) load should be expanded by the IR-level AtomicExpand pass.
SDValue LowerCallResult(SDValue Chain, SDValue InGlue, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals, const SmallVectorImpl< SDValue > &OutVals, SDValue Callee) const
LowerCallResult - Lower the result values of an ISD::CALL into the appropriate copies out of appropri...
SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const
SDValue LowerToTLSInitialExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG) const
SDValue LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA, SelectionDAG &DAG) const
bool allowsMemoryAccess(LLVMContext &Context, const DataLayout &DL, EVT VT, unsigned AddrSpace, Align Alignment, MachineMemOperand::Flags Flags, unsigned *Fast) const override
Return true if the target supports a memory access of this type for the given address space and align...
SDValue LowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const
bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT, unsigned Index) const override
Return true if EXTRACT_SUBVECTOR is cheap for extracting this result type from this source type with ...
SDValue LowerROTL(SDValue Op, SelectionDAG &DAG) const
SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const
SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const
SDValue LowerLoad(SDValue Op, SelectionDAG &DAG) const
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
bool isShuffleMaskLegal(ArrayRef< int > Mask, EVT VT) const override
Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations,...
LegalizeAction getCustomOperationAction(SDNode &Op) const override
How to legalize this custom operation?
SDValue LowerToTLSLocalExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG) const
SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const
bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override
Return true if a truncation from FromTy to ToTy is permitted when deciding whether a call is in tail ...
SDValue LowerUAddSubOCarry(SDValue Op, SelectionDAG &DAG) const
bool shouldExpandBuildVectorWithShuffles(EVT VT, unsigned DefinedValues) const override
SDValue LowerREADCYCLECOUNTER(SDValue Op, SelectionDAG &DAG) const
SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const
SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals) const override
LowerCall - Functions arguments are copied from virtual regs to (physical regs)/(stack frame),...
bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace, Align Alignment, MachineMemOperand::Flags Flags, unsigned *Fast) const override
Determine if the target supports unaligned memory accesses.
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
SDValue LowerStore(SDValue Op, SelectionDAG &DAG) const
SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG) const
SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
This callback is invoked when a node result type is illegal for the target, and the operation was reg...
Value * emitStoreConditional(IRBuilderBase &Builder, Value *Val, Value *Addr, AtomicOrdering Ord) const override
Perform a store-conditional operation to Addr.
bool hasBitTest(SDValue X, SDValue Y) const override
Return true if the target has a bit-test instruction: (X & (1 << Y)) ==/!= 0 This knowledge can be us...
HexagonTargetLowering(const TargetMachine &TM, const HexagonSubtarget &ST)
SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const
bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override
Return true if folding a constant offset with the given GlobalAddress is legal.
bool IsEligibleForTailCallOptimization(SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg, bool isCalleeStructRet, bool isCallerStructRet, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SmallVectorImpl< ISD::InputArg > &Ins, SelectionDAG &DAG) const
IsEligibleForTailCallOptimization - Check whether the call is eligible for tail call optimization.
SDValue LowerVSELECT(SDValue Op, SelectionDAG &DAG) const
void LowerOperationWrapper(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
This callback is invoked by the type legalizer to legalize nodes with an illegal operand type but leg...
SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const
SDValue LowerVECTOR_SHIFT(SDValue Op, SelectionDAG &DAG) const
SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const
SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const
bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I, MachineFunction &MF, unsigned Intrinsic) const override
Given an intrinsic, checks if on the target the intrinsic will need to map to a MemIntrinsicNode (tou...
AtomicExpansionKind shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const override
Returns how the given atomic cmpxchg should be expanded by the IR-level AtomicExpand pass.
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
SDValue LowerBITCAST(SDValue Op, SelectionDAG &DAG) const
bool isFMAFasterThanFMulAndFAdd(const MachineFunction &, EVT) const override
Return true if an FMA operation is faster than a pair of mul and add instructions.
SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const
SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const
LegalizeTypeAction getPreferredVectorAction(MVT VT) const override
Return the preferred vector type legalization action.
SDValue LowerGLOBALADDRESS(SDValue Op, SelectionDAG &DAG) const
Register getRegisterByName(const char *RegName, LLT VT, const MachineFunction &MF) const override
Return the register ID of the name passed in.
SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const
bool shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtTy, EVT NewVT) const override
Return true if it is profitable to reduce a load to a smaller type.
SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG) const
SDValue LowerREADSTEADYCOUNTER(SDValue Op, SelectionDAG &DAG) const
HexagonTargetObjectFile * getObjFileLowering() const override
bool isGlobalInSmallSection(const GlobalObject *GO, const TargetMachine &TM) const
Return true if this global value should be placed into small data/bss section.
Common base class shared among various IRBuilders.
IntegerType * getIntNTy(unsigned N)
Fetch the type representing an N-bit integer.
CallInst * CreateIntrinsic(Intrinsic::ID ID, ArrayRef< Type * > Types, ArrayRef< Value * > Args, Instruction *FMFSource=nullptr, const Twine &Name="")
Create a call to intrinsic ID with Args, mangled using Types.
ConstantInt * getInt8(uint8_t C)
Get a constant 8-bit value.
BasicBlock * GetInsertBlock() const
ConstantInt * getInt32(uint32_t C)
Get a constant 32-bit value.
Value * CreateICmpEQ(Value *LHS, Value *RHS, const Twine &Name="")
Value * CreateBitCast(Value *V, Type *DestTy, const Twine &Name="")
Value * CreateZExt(Value *V, Type *DestTy, const Twine &Name="", bool IsNonNeg=false)
This provides a uniform API for creating instructions and inserting them into a basic block: either a...
Class to represent integer types.
static IntegerType * get(LLVMContext &C, unsigned NumBits)
This static method is the primary way of constructing an IntegerType.
This is an important class for using LLVM in a threaded context.
void diagnose(const DiagnosticInfo &DI)
Report a message to the currently installed diagnostic handler.
Base class for LoadSDNode and StoreSDNode.
ISD::MemIndexedMode getAddressingMode() const
Return the addressing mode for this load or store: unindexed, pre-inc, pre-dec, post-inc,...
bool isUnindexed() const
Return true if this is NOT a pre/post inc/dec load/store.
bool isIndexed() const
Return true if this is a pre/post inc/dec load/store.
An instruction for reading from memory.
This class is used to represent ISD::LOAD nodes.
const SDValue & getBasePtr() const
const SDValue & getOffset() const
ISD::LoadExtType getExtensionType() const
Return whether this is a plain node, or one of the varieties of value-extending loads.
unsigned getVectorMinNumElements() const
Given a vector type, return the minimum number of elements it contains.
unsigned getVectorNumElements() const
bool isVector() const
Return true if this is a vector value type.
bool isInteger() const
Return true if this is an integer or a vector integer type.
bool isScalableVector() const
Return true if this is a vector value type where the runtime length is machine dependent.
static MVT getVT(Type *Ty, bool HandleUnknown=false)
Return the value type corresponding to the specified type.
static auto integer_valuetypes()
TypeSize getSizeInBits() const
Returns the size of the specified MVT in bits.
static auto fixedlen_vector_valuetypes()
bool isScalarInteger() const
Return true if this is an integer, not including vectors.
TypeSize getStoreSizeInBits() const
Return the number of bits overwritten by a store of the specified value type.
static MVT getVectorVT(MVT VT, unsigned NumElements)
MVT getVectorElementType() const
bool isFloatingPoint() const
Return true if this is a FP or a vector FP type.
static MVT getIntegerVT(unsigned BitWidth)
static auto fp_valuetypes()
void print(raw_ostream &OS, const SlotIndexes *=nullptr, bool IsStandalone=true) const
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool IsImmutable, bool isAliased=false)
Create a new object at a fixed location on the stack.
void setAdjustsStack(bool V)
void ensureMaxAlignment(Align Alignment)
Make sure the function is at least Align bytes aligned.
void setFrameAddressIsTaken(bool T)
void setHasTailCall(bool V=true)
void setReturnAddressIsTaken(bool s)
unsigned getNumFixedObjects() const
Return the number of fixed objects.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, LLT MemTy, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
Function & getFunction()
Return the LLVM function that this machine code represents.
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Register addLiveIn(MCRegister PReg, const TargetRegisterClass *RC)
addLiveIn - Add the specified physical register as a live-in value and create a corresponding virtual...
Representation of each machine instruction.
A description of a memory reference used in the backend.
Flags
Flags values. These may be or'd together.
@ MOVolatile
The memory access is volatile.
@ MOLoad
The memory access reads data.
@ MOStore
The memory access writes data.
Flags getFlags() const
Return the raw flags of the source value,.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
const MDNode * getRanges() const
Returns the Ranges that describes the dereference.
AAMDNodes getAAInfo() const
Returns the AA info that describes the dereference.
MachineMemOperand * getMemOperand() const
Return a MachineMemOperand object describing the memory reference performed by operation.
const MachinePointerInfo & getPointerInfo() const
const SDValue & getChain() const
EVT getMemoryVT() const
Return the type of the in-memory value.
A Module instance is used to store all the information related to an LLVM module.
MutableArrayRef - Represent a mutable reference to an array (0 or more elements consecutively in memo...
unsigned getOpcode() const
Return the opcode for this Instruction or ConstantExpr.
BasicBlock * getIncomingBlock(unsigned i) const
Return incoming basic block number i.
Value * getIncomingValue(unsigned i) const
Return incoming value number x.
unsigned getNumIncomingValues() const
Return the number of incoming edges.
Wrapper class representing virtual and physical registers.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
const DebugLoc & getDebugLoc() const
Represents one node in the SelectionDAG.
EVT getValueType(unsigned ResNo) const
Return the type of a specified result.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
SDNode * getNode() const
get the SDNode which holds the desired result
SDValue getValue(unsigned R) const
EVT getValueType() const
Return the ValueType of the referenced return value.
const SDValue & getOperand(unsigned i) const
unsigned getOpcode() const
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
SDValue getTargetGlobalAddress(const GlobalValue *GV, const SDLoc &DL, EVT VT, int64_t offset=0, unsigned TargetFlags=0)
const TargetSubtargetInfo & getSubtarget() const
SDValue getCopyToReg(SDValue Chain, const SDLoc &dl, Register Reg, SDValue N)
SDValue getMergeValues(ArrayRef< SDValue > Ops, const SDLoc &dl)
Create a MERGE_VALUES node from the given operands.
SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
SDValue getMemcpy(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, Align Alignment, bool isVol, bool AlwaysInline, const CallInst *CI, std::optional< bool > OverrideTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo, const AAMDNodes &AAInfo=AAMDNodes(), AAResults *AA=nullptr)
SDValue getSetCC(const SDLoc &DL, EVT VT, SDValue LHS, SDValue RHS, ISD::CondCode Cond, SDValue Chain=SDValue(), bool IsSignaling=false)
Helper function to make it easier to build SetCC's if you just have an ISD::CondCode instead of an SD...
SDValue getConstantFP(double Val, const SDLoc &DL, EVT VT, bool isTarget=false)
Create a ConstantFPSDNode wrapping a constant value.
SDValue getRegister(Register Reg, EVT VT)
SDValue getLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, MaybeAlign Alignment=MaybeAlign(), MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
Loads are not normal binary operators: their result type is not determined by their operands,...
SDValue getGLOBAL_OFFSET_TABLE(EVT VT)
Return a GLOBAL_OFFSET_TABLE node. This does not have a useful SDLoc.
SDValue getTargetJumpTable(int JTI, EVT VT, unsigned TargetFlags=0)
SDValue getUNDEF(EVT VT)
Return an UNDEF node. UNDEF does not have a useful SDLoc.
SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2, SDValue InGlue, const SDLoc &DL)
Return a new CALLSEQ_END node, which always must have a glue result (to ensure it's not CSE'd).
SDValue getBitcast(EVT VT, SDValue V)
Return a bitcast using the SDLoc of the value operand, and casting to the provided type.
SDValue getCopyFromReg(SDValue Chain, const SDLoc &dl, Register Reg, EVT VT)
SDValue getSelect(const SDLoc &DL, EVT VT, SDValue Cond, SDValue LHS, SDValue RHS, SDNodeFlags Flags=SDNodeFlags())
Helper function to make it easier to build Select's if you just have operands and don't want to check...
SDValue getZeroExtendInReg(SDValue Op, const SDLoc &DL, EVT VT)
Return the expression required to zero extend the Op value assuming it was the smaller SrcTy value.
const DataLayout & getDataLayout() const
SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
Create a ConstantSDNode wrapping a constant value.
SDValue getMemBasePlusOffset(SDValue Base, TypeSize Offset, const SDLoc &DL, const SDNodeFlags Flags=SDNodeFlags())
Returns sum of the base pointer and offset.
SDValue getTruncStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, EVT SVT, Align Alignment, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
SDValue getStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, Align Alignment, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
Helper function to build ISD::STORE nodes.
SDValue getCALLSEQ_START(SDValue Chain, uint64_t InSize, uint64_t OutSize, const SDLoc &DL)
Return a new CALLSEQ_START node, that starts new call frame, in which InSize bytes are set up inside ...
SDValue getSExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT)
Convert Op, which must be of integer type, to the integer type VT, by either sign-extending or trunca...
SDValue getIndexedStore(SDValue OrigStore, const SDLoc &dl, SDValue Base, SDValue Offset, ISD::MemIndexedMode AM)
SDValue getAnyExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT)
Convert Op, which must be of integer type, to the integer type VT, by either any-extending or truncat...
SDValue getIntPtrConstant(uint64_t Val, const SDLoc &DL, bool isTarget=false)
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
SDValue getTargetBlockAddress(const BlockAddress *BA, EVT VT, int64_t Offset=0, unsigned TargetFlags=0)
void ReplaceAllUsesOfValueWith(SDValue From, SDValue To)
Replace any uses of From with To, leaving uses of other values produced by From.getNode() alone.
MachineFunction & getMachineFunction() const
SDValue getFrameIndex(int FI, EVT VT, bool isTarget=false)
SDValue getRegisterMask(const uint32_t *RegMask)
SDValue getZExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT)
Convert Op, which must be of integer type, to the integer type VT, by either zero-extending or trunca...
LLVMContext * getContext() const
SDValue getTargetExternalSymbol(const char *Sym, EVT VT, unsigned TargetFlags=0)
SDValue getTargetConstantPool(const Constant *C, EVT VT, MaybeAlign Align=std::nullopt, int Offset=0, unsigned TargetFlags=0)
SDValue getEntryNode() const
Return the token chain corresponding to the entry of the function.
SDValue getVectorShuffle(EVT VT, const SDLoc &dl, SDValue N1, SDValue N2, ArrayRef< int > Mask)
Return an ISD::VECTOR_SHUFFLE node.
SDValue getLogicalNOT(const SDLoc &DL, SDValue Val, EVT VT)
Create a logical NOT operation as (XOR Val, BooleanOne).
static void commuteMask(MutableArrayRef< int > Mask)
Change values in a shuffle permute mask assuming the two vector operands have swapped position.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
An instruction for storing to memory.
This class is used to represent ISD::STORE nodes.
const SDValue & getBasePtr() const
const SDValue & getOffset() const
const SDValue & getValue() const
StringRef - Represent a constant reference to a string, i.e.
constexpr size_t size() const
size - Get the string size.
A switch()-like statement whose cases are string literals.
StringSwitch & Case(StringLiteral S, T Value)
void setBooleanVectorContents(BooleanContent Ty)
Specify how the target extends the result of a vector boolean value from a vector of i1 to a wider ty...
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
Indicate that the specified operation does not work with the specified type and indicate what to do a...
LegalizeAction
This enum indicates whether operations are valid for a target, and if not, what action should be used...
unsigned MaxStoresPerMemcpyOptSize
Likewise for functions with the OptSize attribute.
virtual const TargetRegisterClass * getRegClassFor(MVT VT, bool isDivergent=false) const
Return the register class that should be used for the specified value type.
const TargetMachine & getTargetMachine() const
LegalizeTypeAction
This enum indicates whether a types are legal for a target, and if not, what action should be used to...
void setIndexedLoadAction(ArrayRef< unsigned > IdxModes, MVT VT, LegalizeAction Action)
Indicate that the specified indexed load does or does not work with the specified type and indicate w...
void setPrefLoopAlignment(Align Alignment)
Set the target's preferred loop alignment.
void setMaxAtomicSizeInBitsSupported(unsigned SizeInBits)
Set the maximum atomic operation size supported by the backend.
void setMinFunctionAlignment(Align Alignment)
Set the target's minimum function alignment.
unsigned MaxStoresPerMemsetOptSize
Likewise for functions with the OptSize attribute.
void setBooleanContents(BooleanContent Ty)
Specify how the target extends the result of integer and floating point boolean values from i1 to a w...
unsigned MaxStoresPerMemmove
Specify maximum number of store instructions per memmove call.
void computeRegisterProperties(const TargetRegisterInfo *TRI)
Once all of the register classes are added, this allows us to compute derived properties we expose.
unsigned MaxStoresPerMemmoveOptSize
Likewise for functions with the OptSize attribute.
void addRegisterClass(MVT VT, const TargetRegisterClass *RC)
Add the specified register class as an available regclass for the specified value type.
void setIndexedStoreAction(ArrayRef< unsigned > IdxModes, MVT VT, LegalizeAction Action)
Indicate that the specified indexed store does or does not work with the specified type and indicate ...
virtual MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
void setLibcallName(RTLIB::Libcall Call, const char *Name)
Rename the default libcall routine name for the specified libcall.
void setPrefFunctionAlignment(Align Alignment)
Set the target's preferred function alignment.
unsigned MaxStoresPerMemset
Specify maximum number of store instructions per memset call.
virtual bool shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtTy, EVT NewVT) const
Return true if it is profitable to reduce a load to a smaller type.
void setMinimumJumpTableEntries(unsigned Val)
Indicate the minimum number of blocks to generate jump tables.
void setTruncStoreAction(MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified truncating store does not work with the specified type and indicate what ...
@ UndefinedBooleanContent
bool isOperationLegalOrCustom(unsigned Op, EVT VT, bool LegalOnly=false) const
Return true if the specified operation is legal on this target or can be made legal with custom lower...
virtual bool allowsMemoryAccess(LLVMContext &Context, const DataLayout &DL, EVT VT, unsigned AddrSpace=0, Align Alignment=Align(1), MachineMemOperand::Flags Flags=MachineMemOperand::MONone, unsigned *Fast=nullptr) const
Return true if the target supports a memory access of this type for the given address space and align...
void setMinCmpXchgSizeInBits(unsigned SizeInBits)
Sets the minimum cmpxchg or ll/sc size supported by the backend.
void setStackPointerRegisterToSaveRestore(Register R)
If set to a physical register, this specifies the register that llvm.savestack/llvm....
void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT)
If Opc/OrigVT is specified as being promoted, the promotion code defaults to trying a larger integer/...
AtomicExpansionKind
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
void setCondCodeAction(ArrayRef< ISD::CondCode > CCs, MVT VT, LegalizeAction Action)
Indicate that the specified condition code is or isn't supported on the target and indicate what to d...
virtual std::pair< const TargetRegisterClass *, uint8_t > findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT) const
Return the largest legal super-reg register class of the register class for the specified type and it...
void setTargetDAGCombine(ArrayRef< ISD::NodeType > NTs)
Targets should invoke this method for each target independent node that they want to provide a custom...
void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified load with extension does not work with the specified type and indicate wh...
bool allowsMemoryAccessForAlignment(LLVMContext &Context, const DataLayout &DL, EVT VT, unsigned AddrSpace=0, Align Alignment=Align(1), MachineMemOperand::Flags Flags=MachineMemOperand::MONone, unsigned *Fast=nullptr) const
This function returns true if the memory access is aligned or if the target allows this specific unal...
unsigned MaxStoresPerMemcpy
Specify maximum number of store instructions per memcpy call.
void setSchedulingPreference(Sched::Preference Pref)
Specify the target scheduling preference.
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
virtual bool isTargetCanonicalConstantNode(SDValue Op) const
Returns true if the given Opc is considered a canonical constant for the target, which should not be ...
SDValue expandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG) const
Expands an unaligned store to 2 half-size stores for integer values, and possibly more for vectors.
virtual ConstraintType getConstraintType(StringRef Constraint) const
Given a constraint, return the type of constraint it is for this target.
std::pair< SDValue, SDValue > expandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG) const
Expands an unaligned load to 2 half-size loads for an integer, and possibly more for vectors.
bool isPositionIndependent() const
virtual std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const
Given a physical register constraint (e.g.
bool verifyReturnAddressArgumentIsConstant(SDValue Op, SelectionDAG &DAG) const
virtual void LowerOperationWrapper(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const
This callback is invoked by the type legalizer to legalize nodes with an illegal operand type but leg...
Primary interface to the complete machine description for the target machine.
TLSModel::Model getTLSModel(const GlobalValue *GV) const
Returns the TLS model which should be used for the given global variable.
Reloc::Model getRelocationModel() const
Returns the code generation relocation model.
bool shouldAssumeDSOLocal(const GlobalValue *GV) const
unsigned getID() const
Return the register class ID number.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
static constexpr TypeSize getFixed(ScalarTy ExactSize)
The instances of the Type class are immutable: once they are created, they are never changed.
bool isSized(SmallPtrSetImpl< Type * > *Visited=nullptr) const
Return true if it makes sense to take the size of this type.
static IntegerType * getInt32Ty(LLVMContext &C)
bool isIntegerTy() const
True if this is an instance of IntegerType.
TypeSize getPrimitiveSizeInBits() const LLVM_READONLY
Return the basic size of this type if it is a primitive type.
LLVM Value Representation.
Type * getType() const
All values are typed, get the type of this value.
const ParentTy * getParent() const
A raw_ostream that writes to an std::string.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
@ Fast
Attempts to make calls as fast as possible (e.g.
@ C
The default llvm calling convention, compatible with C.
@ MO_PCREL
MO_PCREL - On a symbol operand, indicates a PC-relative relocation Used for computing a global addres...
@ MO_GOT
MO_GOT - Indicates a GOT-relative relocation.
@ SETCC
SetCC operator - This evaluates to a true value iff the condition is true.
@ STACKRESTORE
STACKRESTORE has two operands, an input chain and a pointer to restore to it returns an output chain.
@ STACKSAVE
STACKSAVE - STACKSAVE has one operand, an input chain.
@ SMUL_LOHI
SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing a signed/unsigned value of type i[2...
@ INSERT_SUBVECTOR
INSERT_SUBVECTOR(VECTOR1, VECTOR2, IDX) - Returns a vector with VECTOR2 inserted into VECTOR1.
@ BSWAP
Byte Swap and Counting operators.
@ VAEND
VAEND, VASTART - VAEND and VASTART have three operands: an input chain, pointer, and a SRCVALUE.
@ ADD
Simple integer binary arithmetic operators.
@ LOAD
LOAD and STORE have token chains as their first operand, then the same operands as an LLVM load/store...
@ ANY_EXTEND
ANY_EXTEND - Used for integer types. The high bits are undefined.
@ FMA
FMA - Perform a * b + c with no intermediate rounding step.
@ INTRINSIC_VOID
OUTCHAIN = INTRINSIC_VOID(INCHAIN, INTRINSICID, arg1, arg2, ...) This node represents a target intrin...
@ SINT_TO_FP
[SU]INT_TO_FP - These operators convert integers (whose interpreted sign depends on the first letter)...
@ CONCAT_VECTORS
CONCAT_VECTORS(VECTOR0, VECTOR1, ...) - Given a number of values of vector type with the same length ...
@ FADD
Simple binary floating point operators.
@ ABS
ABS - Determine the unsigned absolute value of a signed integer value of the same bitwidth.
@ ATOMIC_FENCE
OUTCHAIN = ATOMIC_FENCE(INCHAIN, ordering, scope) This corresponds to the fence instruction.
@ SDIVREM
SDIVREM/UDIVREM - Divide two integers and produce both a quotient and remainder result.
@ FP16_TO_FP
FP16_TO_FP, FP_TO_FP16 - These operators are used to perform promotions and truncation for half-preci...
@ BITCAST
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
@ BUILD_PAIR
BUILD_PAIR - This is the opposite of EXTRACT_ELEMENT in some ways.
@ FLDEXP
FLDEXP - ldexp, inspired by libm (op0 * 2**op1).
@ EH_RETURN
OUTCHAIN = EH_RETURN(INCHAIN, OFFSET, HANDLER) - This node represents 'eh_return' gcc dwarf builtin,...
@ SIGN_EXTEND
Conversion operators.
@ SCALAR_TO_VECTOR
SCALAR_TO_VECTOR(VAL) - This represents the operation of loading a scalar value into element 0 of the...
@ READSTEADYCOUNTER
READSTEADYCOUNTER - This corresponds to the readfixedcounter intrinsic.
@ PREFETCH
PREFETCH - This corresponds to a prefetch intrinsic.
@ FSINCOS
FSINCOS - Compute both fsin and fcos as a single operation.
@ FNEG
Perform various unary floating-point operations inspired by libm.
@ BR_CC
BR_CC - Conditional branch.
@ SSUBO
Same for subtraction.
@ BR_JT
BR_JT - Jumptable branch.
@ SELECT
Select(COND, TRUEVAL, FALSEVAL).
@ SPLAT_VECTOR
SPLAT_VECTOR(VAL) - Returns a vector with the scalar value VAL duplicated in all lanes.
@ VACOPY
VACOPY - VACOPY has 5 operands: an input chain, a destination pointer, a source pointer,...
@ SADDO
RESULT, BOOL = [SU]ADDO(LHS, RHS) - Overflow-aware nodes for addition.
@ SHL
Shift and rotation operations.
@ VECTOR_SHUFFLE
VECTOR_SHUFFLE(VEC1, VEC2) - Returns a vector, of the same type as VEC1/VEC2.
@ EXTRACT_SUBVECTOR
EXTRACT_SUBVECTOR(VECTOR, IDX) - Returns a subvector from VECTOR.
@ EXTRACT_VECTOR_ELT
EXTRACT_VECTOR_ELT(VECTOR, IDX) - Returns a single element from VECTOR identified by the (potentially...
@ ZERO_EXTEND
ZERO_EXTEND - Used for integer types, zeroing the new bits.
@ DEBUGTRAP
DEBUGTRAP - Trap intended to get the attention of a debugger.
@ SELECT_CC
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
@ FMINNUM
FMINNUM/FMAXNUM - Perform floating-point minimum or maximum on two values.
@ DYNAMIC_STACKALLOC
DYNAMIC_STACKALLOC - Allocate some number of bytes on the stack aligned to a specified boundary.
@ SIGN_EXTEND_INREG
SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to sign extend a small value in ...
@ SMIN
[US]{MIN/MAX} - Binary minimum or maximum of signed or unsigned integers.
@ GLOBAL_OFFSET_TABLE
The address of the GOT.
@ VSELECT
Select with a vector condition (op #0) and two vector operands (ops #1 and #2), returning a vector re...
@ UADDO_CARRY
Carry-using nodes for multiple precision addition and subtraction.
@ INLINEASM_BR
INLINEASM_BR - Branching version of inline asm. Used by asm-goto.
@ FRAMEADDR
FRAMEADDR, RETURNADDR - These nodes represent llvm.frameaddress and llvm.returnaddress on the DAG.
@ FP_TO_SINT
FP_TO_[US]INT - Convert a floating point value to a signed or unsigned integer.
@ READCYCLECOUNTER
READCYCLECOUNTER - This corresponds to the readcyclecounter intrinsic.
@ AND
Bitwise operators - logical and, logical or, logical xor.
@ TRAP
TRAP - Trapping instruction.
@ INTRINSIC_WO_CHAIN
RESULT = INTRINSIC_WO_CHAIN(INTRINSICID, arg1, arg2, ...) This node represents a target intrinsic fun...
@ INSERT_VECTOR_ELT
INSERT_VECTOR_ELT(VECTOR, VAL, IDX) - Returns VECTOR with the element at IDX replaced with VAL.
@ TokenFactor
TokenFactor - This node takes multiple tokens as input and produces a single token result.
@ INLINEASM
INLINEASM - Represents an inline asm block.
@ TRUNCATE
TRUNCATE - Completely drop the high bits.
@ VAARG
VAARG - VAARG has four operands: an input chain, a pointer, a SRCVALUE, and the alignment.
@ SHL_PARTS
SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded integer shift operations.
@ AssertSext
AssertSext, AssertZext - These nodes record if a register contains a value that has already been zero...
@ FCOPYSIGN
FCOPYSIGN(X, Y) - Return the value of X with the sign of Y.
@ INTRINSIC_W_CHAIN
RESULT,OUTCHAIN = INTRINSIC_W_CHAIN(INCHAIN, INTRINSICID, arg1, ...) This node represents a target in...
@ BUILD_VECTOR
BUILD_VECTOR(ELT0, ELT1, ELT2, ELT3,...) - Return a fixed-width vector with the specified,...
MemIndexedMode
MemIndexedMode enum - This enum defines the load / store indexed addressing modes.
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...
LoadExtType
LoadExtType enum - This enum defines the three variants of LOADEXT (load with extension).
initializer< Ty > init(const Ty &Val)
This is an optimization pass for GlobalISel generic memory operations.
bool all_of(R &&range, UnaryPredicate P)
Provide wrappers to std::all_of which take ranges instead of having to pass begin/end explicitly.
auto size(R &&Range, std::enable_if_t< std::is_base_of< std::random_access_iterator_tag, typename std::iterator_traits< decltype(Range.begin())>::iterator_category >::value, void > *=nullptr)
Get the size of a range.
bool isNullConstant(SDValue V)
Returns true if V is a constant integer zero.
bool isAligned(Align Lhs, uint64_t SizeInBytes)
Checks that SizeInBytes is a multiple of the alignment.
int countr_zero(T Val)
Count number of 0's from the least significant bit to the most stopping at the first 1.
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
FormattedNumber format_hex(uint64_t N, unsigned Width, bool Upper=false)
format_hex - Output N as a fixed width hexadecimal.
raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.
AtomicOrdering
Atomic ordering for LLVM's memory model.
@ First
Helpers to iterate all locations in the MemoryEffectsBase class.
DWARFExpression::Operation Op
int getNextAvailablePluginDiagnosticKind()
Get the next available kind ID for a plugin diagnostic.
unsigned M0(unsigned Val)
constexpr unsigned BitWidth
auto find_if(R &&Range, UnaryPredicate P)
Provide wrappers to std::find_if which take ranges instead of having to pass begin/end explicitly.
unsigned Log2(Align A)
Returns the log2 of the alignment.
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
This struct is a compact representation of a valid (non-zero power of two) alignment.
uint64_t value() const
This is a hole in the type system and should not be abused.
bool isSimple() const
Test if the given EVT is simple (as opposed to being extended).
bool bitsGT(EVT VT) const
Return true if this has more bits than VT.
TypeSize getSizeInBits() const
Return the size of the specified value type in bits.
static EVT getEVT(Type *Ty, bool HandleUnknown=false)
Return the value type corresponding to the specified type.
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
EVT getVectorElementType() const
Given a vector type, return the type of each element.
This class contains a discriminated union of information about pointers in memory operands,...
static MachinePointerInfo getStack(MachineFunction &MF, int64_t Offset, uint8_t ID=0)
Stack pointer relative access.
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
This struct is a compact representation of a valid (power of two) or undefined (0) alignment.
This represents a list of ValueType's that has been intern'd by a SelectionDAG.
This represents an addressing mode of: BaseGV + BaseOffs + BaseReg + Scale*ScaleReg + ScalableOffset*...
This structure contains all information that is necessary for lowering calls.
SmallVector< ISD::InputArg, 32 > Ins
SmallVector< ISD::OutputArg, 32 > Outs
SmallVector< SDValue, 32 > OutVals
bool isBeforeLegalizeOps() const