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RISCVBaseInfo.h
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1//===-- RISCVBaseInfo.h - Top level definitions for RISC-V MC ---*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains small standalone enum definitions for the RISC-V target
10// useful for the compiler back-end and the MC libraries.
11//
12//===----------------------------------------------------------------------===//
13#ifndef LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVBASEINFO_H
14#define LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVBASEINFO_H
15
17#include "llvm/ADT/APFloat.h"
18#include "llvm/ADT/APInt.h"
19#include "llvm/ADT/StringRef.h"
21#include "llvm/MC/MCInstrDesc.h"
25
26namespace llvm {
27
28// RISCVII - This namespace holds all of the target specific flags that
29// instruction info tracks. All definitions must match RISCVInstrFormats.td.
30namespace RISCVII {
31enum {
55
58
64
67
68 // Force a tail agnostic policy even this instruction has a tied destination.
71
72 // Is this a _TIED vector pseudo instruction. For these instructions we
73 // shouldn't skip the tied operand when converting to MC instructions.
76
77 // Does this instruction have a SEW operand. It will be the last explicit
78 // operand unless there is a vector policy operand. Used by RVV Pseudos.
81
82 // Does this instruction have a VL operand. It will be the second to last
83 // explicit operand unless there is a vector policy operand. Used by RVV
84 // Pseudos.
87
88 // Does this instruction have a vector policy operand. It will be the last
89 // explicit operand. Used by RVV Pseudos.
92
93 // Is this instruction a vector widening reduction instruction. Used by RVV
94 // Pseudos.
97
98 // Does this instruction care about mask policy. If it is not, the mask policy
99 // could be either agnostic or undisturbed. For example, unmasked, store, and
100 // reduction operations result would not be affected by mask policy, so
101 // compiler has free to select either one.
104
105 // Indicates that the result can be considered sign extended from bit 31. Some
106 // instructions with this flag aren't W instructions, but are either sign
107 // extended from a smaller size, always outputs a small integer, or put zeros
108 // in bits 63:31. Used by the SExtWRemoval pass.
111
114
117
118 // Indicates whether these instructions can partially overlap between source
119 // registers and destination registers according to the vector spec.
120 // 0 -> not a vector pseudo
121 // 1 -> default value for vector pseudos. not widening or narrowing.
122 // 2 -> narrowing case
123 // 3 -> widening case
126
129
132
133 // Indicates the EEW of a vector instruction's destination operand.
134 // 0 -> 1
135 // 1 -> SEW
136 // 2 -> SEW * 2
137 // 3 -> SEW * 4
140};
141
142// Helper functions to read TSFlags.
143/// \returns the format of the instruction.
144static inline unsigned getFormat(uint64_t TSFlags) {
145 return (TSFlags & InstFormatMask) >> InstFormatShift;
146}
147/// \returns the LMUL for the instruction.
148static inline VLMUL getLMul(uint64_t TSFlags) {
149 return static_cast<VLMUL>((TSFlags & VLMulMask) >> VLMulShift);
150}
151/// \returns true if tail agnostic is enforced for the instruction.
152static inline bool doesForceTailAgnostic(uint64_t TSFlags) {
153 return TSFlags & ForceTailAgnosticMask;
154}
155/// \returns true if this a _TIED pseudo.
156static inline bool isTiedPseudo(uint64_t TSFlags) {
157 return TSFlags & IsTiedPseudoMask;
158}
159/// \returns true if there is a SEW operand for the instruction.
160static inline bool hasSEWOp(uint64_t TSFlags) {
161 return TSFlags & HasSEWOpMask;
162}
163/// \returns true if there is a VL operand for the instruction.
164static inline bool hasVLOp(uint64_t TSFlags) {
165 return TSFlags & HasVLOpMask;
166}
167/// \returns true if there is a vector policy operand for this instruction.
168static inline bool hasVecPolicyOp(uint64_t TSFlags) {
169 return TSFlags & HasVecPolicyOpMask;
170}
171/// \returns true if it is a vector widening reduction instruction.
172static inline bool isRVVWideningReduction(uint64_t TSFlags) {
173 return TSFlags & IsRVVWideningReductionMask;
174}
175/// \returns true if mask policy is valid for the instruction.
176static inline bool usesMaskPolicy(uint64_t TSFlags) {
177 return TSFlags & UsesMaskPolicyMask;
178}
179
180/// \returns true if there is a rounding mode operand for this instruction
181static inline bool hasRoundModeOp(uint64_t TSFlags) {
182 return TSFlags & HasRoundModeOpMask;
183}
184
185/// \returns true if this instruction uses vxrm
186static inline bool usesVXRM(uint64_t TSFlags) { return TSFlags & UsesVXRMMask; }
187
188/// \returns true if the elements in the body are affected by VL,
189/// e.g. vslide1down.vx/vredsum.vs/viota.m
190static inline bool elementsDependOnVL(uint64_t TSFlags) {
191 return TSFlags & ElementsDependOnVLMask;
192}
193
194/// \returns true if the elements in the body are affected by the mask,
195/// e.g. vredsum.vs/viota.m
196static inline bool elementsDependOnMask(uint64_t TSFlags) {
197 return TSFlags & ElementsDependOnMaskMask;
198}
199
200static inline unsigned getVLOpNum(const MCInstrDesc &Desc) {
201 const uint64_t TSFlags = Desc.TSFlags;
202 // This method is only called if we expect to have a VL operand, and all
203 // instructions with VL also have SEW.
204 assert(hasSEWOp(TSFlags) && hasVLOp(TSFlags));
205 unsigned Offset = 2;
206 if (hasVecPolicyOp(TSFlags))
207 Offset = 3;
208 return Desc.getNumOperands() - Offset;
209}
210
211static inline unsigned getTailExpandUseRegNo(const FeatureBitset &FeatureBits) {
212 // For Zicfilp, PseudoTAIL should be expanded to a software guarded branch.
213 // It means to use t2(x7) as rs1 of JALR to expand PseudoTAIL.
214 return FeatureBits[RISCV::FeatureStdExtZicfilp] ? RISCV::X7 : RISCV::X6;
215}
216
217static inline unsigned getSEWOpNum(const MCInstrDesc &Desc) {
218 const uint64_t TSFlags = Desc.TSFlags;
219 assert(hasSEWOp(TSFlags));
220 unsigned Offset = 1;
221 if (hasVecPolicyOp(TSFlags))
222 Offset = 2;
223 return Desc.getNumOperands() - Offset;
224}
225
226static inline unsigned getVecPolicyOpNum(const MCInstrDesc &Desc) {
227 assert(hasVecPolicyOp(Desc.TSFlags));
228 return Desc.getNumOperands() - 1;
229}
230
231/// \returns the index to the rounding mode immediate value if any, otherwise
232/// returns -1.
233static inline int getFRMOpNum(const MCInstrDesc &Desc) {
234 const uint64_t TSFlags = Desc.TSFlags;
235 if (!hasRoundModeOp(TSFlags) || usesVXRM(TSFlags))
236 return -1;
237
238 // The operand order
239 // --------------------------------------
240 // | n-1 (if any) | n-2 | n-3 | n-4 |
241 // | policy | sew | vl | frm |
242 // --------------------------------------
243 return getVLOpNum(Desc) - 1;
244}
245
246/// \returns the index to the rounding mode immediate value if any, otherwise
247/// returns -1.
248static inline int getVXRMOpNum(const MCInstrDesc &Desc) {
249 const uint64_t TSFlags = Desc.TSFlags;
250 if (!hasRoundModeOp(TSFlags) || !usesVXRM(TSFlags))
251 return -1;
252 // The operand order
253 // --------------------------------------
254 // | n-1 (if any) | n-2 | n-3 | n-4 |
255 // | policy | sew | vl | vxrm |
256 // --------------------------------------
257 return getVLOpNum(Desc) - 1;
258}
259
260// Is the first def operand tied to the first use operand. This is true for
261// vector pseudo instructions that have a merge operand for tail/mask
262// undisturbed. It's also true for vector FMA instructions where one of the
263// operands is also the destination register.
264static inline bool isFirstDefTiedToFirstUse(const MCInstrDesc &Desc) {
265 return Desc.getNumDefs() < Desc.getNumOperands() &&
266 Desc.getOperandConstraint(Desc.getNumDefs(), MCOI::TIED_TO) == 0;
267}
268
269// RISC-V Specific Machine Operand Flags
270enum {
273 MO_LO = 3,
274 MO_HI = 4,
287
288 // Used to differentiate between target-specific "direct" flags and "bitmask"
289 // flags. A machine operand can only have one "direct" flag, but can have
290 // multiple "bitmask" flags.
293} // namespace RISCVII
294
295namespace RISCVOp {
296enum OperandType : unsigned {
342 // Operand is a 3-bit rounding mode, '111' indicates FRM register.
343 // Represents 'frm' argument passing to floating-point operations.
345 // Operand is a 3-bit rounding mode where only RTZ is valid.
347 // Condition code used by select and short forward branch pseudos.
349 // Vector policy operand.
351 // Vector SEW operand. Stores in log2(SEW).
353 // Special SEW for mask only instructions. Always 0.
355 // Vector rounding mode for VXRM or FRM.
358 // Operand is either a register or uimm5, this is used by V extension pseudo
359 // instructions to represent a value that be passed as AVL to either vsetvli
360 // or vsetivli.
362};
363} // namespace RISCVOp
364
365// Describes the predecessor/successor bits used in the FENCE instruction.
366namespace RISCVFenceField {
368 I = 8,
369 O = 4,
370 R = 2,
371 W = 1
373}
374
375// Describes the supported floating point rounding mode encodings.
376namespace RISCVFPRndMode {
378 RNE = 0,
379 RTZ = 1,
380 RDN = 2,
381 RUP = 3,
382 RMM = 4,
383 DYN = 7,
384 Invalid
386
388 switch (RndMode) {
389 default:
390 llvm_unreachable("Unknown floating point rounding mode");
392 return "rne";
394 return "rtz";
396 return "rdn";
398 return "rup";
400 return "rmm";
402 return "dyn";
403 }
404}
405
415}
416
417inline static bool isValidRoundingMode(unsigned Mode) {
418 switch (Mode) {
419 default:
420 return false;
427 return true;
428 }
429}
430} // namespace RISCVFPRndMode
431
432namespace RISCVVXRndMode {
434 RNU = 0,
435 RNE = 1,
436 RDN = 2,
437 ROD = 3,
438};
439} // namespace RISCVVXRndMode
440
441//===----------------------------------------------------------------------===//
442// Floating-point Immediates
443//
444
445namespace RISCVLoadFPImm {
446float getFPImm(unsigned Imm);
447
448/// getLoadFPImm - Return a 5-bit binary encoding of the floating-point
449/// immediate value. If the value cannot be represented as a 5-bit binary
450/// encoding, then return -1.
451int getLoadFPImm(APFloat FPImm);
452} // namespace RISCVLoadFPImm
453
454namespace RISCVSysReg {
455struct SysReg {
456 const char Name[32];
457 unsigned Encoding;
458 // FIXME: add these additional fields when needed.
459 // Privilege Access: Read, Write, Read-Only.
460 // unsigned ReadWrite;
461 // Privilege Mode: User, System or Machine.
462 // unsigned Mode;
463 // Check field name.
464 // unsigned Extra;
465 // Register number without the privilege bits.
466 // unsigned Number;
471
472 bool haveRequiredFeatures(const FeatureBitset &ActiveFeatures) const {
473 // Not in 32-bit mode.
474 if (IsRV32Only && ActiveFeatures[RISCV::Feature64Bit])
475 return false;
476 // No required feature associated with the system register.
478 return true;
479 return (FeaturesRequired & ActiveFeatures) == FeaturesRequired;
480 }
481};
482
483#define GET_SysRegEncodings_DECL
484#define GET_SysRegsList_DECL
485#include "RISCVGenSearchableTables.inc"
486} // end namespace RISCVSysReg
487
488namespace RISCVInsnOpcode {
490 const char *Name;
491 unsigned Value;
492};
493
494#define GET_RISCVOpcodesList_DECL
495#include "RISCVGenSearchableTables.inc"
496} // end namespace RISCVInsnOpcode
497
498namespace RISCVABI {
499
500enum ABI {
511
512// Returns the target ABI, or else a StringError if the requested ABIName is
513// not supported for the given TT and FeatureBits combination.
514ABI computeTargetABI(const Triple &TT, const FeatureBitset &FeatureBits,
515 StringRef ABIName);
516
517ABI getTargetABI(StringRef ABIName);
518
519// Returns the register used to hold the stack pointer after realignment.
521
522// Returns the register holding shadow call stack pointer.
524
525} // namespace RISCVABI
526
527namespace RISCVFeatures {
528
529// Validates if the given combination of features are valid for the target
530// triple. Exits with report_fatal_error if not.
531void validate(const Triple &TT, const FeatureBitset &FeatureBits);
532
534parseFeatureBits(bool IsRV64, const FeatureBitset &FeatureBits);
535
536} // namespace RISCVFeatures
537
538namespace RISCVRVC {
539bool compress(MCInst &OutInst, const MCInst &MI, const MCSubtargetInfo &STI);
540bool uncompress(MCInst &OutInst, const MCInst &MI, const MCSubtargetInfo &STI);
541} // namespace RISCVRVC
542
543namespace RISCVZC {
545 RA = 4,
556 // note - to include s10, s11 must also be included
559};
560
561inline unsigned encodeRlist(MCRegister EndReg, bool IsRV32E = false) {
562 assert((!IsRV32E || EndReg <= RISCV::X9) && "Invalid Rlist for RV32E");
563 switch (EndReg) {
564 case RISCV::X1:
565 return RLISTENCODE::RA;
566 case RISCV::X8:
567 return RLISTENCODE::RA_S0;
568 case RISCV::X9:
570 case RISCV::X18:
572 case RISCV::X19:
574 case RISCV::X20:
576 case RISCV::X21:
578 case RISCV::X22:
580 case RISCV::X23:
582 case RISCV::X24:
584 case RISCV::X25:
586 case RISCV::X26:
588 case RISCV::X27:
590 default:
591 llvm_unreachable("Undefined input.");
592 }
593}
594
595inline static unsigned getStackAdjBase(unsigned RlistVal, bool IsRV64) {
597 "{ra, s0-s10} is not supported, s11 must be included.");
598 if (!IsRV64) {
599 switch (RlistVal) {
600 case RLISTENCODE::RA:
604 return 16;
609 return 32;
613 return 48;
615 return 64;
616 }
617 } else {
618 switch (RlistVal) {
619 case RLISTENCODE::RA:
621 return 16;
624 return 32;
627 return 48;
630 return 64;
633 return 80;
635 return 96;
637 return 112;
638 }
639 }
640 llvm_unreachable("Unexpected RlistVal");
641}
642
643inline static bool getSpimm(unsigned RlistVal, unsigned &SpimmVal,
644 int64_t StackAdjustment, bool IsRV64) {
645 if (RlistVal == RLISTENCODE::INVALID_RLIST)
646 return false;
647 unsigned StackAdjBase = getStackAdjBase(RlistVal, IsRV64);
648 StackAdjustment -= StackAdjBase;
649 if (StackAdjustment % 16 != 0)
650 return false;
651 SpimmVal = StackAdjustment / 16;
652 if (SpimmVal > 3)
653 return false;
654 return true;
655}
656
657void printRlist(unsigned SlistEncode, raw_ostream &OS);
658} // namespace RISCVZC
659
660} // namespace llvm
661
662#endif
This file declares a class to represent arbitrary precision floating point values and provide a varie...
This file implements a class to represent arbitrary precision integral constant values and operations...
IRTranslator LLVM IR MI
static cl::opt< RegAllocEvictionAdvisorAnalysis::AdvisorMode > Mode("regalloc-enable-advisor", cl::Hidden, cl::init(RegAllocEvictionAdvisorAnalysis::AdvisorMode::Default), cl::desc("Enable regalloc advisor mode"), cl::values(clEnumValN(RegAllocEvictionAdvisorAnalysis::AdvisorMode::Default, "default", "Default"), clEnumValN(RegAllocEvictionAdvisorAnalysis::AdvisorMode::Release, "release", "precompiled"), clEnumValN(RegAllocEvictionAdvisorAnalysis::AdvisorMode::Development, "development", "for training")))
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
raw_pwrite_stream & OS
This file implements the StringSwitch template, which mimics a switch() statement whose cases are str...
Tagged union holding either a T or a Error.
Definition: Error.h:481
Container class for subtarget features.
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:185
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:198
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:33
Generic base class for all target subtargets.
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:51
A switch()-like statement whose cases are string literals.
Definition: StringSwitch.h:44
StringSwitch & Case(StringLiteral S, T Value)
Definition: StringSwitch.h:69
R Default(T Value)
Definition: StringSwitch.h:182
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:52
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ OPERAND_FIRST_TARGET
Definition: MCInstrDesc.h:78
ABI getTargetABI(StringRef ABIName)
ABI computeTargetABI(const Triple &TT, const FeatureBitset &FeatureBits, StringRef ABIName)
MCRegister getBPReg()
MCRegister getSCSPReg()
static bool isValidRoundingMode(unsigned Mode)
static RoundingMode stringToRoundingMode(StringRef Str)
static StringRef roundingModeToString(RoundingMode RndMode)
void validate(const Triple &TT, const FeatureBitset &FeatureBits)
llvm::Expected< std::unique_ptr< RISCVISAInfo > > parseFeatureBits(bool IsRV64, const FeatureBitset &FeatureBits)
static unsigned getVecPolicyOpNum(const MCInstrDesc &Desc)
static bool usesMaskPolicy(uint64_t TSFlags)
static bool hasRoundModeOp(uint64_t TSFlags)
static bool isTiedPseudo(uint64_t TSFlags)
static unsigned getVLOpNum(const MCInstrDesc &Desc)
static bool doesForceTailAgnostic(uint64_t TSFlags)
static unsigned getFormat(uint64_t TSFlags)
static VLMUL getLMul(uint64_t TSFlags)
static bool hasVLOp(uint64_t TSFlags)
static bool elementsDependOnMask(uint64_t TSFlags)
@ TargetOverlapConstraintTypeMask
@ TargetOverlapConstraintTypeShift
@ IsRVVWideningReductionShift
Definition: RISCVBaseInfo.h:95
@ IsRVVWideningReductionMask
Definition: RISCVBaseInfo.h:96
static int getFRMOpNum(const MCInstrDesc &Desc)
static int getVXRMOpNum(const MCInstrDesc &Desc)
static bool hasVecPolicyOp(uint64_t TSFlags)
static bool usesVXRM(uint64_t TSFlags)
static unsigned getTailExpandUseRegNo(const FeatureBitset &FeatureBits)
static bool isRVVWideningReduction(uint64_t TSFlags)
static unsigned getSEWOpNum(const MCInstrDesc &Desc)
static bool elementsDependOnVL(uint64_t TSFlags)
static bool hasSEWOp(uint64_t TSFlags)
static bool isFirstDefTiedToFirstUse(const MCInstrDesc &Desc)
int getLoadFPImm(APFloat FPImm)
getLoadFPImm - Return a 5-bit binary encoding of the floating-point immediate value.
float getFPImm(unsigned Imm)
@ OPERAND_UIMMLOG2XLEN_NONZERO
@ OPERAND_UIMM10_LSB00_NONZERO
@ OPERAND_SIMM10_LSB0000_NONZERO
bool uncompress(MCInst &OutInst, const MCInst &MI, const MCSubtargetInfo &STI)
bool compress(MCInst &OutInst, const MCInst &MI, const MCSubtargetInfo &STI)
static unsigned getStackAdjBase(unsigned RlistVal, bool IsRV64)
unsigned encodeRlist(MCRegister EndReg, bool IsRV32E=false)
void printRlist(unsigned SlistEncode, raw_ostream &OS)
static bool getSpimm(unsigned RlistVal, unsigned &SpimmVal, int64_t StackAdjustment, bool IsRV64)
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Offset
Definition: DWP.cpp:480
Description of the encoding of one expression Op.
FeatureBitset FeaturesRequired
bool haveRequiredFeatures(const FeatureBitset &ActiveFeatures) const