LLVM 20.0.0git
RISCVTargetParser.h
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1//===-- RISCVTargetParser - Parser for target features ----------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements a target parser to recognise hardware features
10// for RISC-V CPUs.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_TARGETPARSER_RISCVTARGETPARSER_H
15#define LLVM_TARGETPARSER_RISCVTARGETPARSER_H
16
17#include "llvm/ADT/StringRef.h"
20
21namespace llvm {
22
23class Triple;
24
25namespace RISCV {
26
27namespace RISCVExtensionBitmaskTable {
29 const char *Name;
30 unsigned GroupID;
31 unsigned BitPosition;
32};
33} // namespace RISCVExtensionBitmaskTable
34
35struct CPUModel {
39};
40
41struct CPUInfo {
47 bool is64Bit() const { return DefaultMarch.starts_with("rv64"); }
48};
49
50// We use 64 bits as the known part in the scalable vector types.
51static constexpr unsigned RVVBitsPerBlock = 64;
52
54 SmallVectorImpl<std::string> &EnabledFeatures,
55 bool NeedPlus = false);
56bool parseCPU(StringRef CPU, bool IsRV64);
57bool parseTuneCPU(StringRef CPU, bool IsRV64);
59void fillValidCPUArchList(SmallVectorImpl<StringRef> &Values, bool IsRV64);
65
66} // namespace RISCV
67
68namespace RISCVII {
69enum VLMUL : uint8_t {
70 LMUL_1 = 0,
78};
79
80enum {
84};
85} // namespace RISCVII
86
87namespace RISCVVType {
88// Is this a SEW value that can be encoded into the VTYPE format.
89inline static bool isValidSEW(unsigned SEW) {
90 return isPowerOf2_32(SEW) && SEW >= 8 && SEW <= 64;
91}
92
93// Is this a LMUL value that can be encoded into the VTYPE format.
94inline static bool isValidLMUL(unsigned LMUL, bool Fractional) {
95 return isPowerOf2_32(LMUL) && LMUL <= 8 && (!Fractional || LMUL != 1);
96}
97
98unsigned encodeVTYPE(RISCVII::VLMUL VLMUL, unsigned SEW, bool TailAgnostic,
99 bool MaskAgnostic);
100
101inline static RISCVII::VLMUL getVLMUL(unsigned VType) {
102 unsigned VLMUL = VType & 0x7;
103 return static_cast<RISCVII::VLMUL>(VLMUL);
104}
105
106// Decode VLMUL into 1,2,4,8 and fractional indicator.
107std::pair<unsigned, bool> decodeVLMUL(RISCVII::VLMUL VLMUL);
108
109inline static RISCVII::VLMUL encodeLMUL(unsigned LMUL, bool Fractional) {
110 assert(isValidLMUL(LMUL, Fractional) && "Unsupported LMUL");
111 unsigned LmulLog2 = Log2_32(LMUL);
112 return static_cast<RISCVII::VLMUL>(Fractional ? 8 - LmulLog2 : LmulLog2);
113}
114
115inline static unsigned decodeVSEW(unsigned VSEW) {
116 assert(VSEW < 8 && "Unexpected VSEW value");
117 return 1 << (VSEW + 3);
118}
119
120inline static unsigned encodeSEW(unsigned SEW) {
121 assert(isValidSEW(SEW) && "Unexpected SEW value");
122 return Log2_32(SEW) - 3;
123}
124
125inline static unsigned getSEW(unsigned VType) {
126 unsigned VSEW = (VType >> 3) & 0x7;
127 return decodeVSEW(VSEW);
128}
129
130inline static bool isTailAgnostic(unsigned VType) { return VType & 0x40; }
131
132inline static bool isMaskAgnostic(unsigned VType) { return VType & 0x80; }
133
134void printVType(unsigned VType, raw_ostream &OS);
135
136unsigned getSEWLMULRatio(unsigned SEW, RISCVII::VLMUL VLMul);
137
138std::optional<RISCVII::VLMUL>
139getSameRatioLMUL(unsigned SEW, RISCVII::VLMUL VLMUL, unsigned EEW);
140} // namespace RISCVVType
141
142} // namespace llvm
143
144#endif
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
raw_pwrite_stream & OS
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:573
A wrapper around a string literal that serves as a proxy for constructing global tables of StringRefs...
Definition: StringRef.h:853
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:51
bool starts_with(StringRef Prefix) const
Check if this string starts with the given Prefix.
Definition: StringRef.h:265
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:52
@ TAIL_UNDISTURBED_MASK_UNDISTURBED
static bool isTailAgnostic(unsigned VType)
static RISCVII::VLMUL getVLMUL(unsigned VType)
static unsigned decodeVSEW(unsigned VSEW)
std::pair< unsigned, bool > decodeVLMUL(RISCVII::VLMUL VLMUL)
unsigned getSEWLMULRatio(unsigned SEW, RISCVII::VLMUL VLMul)
static bool isValidLMUL(unsigned LMUL, bool Fractional)
static RISCVII::VLMUL encodeLMUL(unsigned LMUL, bool Fractional)
static bool isMaskAgnostic(unsigned VType)
static unsigned encodeSEW(unsigned SEW)
static bool isValidSEW(unsigned SEW)
void printVType(unsigned VType, raw_ostream &OS)
unsigned encodeVTYPE(RISCVII::VLMUL VLMUL, unsigned SEW, bool TailAgnostic, bool MaskAgnostic)
static unsigned getSEW(unsigned VType)
std::optional< RISCVII::VLMUL > getSameRatioLMUL(unsigned SEW, RISCVII::VLMUL VLMUL, unsigned EEW)
bool hasFastVectorUnalignedAccess(StringRef CPU)
void getFeaturesForCPU(StringRef CPU, SmallVectorImpl< std::string > &EnabledFeatures, bool NeedPlus=false)
void fillValidTuneCPUArchList(SmallVectorImpl< StringRef > &Values, bool IsRV64)
CPUModel getCPUModel(StringRef CPU)
StringRef getMArchFromMcpu(StringRef CPU)
bool parseCPU(StringRef CPU, bool IsRV64)
bool hasFastScalarUnalignedAccess(StringRef CPU)
static constexpr unsigned RVVBitsPerBlock
bool hasValidCPUModel(StringRef CPU)
bool parseTuneCPU(StringRef CPU, bool IsRV64)
void fillValidCPUArchList(SmallVectorImpl< StringRef > &Values, bool IsRV64)
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
unsigned Log2_32(uint32_t Value)
Return the floor log base 2 of the specified value, -1 if the value is zero.
Definition: MathExtras.h:340
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
Definition: MathExtras.h:291
StringLiteral DefaultMarch