Classes
struct	CPUInfo
struct	CPUModel
struct	DemandedFields
	Which subfields of VL or VTYPE have values we need to preserve? More...
struct	NDSVLNPseudo
struct	ParserError
	Fatal errors encountered during parsing. More...
struct	ParserWarning
	Warnings encountered during parsing. More...
struct	RISCVMaskedPseudoInfo
class	RISCVVSETVLIInfoAnalysis
struct	VLEPseudo
struct	VLSEGPseudo
struct	VLX_VSXPseudo
struct	VLXSEGPseudo
struct	VSEPseudo
class	VSETVLIInfo
	Defines the abstract state with which the forward dataflow models the values of the VL and VTYPE registers after insertion. More...
struct	VSSEGPseudo
struct	VSXSEGPseudo
struct	VXMemOpInfo

Typedefs
using	Specifier = uint16_t

Enumerations
enum	PartialMappingIdx { PMI_GPRB32 = 0 , PMI_GPRB64 = 1 , PMI_FPRB16 = 2 , PMI_FPRB32 = 3 , PMI_FPRB64 = 4 , PMI_VRB64 = 5 , PMI_VRB128 = 6 , PMI_VRB256 = 7 , PMI_VRB512 = 8 }
enum	ValueMappingIdx { InvalidIdx = 0 , GPRB32Idx = 1 , GPRB64Idx = 4 , FPRB16Idx = 7 , FPRB32Idx = 10 , FPRB64Idx = 13 , VRB64Idx = 16 , VRB128Idx = 19 , VRB256Idx = 22 , VRB512Idx = 25 }
enum	Fixups { fixup_riscv_hi20 = FirstTargetFixupKind , fixup_riscv_lo12_i , fixup_riscv_12_i , fixup_riscv_lo12_s , fixup_riscv_pcrel_hi20 , fixup_riscv_pcrel_lo12_i , fixup_riscv_pcrel_lo12_s , fixup_riscv_jal , fixup_riscv_branch , fixup_riscv_rvc_jump , fixup_riscv_rvc_branch , fixup_riscv_rvc_imm , fixup_riscv_call , fixup_riscv_call_plt , fixup_riscv_qc_e_branch , fixup_riscv_qc_e_32 , fixup_riscv_qc_abs20_u , fixup_riscv_qc_e_call_plt , fixup_riscv_nds_branch_10 , fixup_riscv_invalid , NumTargetFixupKinds = fixup_riscv_invalid - FirstTargetFixupKind }
enum	{ S_None , S_LO = FirstTargetFixupKind , S_PCREL_LO , S_PCREL_HI , S_TPREL_LO , S_CALL_PLT , S_GOT_HI , S_QC_ABS20 }
enum	CPUKind : unsigned

Functions
LLVM_ABI void	getFeaturesForCPU (StringRef CPU, SmallVectorImpl< std::string > &EnabledFeatures, bool NeedPlus=false)
LLVM_ABI void	getAllTuneFeatures (SmallVectorImpl< StringRef > &TuneFeatures)
LLVM_ABI void	getCPUConfigurableTuneFeatures (StringRef CPU, SmallVectorImpl< StringRef > &Directives)
LLVM_ABI Error	parseTuneFeatureString (StringRef ProcName, StringRef TFString, SmallVectorImpl< std::string > &TuneFeatures)
	Parse the tune feature string with the respective processor.
LLVM_ABI bool	parseCPU (StringRef CPU, bool IsRV64)
LLVM_ABI bool	parseTuneCPU (StringRef CPU, bool IsRV64)
LLVM_ABI StringRef	getMArchFromMcpu (StringRef CPU)
LLVM_ABI void	fillValidCPUArchList (SmallVectorImpl< StringRef > &Values, bool IsRV64)
LLVM_ABI void	fillValidTuneCPUArchList (SmallVectorImpl< StringRef > &Values, bool IsRV64)
LLVM_ABI bool	hasFastScalarUnalignedAccess (StringRef CPU)
LLVM_ABI bool	hasFastVectorUnalignedAccess (StringRef CPU)
LLVM_ABI bool	hasValidCPUModel (StringRef CPU)
LLVM_ABI CPUModel	getCPUModel (StringRef CPU)
LLVM_ABI StringRef	getCPUNameFromCPUModel (const CPUModel &Model)
Specifier	parseSpecifierName (StringRef name)
StringRef	getSpecifierName (Specifier Kind)
void	updateCZceFeatureImplications (MCSubtargetInfo &STI)
ArrayRef< MCPhysReg >	getArgGPRs (const RISCVABI::ABI ABI)
bool	isRVVSpill (const MachineInstr &MI)
bool	isVectorCopy (const TargetRegisterInfo *TRI, const MachineInstr &MI)
	Return true if `MI` is a copy that will be lowered to one or more vmvNr.vs.
std::optional< std::pair< unsigned, unsigned > >	isRVVSpillForZvlsseg (unsigned Opcode)
bool	hasEqualFRM (const MachineInstr &MI1, const MachineInstr &MI2)
std::optional< unsigned >	getVectorLowDemandedScalarBits (unsigned Opcode, unsigned Log2SEW)
unsigned	getRVVMCOpcode (unsigned RVVPseudoOpcode)
unsigned	getDestLog2EEW (const MCInstrDesc &Desc, unsigned Log2SEW)
bool	isVLKnownLE (const MachineOperand &LHS, const MachineOperand &RHS)
	Given two VL operands, do we know that LHS <= RHS?
static VNInfo *	getVNInfoFromReg (Register Reg, const MachineInstr &MI, const LiveIntervals *LIS)
	Given a virtual register `Reg`, return the corresponding VNInfo for it.
static const MachineOperand &	getVLOp (const MachineInstr &MI)
static const MachineOperand &	getSEWOp (const MachineInstr &MI)
static const MachineOperand &	getVecPolicyOp (const MachineInstr &MI)
static const MachineOperand &	getTWidenOp (const MachineInstr &MI)
static std::optional< unsigned >	getEEWForLoadStore (const MachineInstr &MI)
	Get the EEW for a load or store instruction.
static bool	isMaskRegOp (const MachineInstr &MI)
	Return true if this is an operation on mask registers.
static bool	hasUndefinedPassthru (const MachineInstr &MI)
	Return true if the inactive elements in the result are entirely undefined.
static bool	isLMUL1OrSmaller (RISCVVType::VLMUL LMUL)
bool	areCompatibleVTYPEs (uint64_t CurVType, uint64_t NewVType, const DemandedFields &Used)
	Return true if moving from CurVType to NewVType is indistinguishable from the perspective of an instruction (or set of instructions) which use only the Used subfields and properties.
DemandedFields	getDemanded (const MachineInstr &MI, const RISCVSubtarget *ST)
	Return the fields and properties demanded by the provided instruction.
static unsigned	computeVLMAX (unsigned VLEN, unsigned SEW, RISCVVType::VLMUL VLMul)
LLVM_ATTRIBUTE_USED raw_ostream &	operator<< (raw_ostream &OS, const DemandedFields &DF)
LLVM_ATTRIBUTE_USED raw_ostream &	operator<< (raw_ostream &OS, const VSETVLIInfo &V)
static const CPUInfo *	getCPUInfoByName (StringRef CPU)

Variables
static constexpr unsigned	RVVBitsPerBlock = 64
static constexpr unsigned	RVVBytesPerBlock = RVVBitsPerBlock / 8
const RegisterBankInfo::PartialMapping	PartMappings []
const RegisterBankInfo::ValueMapping	ValueMappings []
static constexpr int64_t	VLMaxSentinel = -1LL
static constexpr unsigned	FPMASK_Negative_Infinity = 0x001
static constexpr unsigned	FPMASK_Negative_Normal = 0x002
static constexpr unsigned	FPMASK_Negative_Subnormal = 0x004
static constexpr unsigned	FPMASK_Negative_Zero = 0x008
static constexpr unsigned	FPMASK_Positive_Zero = 0x010
static constexpr unsigned	FPMASK_Positive_Subnormal = 0x020
static constexpr unsigned	FPMASK_Positive_Normal = 0x040
static constexpr unsigned	FPMASK_Positive_Infinity = 0x080
static constexpr unsigned	FPMASK_Signaling_NaN = 0x100
static constexpr unsigned	FPMASK_Quiet_NaN = 0x200
constexpr CPUInfo	RISCVCPUInfo []

Typedef Documentation

◆ Specifier

using llvm::RISCV::Specifier = uint16_t

Definition at line 36 of file RISCVMCAsmInfo.h.

Enumeration Type Documentation

◆ anonymous enum

anonymous enum

Enumerator
S_None
S_LO
S_PCREL_LO
S_PCREL_HI
S_TPREL_LO
S_CALL_PLT
S_GOT_HI
S_QC_ABS20

Definition at line 39 of file RISCVMCAsmInfo.h.

◆ CPUKind

enum llvm::RISCV::CPUKind : unsigned

Definition at line 29 of file RISCVTargetParser.cpp.

◆ Fixups

enum llvm::RISCV::Fixups

Enumerator
fixup_riscv_hi20
fixup_riscv_lo12_i
fixup_riscv_12_i
fixup_riscv_lo12_s
fixup_riscv_pcrel_hi20
fixup_riscv_pcrel_lo12_i
fixup_riscv_pcrel_lo12_s
fixup_riscv_jal
fixup_riscv_branch
fixup_riscv_rvc_jump
fixup_riscv_rvc_branch
fixup_riscv_rvc_imm
fixup_riscv_call
fixup_riscv_call_plt
fixup_riscv_qc_e_branch
fixup_riscv_qc_e_32
fixup_riscv_qc_abs20_u
fixup_riscv_qc_e_call_plt
fixup_riscv_nds_branch_10
fixup_riscv_invalid
NumTargetFixupKinds

Definition at line 18 of file RISCVFixupKinds.h.

◆ PartialMappingIdx

enum llvm::RISCV::PartialMappingIdx

Enumerator
PMI_GPRB32
PMI_GPRB64
PMI_FPRB16
PMI_FPRB32
PMI_FPRB64
PMI_VRB64
PMI_VRB128
PMI_VRB256
PMI_VRB512

Definition at line 43 of file RISCVRegisterBankInfo.cpp.

◆ ValueMappingIdx

enum llvm::RISCV::ValueMappingIdx

Enumerator
InvalidIdx
GPRB32Idx
GPRB64Idx
FPRB16Idx
FPRB32Idx
FPRB64Idx
VRB64Idx
VRB128Idx
VRB256Idx
VRB512Idx

Definition at line 96 of file RISCVRegisterBankInfo.cpp.

Function Documentation

◆ areCompatibleVTYPEs()

bool llvm::RISCV::areCompatibleVTYPEs	(	uint64_t	CurVType,
		uint64_t	NewVType,
		const DemandedFields &	Used )

Return true if moving from CurVType to NewVType is indistinguishable from the perspective of an instruction (or set of instructions) which use only the Used subfields and properties.

Definition at line 114 of file RISCVVSETVLIInfoAnalysis.cpp.

References llvm::RISCVVType::getSEW(), llvm::RISCVVType::getSEWLMULRatio(), llvm::RISCVVType::getVLMUL(), llvm::RISCVVType::getXSfmmWiden(), llvm::RISCVVType::hasXSfmmWiden(), llvm::RISCVVType::isAltFmt(), isLMUL1OrSmaller(), llvm::RISCVVType::isMaskAgnostic(), llvm::RISCVVType::isTailAgnostic(), llvm::RISCV::DemandedFields::LMULEqual, llvm::RISCV::DemandedFields::LMULLessThanOrEqualToM1, llvm::RISCV::DemandedFields::LMULNone, llvm::RISCV::DemandedFields::SEWEqual, llvm::RISCV::DemandedFields::SEWGreaterThanOrEqual, llvm::RISCV::DemandedFields::SEWGreaterThanOrEqualAndLessThan64, and llvm::RISCV::DemandedFields::SEWNone.

Referenced by llvm::RISCV::VSETVLIInfo::hasCompatibleVTYPE().

◆ computeVLMAX()

unsigned llvm::RISCV::computeVLMAX	(	unsigned	VLEN,
		unsigned	SEW,
		RISCVVType::VLMUL	VLMul )

static

Definition at line 395 of file RISCVVSETVLIInfoAnalysis.cpp.

References llvm::RISCVVType::decodeVLMUL().

Referenced by llvm::RISCV::RISCVVSETVLIInfoAnalysis::computeInfoForInstr().

◆ fillValidCPUArchList()

void llvm::RISCV::fillValidCPUArchList	(	SmallVectorImpl< StringRef > &	Values,
		bool	IsRV64 )

Definition at line 115 of file RISCVTargetParser.cpp.

References llvm::CallingConv::C, llvm::SmallVectorImpl< T >::emplace_back(), and RISCVCPUInfo.

◆ fillValidTuneCPUArchList()

void llvm::RISCV::fillValidTuneCPUArchList	(	SmallVectorImpl< StringRef > &	Values,
		bool	IsRV64 )

Definition at line 122 of file RISCVTargetParser.cpp.

References llvm::CallingConv::C, llvm::SmallVectorImpl< T >::emplace_back(), and RISCVCPUInfo.

◆ getAllTuneFeatures()

void llvm::RISCV::getAllTuneFeatures ( SmallVectorImpl< StringRef > & TuneFeatures )

Definition at line 249 of file RISCVTargetParser.cpp.

◆ getArgGPRs()

ArrayRef< MCPhysReg > llvm::RISCV::getArgGPRs ( const RISCVABI::ABI ABI )

Definition at line 127 of file RISCVCallingConv.cpp.

References llvm::RISCVABI::ABI_ILP32E, llvm::RISCVABI::ABI_LP64E, and llvm::ArrayRef().

Referenced by llvm::CC_RISCV(), CC_RISCVAssign2XLen(), and llvm::RISCVTargetLowering::LowerFormalArguments().

◆ getCPUConfigurableTuneFeatures()

void llvm::RISCV::getCPUConfigurableTuneFeatures	(	StringRef	CPU,
		SmallVectorImpl< StringRef > &	Directives )

Definition at line 347 of file RISCVTargetParser.cpp.

References llvm::SmallVectorImpl< T >::assign(), llvm::SmallSet< T, N, C >::begin(), and llvm::SmallSet< T, N, C >::end().

◆ getCPUInfoByName()

const CPUInfo * llvm::RISCV::getCPUInfoByName ( StringRef CPU )

static

Definition at line 50 of file RISCVTargetParser.cpp.

References llvm::CallingConv::C, and RISCVCPUInfo.

Referenced by getCPUModel(), getMArchFromMcpu(), hasFastScalarUnalignedAccess(), hasFastVectorUnalignedAccess(), and parseCPU().

◆ getCPUModel()

CPUModel llvm::RISCV::getCPUModel ( StringRef CPU )

Definition at line 69 of file RISCVTargetParser.cpp.

References getCPUInfoByName().

Referenced by hasValidCPUModel().

◆ getCPUNameFromCPUModel()

StringRef llvm::RISCV::getCPUNameFromCPUModel ( const CPUModel & Model )

Definition at line 76 of file RISCVTargetParser.cpp.

References llvm::CallingConv::C, and RISCVCPUInfo.

◆ getDemanded()

DemandedFields llvm::RISCV::getDemanded	(	const MachineInstr &	MI,
		const RISCVSubtarget *	ST )

Return the fields and properties demanded by the provided instruction.

Definition at line 175 of file RISCVVSETVLIInfoAnalysis.cpp.

◆ getDestLog2EEW()

unsigned llvm::RISCV::getDestLog2EEW	(	const MCInstrDesc &	Desc,
		unsigned	Log2SEW )

Definition at line 5130 of file RISCVInstrInfo.cpp.

References assert(), llvm::RISCVII::DestEEWMask, llvm::RISCVII::DestEEWShift, and Scaled.

Referenced by INITIALIZE_PASS().

◆ getEEWForLoadStore()

std::optional< unsigned > llvm::RISCV::getEEWForLoadStore ( const MachineInstr & MI )

static

Get the EEW for a load or store instruction.

Return std::nullopt if MI is not a load or store which ignores SEW.

Definition at line 52 of file RISCVVSETVLIInfoAnalysis.cpp.

References getRVVMCOpcode(), and MI.

Referenced by llvm::RISCV::RISCVVSETVLIInfoAnalysis::computeInfoForInstr(), and getDemanded().

◆ getFeaturesForCPU()

void llvm::RISCV::getFeaturesForCPU	(	StringRef	CPU,
		SmallVectorImpl< std::string > &	EnabledFeatures,
		bool	NeedPlus = false )

Definition at line 132 of file RISCVTargetParser.cpp.

References llvm::SmallVectorImpl< T >::clear(), llvm::errorToBool(), F, getMArchFromMcpu(), llvm::RISCVISAInfo::parseArchString(), and llvm::SmallVectorTemplateBase< T, bool >::push_back().

◆ getMArchFromMcpu()

StringRef llvm::RISCV::getMArchFromMcpu ( StringRef CPU )

Definition at line 108 of file RISCVTargetParser.cpp.

References getCPUInfoByName().

Referenced by getFeaturesForCPU().

◆ getRVVMCOpcode()

unsigned llvm::RISCV::getRVVMCOpcode ( unsigned RVVPseudoOpcode )

Definition at line 5122 of file RISCVInstrInfo.cpp.

References llvm::RVV.

Referenced by llvm::RISCVInstrInfo::copyPhysRegVector(), getEEWForLoadStore(), getFoldedOpcode(), getMinimumVLForVSLIDEDOWN_VX(), llvm::RISCVInstrInfo::getReassociateOperandIndices(), INITIALIZE_PASS(), llvm::RISCVInstrInfo::isHighLatencyDef(), llvm::RISCVInstrInfo::isReMaterializableImpl(), isSegmentedStoreInstr(), vectorPseudoHasAllNBitUsers(), and vectorPseudoHasAllNBitUsers().

◆ getSEWOp()

const MachineOperand & llvm::RISCV::getSEWOp ( const MachineInstr & MI )

static

Definition at line 38 of file RISCVVSETVLIInfoAnalysis.cpp.

References llvm::RISCVII::getSEWOpNum(), and MI.

Referenced by llvm::RISCV::RISCVVSETVLIInfoAnalysis::computeInfoForInstr(), and isMaskRegOp().

◆ getSpecifierName()

StringRef llvm::RISCV::getSpecifierName ( Specifier Kind )

Definition at line 46 of file RISCVMCExpr.cpp.

References llvm_unreachable, S_CALL_PLT, S_GOT_HI, S_LO, S_None, S_PCREL_HI, S_PCREL_LO, S_QC_ABS20, and S_TPREL_LO.

Referenced by llvm::RISCVMCAsmInfo::printSpecifierExpr(), and llvm::RISCVMCAsmInfoDarwin::printSpecifierExpr().

◆ getTWidenOp()

const MachineOperand & llvm::RISCV::getTWidenOp ( const MachineInstr & MI )

static

Definition at line 46 of file RISCVVSETVLIInfoAnalysis.cpp.

References llvm::RISCVII::getTWidenOpNum(), and MI.

Referenced by llvm::RISCV::RISCVVSETVLIInfoAnalysis::computeInfoForInstr().

◆ getVecPolicyOp()

const MachineOperand & llvm::RISCV::getVecPolicyOp ( const MachineInstr & MI )

static

Definition at line 42 of file RISCVVSETVLIInfoAnalysis.cpp.

References llvm::RISCVII::getVecPolicyOpNum(), and MI.

Referenced by llvm::RISCV::RISCVVSETVLIInfoAnalysis::computeInfoForInstr().

◆ getVectorLowDemandedScalarBits()

std::optional< unsigned > llvm::RISCV::getVectorLowDemandedScalarBits	(	unsigned	Opcode,
		unsigned	Log2SEW )

Definition at line 5005 of file RISCVInstrInfo.cpp.

Referenced by vectorPseudoHasAllNBitUsers(), and vectorPseudoHasAllNBitUsers().

◆ getVLOp()

const MachineOperand & llvm::RISCV::getVLOp ( const MachineInstr & MI )

static

Definition at line 34 of file RISCVVSETVLIInfoAnalysis.cpp.

References llvm::RISCVII::getVLOpNum(), and MI.

Referenced by llvm::RISCV::RISCVVSETVLIInfoAnalysis::computeInfoForInstr(), and getDemanded().

◆ getVNInfoFromReg()

VNInfo * llvm::RISCV::getVNInfoFromReg	(	Register	Reg,
		const MachineInstr &	MI,
		const LiveIntervals *	LIS )

static

Given a virtual register Reg, return the corresponding VNInfo for it.

This will return nullptr if the virtual register is an implicit_def or if LiveIntervals is not available.

Definition at line 24 of file RISCVVSETVLIInfoAnalysis.cpp.

References assert(), llvm::SlotIndexes::getInstructionIndex(), llvm::LiveIntervals::getInterval(), llvm::LiveIntervals::getSlotIndexes(), MI, and Reg.

Referenced by llvm::RISCV::RISCVVSETVLIInfoAnalysis::computeInfoForInstr(), and llvm::RISCV::RISCVVSETVLIInfoAnalysis::getInfoForVSETVLI().

◆ hasEqualFRM()

bool llvm::RISCV::hasEqualFRM	(	const MachineInstr &	MI1,
		const MachineInstr &	MI2 )

Definition at line 4992 of file RISCVInstrInfo.cpp.

References llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), and llvm::MachineInstr::getOperand().

Referenced by canCombineFPFusedMultiply(), and llvm::RISCVInstrInfo::hasReassociableSibling().

◆ hasFastScalarUnalignedAccess()

bool llvm::RISCV::hasFastScalarUnalignedAccess ( StringRef CPU )

Definition at line 57 of file RISCVTargetParser.cpp.

References getCPUInfoByName().

◆ hasFastVectorUnalignedAccess()

bool llvm::RISCV::hasFastVectorUnalignedAccess ( StringRef CPU )

Definition at line 62 of file RISCVTargetParser.cpp.

References getCPUInfoByName().

◆ hasUndefinedPassthru()

bool llvm::RISCV::hasUndefinedPassthru ( const MachineInstr & MI )

static

Return true if the inactive elements in the result are entirely undefined.

Note that this is different from "agnostic" as defined by the vector specification. Agnostic requires each lane to either be undisturbed, or take the value -1; no other value is allowed.

Definition at line 93 of file RISCVVSETVLIInfoAnalysis.cpp.

References llvm::MachineOperand::getReg(), llvm::MachineOperand::isUndef(), llvm::Register::isValid(), and MI.

Referenced by llvm::RISCV::RISCVVSETVLIInfoAnalysis::computeInfoForInstr(), and getDemanded().

◆ hasValidCPUModel()

bool llvm::RISCV::hasValidCPUModel ( StringRef CPU )

Definition at line 67 of file RISCVTargetParser.cpp.

References getCPUModel(), and llvm::RISCV::CPUModel::isValid().

◆ isLMUL1OrSmaller()

bool llvm::RISCV::isLMUL1OrSmaller ( RISCVVType::VLMUL LMUL )

static

Definition at line 106 of file RISCVVSETVLIInfoAnalysis.cpp.

References llvm::RISCVVType::decodeVLMUL().

Referenced by areCompatibleVTYPEs().

◆ isMaskRegOp()

bool llvm::RISCV::isMaskRegOp ( const MachineInstr & MI )

static

Return true if this is an operation on mask registers.

Note that this includes both arithmetic/logical ops and load/store (vlm/vsm).

Definition at line 81 of file RISCVVSETVLIInfoAnalysis.cpp.

References llvm::MachineOperand::getImm(), getSEWOp(), llvm::RISCVII::hasSEWOp(), and MI.

Referenced by getDemanded().

◆ isRVVSpill()

bool llvm::RISCV::isRVVSpill ( const MachineInstr & MI )

Definition at line 4933 of file RISCVInstrInfo.cpp.

References getLMULForRVVWholeLoadStore(), isRVVSpillForZvlsseg(), and MI.

Referenced by llvm::RISCVRegisterInfo::eliminateFrameIndex(), and getScavSlotsNumForRVV().

◆ isRVVSpillForZvlsseg()

std::optional< std::pair< unsigned, unsigned > > llvm::RISCV::isRVVSpillForZvlsseg ( unsigned Opcode )

Definition at line 4952 of file RISCVInstrInfo.cpp.

Referenced by isRVVSpill(), and llvm::RISCVRegisterInfo::lowerSegmentSpillReload().

◆ isVectorCopy()

bool llvm::RISCV::isVectorCopy	(	const TargetRegisterInfo *	TRI,
		const MachineInstr &	MI )

Return true if MI is a copy that will be lowered to one or more vmvNr.vs.

Definition at line 4944 of file RISCVInstrInfo.cpp.

References llvm::RISCVRegisterInfo::isRVVRegClass(), MI, and TRI.

Referenced by getDemanded().

◆ isVLKnownLE()

bool llvm::RISCV::isVLKnownLE	(	const MachineOperand &	LHS,
		const MachineOperand &	RHS )

Given two VL operands, do we know that LHS <= RHS?

Given two VL operands, do we know that LHS <= RHS? Must be used in SSA form.

Definition at line 5155 of file RISCVInstrInfo.cpp.

References assert(), getEffectiveImm(), and VLMaxSentinel.

◆ operator<<() [1/2]

LLVM_ATTRIBUTE_USED raw_ostream & llvm::RISCV::operator<<	(	raw_ostream &	OS,
		const DemandedFields &	DF )

inline

Definition at line 157 of file RISCVVSETVLIInfoAnalysis.h.

References DF.

◆ operator<<() [2/2]

LLVM_ATTRIBUTE_USED raw_ostream & llvm::RISCV::operator<<	(	raw_ostream &	OS,
		const VSETVLIInfo &	V )

inline

Definition at line 565 of file RISCVVSETVLIInfoAnalysis.h.

◆ parseCPU()

bool llvm::RISCV::parseCPU	(	StringRef	CPU,
		bool	IsRV64 )

Definition at line 86 of file RISCVTargetParser.cpp.

References getCPUInfoByName().

Referenced by parseTuneCPU().

◆ parseSpecifierName()

RISCV::Specifier llvm::RISCV::parseSpecifierName ( StringRef name )

Definition at line 23 of file RISCVMCExpr.cpp.

References llvm::StringSwitch< T, R >::Case(), llvm::StringSwitch< T, R >::Default(), name, S_GOT_HI, S_LO, S_PCREL_HI, S_PCREL_LO, S_QC_ABS20, and S_TPREL_LO.

◆ parseTuneCPU()

bool llvm::RISCV::parseTuneCPU	(	StringRef	CPU,
		bool	IsRV64 )

Definition at line 94 of file RISCVTargetParser.cpp.

References llvm::StringSwitch< T, R >::Case(), llvm::StringSwitch< T, R >::Default(), ENUM, parseCPU(), and TUNE_PROC.

◆ parseTuneFeatureString()

Error llvm::RISCV::parseTuneFeatureString	(	StringRef	ProcName,
		StringRef	TFString,
		SmallVectorImpl< std::string > &	TuneFeatures )

Parse the tune feature string with the respective processor.

If ProcName is empty, directives are not filtered by processor.

Definition at line 253 of file RISCVTargetParser.cpp.

References llvm::SmallVectorImpl< T >::emplace_back(), llvm::StringRef::empty(), llvm::join(), llvm::make_error(), llvm::set_intersection(), llvm::StringRef::split(), llvm::Error::success(), and llvm::StringRef::trim().

◆ updateCZceFeatureImplications()

void llvm::RISCV::updateCZceFeatureImplications ( MCSubtargetInfo & STI )

Definition at line 87 of file RISCVMCTargetDesc.cpp.

References llvm::MCSubtargetInfo::hasFeature(), and llvm::MCSubtargetInfo::ToggleFeature().

Referenced by createRISCVMCSubtargetInfo().

Variable Documentation

◆ FPMASK_Negative_Infinity

unsigned llvm::RISCV::FPMASK_Negative_Infinity = 0x001

staticconstexpr

Definition at line 405 of file RISCVInstrInfo.h.

◆ FPMASK_Negative_Normal

unsigned llvm::RISCV::FPMASK_Negative_Normal = 0x002

staticconstexpr

Definition at line 406 of file RISCVInstrInfo.h.

◆ FPMASK_Negative_Subnormal

unsigned llvm::RISCV::FPMASK_Negative_Subnormal = 0x004

staticconstexpr

Definition at line 407 of file RISCVInstrInfo.h.

◆ FPMASK_Negative_Zero

unsigned llvm::RISCV::FPMASK_Negative_Zero = 0x008

staticconstexpr

Definition at line 408 of file RISCVInstrInfo.h.

◆ FPMASK_Positive_Infinity

unsigned llvm::RISCV::FPMASK_Positive_Infinity = 0x080

staticconstexpr

Definition at line 412 of file RISCVInstrInfo.h.

◆ FPMASK_Positive_Normal

unsigned llvm::RISCV::FPMASK_Positive_Normal = 0x040

staticconstexpr

Definition at line 411 of file RISCVInstrInfo.h.

◆ FPMASK_Positive_Subnormal

unsigned llvm::RISCV::FPMASK_Positive_Subnormal = 0x020

staticconstexpr

Definition at line 410 of file RISCVInstrInfo.h.

◆ FPMASK_Positive_Zero

unsigned llvm::RISCV::FPMASK_Positive_Zero = 0x010

staticconstexpr

Definition at line 409 of file RISCVInstrInfo.h.

◆ FPMASK_Quiet_NaN

unsigned llvm::RISCV::FPMASK_Quiet_NaN = 0x200

staticconstexpr

Definition at line 414 of file RISCVInstrInfo.h.

◆ FPMASK_Signaling_NaN

unsigned llvm::RISCV::FPMASK_Signaling_NaN = 0x100

staticconstexpr

Definition at line 413 of file RISCVInstrInfo.h.

◆ PartMappings

const RegisterBankInfo::PartialMapping llvm::RISCV::PartMappings[]

Initial value:

= {
    
    {0, 32, GPRBRegBank},
    {0, 64, GPRBRegBank},
    {0, 16, FPRBRegBank},
    {0, 32, FPRBRegBank},
    {0, 64, FPRBRegBank},
    {0, 64, VRBRegBank},
    {0, 128, VRBRegBank},
    {0, 256, VRBRegBank},
    {0, 512, VRBRegBank},
    
}

Definition at line 29 of file RISCVRegisterBankInfo.cpp.

◆ RISCVCPUInfo

CPUInfo llvm::RISCV::RISCVCPUInfo[]

constexpr

Initial value:

= {
#define PROC(ENUM, NAME, DEFAULT_MARCH, FAST_SCALAR_UNALIGN,                   FAST_VECTOR_UNALIGN, MVENDORID, MARCHID, MIMPID)                  
                                                                         \
                                                                               \
                                                                               \
                                                                               \
                                                                               \
                                                                               \
                                                                               \
    
 
}

Definition at line 37 of file RISCVTargetParser.cpp.

Referenced by fillValidCPUArchList(), fillValidTuneCPUArchList(), getCPUInfoByName(), and getCPUNameFromCPUModel().

◆ RVVBitsPerBlock

unsigned llvm::RISCV::RVVBitsPerBlock = 64

staticconstexpr

Definition at line 68 of file RISCVTargetParser.h.

Referenced by computeKnownBitsFromOperator(), llvm::RISCVTargetLowering::computeVLMAX(), llvm::RISCVSubtarget::expandVScale(), getContainerForFixedLengthVector(), getLMUL1Ty(), llvm::RISCVTargetLowering::getM1VT(), llvm::RISCVTTIImpl::getMaxVScale(), llvm::RISCVTargetLowering::getRegClassIDForVecVT(), llvm::RISCVTTIImpl::getRegisterBitWidth(), llvm::RISCVTTIImpl::getRegUsageForType(), llvm::RISCVTargetMachine::getSubtargetImpl(), llvm::RISCVTTIImpl::getVScaleForTuning(), isTupleInsertInstr(), isValidEGW(), llvm::RISCVInstrInfo::loadRegFromStackSlot(), lowerGetVectorLength(), llvm::RISCVTargetLowering::LowerOperation(), llvm::RISCVTargetLowering::RISCVTargetLowering(), llvm::RISCVDAGToDAGISel::Select(), llvm::RISCVDAGToDAGISel::selectVLXSEG(), llvm::RISCVDAGToDAGISel::selectVSXSEG(), llvm::RISCVTargetLowering::splitValueIntoRegisterParts(), llvm::RISCVInstrInfo::storeRegToStackSlot(), and llvm::RISCVSubtarget::useRVVForFixedLengthVectors().

◆ RVVBytesPerBlock

unsigned llvm::RISCV::RVVBytesPerBlock = RVVBitsPerBlock / 8

staticconstexpr

Definition at line 69 of file RISCVTargetParser.h.

Referenced by llvm::RISCVRegisterInfo::adjustReg(), llvm::RISCVTargetLowering::getOptimalMemOpType(), llvm::RISCVInstrInfo::isLoadFromStackSlot(), and llvm::RISCVInstrInfo::isStoreToStackSlot().

◆ ValueMappings

const RegisterBankInfo::ValueMapping llvm::RISCV::ValueMappings[]

Definition at line 55 of file RISCVRegisterBankInfo.cpp.

Referenced by getFPValueMapping(), llvm::RISCVRegisterBankInfo::getInstrMapping(), and getVRBValueMapping().

◆ VLMaxSentinel

int64_t llvm::RISCV::VLMaxSentinel = -1LL

staticconstexpr

Definition at line 399 of file RISCVInstrInfo.h.

Referenced by llvm::RISCV::RISCVVSETVLIInfoAnalysis::computeInfoForInstr(), isVLKnownLE(), and llvm::RISCVDAGToDAGISel::selectVLOp().

Classes

Typedefs

Enumerations

Functions

Variables

Typedef Documentation

◆ Specifier

Enumeration Type Documentation

◆ anonymous enum

◆ CPUKind

◆ Fixups

◆ PartialMappingIdx

◆ ValueMappingIdx

Function Documentation

◆ areCompatibleVTYPEs()

◆ computeVLMAX()

◆ fillValidCPUArchList()

◆ fillValidTuneCPUArchList()

◆ getAllTuneFeatures()

◆ getArgGPRs()

◆ getCPUConfigurableTuneFeatures()

◆ getCPUInfoByName()

◆ getCPUModel()

◆ getCPUNameFromCPUModel()

◆ getDemanded()

◆ getDestLog2EEW()

◆ getEEWForLoadStore()

◆ getFeaturesForCPU()

◆ getMArchFromMcpu()

◆ getRVVMCOpcode()

◆ getSEWOp()

◆ getSpecifierName()

◆ getTWidenOp()

◆ getVecPolicyOp()

◆ getVectorLowDemandedScalarBits()

◆ getVLOp()

◆ getVNInfoFromReg()

◆ hasEqualFRM()

◆ hasFastScalarUnalignedAccess()

◆ hasFastVectorUnalignedAccess()

◆ hasUndefinedPassthru()

◆ hasValidCPUModel()

◆ isLMUL1OrSmaller()

◆ isMaskRegOp()

◆ isRVVSpill()

◆ isRVVSpillForZvlsseg()

◆ isVectorCopy()

◆ isVLKnownLE()

◆ operator<<() [1/2]

◆ operator<<() [2/2]

◆ parseCPU()

◆ parseSpecifierName()

◆ parseTuneCPU()

◆ parseTuneFeatureString()

◆ updateCZceFeatureImplications()

Variable Documentation

◆ FPMASK_Negative_Infinity

◆ FPMASK_Negative_Normal

◆ FPMASK_Negative_Subnormal

◆ FPMASK_Negative_Zero

◆ FPMASK_Positive_Infinity

◆ FPMASK_Positive_Normal

◆ FPMASK_Positive_Subnormal

◆ FPMASK_Positive_Zero

◆ FPMASK_Quiet_NaN

◆ FPMASK_Signaling_NaN

◆ PartMappings

◆ RISCVCPUInfo

◆ RVVBitsPerBlock

◆ RVVBytesPerBlock

◆ ValueMappings

◆ VLMaxSentinel