36#define GET_INSTRINFO_MC_DESC
37#define ENABLE_INSTR_PREDICATE_VERIFIER
38#include "RISCVGenInstrInfo.inc"
40#define GET_REGINFO_MC_DESC
41#include "RISCVGenRegisterInfo.inc"
43#define GET_SUBTARGETINFO_MC_DESC
44#include "RISCVGenSubtargetInfo.inc"
50#define GET_RISCVVInversePseudosTable_IMPL
51#include "RISCVGenSearchableTables.inc"
59 InitRISCVMCInstrInfo(
X);
65 InitRISCVMCRegisterInfo(
X, RISCV::X1);
83 bool LargeCodeModel =
false) {
91 if (CPU.
empty() || CPU ==
"generic")
92 CPU = TT.isArch64Bit() ?
"generic-rv64" :
"generic-rv32";
94 return createRISCVMCSubtargetInfoImpl(TT, CPU, CPU, FS);
98 unsigned SyntaxVariant,
108 if (TT.isOSBinFormatELF())
126 int64_t GPRState[31] = {};
127 std::bitset<31> GPRValidMask;
129 static bool isGPR(
unsigned Reg) {
130 return Reg >= RISCV::X0 &&
Reg <= RISCV::X31;
133 static unsigned getRegIndex(
unsigned Reg) {
134 assert(isGPR(Reg) && Reg != RISCV::X0 &&
"Invalid GPR reg");
135 return Reg - RISCV::X1;
138 void setGPRState(
unsigned Reg, std::optional<int64_t>
Value) {
139 if (Reg == RISCV::X0)
142 auto Index = getRegIndex(Reg);
146 GPRValidMask.set(
Index);
148 GPRValidMask.reset(
Index);
152 std::optional<int64_t> getGPRState(
unsigned Reg)
const {
153 if (Reg == RISCV::X0)
156 auto Index = getRegIndex(Reg);
158 if (GPRValidMask.test(
Index))
159 return GPRState[
Index];
164 explicit RISCVMCInstrAnalysis(
const MCInstrInfo *Info)
167 void resetState()
override { GPRValidMask.reset(); }
185 for (
unsigned I = 0;
I < NumDefs; ++
I) {
188 setGPRState(DefReg, std::nullopt);
278 return isBranchImpl(Inst);
285 return isBranchImpl(Inst);
304 static bool maybeReturnAddress(
unsigned Reg) {
306 return Reg == RISCV::X1 ||
Reg == RISCV::X5;
309 static bool isBranchImpl(
const MCInst &Inst) {
327 return new RISCVMCInstrAnalysis(
Info);
332 std::unique_ptr<MCAsmBackend> &&MAB,
333 std::unique_ptr<MCObjectWriter> &&MOW,
334 std::unique_ptr<MCCodeEmitter> &&MCE) {
unsigned const MachineRegisterInfo * MRI
Analysis containing CSE Info
#define LLVM_EXTERNAL_VISIBILITY
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
PassInstrumentationCallbacks PIC
static MCRegisterInfo * createRISCVMCRegisterInfo(const Triple &TT)
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTargetMC()
static MCInstPrinter * createRISCVMCInstPrinter(const Triple &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI)
static MCObjectFileInfo * createRISCVMCObjectFileInfo(MCContext &Ctx, bool PIC, bool LargeCodeModel=false)
static MCTargetStreamer * createRISCVNullTargetStreamer(MCStreamer &S)
static MCSubtargetInfo * createRISCVMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS)
static MCTargetStreamer * createRISCVObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI)
static MCInstrAnalysis * createRISCVInstrAnalysis(const MCInstrInfo *Info)
static MCTargetStreamer * createRISCVAsmTargetStreamer(MCStreamer &S, formatted_raw_ostream &OS, MCInstPrinter *InstPrint)
static MCInstrInfo * createRISCVMCInstrInfo()
static MCAsmInfo * createRISCVMCAsmInfo(const MCRegisterInfo &MRI, const Triple &TT, const MCTargetOptions &Options)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This class is intended to be used as a base class for asm properties and features specific to the tar...
void addInitialFrameState(const MCCFIInstruction &Inst)
static MCCFIInstruction cfiDefCfa(MCSymbol *L, unsigned Register, int64_t Offset, SMLoc Loc={})
.cfi_def_cfa defines a rule for computing CFA as: take address from Register and add Offset to it.
Context object for machine code objects.
This is an instance of a target assembly language printer that converts an MCInst to valid target ass...
Instances of this class represent a single low-level machine instruction.
unsigned getOpcode() const
const MCOperand & getOperand(unsigned i) const
virtual bool isCall(const MCInst &Inst) const
virtual bool isBranch(const MCInst &Inst) const
virtual bool isUnconditionalBranch(const MCInst &Inst) const
virtual bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size, uint64_t &Target) const
Given a branch instruction try to get the address the branch targets.
virtual bool isTerminator(const MCInst &Inst) const
virtual void resetState()
Clear the internal state. See updateState for more information.
virtual bool isConditionalBranch(const MCInst &Inst) const
virtual bool isReturn(const MCInst &Inst) const
virtual void updateState(const MCInst &Inst, uint64_t Addr)
Update internal state with Inst at Addr.
virtual bool isIndirectBranch(const MCInst &Inst) const
Interface to description of machine instruction set.
void initMCObjectFileInfo(MCContext &MCCtx, bool PIC, bool LargeCodeModel=false)
unsigned getReg() const
Returns the register number.
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Wrapper class representing physical registers. Should be passed by value.
Streaming machine code generation interface.
Generic base class for all target subtargets.
const Triple & getTargetTriple() const
Target specific streamer interface.
StringRef - Represent a constant reference to a string, i.e.
constexpr bool empty() const
empty - Check if the string is empty.
Target - Wrapper for Target specific information.
Triple - Helper class for working with autoconf configuration names.
LLVM Value Representation.
Reg
All possible values of the reg field in the ModR/M byte.
This is an optimization pass for GlobalISel generic memory operations.
MCCodeEmitter * createRISCVMCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx)
Target & getTheRISCV32Target()
MCAsmBackend * createRISCVAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
Target & getTheRISCV64Target()
MCELFStreamer * createRISCVELFStreamer(MCContext &C, std::unique_ptr< MCAsmBackend > MAB, std::unique_ptr< MCObjectWriter > MOW, std::unique_ptr< MCCodeEmitter > MCE)
static void RegisterMCRegInfo(Target &T, Target::MCRegInfoCtorFnTy Fn)
RegisterMCRegInfo - Register a MCRegisterInfo implementation for the given target.
static void RegisterMCAsmBackend(Target &T, Target::MCAsmBackendCtorTy Fn)
RegisterMCAsmBackend - Register a MCAsmBackend implementation for the given target.
static void RegisterMCCodeEmitter(Target &T, Target::MCCodeEmitterCtorTy Fn)
RegisterMCCodeEmitter - Register a MCCodeEmitter implementation for the given target.
static void RegisterMCAsmInfo(Target &T, Target::MCAsmInfoCtorFnTy Fn)
RegisterMCAsmInfo - Register a MCAsmInfo implementation for the given target.
static void RegisterMCSubtargetInfo(Target &T, Target::MCSubtargetInfoCtorFnTy Fn)
RegisterMCSubtargetInfo - Register a MCSubtargetInfo implementation for the given target.
static void RegisterObjectTargetStreamer(Target &T, Target::ObjectTargetStreamerCtorTy Fn)
static void RegisterMCInstrAnalysis(Target &T, Target::MCInstrAnalysisCtorFnTy Fn)
RegisterMCInstrAnalysis - Register a MCInstrAnalysis implementation for the given target.
static void RegisterELFStreamer(Target &T, Target::ELFStreamerCtorTy Fn)
static void RegisterNullTargetStreamer(Target &T, Target::NullTargetStreamerCtorTy Fn)
static void RegisterMCInstPrinter(Target &T, Target::MCInstPrinterCtorTy Fn)
RegisterMCInstPrinter - Register a MCInstPrinter implementation for the given target.
static void RegisterMCInstrInfo(Target &T, Target::MCInstrInfoCtorFnTy Fn)
RegisterMCInstrInfo - Register a MCInstrInfo implementation for the given target.
static void RegisterMCObjectFileInfo(Target &T, Target::MCObjectFileInfoCtorFnTy Fn)
Register a MCObjectFileInfo implementation for the given target.
static void RegisterAsmTargetStreamer(Target &T, Target::AsmTargetStreamerCtorTy Fn)