LLVM 20.0.0git
RISCVMCTargetDesc.cpp
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1//===-- RISCVMCTargetDesc.cpp - RISC-V Target Descriptions ----------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8///
9/// This file provides RISC-V specific target descriptions.
10///
11//===----------------------------------------------------------------------===//
12
13#include "RISCVMCTargetDesc.h"
14#include "RISCVBaseInfo.h"
15#include "RISCVELFStreamer.h"
16#include "RISCVInstPrinter.h"
17#include "RISCVMCAsmInfo.h"
19#include "RISCVTargetStreamer.h"
21#include "llvm/ADT/STLExtras.h"
23#include "llvm/MC/MCAsmInfo.h"
26#include "llvm/MC/MCInstrInfo.h"
30#include "llvm/MC/MCStreamer.h"
34#include <bitset>
35
36#define GET_INSTRINFO_MC_DESC
37#define ENABLE_INSTR_PREDICATE_VERIFIER
38#include "RISCVGenInstrInfo.inc"
39
40#define GET_REGINFO_MC_DESC
41#include "RISCVGenRegisterInfo.inc"
42
43#define GET_SUBTARGETINFO_MC_DESC
44#include "RISCVGenSubtargetInfo.inc"
45
47
48using namespace RISCV;
49
50#define GET_RISCVVInversePseudosTable_IMPL
51#include "RISCVGenSearchableTables.inc"
52
53} // namespace llvm::RISCVVInversePseudosTable
54
55using namespace llvm;
56
58 MCInstrInfo *X = new MCInstrInfo();
59 InitRISCVMCInstrInfo(X);
60 return X;
61}
62
65 InitRISCVMCRegisterInfo(X, RISCV::X1);
66 return X;
67}
68
70 const Triple &TT,
71 const MCTargetOptions &Options) {
72 MCAsmInfo *MAI = new RISCVMCAsmInfo(TT);
73
74 MCRegister SP = MRI.getDwarfRegNum(RISCV::X2, true);
75 MCCFIInstruction Inst = MCCFIInstruction::cfiDefCfa(nullptr, SP, 0);
76 MAI->addInitialFrameState(Inst);
77
78 return MAI;
79}
80
81static MCObjectFileInfo *
83 bool LargeCodeModel = false) {
85 MOFI->initMCObjectFileInfo(Ctx, PIC, LargeCodeModel);
86 return MOFI;
87}
88
90 StringRef CPU, StringRef FS) {
91 if (CPU.empty() || CPU == "generic")
92 CPU = TT.isArch64Bit() ? "generic-rv64" : "generic-rv32";
93
94 return createRISCVMCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS);
95}
96
98 unsigned SyntaxVariant,
99 const MCAsmInfo &MAI,
100 const MCInstrInfo &MII,
101 const MCRegisterInfo &MRI) {
102 return new RISCVInstPrinter(MAI, MII, MRI);
103}
104
105static MCTargetStreamer *
107 const Triple &TT = STI.getTargetTriple();
108 if (TT.isOSBinFormatELF())
109 return new RISCVTargetELFStreamer(S, STI);
110 return nullptr;
111}
112
113static MCTargetStreamer *
115 MCInstPrinter *InstPrint) {
116 return new RISCVTargetAsmStreamer(S, OS);
117}
118
120 return new RISCVTargetStreamer(S);
121}
122
123namespace {
124
125class RISCVMCInstrAnalysis : public MCInstrAnalysis {
126 int64_t GPRState[31] = {};
127 std::bitset<31> GPRValidMask;
128
129 static bool isGPR(unsigned Reg) {
130 return Reg >= RISCV::X0 && Reg <= RISCV::X31;
131 }
132
133 static unsigned getRegIndex(unsigned Reg) {
134 assert(isGPR(Reg) && Reg != RISCV::X0 && "Invalid GPR reg");
135 return Reg - RISCV::X1;
136 }
137
138 void setGPRState(unsigned Reg, std::optional<int64_t> Value) {
139 if (Reg == RISCV::X0)
140 return;
141
142 auto Index = getRegIndex(Reg);
143
144 if (Value) {
145 GPRState[Index] = *Value;
146 GPRValidMask.set(Index);
147 } else {
148 GPRValidMask.reset(Index);
149 }
150 }
151
152 std::optional<int64_t> getGPRState(unsigned Reg) const {
153 if (Reg == RISCV::X0)
154 return 0;
155
156 auto Index = getRegIndex(Reg);
157
158 if (GPRValidMask.test(Index))
159 return GPRState[Index];
160 return std::nullopt;
161 }
162
163public:
164 explicit RISCVMCInstrAnalysis(const MCInstrInfo *Info)
166
167 void resetState() override { GPRValidMask.reset(); }
168
169 void updateState(const MCInst &Inst, uint64_t Addr) override {
170 // Terminators mark the end of a basic block which means the sequentially
171 // next instruction will be the first of another basic block and the current
172 // state will typically not be valid anymore. For calls, we assume all
173 // registers may be clobbered by the callee (TODO: should we take the
174 // calling convention into account?).
175 if (isTerminator(Inst) || isCall(Inst)) {
176 resetState();
177 return;
178 }
179
180 switch (Inst.getOpcode()) {
181 default: {
182 // Clear the state of all defined registers for instructions that we don't
183 // explicitly support.
184 auto NumDefs = Info->get(Inst.getOpcode()).getNumDefs();
185 for (unsigned I = 0; I < NumDefs; ++I) {
186 auto DefReg = Inst.getOperand(I).getReg();
187 if (isGPR(DefReg))
188 setGPRState(DefReg, std::nullopt);
189 }
190 break;
191 }
192 case RISCV::AUIPC:
193 setGPRState(Inst.getOperand(0).getReg(),
194 Addr + (Inst.getOperand(1).getImm() << 12));
195 break;
196 }
197 }
198
199 bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size,
200 uint64_t &Target) const override {
201 if (isConditionalBranch(Inst)) {
202 int64_t Imm;
203 if (Size == 2)
204 Imm = Inst.getOperand(1).getImm();
205 else
206 Imm = Inst.getOperand(2).getImm();
207 Target = Addr + Imm;
208 return true;
209 }
210
211 if (Inst.getOpcode() == RISCV::C_JAL || Inst.getOpcode() == RISCV::C_J) {
212 Target = Addr + Inst.getOperand(0).getImm();
213 return true;
214 }
215
216 if (Inst.getOpcode() == RISCV::JAL) {
217 Target = Addr + Inst.getOperand(1).getImm();
218 return true;
219 }
220
221 if (Inst.getOpcode() == RISCV::JALR) {
222 if (auto TargetRegState = getGPRState(Inst.getOperand(1).getReg())) {
223 Target = *TargetRegState + Inst.getOperand(2).getImm();
224 return true;
225 }
226
227 return false;
228 }
229
230 return false;
231 }
232
233 bool isTerminator(const MCInst &Inst) const override {
235 return true;
236
237 switch (Inst.getOpcode()) {
238 default:
239 return false;
240 case RISCV::JAL:
241 case RISCV::JALR:
242 return Inst.getOperand(0).getReg() == RISCV::X0;
243 }
244 }
245
246 bool isCall(const MCInst &Inst) const override {
247 if (MCInstrAnalysis::isCall(Inst))
248 return true;
249
250 switch (Inst.getOpcode()) {
251 default:
252 return false;
253 case RISCV::JAL:
254 case RISCV::JALR:
255 return Inst.getOperand(0).getReg() != RISCV::X0;
256 }
257 }
258
259 bool isReturn(const MCInst &Inst) const override {
261 return true;
262
263 switch (Inst.getOpcode()) {
264 default:
265 return false;
266 case RISCV::JALR:
267 return Inst.getOperand(0).getReg() == RISCV::X0 &&
268 maybeReturnAddress(Inst.getOperand(1).getReg());
269 case RISCV::C_JR:
270 return maybeReturnAddress(Inst.getOperand(0).getReg());
271 }
272 }
273
274 bool isBranch(const MCInst &Inst) const override {
276 return true;
277
278 return isBranchImpl(Inst);
279 }
280
281 bool isUnconditionalBranch(const MCInst &Inst) const override {
283 return true;
284
285 return isBranchImpl(Inst);
286 }
287
288 bool isIndirectBranch(const MCInst &Inst) const override {
290 return true;
291
292 switch (Inst.getOpcode()) {
293 default:
294 return false;
295 case RISCV::JALR:
296 return Inst.getOperand(0).getReg() == RISCV::X0 &&
297 !maybeReturnAddress(Inst.getOperand(1).getReg());
298 case RISCV::C_JR:
299 return !maybeReturnAddress(Inst.getOperand(0).getReg());
300 }
301 }
302
303private:
304 static bool maybeReturnAddress(unsigned Reg) {
305 // X1 is used for normal returns, X5 for returns from outlined functions.
306 return Reg == RISCV::X1 || Reg == RISCV::X5;
307 }
308
309 static bool isBranchImpl(const MCInst &Inst) {
310 switch (Inst.getOpcode()) {
311 default:
312 return false;
313 case RISCV::JAL:
314 return Inst.getOperand(0).getReg() == RISCV::X0;
315 case RISCV::JALR:
316 return Inst.getOperand(0).getReg() == RISCV::X0 &&
317 !maybeReturnAddress(Inst.getOperand(1).getReg());
318 case RISCV::C_JR:
319 return !maybeReturnAddress(Inst.getOperand(0).getReg());
320 }
321 }
322};
323
324} // end anonymous namespace
325
327 return new RISCVMCInstrAnalysis(Info);
328}
329
330namespace {
332 std::unique_ptr<MCAsmBackend> &&MAB,
333 std::unique_ptr<MCObjectWriter> &&MOW,
334 std::unique_ptr<MCCodeEmitter> &&MCE) {
335 return createRISCVELFStreamer(Context, std::move(MAB), std::move(MOW),
336 std::move(MCE));
337}
338} // end anonymous namespace
339
354
355 // Register the asm target streamer.
357 // Register the null target streamer.
360 }
361}
unsigned const MachineRegisterInfo * MRI
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:131
uint64_t Addr
uint64_t Size
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
static LVOptions Options
Definition: LVOptions.cpp:25
#define I(x, y, z)
Definition: MD5.cpp:58
PassInstrumentationCallbacks PIC
static MCRegisterInfo * createRISCVMCRegisterInfo(const Triple &TT)
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTargetMC()
static MCInstPrinter * createRISCVMCInstPrinter(const Triple &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI)
static MCObjectFileInfo * createRISCVMCObjectFileInfo(MCContext &Ctx, bool PIC, bool LargeCodeModel=false)
static MCTargetStreamer * createRISCVNullTargetStreamer(MCStreamer &S)
static MCSubtargetInfo * createRISCVMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS)
static MCTargetStreamer * createRISCVObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI)
static MCInstrAnalysis * createRISCVInstrAnalysis(const MCInstrInfo *Info)
static MCTargetStreamer * createRISCVAsmTargetStreamer(MCStreamer &S, formatted_raw_ostream &OS, MCInstPrinter *InstPrint)
static MCInstrInfo * createRISCVMCInstrInfo()
static MCAsmInfo * createRISCVMCAsmInfo(const MCRegisterInfo &MRI, const Triple &TT, const MCTargetOptions &Options)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file contains some templates that are useful if you are working with the STL at all.
raw_pwrite_stream & OS
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:56
void addInitialFrameState(const MCCFIInstruction &Inst)
Definition: MCAsmInfo.cpp:75
static MCCFIInstruction cfiDefCfa(MCSymbol *L, unsigned Register, int64_t Offset, SMLoc Loc={})
.cfi_def_cfa defines a rule for computing CFA as: take address from Register and add Offset to it.
Definition: MCDwarf.h:558
Context object for machine code objects.
Definition: MCContext.h:83
This is an instance of a target assembly language printer that converts an MCInst to valid target ass...
Definition: MCInstPrinter.h:45
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
unsigned getOpcode() const
Definition: MCInst.h:198
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:206
virtual bool isCall(const MCInst &Inst) const
virtual bool isBranch(const MCInst &Inst) const
virtual bool isUnconditionalBranch(const MCInst &Inst) const
virtual bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size, uint64_t &Target) const
Given a branch instruction try to get the address the branch targets.
virtual bool isTerminator(const MCInst &Inst) const
virtual void resetState()
Clear the internal state. See updateState for more information.
virtual bool isConditionalBranch(const MCInst &Inst) const
virtual bool isReturn(const MCInst &Inst) const
virtual void updateState(const MCInst &Inst, uint64_t Addr)
Update internal state with Inst at Addr.
virtual bool isIndirectBranch(const MCInst &Inst) const
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:26
void initMCObjectFileInfo(MCContext &MCCtx, bool PIC, bool LargeCodeModel=false)
int64_t getImm() const
Definition: MCInst.h:80
unsigned getReg() const
Returns the register number.
Definition: MCInst.h:69
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:33
Streaming machine code generation interface.
Definition: MCStreamer.h:213
Generic base class for all target subtargets.
const Triple & getTargetTriple() const
Target specific streamer interface.
Definition: MCStreamer.h:94
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
constexpr bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:134
Target - Wrapper for Target specific information.
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
LLVM Value Representation.
Definition: Value.h:74
formatted_raw_ostream - A raw_ostream that wraps another one and keeps track of line and column posit...
Reg
All possible values of the reg field in the ModR/M byte.
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
MCCodeEmitter * createRISCVMCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx)
Target & getTheRISCV32Target()
MCAsmBackend * createRISCVAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
Target & getTheRISCV64Target()
MCELFStreamer * createRISCVELFStreamer(MCContext &C, std::unique_ptr< MCAsmBackend > MAB, std::unique_ptr< MCObjectWriter > MOW, std::unique_ptr< MCCodeEmitter > MCE)
static void RegisterMCRegInfo(Target &T, Target::MCRegInfoCtorFnTy Fn)
RegisterMCRegInfo - Register a MCRegisterInfo implementation for the given target.
static void RegisterMCAsmBackend(Target &T, Target::MCAsmBackendCtorTy Fn)
RegisterMCAsmBackend - Register a MCAsmBackend implementation for the given target.
static void RegisterMCCodeEmitter(Target &T, Target::MCCodeEmitterCtorTy Fn)
RegisterMCCodeEmitter - Register a MCCodeEmitter implementation for the given target.
static void RegisterMCAsmInfo(Target &T, Target::MCAsmInfoCtorFnTy Fn)
RegisterMCAsmInfo - Register a MCAsmInfo implementation for the given target.
static void RegisterMCSubtargetInfo(Target &T, Target::MCSubtargetInfoCtorFnTy Fn)
RegisterMCSubtargetInfo - Register a MCSubtargetInfo implementation for the given target.
static void RegisterObjectTargetStreamer(Target &T, Target::ObjectTargetStreamerCtorTy Fn)
static void RegisterMCInstrAnalysis(Target &T, Target::MCInstrAnalysisCtorFnTy Fn)
RegisterMCInstrAnalysis - Register a MCInstrAnalysis implementation for the given target.
static void RegisterELFStreamer(Target &T, Target::ELFStreamerCtorTy Fn)
static void RegisterNullTargetStreamer(Target &T, Target::NullTargetStreamerCtorTy Fn)
static void RegisterMCInstPrinter(Target &T, Target::MCInstPrinterCtorTy Fn)
RegisterMCInstPrinter - Register a MCInstPrinter implementation for the given target.
static void RegisterMCInstrInfo(Target &T, Target::MCInstrInfoCtorFnTy Fn)
RegisterMCInstrInfo - Register a MCInstrInfo implementation for the given target.
static void RegisterMCObjectFileInfo(Target &T, Target::MCObjectFileInfoCtorFnTy Fn)
Register a MCObjectFileInfo implementation for the given target.
static void RegisterAsmTargetStreamer(Target &T, Target::AsmTargetStreamerCtorTy Fn)