LLVM 22.0.0git
Public Member Functions | Protected Attributes | Friends | List of all members
llvm::MCInstrAnalysis Class Reference

#include "llvm/MC/MCInstrAnalysis.h"

Inheritance diagram for llvm::MCInstrAnalysis:
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Public Member Functions

 MCInstrAnalysis (const MCInstrInfo *Info)
virtual ~MCInstrAnalysis ()=default
virtual void resetState ()
 Clear the internal state. See updateState for more information.
virtual void updateState (const MCInst &Inst, uint64_t Addr)
 Update internal state with Inst at Addr.
virtual bool isBranch (const MCInst &Inst) const
virtual bool isConditionalBranch (const MCInst &Inst) const
virtual bool isUnconditionalBranch (const MCInst &Inst) const
virtual bool isIndirectBranch (const MCInst &Inst) const
virtual bool isCall (const MCInst &Inst) const
virtual bool isReturn (const MCInst &Inst) const
virtual bool isTerminator (const MCInst &Inst) const
virtual bool isBarrier (const MCInst &Inst) const
virtual bool mayAffectControlFlow (const MCInst &Inst, const MCRegisterInfo &MCRI) const
virtual bool clearsSuperRegisters (const MCRegisterInfo &MRI, const MCInst &Inst, APInt &Writes) const
 Returns true if at least one of the register writes performed by.
virtual bool isZeroIdiom (const MCInst &MI, APInt &Mask, unsigned CPUID) const
 Returns true if MI is a dependency breaking zero-idiom for the given subtarget.
virtual bool isDependencyBreaking (const MCInst &MI, APInt &Mask, unsigned CPUID) const
 Returns true if MI is a dependency breaking instruction for the subtarget associated with CPUID .
virtual bool isOptimizableRegisterMove (const MCInst &MI, unsigned CPUID) const
 Returns true if MI is a candidate for move elimination.
virtual bool evaluateBranch (const MCInst &Inst, uint64_t Addr, uint64_t Size, uint64_t &Target) const
 Given a branch instruction try to get the address the branch targets.
virtual std::optional< uint64_t > evaluateMemoryOperandAddress (const MCInst &Inst, const MCSubtargetInfo *STI, uint64_t Addr, uint64_t Size) const
 Given an instruction tries to get the address of a memory operand.
virtual std::optional< uint64_t > getMemoryOperandRelocationOffset (const MCInst &Inst, uint64_t Size) const
 Given an instruction with a memory operand that could require relocation, returns the offset within the instruction of that relocation.
virtual std::vector< std::pair< uint64_t, uint64_t > > findPltEntries (uint64_t PltSectionVA, ArrayRef< uint8_t > PltContents, const MCSubtargetInfo &STI) const
 Returns (PLT virtual address, GOT virtual address) pairs for PLT entries.

Protected Attributes

const MCInstrInfo * Info

Friends

class Target

Detailed Description

Definition at line 31 of file MCInstrAnalysis.h.

Constructor & Destructor Documentation

◆ MCInstrAnalysis()

llvm::MCInstrAnalysis::MCInstrAnalysis ( const MCInstrInfo * Info)
inline

Definition at line 38 of file MCInstrAnalysis.h.

References Info.

Referenced by llvm::AMDGPU::AMDGPUMCInstrAnalysis::AMDGPUMCInstrAnalysis(), and llvm::X86_MC::X86MCInstrAnalysis::X86MCInstrAnalysis().

◆ ~MCInstrAnalysis()

virtual llvm::MCInstrAnalysis::~MCInstrAnalysis ( )
virtualdefault

Member Function Documentation

◆ clearsSuperRegisters()

bool MCInstrAnalysis::clearsSuperRegisters ( const MCRegisterInfo & MRI,
const MCInst & Inst,
APInt & Writes ) const
virtual

Returns true if at least one of the register writes performed by.

Parameters
Instimplicitly clears the upper portion of all super-registers.

Example: on X86-64, a write to EAX implicitly clears the upper half of RAX. Also (still on x86) an XMM write perfomed by an AVX 128-bit instruction implicitly clears the upper portion of the correspondent YMM register.

This method also updates an APInt which is used as mask of register writes. There is one bit for every explicit/implicit write performed by the instruction. If a write implicitly clears its super-registers, then the corresponding bit is set (vic. the corresponding bit is cleared).

The first bits in the APint are related to explicit writes. The remaining bits are related to implicit writes. The sequence of writes follows the machine operand sequence. For implicit writes, the sequence is defined by the MCInstrDesc.

The assumption is that the bit-width of the APInt is correctly set by the caller. The default implementation conservatively assumes that none of the writes clears the upper portion of a super-register.

Reimplemented in llvm::X86_MC::X86MCInstrAnalysis.

Definition at line 20 of file MCInstrAnalysis.cpp.

References llvm::APInt::clearAllBits(), and MRI.

◆ evaluateBranch()

bool MCInstrAnalysis::evaluateBranch ( const MCInst & Inst,
uint64_t Addr,
uint64_t Size,
uint64_t & Target ) const
virtual

Given a branch instruction try to get the address the branch targets.

Return true on success, and the address in Target.

Reimplemented in llvm::AMDGPU::AMDGPUMCInstrAnalysis, and llvm::X86_MC::X86MCInstrAnalysis.

Definition at line 27 of file MCInstrAnalysis.cpp.

◆ evaluateMemoryOperandAddress()

std::optional< uint64_t > MCInstrAnalysis::evaluateMemoryOperandAddress ( const MCInst & Inst,
const MCSubtargetInfo * STI,
uint64_t Addr,
uint64_t Size ) const
virtual

Given an instruction tries to get the address of a memory operand.

Returns the address on success.

Reimplemented in llvm::X86_MC::X86MCInstrAnalysis.

Definition at line 33 of file MCInstrAnalysis.cpp.

References Size.

Referenced by llvm::orc::addFunctionPointerRelocationsToCurrentSymbol().

◆ findPltEntries()

virtual std::vector< std::pair< uint64_t, uint64_t > > llvm::MCInstrAnalysis::findPltEntries ( uint64_t PltSectionVA,
ArrayRef< uint8_t > PltContents,
const MCSubtargetInfo & STI ) const
inlinevirtual

Returns (PLT virtual address, GOT virtual address) pairs for PLT entries.

Reimplemented in llvm::X86_MC::X86MCInstrAnalysis.

Definition at line 202 of file MCInstrAnalysis.h.

◆ getMemoryOperandRelocationOffset()

std::optional< uint64_t > MCInstrAnalysis::getMemoryOperandRelocationOffset ( const MCInst & Inst,
uint64_t Size ) const
virtual

Given an instruction with a memory operand that could require relocation, returns the offset within the instruction of that relocation.

Reimplemented in llvm::X86_MC::X86MCInstrAnalysis.

Definition at line 40 of file MCInstrAnalysis.cpp.

References Size.

Referenced by llvm::orc::addFunctionPointerRelocationsToCurrentSymbol().

◆ isBarrier()

virtual bool llvm::MCInstrAnalysis::isBarrier ( const MCInst & Inst) const
inlinevirtual

Definition at line 84 of file MCInstrAnalysis.h.

References llvm::MCInst::getOpcode(), and Info.

◆ isBranch()

virtual bool llvm::MCInstrAnalysis::isBranch ( const MCInst & Inst) const
inlinevirtual

Definition at line 56 of file MCInstrAnalysis.h.

References llvm::MCInst::getOpcode(), and Info.

◆ isCall()

virtual bool llvm::MCInstrAnalysis::isCall ( const MCInst & Inst) const
inlinevirtual

Definition at line 72 of file MCInstrAnalysis.h.

References llvm::MCInst::getOpcode(), and Info.

Referenced by mayAffectControlFlow().

◆ isConditionalBranch()

virtual bool llvm::MCInstrAnalysis::isConditionalBranch ( const MCInst & Inst) const
inlinevirtual

Definition at line 60 of file MCInstrAnalysis.h.

References llvm::MCInst::getOpcode(), and Info.

◆ isDependencyBreaking()

virtual bool llvm::MCInstrAnalysis::isDependencyBreaking ( const MCInst & MI,
APInt & Mask,
unsigned CPUID ) const
inlinevirtual

Returns true if MI is a dependency breaking instruction for the subtarget associated with CPUID .

The value computed by a dependency breaking instruction is not dependent on the inputs. An example of dependency breaking instruction on X86 is XOR eax, eax.

If MI is a dependency breaking instruction for subtarget CPUID, then Mask can be inspected to identify independent operands.

Essentially, each bit of the mask corresponds to an input operand. Explicit operands are laid out first in the mask; implicit operands follow explicit operands. Bits are set for operands that are independent.

Note that the number of bits in Mask may not be equivalent to the sum of explicit and implicit operands in MI. Operands that don't have a corresponding bit in Mask are assumed "not independente".

The only exception is for when Mask is all zeroes. That means: explicit input operands of MI are independent.

Definition at line 167 of file MCInstrAnalysis.h.

References isZeroIdiom(), and MI.

◆ isIndirectBranch()

virtual bool llvm::MCInstrAnalysis::isIndirectBranch ( const MCInst & Inst) const
inlinevirtual

Definition at line 68 of file MCInstrAnalysis.h.

References llvm::MCInst::getOpcode(), and Info.

Referenced by mayAffectControlFlow().

◆ isOptimizableRegisterMove()

virtual bool llvm::MCInstrAnalysis::isOptimizableRegisterMove ( const MCInst & MI,
unsigned CPUID ) const
inlinevirtual

Returns true if MI is a candidate for move elimination.

Different subtargets may apply different constraints to optimizable register moves. For example, on most X86 subtargets, a candidate for move elimination cannot specify the same register for both source and destination.

Definition at line 178 of file MCInstrAnalysis.h.

References MI.

◆ isReturn()

virtual bool llvm::MCInstrAnalysis::isReturn ( const MCInst & Inst) const
inlinevirtual

Definition at line 76 of file MCInstrAnalysis.h.

References llvm::MCInst::getOpcode(), and Info.

Referenced by mayAffectControlFlow().

◆ isTerminator()

virtual bool llvm::MCInstrAnalysis::isTerminator ( const MCInst & Inst) const
inlinevirtual

Definition at line 80 of file MCInstrAnalysis.h.

References llvm::MCInst::getOpcode(), and Info.

Referenced by llvm::AMDGPU::AMDGPUMCInstrAnalysis::updateState().

◆ isUnconditionalBranch()

virtual bool llvm::MCInstrAnalysis::isUnconditionalBranch ( const MCInst & Inst) const
inlinevirtual

Definition at line 64 of file MCInstrAnalysis.h.

References llvm::MCInst::getOpcode(), and Info.

◆ isZeroIdiom()

virtual bool llvm::MCInstrAnalysis::isZeroIdiom ( const MCInst & MI,
APInt & Mask,
unsigned CPUID ) const
inlinevirtual

Returns true if MI is a dependency breaking zero-idiom for the given subtarget.

Mask is used to identify input operands that have their dependency broken. Each bit of the mask is associated with a specific input operand. Bits associated with explicit input operands are laid out first in the mask; implicit operands come after explicit operands.

Dependencies are broken only for operands that have their corresponding bit set. Operands that have their bit cleared, or that don't have a corresponding bit in the mask don't have their dependency broken. Note that Mask may not be big enough to describe all operands. The assumption for operands that don't have a correspondent bit in the mask is that those are still data dependent.

The only exception to the rule is for when Mask has all zeroes. A zero mask means: dependencies are broken for all explicit register operands.

Definition at line 142 of file MCInstrAnalysis.h.

References MI.

Referenced by isDependencyBreaking().

◆ mayAffectControlFlow()

virtual bool llvm::MCInstrAnalysis::mayAffectControlFlow ( const MCInst & Inst,
const MCRegisterInfo & MCRI ) const
inlinevirtual

Definition at line 88 of file MCInstrAnalysis.h.

References llvm::MCInst::getOpcode(), llvm::MCRegisterInfo::getProgramCounter(), Info, isBranch(), isCall(), isIndirectBranch(), and isReturn().

◆ resetState()

virtual void llvm::MCInstrAnalysis::resetState ( )
inlinevirtual

Clear the internal state. See updateState for more information.

Reimplemented in llvm::AMDGPU::AMDGPUMCInstrAnalysis.

Definition at line 42 of file MCInstrAnalysis.h.

◆ updateState()

virtual void llvm::MCInstrAnalysis::updateState ( const MCInst & Inst,
uint64_t Addr )
inlinevirtual

Update internal state with Inst at Addr.

For some types of analyses, inspecting a single instruction is not sufficient. Some examples are auipc/jalr pairs on RISC-V or adrp/ldr pairs on AArch64. To support inspecting multiple instructions, targets may keep track of an internal state while analysing instructions. Clients should call updateState for every instruction which allows later calls to one of the analysis functions to take previous instructions into account. Whenever state becomes irrelevant (e.g., when starting to disassemble a new function), clients should call resetState to clear it.

Reimplemented in llvm::AMDGPU::AMDGPUMCInstrAnalysis.

Definition at line 54 of file MCInstrAnalysis.h.

◆ Target

friend class Target
friend

Definition at line 33 of file MCInstrAnalysis.h.

References Target.

Referenced by llvm::AMDGPU::AMDGPUMCInstrAnalysis::evaluateBranch(), llvm::X86_MC::X86MCInstrAnalysis::evaluateBranch(), and Target.

Member Data Documentation

◆ Info

const MCInstrInfo* llvm::MCInstrAnalysis::Info
protected

Definition at line 35 of file MCInstrAnalysis.h.

Referenced by llvm::AMDGPU::AMDGPUMCInstrAnalysis::AMDGPUMCInstrAnalysis(), llvm::X86_MC::X86MCInstrAnalysis::clearsSuperRegisters(), llvm::AMDGPU::AMDGPUMCInstrAnalysis::evaluateBranch(), llvm::X86_MC::X86MCInstrAnalysis::evaluateBranch(), llvm::X86_MC::X86MCInstrAnalysis::evaluateMemoryOperandAddress(), llvm::X86_MC::X86MCInstrAnalysis::getMemoryOperandRelocationOffset(), isBarrier(), isBranch(), isCall(), isConditionalBranch(), isIndirectBranch(), isReturn(), isTerminator(), isUnconditionalBranch(), mayAffectControlFlow(), and MCInstrAnalysis().

The documentation for this class was generated from the following files:
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