LLVM 20.0.0git
MCInstrAnalysis.cpp
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1//===- MCInstrAnalysis.cpp - InstrDesc target hooks -----------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
10
11#include "llvm/ADT/APInt.h"
12#include <cstdint>
13
14namespace llvm {
15class MCSubtargetInfo;
16}
17
18using namespace llvm;
19
21 const MCInst &Inst,
22 APInt &Writes) const {
23 Writes.clearAllBits();
24 return false;
25}
26
27bool MCInstrAnalysis::evaluateBranch(const MCInst & /*Inst*/, uint64_t /*Addr*/,
28 uint64_t /*Size*/,
29 uint64_t & /*Target*/) const {
30 return false;
31}
32
34 const MCInst &Inst, const MCSubtargetInfo *STI, uint64_t Addr,
35 uint64_t Size) const {
36 return std::nullopt;
37}
38
39std::optional<uint64_t>
41 uint64_t Size) const {
42 return std::nullopt;
43}
unsigned const MachineRegisterInfo * MRI
This file implements a class to represent arbitrary precision integral constant values and operations...
uint64_t Addr
uint64_t Size
SmallVector< uint32_t, 0 > Writes
Definition: ELF_riscv.cpp:497
Class for arbitrary precision integers.
Definition: APInt.h:78
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
virtual std::optional< uint64_t > getMemoryOperandRelocationOffset(const MCInst &Inst, uint64_t Size) const
Given an instruction with a memory operand that could require relocation, returns the offset within t...
virtual bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size, uint64_t &Target) const
Given a branch instruction try to get the address the branch targets.
virtual std::optional< uint64_t > evaluateMemoryOperandAddress(const MCInst &Inst, const MCSubtargetInfo *STI, uint64_t Addr, uint64_t Size) const
Given an instruction tries to get the address of a memory operand.
virtual bool clearsSuperRegisters(const MCRegisterInfo &MRI, const MCInst &Inst, APInt &Writes) const
Returns true if at least one of the register writes performed by.
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Generic base class for all target subtargets.
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18