24#define PROC(ENUM, NAME, DEFAULT_MARCH, FAST_SCALAR_UNALIGN, \
25 FAST_VECTOR_UNALIGN) \
27#define TUNE_PROC(ENUM, NAME) CK_##ENUM,
28#include "llvm/TargetParser/RISCVTargetParserDef.inc"
40#define PROC(ENUM, NAME, DEFAULT_MARCH, FAST_SCALAR_UNALIGN, \
41 FAST_VECTOR_UNALIGN) \
42 {NAME, DEFAULT_MARCH, FAST_SCALAR_UNALIGN, FAST_VECTOR_UNALIGN},
43#include "llvm/TargetParser/RISCVTargetParserDef.inc"
55 return Info &&
Info->FastScalarUnalignedAccess;
60 return Info &&
Info->FastVectorUnalignedAccess;
68 return Info->is64Bit() == IsRV64;
72 std::optional<CPUKind> Kind =
75 #include "llvm/TargetParser/RISCVTargetParserDef.inc"
76 .Default(std::nullopt);
89 return Info->DefaultMarch;
94 if (IsRV64 ==
C.is64Bit())
101 if (IsRV64 ==
C.is64Bit())
104#define TUNE_PROC(ENUM, NAME) Values.emplace_back(StringRef(NAME));
105#include "llvm/TargetParser/RISCVTargetParserDef.inc"
113 if (MarchFromCPU ==
"")
116 EnabledFeatures.
clear();
123 std::vector<std::string> FeatStrings =
124 (*RII)->toFeatures(
false);
125 for (
const auto &
F : FeatStrings)
132namespace RISCVExtensionBitmaskTable {
133#define GET_RISCVExtensionBitmaskTable_IMPL
134#include "llvm/TargetParser/RISCVTargetParserDef.inc"
140 bool operator()(
const RISCVExtensionBitmaskTable::RISCVExtensionBitmask &
LHS,
142 return StringRef(
LHS.Name) <
RHS;
149namespace RISCVVType {
162 unsigned VLMULBits =
static_cast<unsigned>(VLMUL);
164 unsigned VTypeI = (VSEWBits << 3) | (VLMULBits & 0x7);
181 return std::make_pair(1 <<
static_cast<unsigned>(VLMUL),
false);
185 return std::make_pair(1 << (8 -
static_cast<unsigned>(VLMUL)),
true);
190 unsigned Sew =
getSEW(VType);
220 LMul = Fractional ? (8 / LMul) : (LMul * 8);
222 assert(SEW >= 8 &&
"Unexpected SEW value");
223 return (SEW * 8) / LMul;
226std::optional<RISCVII::VLMUL>
229 unsigned EMULFixedPoint = (EEW * 8) / Ratio;
230 bool Fractional = EMULFixedPoint < 8;
231 unsigned EMUL = Fractional ? 8 / EMULFixedPoint : EMULFixedPoint / 8;
Analysis containing CSE Info
#define TUNE_PROC(ENUM, NAME)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file defines the SmallVector class.
This file implements the StringSwitch template, which mimics a switch() statement whose cases are str...
static llvm::Expected< std::unique_ptr< RISCVISAInfo > > parseArchString(StringRef Arch, bool EnableExperimentalExtension, bool ExperimentalExtensionVersionCheck=true)
Parse RISC-V ISA info from arch string.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
reference emplace_back(ArgTypes &&... Args)
void push_back(const T &Elt)
A wrapper around a string literal that serves as a proxy for constructing global tables of StringRefs...
StringRef - Represent a constant reference to a string, i.e.
bool starts_with(StringRef Prefix) const
Check if this string starts with the given Prefix.
A switch()-like statement whose cases are string literals.
This class implements an extremely fast bulk output stream that can only output to a stream.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ C
The default llvm calling convention, compatible with C.
static bool isTailAgnostic(unsigned VType)
static RISCVII::VLMUL getVLMUL(unsigned VType)
std::pair< unsigned, bool > decodeVLMUL(RISCVII::VLMUL VLMUL)
unsigned getSEWLMULRatio(unsigned SEW, RISCVII::VLMUL VLMul)
static bool isValidLMUL(unsigned LMUL, bool Fractional)
static RISCVII::VLMUL encodeLMUL(unsigned LMUL, bool Fractional)
static bool isMaskAgnostic(unsigned VType)
static unsigned encodeSEW(unsigned SEW)
static bool isValidSEW(unsigned SEW)
void printVType(unsigned VType, raw_ostream &OS)
unsigned encodeVTYPE(RISCVII::VLMUL VLMUL, unsigned SEW, bool TailAgnostic, bool MaskAgnostic)
static unsigned getSEW(unsigned VType)
std::optional< RISCVII::VLMUL > getSameRatioLMUL(unsigned SEW, RISCVII::VLMUL VLMUL, unsigned EEW)
bool hasFastVectorUnalignedAccess(StringRef CPU)
void getFeaturesForCPU(StringRef CPU, SmallVectorImpl< std::string > &EnabledFeatures, bool NeedPlus=false)
void fillValidTuneCPUArchList(SmallVectorImpl< StringRef > &Values, bool IsRV64)
static const CPUInfo * getCPUInfoByName(StringRef CPU)
constexpr CPUInfo RISCVCPUInfo[]
StringRef getMArchFromMcpu(StringRef CPU)
bool parseCPU(StringRef CPU, bool IsRV64)
bool hasFastScalarUnalignedAccess(StringRef CPU)
bool parseTuneCPU(StringRef CPU, bool IsRV64)
void fillValidCPUArchList(SmallVectorImpl< StringRef > &Values, bool IsRV64)
This is an optimization pass for GlobalISel generic memory operations.
bool errorToBool(Error Err)
Helper for converting an Error to a bool.
StringLiteral DefaultMarch
bool FastVectorUnalignedAccess
bool FastScalarUnalignedAccess