13#ifndef LLVM_LIB_TARGET_RISCV_RISCVSUBTARGET_H
14#define LLVM_LIB_TARGET_RISCV_RISCVSUBTARGET_H
30#define GET_RISCV_MACRO_FUSION_PRED_DECL
31#include "RISCVGenMacroFusion.inc"
33#define GET_SUBTARGETINFO_HEADER
34#include "RISCVGenSubtargetInfo.inc"
39namespace RISCVTuneInfoTable {
58#define GET_RISCVTuneInfoTable_DECL
59#include "RISCVGenSearchableTables.inc"
72 virtual void anchor();
76#define GET_SUBTARGETINFO_MACRO(ATTRIBUTE, DEFAULT, GETTER) \
77 bool ATTRIBUTE = DEFAULT;
78#include "RISCVGenSubtargetInfo.inc"
81 unsigned RVVVectorBitsMin;
82 unsigned RVVVectorBitsMax;
83 uint8_t MaxInterleaveFactor = 2;
85 std::bitset<RISCV::NUM_TARGET_REGS> UserReservedRegister;
113 return &FrameLowering;
142#define GET_SUBTARGETINFO_MACRO(ATTRIBUTE, DEFAULT, GETTER) \
143 bool GETTER() const { return ATTRIBUTE; }
144#include "RISCVGenSubtargetInfo.inc"
149 return HasStdExtC || HasStdExtZcf || HasStdExtZce;
156 return HasStdExtZfhmin || HasStdExtZhinxmin;
159 return HasStdExtZfhmin || HasStdExtZfbfmin;
165 hasShortForwardBranchOpt();
170 return is64Bit() ? MVT::i64 : MVT::i32;
190 return VLen == 0 ? ZvlLen : VLen;
194 return VLen == 0 ? 65536 : VLen;
208 if (
auto VLen =
getRealVLen(); VLen &&
X.isScalable()) {
210 X = Quantity::getFixed(
X.getKnownMinValue() * VScale);
222 assert(i < RISCV::NUM_TARGET_REGS &&
"Register out of range");
223 return UserReservedRegister[i];
284 &Mutations)
const override;
286 bool useAA()
const override;
295 unsigned NumStridedMemAccesses,
296 unsigned NumPrefetches,
297 bool HasCall)
const override {
This file describes how to lower LLVM calls to machine code calls.
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
Interface for Targets to specify which operations they can successfully select and how the others sho...
This file declares the targeting of the RegisterBankInfo class for RISC-V.
static cl::opt< unsigned > RVVVectorLMULMax("riscv-v-fixed-length-vector-lmul-max", cl::desc("The maximum LMUL value to use for fixed length vectors. " "Fractional LMUL values are not supported."), cl::init(8), cl::Hidden)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This class provides the information for the target register banks.
RISCVABI::ABI getTargetABI() const
unsigned getMinimumJumpTableEntries() const
bool hasStdExtCOrZca() const
void getPostRAMutations(std::vector< std::unique_ptr< ScheduleDAGMutation > > &Mutations) const override
const LegalizerInfo * getLegalizerInfo() const override
std::unique_ptr< LegalizerInfo > Legalizer
unsigned getMaxLMULForFixedLengthVectors() const
bool hasVInstructionsI64() const
unsigned getMaxPrefetchIterationsAhead() const override
bool hasVInstructionsF64() const
bool hasStdExtDOrZdinx() const
const SelectionDAGTargetInfo * getSelectionDAGInfo() const override
bool hasStdExtZfhOrZhinx() const
unsigned getTailDupAggressiveThreshold() const
unsigned getRealMinVLen() const
Quantity expandVScale(Quantity X) const
If the ElementCount or TypeSize X is scalable and VScale (VLEN) is exactly known, returns X converted...
bool useRVVForFixedLengthVectors() const
bool isTargetFuchsia() const
bool hasVInstructionsBF16Minimal() const
unsigned getDLenFactor() const
unsigned getMinRVVVectorSizeInBits() const
std::unique_ptr< InstructionSelector > InstSelector
bool hasVInstructionsF16Minimal() const
bool hasConditionalMoveFusion() const
bool isRegisterReservedByUser(Register i) const
bool hasVInstructionsF16() const
const RISCVRegisterBankInfo * getRegBankInfo() const override
const CallLowering * getCallLowering() const override
bool enableMachineScheduler() const override
InstructionSelector * getInstructionSelector() const override
unsigned getMaxBuildIntsCost() const
Align getPrefLoopAlignment() const
bool hasVInstructions() const
bool useAA() const override
Enable use of alias analysis during code generation (during MI scheduling, DAGCombine,...
bool hasVInstructionsAnyF() const
std::optional< unsigned > getRealVLen() const
bool useConstantPoolForLargeInts() const
bool hasStdExtCOrZcfOrZce() const
Align getPrefFunctionAlignment() const
RISCVProcFamilyEnum getProcFamily() const
Returns RISC-V processor family.
unsigned getMaxRVVVectorSizeInBits() const
bool hasStdExtZfhminOrZhinxmin() const
unsigned getRealMaxVLen() const
unsigned getMinPrefetchStride(unsigned NumMemAccesses, unsigned NumStridedMemAccesses, unsigned NumPrefetches, bool HasCall) const override
void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS)
const RISCVRegisterInfo * getRegisterInfo() const override
std::unique_ptr< RISCVRegisterBankInfo > RegBankInfo
const RISCVInstrInfo * getInstrInfo() const override
unsigned getCacheLineSize() const override
std::unique_ptr< CallLowering > CallLoweringInfo
bool hasStdExtCOrZcd() const
bool hasVInstructionsFullMultiply() const
const RISCVTargetLowering * getTargetLowering() const override
bool hasVInstructionsF32() const
unsigned getMaxInterleaveFactor() const
bool supportsInitUndef() const override
bool enableSubRegLiveness() const override
bool isTargetAndroid() const
bool hasStdExtFOrZfinx() const
bool enablePostRAScheduler() const override
bool hasStdExtZvl() const
bool hasHalfFPLoadStoreMove() const
const RISCVFrameLowering * getFrameLowering() const override
unsigned getPrefetchDistance() const override
Wrapper class representing virtual and physical registers.
Targets can subclass this to parameterize the SelectionDAG lowering and instruction selection process...
StringRef - Represent a constant reference to a string, i.e.
Primary interface to the complete machine description for the target machine.
Triple - Helper class for working with autoconf configuration names.
static constexpr unsigned RVVBitsPerBlock
This is an optimization pass for GlobalISel generic memory operations.
This struct is a compact representation of a valid (non-zero power of two) alignment.
uint16_t PrefetchDistance
uint8_t PrefLoopAlignment
uint8_t PrefFunctionAlignment
unsigned MaxPrefetchIterationsAhead
unsigned TailDupAggressiveThreshold
uint16_t MinPrefetchStride
unsigned MinimumJumpTableEntries