22#define GET_TARGET_REGBANK_IMPL
23#include "RISCVGenRegisterBank.inc"
134bool RISCVRegisterBankInfo::hasFPConstraints(
142 if (
MI.getOpcode() != TargetOpcode::COPY)
151 switch (
MI.getOpcode()) {
152 case TargetOpcode::G_FPTOSI:
153 case TargetOpcode::G_FPTOUI:
154 case TargetOpcode::G_FCMP:
160 return hasFPConstraints(
MI,
MRI,
TRI);
166 switch (
MI.getOpcode()) {
167 case TargetOpcode::G_SITOFP:
168 case TargetOpcode::G_UITOFP:
174 return hasFPConstraints(
MI,
MRI,
TRI);
177bool RISCVRegisterBankInfo::anyUseOnlyUseFP(
181 MRI.use_nodbg_instructions(Def),
190 else if (
Size == 128)
192 else if (
Size == 256)
194 else if (
Size == 512)
204 const unsigned Opc =
MI.getOpcode();
220 assert((GPRSize == 32 || GPRSize == 64) &&
"Unexpected GPR size");
222 unsigned NumOperands =
MI.getNumOperands();
228 case TargetOpcode::G_ADD:
229 case TargetOpcode::G_SUB:
230 case TargetOpcode::G_SHL:
231 case TargetOpcode::G_ASHR:
232 case TargetOpcode::G_LSHR:
233 case TargetOpcode::G_AND:
234 case TargetOpcode::G_OR:
235 case TargetOpcode::G_XOR:
236 case TargetOpcode::G_MUL:
237 case TargetOpcode::G_SDIV:
238 case TargetOpcode::G_SREM:
239 case TargetOpcode::G_SMULH:
240 case TargetOpcode::G_SMAX:
241 case TargetOpcode::G_SMIN:
242 case TargetOpcode::G_UDIV:
243 case TargetOpcode::G_UREM:
244 case TargetOpcode::G_UMULH:
245 case TargetOpcode::G_UMAX:
246 case TargetOpcode::G_UMIN:
247 case TargetOpcode::G_PTR_ADD:
248 case TargetOpcode::G_PTRTOINT:
249 case TargetOpcode::G_INTTOPTR:
250 case TargetOpcode::G_FADD:
251 case TargetOpcode::G_FSUB:
252 case TargetOpcode::G_FMUL:
253 case TargetOpcode::G_FDIV:
254 case TargetOpcode::G_FABS:
255 case TargetOpcode::G_FNEG:
256 case TargetOpcode::G_FSQRT:
257 case TargetOpcode::G_FMAXNUM:
258 case TargetOpcode::G_FMINNUM: {
259 LLT Ty =
MRI.getType(
MI.getOperand(0).getReg());
268 Mapping = GPRValueMapping;
272 for (
unsigned Idx = 1;
Idx != NumOperands; ++
Idx) {
273 LLT OpTy =
MRI.getType(
MI.getOperand(
Idx).getReg());
275 "Operand has incompatible type");
284 case TargetOpcode::G_SEXTLOAD:
285 case TargetOpcode::G_ZEXTLOAD:
288 case TargetOpcode::G_IMPLICIT_DEF: {
290 LLT DstTy =
MRI.getType(Dst);
292 auto Mapping = GPRValueMapping;
300 else if (anyUseOnlyUseFP(Dst,
MRI,
TRI))
311 case TargetOpcode::G_LOAD: {
312 LLT Ty =
MRI.getType(
MI.getOperand(0).getReg());
315 OpdsMapping[1] = GPRValueMapping;
322 OpdsMapping[0] = GPRValueMapping;
325 if (GPRSize == 32 &&
Size.getFixedValue() == 64) {
334 if (anyUseOnlyUseFP(
MI.getOperand(0).getReg(),
MRI,
TRI))
343 case TargetOpcode::G_STORE: {
344 LLT Ty =
MRI.getType(
MI.getOperand(0).getReg());
347 OpdsMapping[1] = GPRValueMapping;
354 OpdsMapping[0] = GPRValueMapping;
357 if (GPRSize == 32 &&
Size.getFixedValue() == 64) {
368 case TargetOpcode::G_SELECT: {
369 LLT Ty =
MRI.getType(
MI.getOperand(0).getReg());
372 auto &Sel = cast<GSelect>(
MI);
373 LLT TestTy =
MRI.getType(Sel.getCondReg());
374 assert(TestTy.
isVector() &&
"Unexpected condition argument type");
375 OpdsMapping[0] = OpdsMapping[2] = OpdsMapping[3] =
397 if (
any_of(
MRI.use_nodbg_instructions(
MI.getOperand(0).getReg()),
399 return onlyUsesFP(UseMI, MRI, TRI);
426 OpdsMapping[1] = GPRValueMapping;
432 OpdsMapping[0] = OpdsMapping[2] = OpdsMapping[3] = Mapping;
435 case TargetOpcode::G_FPTOSI:
436 case TargetOpcode::G_FPTOUI:
437 case RISCV::G_FCLASS: {
438 LLT Ty =
MRI.getType(
MI.getOperand(1).getReg());
439 OpdsMapping[0] = GPRValueMapping;
443 case TargetOpcode::G_SITOFP:
444 case TargetOpcode::G_UITOFP: {
445 LLT Ty =
MRI.getType(
MI.getOperand(0).getReg());
447 OpdsMapping[1] = GPRValueMapping;
450 case TargetOpcode::G_FCMP: {
451 LLT Ty =
MRI.getType(
MI.getOperand(2).getReg());
455 OpdsMapping[0] = GPRValueMapping;
459 case TargetOpcode::G_MERGE_VALUES: {
461 LLT Ty =
MRI.getType(
MI.getOperand(0).getReg());
465 OpdsMapping[1] = GPRValueMapping;
466 OpdsMapping[2] = GPRValueMapping;
470 case TargetOpcode::G_UNMERGE_VALUES: {
472 LLT Ty =
MRI.getType(
MI.getOperand(2).getReg());
475 OpdsMapping[0] = GPRValueMapping;
476 OpdsMapping[1] = GPRValueMapping;
483 for (
unsigned Idx = 0;
Idx < NumOperands; ++
Idx) {
484 auto &MO =
MI.getOperand(
Idx);
485 if (!MO.isReg() || !MO.getReg())
487 LLT Ty =
MRI.getType(MO.getReg());
497 OpdsMapping[
Idx] = GPRValueMapping;
unsigned const MachineRegisterInfo * MRI
MachineInstrBuilder & UseMI
MachineInstrBuilder MachineInstrBuilder & DefMI
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
Declares convenience wrapper classes for interpreting MachineInstr instances as specific generic oper...
unsigned const TargetRegisterInfo * TRI
static const RegisterBankInfo::ValueMapping * getFPValueMapping(unsigned Size)
static const RegisterBankInfo::ValueMapping * getVRBValueMapping(unsigned Size)
This file declares the targeting of the RegisterBankInfo class for RISC-V.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
constexpr bool isValid() const
constexpr bool isVector() const
constexpr TypeSize getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Representation of each machine instruction.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
RISCVRegisterBankInfo(unsigned HwMode)
const InstructionMapping & getInstrMapping(const MachineInstr &MI) const override
Get the mapping of the different operands of MI on the register bank.
Helper class that represents how the value of an instruction may be mapped and what is the related co...
bool isValid() const
Check whether this object is valid.
const InstructionMapping & getInstructionMapping(unsigned ID, unsigned Cost, const ValueMapping *OperandsMapping, unsigned NumOperands) const
Method to get a uniquely generated InstructionMapping.
const RegisterBank & getRegBank(unsigned ID)
Get the register bank identified by ID.
unsigned getMaximumSize(unsigned RegBankID) const
Get the maximum size in bits that fits in the given register bank.
const ValueMapping * getOperandsMapping(Iterator Begin, Iterator End) const
Get the uniquely generated array of ValueMapping for the elements of between Begin and End.
static const unsigned DefaultMappingID
Identifier used when the related instruction mapping instance is generated by target independent code...
const InstructionMapping & getInstrMappingImpl(const MachineInstr &MI) const
Try to get the mapping of MI.
Wrapper class representing virtual and physical registers.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
TargetSubtargetInfo - Generic base class for all target subtargets.
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
constexpr ScalarTy getKnownMinValue() const
Returns the minimum value this quantity can represent.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
const RegisterBankInfo::PartialMapping PartMappings[]
const RegisterBankInfo::ValueMapping ValueMappings[]
This is an optimization pass for GlobalISel generic memory operations.
bool isPreISelGenericOpcode(unsigned Opcode)
Check whether the given Opcode is a generic opcode that is not supposed to appear after ISel.
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
bool isPreISelGenericFloatingPointOpcode(unsigned Opc)
Returns whether opcode Opc is a pre-isel generic floating-point opcode, having only floating-point op...
Helper struct that represents how a value is partially mapped into a register.
Helper struct that represents how a value is mapped through different register banks.