Enumerations

enum OperandType : unsigned {
OPERAND_FIRST_RISCV_IMM = MCOI::OPERAND_FIRST_TARGET , OPERAND_UIMM1 = OPERAND_FIRST_RISCV_IMM , OPERAND_UIMM2 , OPERAND_UIMM2_LSB0 ,
OPERAND_UIMM3 , OPERAND_UIMM4 , OPERAND_UIMM5 , OPERAND_UIMM5_NONZERO ,
OPERAND_UIMM5_GT3 , OPERAND_UIMM5_PLUS1 , OPERAND_UIMM5_GE6_PLUS1 , OPERAND_UIMM5_LSB0 ,
OPERAND_UIMM5_SLIST , OPERAND_UIMM6 , OPERAND_UIMM6_LSB0 , OPERAND_UIMM7 ,
OPERAND_UIMM7_LSB00 , OPERAND_UIMM7_LSB000 , OPERAND_UIMM8_LSB00 , OPERAND_UIMM8 ,
OPERAND_UIMM8_LSB000 , OPERAND_UIMM8_GE32 , OPERAND_UIMM9_LSB000 , OPERAND_UIMM9 ,
OPERAND_UIMM10 , OPERAND_UIMM10_LSB00_NONZERO , OPERAND_UIMM11 , OPERAND_UIMM12 ,
OPERAND_UIMM14_LSB00 , OPERAND_UIMM16 , OPERAND_UIMM16_NONZERO , OPERAND_UIMM20 ,
OPERAND_UIMMLOG2XLEN , OPERAND_UIMMLOG2XLEN_NONZERO , OPERAND_UIMM32 , OPERAND_UIMM48 ,
OPERAND_UIMM64 , OPERAND_THREE , OPERAND_FOUR , OPERAND_IMM5_ZIBI ,
OPERAND_SIMM5 , OPERAND_SIMM5_NONZERO , OPERAND_SIMM5_PLUS1 , OPERAND_SIMM6 ,
OPERAND_SIMM6_NONZERO , OPERAND_SIMM8 , OPERAND_SIMM8_UNSIGNED , OPERAND_SIMM10 ,
OPERAND_SIMM10_LSB0000_NONZERO , OPERAND_SIMM10_UNSIGNED , OPERAND_SIMM11 , OPERAND_SIMM12 ,
OPERAND_SIMM12_LSB00000 , OPERAND_SIMM16 , OPERAND_SIMM16_NONZERO , OPERAND_SIMM20_LI ,
OPERAND_SIMM26 , OPERAND_BARE_SIMM32 , OPERAND_CLUI_IMM , OPERAND_VTYPEI10 ,
OPERAND_VTYPEI11 , OPERAND_RVKRNUM , OPERAND_RVKRNUM_0_7 , OPERAND_RVKRNUM_1_10 ,
OPERAND_RVKRNUM_2_14 , OPERAND_RLIST , OPERAND_RLIST_S0 , OPERAND_STACKADJ ,
OPERAND_FRMARG , OPERAND_RTZARG , OPERAND_COND_CODE , OPERAND_VEC_POLICY ,
OPERAND_SEW , OPERAND_SEW_MASK , OPERAND_VEC_RM , OPERAND_LAST_RISCV_IMM = OPERAND_VEC_RM ,
OPERAND_AVL
}

Enumeration Type Documentation

◆ OperandType

enum llvm::RISCVOp::OperandType : unsigned

Enumerator
OPERAND_FIRST_RISCV_IMM
OPERAND_UIMM1
OPERAND_UIMM2
OPERAND_UIMM2_LSB0
OPERAND_UIMM3
OPERAND_UIMM4
OPERAND_UIMM5
OPERAND_UIMM5_NONZERO
OPERAND_UIMM5_GT3
OPERAND_UIMM5_PLUS1
OPERAND_UIMM5_GE6_PLUS1
OPERAND_UIMM5_LSB0
OPERAND_UIMM5_SLIST
OPERAND_UIMM6
OPERAND_UIMM6_LSB0
OPERAND_UIMM7
OPERAND_UIMM7_LSB00
OPERAND_UIMM7_LSB000
OPERAND_UIMM8_LSB00
OPERAND_UIMM8
OPERAND_UIMM8_LSB000
OPERAND_UIMM8_GE32
OPERAND_UIMM9_LSB000
OPERAND_UIMM9
OPERAND_UIMM10
OPERAND_UIMM10_LSB00_NONZERO
OPERAND_UIMM11
OPERAND_UIMM12
OPERAND_UIMM14_LSB00
OPERAND_UIMM16
OPERAND_UIMM16_NONZERO
OPERAND_UIMM20
OPERAND_UIMMLOG2XLEN
OPERAND_UIMMLOG2XLEN_NONZERO
OPERAND_UIMM32
OPERAND_UIMM48
OPERAND_UIMM64
OPERAND_THREE
OPERAND_FOUR
OPERAND_IMM5_ZIBI
OPERAND_SIMM5
OPERAND_SIMM5_NONZERO
OPERAND_SIMM5_PLUS1
OPERAND_SIMM6
OPERAND_SIMM6_NONZERO
OPERAND_SIMM8
OPERAND_SIMM8_UNSIGNED
OPERAND_SIMM10
OPERAND_SIMM10_LSB0000_NONZERO
OPERAND_SIMM10_UNSIGNED
OPERAND_SIMM11
OPERAND_SIMM12
OPERAND_SIMM12_LSB00000
OPERAND_SIMM16
OPERAND_SIMM16_NONZERO
OPERAND_SIMM20_LI
OPERAND_SIMM26
OPERAND_BARE_SIMM32
OPERAND_CLUI_IMM
OPERAND_VTYPEI10
OPERAND_VTYPEI11
OPERAND_RVKRNUM
OPERAND_RVKRNUM_0_7
OPERAND_RVKRNUM_1_10
OPERAND_RVKRNUM_2_14
OPERAND_RLIST
OPERAND_RLIST_S0
OPERAND_STACKADJ
OPERAND_FRMARG
OPERAND_RTZARG
OPERAND_COND_CODE
OPERAND_VEC_POLICY
OPERAND_SEW
OPERAND_SEW_MASK
OPERAND_VEC_RM
OPERAND_LAST_RISCV_IMM
OPERAND_AVL

Definition at line 304 of file RISCVBaseInfo.h.