16#ifndef LLVM_LIB_TARGET_AARCH64_UTILS_AARCH64BASEINFO_H
17#define LLVM_LIB_TARGET_AARCH64_UTILS_AARCH64BASEINFO_H
32 case AArch64::X0:
return AArch64::W0;
33 case AArch64::X1:
return AArch64::W1;
34 case AArch64::X2:
return AArch64::W2;
35 case AArch64::X3:
return AArch64::W3;
36 case AArch64::X4:
return AArch64::W4;
37 case AArch64::X5:
return AArch64::W5;
38 case AArch64::X6:
return AArch64::W6;
39 case AArch64::X7:
return AArch64::W7;
40 case AArch64::X8:
return AArch64::W8;
41 case AArch64::X9:
return AArch64::W9;
42 case AArch64::X10:
return AArch64::W10;
43 case AArch64::X11:
return AArch64::W11;
44 case AArch64::X12:
return AArch64::W12;
45 case AArch64::X13:
return AArch64::W13;
46 case AArch64::X14:
return AArch64::W14;
47 case AArch64::X15:
return AArch64::W15;
48 case AArch64::X16:
return AArch64::W16;
49 case AArch64::X17:
return AArch64::W17;
50 case AArch64::X18:
return AArch64::W18;
51 case AArch64::X19:
return AArch64::W19;
52 case AArch64::X20:
return AArch64::W20;
53 case AArch64::X21:
return AArch64::W21;
54 case AArch64::X22:
return AArch64::W22;
55 case AArch64::X23:
return AArch64::W23;
56 case AArch64::X24:
return AArch64::W24;
57 case AArch64::X25:
return AArch64::W25;
58 case AArch64::X26:
return AArch64::W26;
59 case AArch64::X27:
return AArch64::W27;
60 case AArch64::X28:
return AArch64::W28;
61 case AArch64::FP:
return AArch64::W29;
62 case AArch64::LR:
return AArch64::W30;
63 case AArch64::SP:
return AArch64::WSP;
64 case AArch64::XZR:
return AArch64::WZR;
72 case AArch64::W0:
return AArch64::X0;
73 case AArch64::W1:
return AArch64::X1;
74 case AArch64::W2:
return AArch64::X2;
75 case AArch64::W3:
return AArch64::X3;
76 case AArch64::W4:
return AArch64::X4;
77 case AArch64::W5:
return AArch64::X5;
78 case AArch64::W6:
return AArch64::X6;
79 case AArch64::W7:
return AArch64::X7;
80 case AArch64::W8:
return AArch64::X8;
81 case AArch64::W9:
return AArch64::X9;
82 case AArch64::W10:
return AArch64::X10;
83 case AArch64::W11:
return AArch64::X11;
84 case AArch64::W12:
return AArch64::X12;
85 case AArch64::W13:
return AArch64::X13;
86 case AArch64::W14:
return AArch64::X14;
87 case AArch64::W15:
return AArch64::X15;
88 case AArch64::W16:
return AArch64::X16;
89 case AArch64::W17:
return AArch64::X17;
90 case AArch64::W18:
return AArch64::X18;
91 case AArch64::W19:
return AArch64::X19;
92 case AArch64::W20:
return AArch64::X20;
93 case AArch64::W21:
return AArch64::X21;
94 case AArch64::W22:
return AArch64::X22;
95 case AArch64::W23:
return AArch64::X23;
96 case AArch64::W24:
return AArch64::X24;
97 case AArch64::W25:
return AArch64::X25;
98 case AArch64::W26:
return AArch64::X26;
99 case AArch64::W27:
return AArch64::X27;
100 case AArch64::W28:
return AArch64::X28;
101 case AArch64::W29:
return AArch64::FP;
102 case AArch64::W30:
return AArch64::LR;
103 case AArch64::WSP:
return AArch64::SP;
104 case AArch64::WZR:
return AArch64::XZR;
111 switch (RegTuple.
id()) {
112 case AArch64::X0_X1_X2_X3_X4_X5_X6_X7:
return AArch64::X0;
113 case AArch64::X2_X3_X4_X5_X6_X7_X8_X9:
return AArch64::X2;
114 case AArch64::X4_X5_X6_X7_X8_X9_X10_X11:
return AArch64::X4;
115 case AArch64::X6_X7_X8_X9_X10_X11_X12_X13:
return AArch64::X6;
116 case AArch64::X8_X9_X10_X11_X12_X13_X14_X15:
return AArch64::X8;
117 case AArch64::X10_X11_X12_X13_X14_X15_X16_X17:
return AArch64::X10;
118 case AArch64::X12_X13_X14_X15_X16_X17_X18_X19:
return AArch64::X12;
119 case AArch64::X14_X15_X16_X17_X18_X19_X20_X21:
return AArch64::X14;
120 case AArch64::X16_X17_X18_X19_X20_X21_X22_X23:
return AArch64::X16;
121 case AArch64::X18_X19_X20_X21_X22_X23_X24_X25:
return AArch64::X18;
122 case AArch64::X20_X21_X22_X23_X24_X25_X26_X27:
return AArch64::X20;
123 case AArch64::X22_X23_X24_X25_X26_X27_X28_FP:
return AArch64::X22;
131 case AArch64::D0:
return AArch64::B0;
132 case AArch64::D1:
return AArch64::B1;
133 case AArch64::D2:
return AArch64::B2;
134 case AArch64::D3:
return AArch64::B3;
135 case AArch64::D4:
return AArch64::B4;
136 case AArch64::D5:
return AArch64::B5;
137 case AArch64::D6:
return AArch64::B6;
138 case AArch64::D7:
return AArch64::B7;
139 case AArch64::D8:
return AArch64::B8;
140 case AArch64::D9:
return AArch64::B9;
141 case AArch64::D10:
return AArch64::B10;
142 case AArch64::D11:
return AArch64::B11;
143 case AArch64::D12:
return AArch64::B12;
144 case AArch64::D13:
return AArch64::B13;
145 case AArch64::D14:
return AArch64::B14;
146 case AArch64::D15:
return AArch64::B15;
147 case AArch64::D16:
return AArch64::B16;
148 case AArch64::D17:
return AArch64::B17;
149 case AArch64::D18:
return AArch64::B18;
150 case AArch64::D19:
return AArch64::B19;
151 case AArch64::D20:
return AArch64::B20;
152 case AArch64::D21:
return AArch64::B21;
153 case AArch64::D22:
return AArch64::B22;
154 case AArch64::D23:
return AArch64::B23;
155 case AArch64::D24:
return AArch64::B24;
156 case AArch64::D25:
return AArch64::B25;
157 case AArch64::D26:
return AArch64::B26;
158 case AArch64::D27:
return AArch64::B27;
159 case AArch64::D28:
return AArch64::B28;
160 case AArch64::D29:
return AArch64::B29;
161 case AArch64::D30:
return AArch64::B30;
162 case AArch64::D31:
return AArch64::B31;
170 case AArch64::B0:
return AArch64::D0;
171 case AArch64::B1:
return AArch64::D1;
172 case AArch64::B2:
return AArch64::D2;
173 case AArch64::B3:
return AArch64::D3;
174 case AArch64::B4:
return AArch64::D4;
175 case AArch64::B5:
return AArch64::D5;
176 case AArch64::B6:
return AArch64::D6;
177 case AArch64::B7:
return AArch64::D7;
178 case AArch64::B8:
return AArch64::D8;
179 case AArch64::B9:
return AArch64::D9;
180 case AArch64::B10:
return AArch64::D10;
181 case AArch64::B11:
return AArch64::D11;
182 case AArch64::B12:
return AArch64::D12;
183 case AArch64::B13:
return AArch64::D13;
184 case AArch64::B14:
return AArch64::D14;
185 case AArch64::B15:
return AArch64::D15;
186 case AArch64::B16:
return AArch64::D16;
187 case AArch64::B17:
return AArch64::D17;
188 case AArch64::B18:
return AArch64::D18;
189 case AArch64::B19:
return AArch64::D19;
190 case AArch64::B20:
return AArch64::D20;
191 case AArch64::B21:
return AArch64::D21;
192 case AArch64::B22:
return AArch64::D22;
193 case AArch64::B23:
return AArch64::D23;
194 case AArch64::B24:
return AArch64::D24;
195 case AArch64::B25:
return AArch64::D25;
196 case AArch64::B26:
return AArch64::D26;
197 case AArch64::B27:
return AArch64::D27;
198 case AArch64::B28:
return AArch64::D28;
199 case AArch64::B29:
return AArch64::D29;
200 case AArch64::B30:
return AArch64::D30;
201 case AArch64::B31:
return AArch64::D31;
209 case AArch64::LDADDAB:
case AArch64::LDADDAH:
210 case AArch64::LDADDAW:
case AArch64::LDADDAX:
211 case AArch64::LDADDALB:
case AArch64::LDADDALH:
212 case AArch64::LDADDALW:
case AArch64::LDADDALX:
213 case AArch64::LDCLRAB:
case AArch64::LDCLRAH:
214 case AArch64::LDCLRAW:
case AArch64::LDCLRAX:
215 case AArch64::LDCLRALB:
case AArch64::LDCLRALH:
216 case AArch64::LDCLRALW:
case AArch64::LDCLRALX:
217 case AArch64::LDEORAB:
case AArch64::LDEORAH:
218 case AArch64::LDEORAW:
case AArch64::LDEORAX:
219 case AArch64::LDEORALB:
case AArch64::LDEORALH:
220 case AArch64::LDEORALW:
case AArch64::LDEORALX:
221 case AArch64::LDSETAB:
case AArch64::LDSETAH:
222 case AArch64::LDSETAW:
case AArch64::LDSETAX:
223 case AArch64::LDSETALB:
case AArch64::LDSETALH:
224 case AArch64::LDSETALW:
case AArch64::LDSETALX:
225 case AArch64::LDSMAXAB:
case AArch64::LDSMAXAH:
226 case AArch64::LDSMAXAW:
case AArch64::LDSMAXAX:
227 case AArch64::LDSMAXALB:
case AArch64::LDSMAXALH:
228 case AArch64::LDSMAXALW:
case AArch64::LDSMAXALX:
229 case AArch64::LDSMINAB:
case AArch64::LDSMINAH:
230 case AArch64::LDSMINAW:
case AArch64::LDSMINAX:
231 case AArch64::LDSMINALB:
case AArch64::LDSMINALH:
232 case AArch64::LDSMINALW:
case AArch64::LDSMINALX:
233 case AArch64::LDUMAXAB:
case AArch64::LDUMAXAH:
234 case AArch64::LDUMAXAW:
case AArch64::LDUMAXAX:
235 case AArch64::LDUMAXALB:
case AArch64::LDUMAXALH:
236 case AArch64::LDUMAXALW:
case AArch64::LDUMAXALX:
237 case AArch64::LDUMINAB:
case AArch64::LDUMINAH:
238 case AArch64::LDUMINAW:
case AArch64::LDUMINAX:
239 case AArch64::LDUMINALB:
case AArch64::LDUMINALH:
240 case AArch64::LDUMINALW:
case AArch64::LDUMINALX:
241 case AArch64::SWPAB:
case AArch64::SWPAH:
242 case AArch64::SWPAW:
case AArch64::SWPAX:
243 case AArch64::SWPALB:
case AArch64::SWPALH:
244 case AArch64::SWPALW:
case AArch64::SWPALX:
284 case EQ:
return "eq";
285 case NE:
return "ne";
286 case HS:
return "hs";
287 case LO:
return "lo";
288 case MI:
return "mi";
289 case PL:
return "pl";
290 case VS:
return "vs";
291 case VC:
return "vc";
292 case HI:
return "hi";
293 case LS:
return "ls";
294 case GE:
return "ge";
295 case LT:
return "lt";
296 case GT:
return "gt";
297 case LE:
return "le";
298 case AL:
return "al";
299 case NV:
return "nv";
306 return static_cast<CondCode>(
static_cast<unsigned>(Code) ^ 0x1);
315 enum {
N = 8, Z = 4,
C = 2, V = 1 };
347 return ActiveFeatures[llvm::AArch64::FeatureAll] ||
370namespace AArch64SVCR {
374#define GET_SVCRValues_DECL
375#define GET_SVCRsList_DECL
376#include "AArch64GenSystemOperands.inc"
383#define GET_ATValues_DECL
384#define GET_ATsList_DECL
385#include "AArch64GenSystemOperands.inc"
392#define GET_DBValues_DECL
393#define GET_DBsList_DECL
394#include "AArch64GenSystemOperands.inc"
397namespace AArch64DBnXS {
401#define GET_DBnXSValues_DECL
402#define GET_DBnXSsList_DECL
403#include "AArch64GenSystemOperands.inc"
410#define GET_DCValues_DECL
411#define GET_DCsList_DECL
412#include "AArch64GenSystemOperands.inc"
419#define GET_ICValues_DECL
420#define GET_ICsList_DECL
421#include "AArch64GenSystemOperands.inc"
424namespace AArch64ISB {
428#define GET_ISBValues_DECL
429#define GET_ISBsList_DECL
430#include "AArch64GenSystemOperands.inc"
433namespace AArch64TSB {
437#define GET_TSBValues_DECL
438#define GET_TSBsList_DECL
439#include "AArch64GenSystemOperands.inc"
442namespace AArch64PRFM {
446#define GET_PRFMValues_DECL
447#define GET_PRFMsList_DECL
448#include "AArch64GenSystemOperands.inc"
451namespace AArch64SVEPRFM {
455#define GET_SVEPRFMValues_DECL
456#define GET_SVEPRFMsList_DECL
457#include "AArch64GenSystemOperands.inc"
460namespace AArch64RPRFM {
464#define GET_RPRFMValues_DECL
465#define GET_RPRFMsList_DECL
466#include "AArch64GenSystemOperands.inc"
469namespace AArch64SVEPredPattern {
474#define GET_SVEPREDPATValues_DECL
475#define GET_SVEPREDPATsList_DECL
476#include "AArch64GenSystemOperands.inc"
479namespace AArch64SVEVecLenSpecifier {
484#define GET_SVEVECLENSPECIFIERValues_DECL
485#define GET_SVEVECLENSPECIFIERsList_DECL
486#include "AArch64GenSystemOperands.inc"
495 case AArch64SVEPredPattern::vl1:
496 case AArch64SVEPredPattern::vl2:
497 case AArch64SVEPredPattern::vl3:
498 case AArch64SVEPredPattern::vl4:
499 case AArch64SVEPredPattern::vl5:
500 case AArch64SVEPredPattern::vl6:
501 case AArch64SVEPredPattern::vl7:
502 case AArch64SVEPredPattern::vl8:
504 case AArch64SVEPredPattern::vl16:
506 case AArch64SVEPredPattern::vl32:
508 case AArch64SVEPredPattern::vl64:
510 case AArch64SVEPredPattern::vl128:
512 case AArch64SVEPredPattern::vl256:
518inline std::optional<unsigned>
520 switch (MinNumElts) {
533 return AArch64SVEPredPattern::vl16;
535 return AArch64SVEPredPattern::vl32;
537 return AArch64SVEPredPattern::vl64;
539 return AArch64SVEPredPattern::vl128;
541 return AArch64SVEPredPattern::vl256;
566namespace AArch64ExactFPImm {
571#define GET_ExactFPImmValues_DECL
572#define GET_ExactFPImmsList_DECL
573#include "AArch64GenSystemOperands.inc"
576namespace AArch64PState {
580#define GET_PStateImm0_15Values_DECL
581#define GET_PStateImm0_15sList_DECL
582#include "AArch64GenSystemOperands.inc"
587#define GET_PStateImm0_1Values_DECL
588#define GET_PStateImm0_1sList_DECL
589#include "AArch64GenSystemOperands.inc"
592namespace AArch64PSBHint {
596#define GET_PSBValues_DECL
597#define GET_PSBsList_DECL
598#include "AArch64GenSystemOperands.inc"
601namespace AArch64PHint {
608 return ActiveFeatures[llvm::AArch64::FeatureAll] ||
613#define GET_PHintValues_DECL
614#define GET_PHintsList_DECL
615#include "AArch64GenSystemOperands.inc"
621namespace AArch64BTIHint {
625#define GET_BTIValues_DECL
626#define GET_BTIsList_DECL
627#include "AArch64GenSystemOperands.inc"
630namespace AArch64SME {
659namespace AArch64Layout {
681inline static const char *
718namespace AArch64SysReg {
727 return ActiveFeatures[llvm::AArch64::FeatureAll] ||
732#define GET_SysRegsList_DECL
733#define GET_SysRegValues_DECL
734#include "AArch64GenSystemOperands.inc"
740namespace AArch64TLBI {
744 #define GET_TLBITable_DECL
745 #include "AArch64GenSystemOperands.inc"
843namespace AArch64PACKey {
869inline static std::optional<AArch64PACKey::ID>
#define LLVM_DECLARE_ENUM_AS_BITMASK(Enum, LargestValue)
LLVM_DECLARE_ENUM_AS_BITMASK can be used to declare an enum type as a bit set, so that bitwise operat...
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
This file implements the StringSwitch template, which mimics a switch() statement whose cases are str...
Container class for subtarget features.
Wrapper class representing physical registers. Should be passed by value.
constexpr unsigned id() const
StringRef - Represent a constant reference to a string, i.e.
A switch()-like statement whose cases are string literals.
StringSwitch & Case(StringLiteral S, T Value)
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
static const char * getCondCodeName(CondCode Code)
static CondCode getInvertedCondCode(CondCode Code)
static unsigned getNZCVToSatisfyCondCode(CondCode Code)
Given a condition code, return NZCV flags that would satisfy that condition.
TOF
Target Operand Flag enum.
@ MO_DLLIMPORT
MO_DLLIMPORT - On a symbol operand, this represents that the reference to the symbol is for an import...
@ MO_NC
MO_NC - Indicates whether the linker is expected to check the symbol reference for overflow.
@ MO_G1
MO_G1 - A symbol operand with this flag (granule 1) represents the bits 16-31 of a 64-bit address,...
@ MO_S
MO_S - Indicates that the bits of the symbol operand represented by MO_G0 etc are signed.
@ MO_PAGEOFF
MO_PAGEOFF - A symbol operand with this flag represents the offset of that symbol within a 4K page.
@ MO_GOT
MO_GOT - This flag indicates that a symbol operand represents the address of the GOT entry for the sy...
@ MO_PREL
MO_PREL - Indicates that the bits of the symbol operand represented by MO_G0 etc are PC relative.
@ MO_G0
MO_G0 - A symbol operand with this flag (granule 0) represents the bits 0-15 of a 64-bit address,...
@ MO_ARM64EC_CALLMANGLE
MO_ARM64EC_CALLMANGLE - Operand refers to the Arm64EC-mangled version of a symbol,...
@ MO_PAGE
MO_PAGE - A symbol operand with this flag represents the pc-relative offset of the 4K page containing...
@ MO_HI12
MO_HI12 - This flag indicates that a symbol operand represents the bits 13-24 of a 64-bit address,...
@ MO_TLS
MO_TLS - Indicates that the operand being accessed is some kind of thread-local symbol.
@ MO_G2
MO_G2 - A symbol operand with this flag (granule 2) represents the bits 32-47 of a 64-bit address,...
@ MO_TAGGED
MO_TAGGED - With MO_PAGE, indicates that the page includes a memory tag in bits 56-63.
@ MO_G3
MO_G3 - A symbol operand with this flag (granule 3) represents the high 16-bits of a 64-bit address,...
@ MO_COFFSTUB
MO_COFFSTUB - On a symbol operand "FOO", this indicates that the reference is actually to the "....
const PHint * lookupPHintByName(StringRef)
const PHint * lookupPHintByEncoding(uint16_t)
uint32_t parseGenericRegister(StringRef Name)
std::string genericRegisterString(uint32_t Bits)
static constexpr unsigned SVEMaxBitsPerVector
static constexpr unsigned SVEBitsPerBlock
@ C
The default llvm calling convention, compatible with C.
This is an optimization pass for GlobalISel generic memory operations.
static std::optional< AArch64PACKey::ID > AArch64StringToPACKeyID(StringRef Name)
Return numeric key ID for 2-letter identifier string.
TailFoldingOpts
An enum to describe what types of loops we should attempt to tail-fold: Disabled: None Reductions: Lo...
static AArch64Layout::VectorLayout AArch64StringToVectorLayout(StringRef LayoutStr)
static const char * AArch64VectorLayoutToString(AArch64Layout::VectorLayout Layout)
std::optional< unsigned > getSVEPredPatternFromNumElements(unsigned MinNumElts)
Return specific VL predicate pattern based on the number of elements.
static bool atomicBarrierDroppedOnZero(unsigned Opcode)
static MCRegister getXRegFromWReg(MCRegister Reg)
static MCRegister getXRegFromXRegTuple(MCRegister RegTuple)
static MCRegister getWRegFromXReg(MCRegister Reg)
unsigned getNumElementsFromSVEPredPattern(unsigned Pattern)
Return the number of active elements for VL1 to VL256 predicate pattern, zero for all other patterns.
static MCRegister getDRegFromBReg(MCRegister Reg)
static MCRegister getBRegFromDReg(MCRegister Reg)
static StringRef AArch64PACKeyIDToString(AArch64PACKey::ID KeyID)
Return 2-letter identifier string for numeric key ID.
bool haveFeatures(FeatureBitset ActiveFeatures) const
FeatureBitset FeaturesRequired
FeatureBitset FeaturesRequired
bool haveFeatures(FeatureBitset ActiveFeatures) const
constexpr SysAliasImm(const char *N, uint16_t E, uint16_t I)
constexpr SysAliasImm(const char *N, uint16_t E, uint16_t I, FeatureBitset F)
constexpr SysAliasReg(const char *N, uint16_t E, bool R, FeatureBitset F)
constexpr SysAliasReg(const char *N, uint16_t E, bool R)
bool haveFeatures(FeatureBitset ActiveFeatures) const
constexpr SysAlias(const char *N, uint16_t E)
FeatureBitset getRequiredFeatures() const
FeatureBitset FeaturesRequired
constexpr SysAlias(const char *N, uint16_t E, FeatureBitset F)