LLVM 23.0.0git
HexagonFrameLowering.h
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1//==- HexagonFrameLowering.h - Define frame lowering for Hexagon -*- C++ -*-==//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONFRAMELOWERING_H
10#define LLVM_LIB_TARGET_HEXAGON_HEXAGONFRAMELOWERING_H
11
12#include "Hexagon.h"
13#include "HexagonBlockRanges.h"
15#include "llvm/ADT/STLExtras.h"
19#include <vector>
20
21namespace llvm {
22
23class BitVector;
26class MachineFunction;
27class MachineInstr;
29class MCRegisterClass;
31
33public:
34 // First register which could possibly hold a variable argument.
38
39 void
41 SmallVectorImpl<int> &ObjectsToAllocate) const override;
42
43 // All of the prolog/epilog functionality, including saving and restoring
44 // callee-saved registers is handled in emitPrologue. This is to have the
45 // logic for shrink-wrapping in one place.
47 override;
49 override {}
50
51 bool enableCalleeSaveSkip(const MachineFunction &MF) const override;
52
59
60 bool
67
68 bool hasReservedCallFrame(const MachineFunction &MF) const override {
69 // We always reserve call frame as a part of the initial stack allocation.
70 return true;
71 }
72
73 bool canSimplifyCallFramePseudos(const MachineFunction &MF) const override {
74 // Override this function to avoid calling hasFP before CSI is set
75 // (the default implementation calls hasFP).
76 return true;
77 }
78
81 MachineBasicBlock::iterator I) const override;
83 RegScavenger *RS = nullptr) const override;
85 RegScavenger *RS) const override;
86
87 bool targetHandlesStackFrameRounding() const override {
88 return true;
89 }
90
92 Register &FrameReg) const override;
93
94 const SpillSlot *getCalleeSavedSpillSlots(unsigned &NumEntries)
95 const override {
96 static const SpillSlot Offsets[] = {
97 { Hexagon::R17, -4 }, { Hexagon::R16, -8 }, { Hexagon::D8, -8 },
98 { Hexagon::R19, -12 }, { Hexagon::R18, -16 }, { Hexagon::D9, -16 },
99 { Hexagon::R21, -20 }, { Hexagon::R20, -24 }, { Hexagon::D10, -24 },
100 { Hexagon::R23, -28 }, { Hexagon::R22, -32 }, { Hexagon::D11, -32 },
101 { Hexagon::R25, -36 }, { Hexagon::R24, -40 }, { Hexagon::D12, -40 },
102 { Hexagon::R27, -44 }, { Hexagon::R26, -48 }, { Hexagon::D13, -48 }
103 };
104 NumEntries = std::size(Offsets);
105 return Offsets;
106 }
107
109 const TargetRegisterInfo *TRI, std::vector<CalleeSavedInfo> &CSI)
110 const override;
111
112 bool needsAligna(const MachineFunction &MF) const;
113 const MachineInstr *getAlignaInstr(const MachineFunction &MF) const;
114
116
118 MachineBasicBlock &PrologueMBB) const override;
119
120protected:
121 bool hasFPImpl(const MachineFunction &MF) const override;
122
123private:
124 using CSIVect = std::vector<CalleeSavedInfo>;
125
126 void expandAlloca(MachineInstr *AI, MachineFunction &MF,
127 const HexagonInstrInfo &TII, Register SP,
128 unsigned CF) const;
129 void insertPrologueInBlock(MachineBasicBlock &MBB, bool PrologueStubs) const;
130 void insertEpilogueInBlock(MachineBasicBlock &MBB) const;
131 void insertAllocframe(MachineBasicBlock &MBB,
132 MachineBasicBlock::iterator InsertPt, unsigned NumBytes) const;
133 bool insertCSRSpillsInBlock(MachineBasicBlock &MBB, const CSIVect &CSI,
134 const HexagonRegisterInfo &HRI, bool &PrologueStubs) const;
135 bool insertCSRRestoresInBlock(MachineBasicBlock &MBB, const CSIVect &CSI,
136 const HexagonRegisterInfo &HRI) const;
137 void updateEntryPaths(MachineFunction &MF, MachineBasicBlock &SaveB) const;
138 bool updateExitPaths(MachineBasicBlock &MBB, MachineBasicBlock &RestoreB,
139 BitVector &DoneT, BitVector &DoneF, BitVector &Path) const;
140 void insertCFIInstructionsAt(MachineBasicBlock &MBB,
142
144 MachineRegisterInfo &MRI, const HexagonInstrInfo &HII,
145 SmallVectorImpl<Register> &NewRegs) const;
146 bool expandStoreInt(MachineBasicBlock &B, MachineBasicBlock::iterator It,
147 MachineRegisterInfo &MRI, const HexagonInstrInfo &HII,
148 SmallVectorImpl<Register> &NewRegs) const;
149 bool expandLoadInt(MachineBasicBlock &B, MachineBasicBlock::iterator It,
150 MachineRegisterInfo &MRI, const HexagonInstrInfo &HII,
151 SmallVectorImpl<Register> &NewRegs) const;
152 bool expandStoreVecPred(MachineBasicBlock &B, MachineBasicBlock::iterator It,
153 MachineRegisterInfo &MRI, const HexagonInstrInfo &HII,
154 SmallVectorImpl<Register> &NewRegs) const;
155 bool expandLoadVecPred(MachineBasicBlock &B, MachineBasicBlock::iterator It,
156 MachineRegisterInfo &MRI, const HexagonInstrInfo &HII,
157 SmallVectorImpl<Register> &NewRegs) const;
158 bool expandStoreVec2(MachineBasicBlock &B, MachineBasicBlock::iterator It,
159 MachineRegisterInfo &MRI, const HexagonInstrInfo &HII,
160 SmallVectorImpl<Register> &NewRegs) const;
161 bool expandLoadVec2(MachineBasicBlock &B, MachineBasicBlock::iterator It,
162 MachineRegisterInfo &MRI, const HexagonInstrInfo &HII,
163 SmallVectorImpl<Register> &NewRegs) const;
164 bool expandStoreVec(MachineBasicBlock &B, MachineBasicBlock::iterator It,
165 MachineRegisterInfo &MRI, const HexagonInstrInfo &HII,
166 SmallVectorImpl<Register> &NewRegs) const;
167 bool expandLoadVec(MachineBasicBlock &B, MachineBasicBlock::iterator It,
168 MachineRegisterInfo &MRI, const HexagonInstrInfo &HII,
169 SmallVectorImpl<Register> &NewRegs) const;
170 bool expandSpillMacros(MachineFunction &MF,
171 SmallVectorImpl<Register> &NewRegs) const;
172
176 const TargetRegisterClass *RC) const;
177 void optimizeSpillSlots(MachineFunction &MF,
178 SmallVectorImpl<Register> &VRegs) const;
179
180 void findShrunkPrologEpilog(MachineFunction &MF, MachineBasicBlock *&PrologB,
181 MachineBasicBlock *&EpilogB) const;
182
183 void addCalleeSaveRegistersAsImpOperand(MachineInstr *MI, const CSIVect &CSI,
184 bool IsDef, bool IsKill) const;
185 bool shouldInlineCSR(const MachineFunction &MF, const CSIVect &CSI) const;
186 bool useSpillFunction(const MachineFunction &MF, const CSIVect &CSI) const;
187 bool useRestoreFunction(const MachineFunction &MF, const CSIVect &CSI) const;
188 bool mayOverflowFrameOffset(MachineFunction &MF) const;
189};
190
191} // end namespace llvm
192
193#endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONFRAMELOWERING_H
MachineBasicBlock & MBB
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
const HexagonInstrInfo * TII
IRTranslator LLVM IR MI
#define I(x, y, z)
Definition MD5.cpp:57
Register const TargetRegisterInfo * TRI
This file contains some templates that are useful if you are working with the STL at all.
Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition ArrayRef.h:40
const MachineInstr * getAlignaInstr(const MachineFunction &MF) const
void insertCFIInstructions(MachineFunction &MF) const
bool hasFPImpl(const MachineFunction &MF) const override
bool enableCalleeSaveSkip(const MachineFunction &MF) const override
Returns true if the target can safely skip saving callee-saved registers for noreturn nounwind functi...
bool targetHandlesStackFrameRounding() const override
targetHandlesStackFrameRounding - Returns true if the target is responsible for rounding up the stack...
MachineBasicBlock::iterator eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const override
This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy p...
bool canSimplifyCallFramePseudos(const MachineFunction &MF) const override
canSimplifyCallFramePseudos - When possible, it's best to simplify the call frame pseudo ops before d...
StackOffset getFrameIndexReference(const MachineFunction &MF, int FI, Register &FrameReg) const override
getFrameIndexReference - This method should return the base register and offset used to reference a f...
void emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const override
Perform most of the PEI work here:
void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS) const override
This method determines which of the registers reported by TargetRegisterInfo::getCalleeSavedRegs() sh...
void orderFrameObjects(const MachineFunction &MF, SmallVectorImpl< int > &ObjectsToAllocate) const override
Order the symbols in the local stack frame.
void processFunctionBeforeFrameFinalized(MachineFunction &MF, RegScavenger *RS=nullptr) const override
processFunctionBeforeFrameFinalized - This method is called immediately before the specified function...
void inlineStackProbe(MachineFunction &MF, MachineBasicBlock &PrologueMBB) const override
Replace a StackProbe stub (if any) with the actual probe code inline.
const SpillSlot * getCalleeSavedSpillSlots(unsigned &NumEntries) const override
getCalleeSavedSpillSlots - This method returns a pointer to an array of pairs, that contains an entry...
bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, ArrayRef< CalleeSavedInfo > CSI, const TargetRegisterInfo *TRI) const override
spillCalleeSavedRegisters - Issues instruction(s) to spill all callee saved registers and returns tru...
void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override
bool needsAligna(const MachineFunction &MF) const
bool assignCalleeSavedSpillSlots(MachineFunction &MF, const TargetRegisterInfo *TRI, std::vector< CalleeSavedInfo > &CSI) const override
assignCalleeSavedSpillSlots - Allows target to override spill slot assignment logic.
bool hasReservedCallFrame(const MachineFunction &MF) const override
hasReservedCallFrame - Under normal circumstances, when a frame pointer is not required,...
bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, MutableArrayRef< CalleeSavedInfo > CSI, const TargetRegisterInfo *TRI) const override
restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee saved registers and returns...
MCRegisterClass - Base class of TargetRegisterClass.
MachineInstrBundleIterator< MachineInstr > iterator
Representation of each machine instruction.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Represent a mutable reference to an array (0 or more elements consecutively in memory),...
Definition ArrayRef.h:294
Wrapper class representing virtual and physical registers.
Definition Register.h:20
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
StackOffset holds a fixed and a scalable offset in bytes.
Definition TypeSize.h:30
TargetFrameLowering(StackDirection D, Align StackAl, int LAO, Align TransAl=Align(1), bool StackReal=true)
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This is an optimization pass for GlobalISel generic memory operations.
MCRegisterClass TargetRegisterClass
Definition FastISel.h:58
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition Alignment.h:39
std::map< RegisterRef, RangeList > RegToRangeMap