82#define DEBUG_TYPE "mips-lower"
88 cl::desc(
"MIPS: Don't trap on integer division by zero."),
94 Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64,
95 Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64
126 unsigned &NumIntermediates,
MVT &RegisterVT)
const {
131 return NumIntermediates;
147 unsigned Flag)
const {
153 unsigned Flag)
const {
159 unsigned Flag)
const {
165 unsigned Flag)
const {
171 unsigned Flag)
const {
173 N->getOffset(), Flag);
562 if (!
TM.isPositionIndependent() || !
TM.getABI().IsO32() ||
582 EVT Ty =
N->getValueType(0);
583 unsigned LO = (Ty == MVT::i32) ? Mips::LO0 : Mips::LO0_64;
584 unsigned HI = (Ty == MVT::i32) ? Mips::HI0 : Mips::HI0_64;
590 N->getOperand(0),
N->getOperand(1));
595 if (
N->hasAnyUseOfValue(0)) {
604 if (
N->hasAnyUseOfValue(1)) {
646 "Illegal Condition Code");
660 if (!
LHS.getValueType().isFloatingPoint())
772 SDValue ValueIfTrue =
N->getOperand(0), ValueIfFalse =
N->getOperand(2);
788 SDValue FCC =
N->getOperand(1), Glue =
N->getOperand(3);
789 return DAG.
getNode(Opc,
SDLoc(
N), ValueIfFalse.getValueType(),
790 ValueIfFalse, FCC, ValueIfTrue, Glue);
799 SDValue FirstOperand =
N->getOperand(0);
800 unsigned FirstOperandOpc = FirstOperand.
getOpcode();
802 EVT ValTy =
N->getValueType(0);
806 unsigned SMPos, SMSize;
812 if (!(CN = dyn_cast<ConstantSDNode>(Mask)) ||
822 if (!(CN = dyn_cast<ConstantSDNode>(FirstOperand.
getOperand(1))))
842 if (!(CN = dyn_cast<ConstantSDNode>(FirstOperand.
getOperand(1))))
847 if (SMPos != Pos || Pos >= ValTy.
getSizeInBits() || SMSize >= 32 ||
869 NewOperand = FirstOperand;
871 return DAG.
getNode(Opc,
DL, ValTy, NewOperand,
886 SDValue And0 =
N->getOperand(0), And1 =
N->getOperand(1);
887 unsigned SMPos0, SMSize0, SMPos1, SMSize1;
894 if (!(CN = dyn_cast<ConstantSDNode>(And0.
getOperand(1))) ||
900 And1.getOperand(0).getOpcode() ==
ISD::SHL) {
902 if (!(CN = dyn_cast<ConstantSDNode>(And1.getOperand(1))) ||
907 if (SMPos0 != SMPos1 || SMSize0 != SMSize1)
912 if (!(CN = dyn_cast<ConstantSDNode>(Shl.
getOperand(1))))
919 EVT ValTy =
N->getValueType(0);
920 if ((Shamt != SMPos0) || (SMPos0 + SMSize0 > ValTy.
getSizeInBits()))
933 if (~CN->
getSExtValue() == ((((int64_t)1 << SMSize0) - 1) << SMPos0) &&
934 ((SMSize0 + SMPos0 <= 64 && Subtarget.
hasMips64r2()) ||
935 (SMSize0 + SMPos0 <= 32))) {
939 if (!(CN1 = dyn_cast<ConstantSDNode>(And1->getOperand(1))))
942 if (!(CN1 = dyn_cast<ConstantSDNode>(
N->getOperand(1))))
951 EVT ValTy =
N->getOperand(0)->getValueType(0);
1026 if (!Mult.hasOneUse())
1034 SDValue MultLHS = Mult->getOperand(0);
1035 SDValue MultRHS = Mult->getOperand(1);
1042 if (!IsSigned && !IsUnsigned)
1048 std::tie(BottomHalf, TopHalf) =
1060 EVT VTs[2] = {MVT::i32, MVT::i32};
1076 !Subtarget.
inMips16Mode() &&
N->getValueType(0) == MVT::i64)
1091 !Subtarget.
inMips16Mode() &&
N->getValueType(0) == MVT::i64)
1109 EVT ValTy =
N->getValueType(0);
1127 SDValue FirstOperand =
N->getOperand(0);
1128 unsigned FirstOperandOpc = FirstOperand.
getOpcode();
1129 SDValue SecondOperand =
N->getOperand(1);
1130 EVT ValTy =
N->getValueType(0);
1134 unsigned SMPos, SMSize;
1139 if (!(CN = dyn_cast<ConstantSDNode>(SecondOperand)))
1151 if (!(CN = dyn_cast<ConstantSDNode>(FirstOperand.
getOperand(1))) ||
1157 if (SMPos != 0 || SMSize > 32 || Pos + SMSize > ValTy.
getSizeInBits())
1172 unsigned Opc =
N->getOpcode();
1211 if (
auto *
C = dyn_cast<ConstantSDNode>(
Y))
1212 return C->getAPIntValue().ule(15);
1220 N->getOperand(0).getOpcode() ==
ISD::SRL) ||
1222 N->getOperand(0).getOpcode() ==
ISD::SHL)) &&
1223 "Expected shift-shift mask");
1225 if (
N->getOperand(0).getValueType().isVector())
1240 switch (
Op.getOpcode())
1287 bool Is64Bit,
bool IsMicroMips) {
1296 TII.get(IsMicroMips ? Mips::TEQ_MM : Mips::TEQ))
1317 switch (
MI.getOpcode()) {
1320 case Mips::ATOMIC_LOAD_ADD_I8:
1321 return emitAtomicBinaryPartword(
MI, BB, 1);
1322 case Mips::ATOMIC_LOAD_ADD_I16:
1323 return emitAtomicBinaryPartword(
MI, BB, 2);
1324 case Mips::ATOMIC_LOAD_ADD_I32:
1325 return emitAtomicBinary(
MI, BB);
1326 case Mips::ATOMIC_LOAD_ADD_I64:
1327 return emitAtomicBinary(
MI, BB);
1329 case Mips::ATOMIC_LOAD_AND_I8:
1330 return emitAtomicBinaryPartword(
MI, BB, 1);
1331 case Mips::ATOMIC_LOAD_AND_I16:
1332 return emitAtomicBinaryPartword(
MI, BB, 2);
1333 case Mips::ATOMIC_LOAD_AND_I32:
1334 return emitAtomicBinary(
MI, BB);
1335 case Mips::ATOMIC_LOAD_AND_I64:
1336 return emitAtomicBinary(
MI, BB);
1338 case Mips::ATOMIC_LOAD_OR_I8:
1339 return emitAtomicBinaryPartword(
MI, BB, 1);
1340 case Mips::ATOMIC_LOAD_OR_I16:
1341 return emitAtomicBinaryPartword(
MI, BB, 2);
1342 case Mips::ATOMIC_LOAD_OR_I32:
1343 return emitAtomicBinary(
MI, BB);
1344 case Mips::ATOMIC_LOAD_OR_I64:
1345 return emitAtomicBinary(
MI, BB);
1347 case Mips::ATOMIC_LOAD_XOR_I8:
1348 return emitAtomicBinaryPartword(
MI, BB, 1);
1349 case Mips::ATOMIC_LOAD_XOR_I16:
1350 return emitAtomicBinaryPartword(
MI, BB, 2);
1351 case Mips::ATOMIC_LOAD_XOR_I32:
1352 return emitAtomicBinary(
MI, BB);
1353 case Mips::ATOMIC_LOAD_XOR_I64:
1354 return emitAtomicBinary(
MI, BB);
1356 case Mips::ATOMIC_LOAD_NAND_I8:
1357 return emitAtomicBinaryPartword(
MI, BB, 1);
1358 case Mips::ATOMIC_LOAD_NAND_I16:
1359 return emitAtomicBinaryPartword(
MI, BB, 2);
1360 case Mips::ATOMIC_LOAD_NAND_I32:
1361 return emitAtomicBinary(
MI, BB);
1362 case Mips::ATOMIC_LOAD_NAND_I64:
1363 return emitAtomicBinary(
MI, BB);
1365 case Mips::ATOMIC_LOAD_SUB_I8:
1366 return emitAtomicBinaryPartword(
MI, BB, 1);
1367 case Mips::ATOMIC_LOAD_SUB_I16:
1368 return emitAtomicBinaryPartword(
MI, BB, 2);
1369 case Mips::ATOMIC_LOAD_SUB_I32:
1370 return emitAtomicBinary(
MI, BB);
1371 case Mips::ATOMIC_LOAD_SUB_I64:
1372 return emitAtomicBinary(
MI, BB);
1374 case Mips::ATOMIC_SWAP_I8:
1375 return emitAtomicBinaryPartword(
MI, BB, 1);
1376 case Mips::ATOMIC_SWAP_I16:
1377 return emitAtomicBinaryPartword(
MI, BB, 2);
1378 case Mips::ATOMIC_SWAP_I32:
1379 return emitAtomicBinary(
MI, BB);
1380 case Mips::ATOMIC_SWAP_I64:
1381 return emitAtomicBinary(
MI, BB);
1383 case Mips::ATOMIC_CMP_SWAP_I8:
1384 return emitAtomicCmpSwapPartword(
MI, BB, 1);
1385 case Mips::ATOMIC_CMP_SWAP_I16:
1386 return emitAtomicCmpSwapPartword(
MI, BB, 2);
1387 case Mips::ATOMIC_CMP_SWAP_I32:
1388 return emitAtomicCmpSwap(
MI, BB);
1389 case Mips::ATOMIC_CMP_SWAP_I64:
1390 return emitAtomicCmpSwap(
MI, BB);
1392 case Mips::ATOMIC_LOAD_MIN_I8:
1393 return emitAtomicBinaryPartword(
MI, BB, 1);
1394 case Mips::ATOMIC_LOAD_MIN_I16:
1395 return emitAtomicBinaryPartword(
MI, BB, 2);
1396 case Mips::ATOMIC_LOAD_MIN_I32:
1397 return emitAtomicBinary(
MI, BB);
1398 case Mips::ATOMIC_LOAD_MIN_I64:
1399 return emitAtomicBinary(
MI, BB);
1401 case Mips::ATOMIC_LOAD_MAX_I8:
1402 return emitAtomicBinaryPartword(
MI, BB, 1);
1403 case Mips::ATOMIC_LOAD_MAX_I16:
1404 return emitAtomicBinaryPartword(
MI, BB, 2);
1405 case Mips::ATOMIC_LOAD_MAX_I32:
1406 return emitAtomicBinary(
MI, BB);
1407 case Mips::ATOMIC_LOAD_MAX_I64:
1408 return emitAtomicBinary(
MI, BB);
1410 case Mips::ATOMIC_LOAD_UMIN_I8:
1411 return emitAtomicBinaryPartword(
MI, BB, 1);
1412 case Mips::ATOMIC_LOAD_UMIN_I16:
1413 return emitAtomicBinaryPartword(
MI, BB, 2);
1414 case Mips::ATOMIC_LOAD_UMIN_I32:
1415 return emitAtomicBinary(
MI, BB);
1416 case Mips::ATOMIC_LOAD_UMIN_I64:
1417 return emitAtomicBinary(
MI, BB);
1419 case Mips::ATOMIC_LOAD_UMAX_I8:
1420 return emitAtomicBinaryPartword(
MI, BB, 1);
1421 case Mips::ATOMIC_LOAD_UMAX_I16:
1422 return emitAtomicBinaryPartword(
MI, BB, 2);
1423 case Mips::ATOMIC_LOAD_UMAX_I32:
1424 return emitAtomicBinary(
MI, BB);
1425 case Mips::ATOMIC_LOAD_UMAX_I64:
1426 return emitAtomicBinary(
MI, BB);
1428 case Mips::PseudoSDIV:
1429 case Mips::PseudoUDIV:
1436 case Mips::SDIV_MM_Pseudo:
1437 case Mips::UDIV_MM_Pseudo:
1440 case Mips::DIV_MMR6:
1441 case Mips::DIVU_MMR6:
1442 case Mips::MOD_MMR6:
1443 case Mips::MODU_MMR6:
1445 case Mips::PseudoDSDIV:
1446 case Mips::PseudoDUDIV:
1453 case Mips::PseudoSELECT_I:
1454 case Mips::PseudoSELECT_I64:
1455 case Mips::PseudoSELECT_S:
1456 case Mips::PseudoSELECT_D32:
1457 case Mips::PseudoSELECT_D64:
1458 return emitPseudoSELECT(
MI, BB,
false, Mips::BNE);
1459 case Mips::PseudoSELECTFP_F_I:
1460 case Mips::PseudoSELECTFP_F_I64:
1461 case Mips::PseudoSELECTFP_F_S:
1462 case Mips::PseudoSELECTFP_F_D32:
1463 case Mips::PseudoSELECTFP_F_D64:
1464 return emitPseudoSELECT(
MI, BB,
true, Mips::BC1F);
1465 case Mips::PseudoSELECTFP_T_I:
1466 case Mips::PseudoSELECTFP_T_I64:
1467 case Mips::PseudoSELECTFP_T_S:
1468 case Mips::PseudoSELECTFP_T_D32:
1469 case Mips::PseudoSELECTFP_T_D64:
1470 return emitPseudoSELECT(
MI, BB,
true, Mips::BC1T);
1471 case Mips::PseudoD_SELECT_I:
1472 case Mips::PseudoD_SELECT_I64:
1473 return emitPseudoD_SELECT(
MI, BB);
1475 return emitLDR_W(
MI, BB);
1477 return emitLDR_D(
MI, BB);
1479 return emitSTR_W(
MI, BB);
1481 return emitSTR_D(
MI, BB);
1497 bool NeedsAdditionalReg =
false;
1498 switch (
MI.getOpcode()) {
1499 case Mips::ATOMIC_LOAD_ADD_I32:
1500 AtomicOp = Mips::ATOMIC_LOAD_ADD_I32_POSTRA;
1502 case Mips::ATOMIC_LOAD_SUB_I32:
1503 AtomicOp = Mips::ATOMIC_LOAD_SUB_I32_POSTRA;
1505 case Mips::ATOMIC_LOAD_AND_I32:
1506 AtomicOp = Mips::ATOMIC_LOAD_AND_I32_POSTRA;
1508 case Mips::ATOMIC_LOAD_OR_I32:
1509 AtomicOp = Mips::ATOMIC_LOAD_OR_I32_POSTRA;
1511 case Mips::ATOMIC_LOAD_XOR_I32:
1512 AtomicOp = Mips::ATOMIC_LOAD_XOR_I32_POSTRA;
1514 case Mips::ATOMIC_LOAD_NAND_I32:
1515 AtomicOp = Mips::ATOMIC_LOAD_NAND_I32_POSTRA;
1517 case Mips::ATOMIC_SWAP_I32:
1518 AtomicOp = Mips::ATOMIC_SWAP_I32_POSTRA;
1520 case Mips::ATOMIC_LOAD_ADD_I64:
1521 AtomicOp = Mips::ATOMIC_LOAD_ADD_I64_POSTRA;
1523 case Mips::ATOMIC_LOAD_SUB_I64:
1524 AtomicOp = Mips::ATOMIC_LOAD_SUB_I64_POSTRA;
1526 case Mips::ATOMIC_LOAD_AND_I64:
1527 AtomicOp = Mips::ATOMIC_LOAD_AND_I64_POSTRA;
1529 case Mips::ATOMIC_LOAD_OR_I64:
1530 AtomicOp = Mips::ATOMIC_LOAD_OR_I64_POSTRA;
1532 case Mips::ATOMIC_LOAD_XOR_I64:
1533 AtomicOp = Mips::ATOMIC_LOAD_XOR_I64_POSTRA;
1535 case Mips::ATOMIC_LOAD_NAND_I64:
1536 AtomicOp = Mips::ATOMIC_LOAD_NAND_I64_POSTRA;
1538 case Mips::ATOMIC_SWAP_I64:
1539 AtomicOp = Mips::ATOMIC_SWAP_I64_POSTRA;
1541 case Mips::ATOMIC_LOAD_MIN_I32:
1542 AtomicOp = Mips::ATOMIC_LOAD_MIN_I32_POSTRA;
1543 NeedsAdditionalReg =
true;
1545 case Mips::ATOMIC_LOAD_MAX_I32:
1546 AtomicOp = Mips::ATOMIC_LOAD_MAX_I32_POSTRA;
1547 NeedsAdditionalReg =
true;
1549 case Mips::ATOMIC_LOAD_UMIN_I32:
1550 AtomicOp = Mips::ATOMIC_LOAD_UMIN_I32_POSTRA;
1551 NeedsAdditionalReg =
true;
1553 case Mips::ATOMIC_LOAD_UMAX_I32:
1554 AtomicOp = Mips::ATOMIC_LOAD_UMAX_I32_POSTRA;
1555 NeedsAdditionalReg =
true;
1557 case Mips::ATOMIC_LOAD_MIN_I64:
1558 AtomicOp = Mips::ATOMIC_LOAD_MIN_I64_POSTRA;
1559 NeedsAdditionalReg =
true;
1561 case Mips::ATOMIC_LOAD_MAX_I64:
1562 AtomicOp = Mips::ATOMIC_LOAD_MAX_I64_POSTRA;
1563 NeedsAdditionalReg =
true;
1565 case Mips::ATOMIC_LOAD_UMIN_I64:
1566 AtomicOp = Mips::ATOMIC_LOAD_UMIN_I64_POSTRA;
1567 NeedsAdditionalReg =
true;
1569 case Mips::ATOMIC_LOAD_UMAX_I64:
1570 AtomicOp = Mips::ATOMIC_LOAD_UMAX_I64_POSTRA;
1571 NeedsAdditionalReg =
true;
1632 if (NeedsAdditionalReg) {
1639 MI.eraseFromParent();
1646 unsigned SrcReg)
const {
1666 int64_t ShiftImm = 32 - (
Size * 8);
1677 "Unsupported size for EmitAtomicBinaryPartial.");
1704 unsigned AtomicOp = 0;
1705 bool NeedsAdditionalReg =
false;
1706 switch (
MI.getOpcode()) {
1707 case Mips::ATOMIC_LOAD_NAND_I8:
1708 AtomicOp = Mips::ATOMIC_LOAD_NAND_I8_POSTRA;
1710 case Mips::ATOMIC_LOAD_NAND_I16:
1711 AtomicOp = Mips::ATOMIC_LOAD_NAND_I16_POSTRA;
1713 case Mips::ATOMIC_SWAP_I8:
1714 AtomicOp = Mips::ATOMIC_SWAP_I8_POSTRA;
1716 case Mips::ATOMIC_SWAP_I16:
1717 AtomicOp = Mips::ATOMIC_SWAP_I16_POSTRA;
1719 case Mips::ATOMIC_LOAD_ADD_I8:
1720 AtomicOp = Mips::ATOMIC_LOAD_ADD_I8_POSTRA;
1722 case Mips::ATOMIC_LOAD_ADD_I16:
1723 AtomicOp = Mips::ATOMIC_LOAD_ADD_I16_POSTRA;
1725 case Mips::ATOMIC_LOAD_SUB_I8:
1726 AtomicOp = Mips::ATOMIC_LOAD_SUB_I8_POSTRA;
1728 case Mips::ATOMIC_LOAD_SUB_I16:
1729 AtomicOp = Mips::ATOMIC_LOAD_SUB_I16_POSTRA;
1731 case Mips::ATOMIC_LOAD_AND_I8:
1732 AtomicOp = Mips::ATOMIC_LOAD_AND_I8_POSTRA;
1734 case Mips::ATOMIC_LOAD_AND_I16:
1735 AtomicOp = Mips::ATOMIC_LOAD_AND_I16_POSTRA;
1737 case Mips::ATOMIC_LOAD_OR_I8:
1738 AtomicOp = Mips::ATOMIC_LOAD_OR_I8_POSTRA;
1740 case Mips::ATOMIC_LOAD_OR_I16:
1741 AtomicOp = Mips::ATOMIC_LOAD_OR_I16_POSTRA;
1743 case Mips::ATOMIC_LOAD_XOR_I8:
1744 AtomicOp = Mips::ATOMIC_LOAD_XOR_I8_POSTRA;
1746 case Mips::ATOMIC_LOAD_XOR_I16:
1747 AtomicOp = Mips::ATOMIC_LOAD_XOR_I16_POSTRA;
1749 case Mips::ATOMIC_LOAD_MIN_I8:
1750 AtomicOp = Mips::ATOMIC_LOAD_MIN_I8_POSTRA;
1751 NeedsAdditionalReg =
true;
1753 case Mips::ATOMIC_LOAD_MIN_I16:
1754 AtomicOp = Mips::ATOMIC_LOAD_MIN_I16_POSTRA;
1755 NeedsAdditionalReg =
true;
1757 case Mips::ATOMIC_LOAD_MAX_I8:
1758 AtomicOp = Mips::ATOMIC_LOAD_MAX_I8_POSTRA;
1759 NeedsAdditionalReg =
true;
1761 case Mips::ATOMIC_LOAD_MAX_I16:
1762 AtomicOp = Mips::ATOMIC_LOAD_MAX_I16_POSTRA;
1763 NeedsAdditionalReg =
true;
1765 case Mips::ATOMIC_LOAD_UMIN_I8:
1766 AtomicOp = Mips::ATOMIC_LOAD_UMIN_I8_POSTRA;
1767 NeedsAdditionalReg =
true;
1769 case Mips::ATOMIC_LOAD_UMIN_I16:
1770 AtomicOp = Mips::ATOMIC_LOAD_UMIN_I16_POSTRA;
1771 NeedsAdditionalReg =
true;
1773 case Mips::ATOMIC_LOAD_UMAX_I8:
1774 AtomicOp = Mips::ATOMIC_LOAD_UMAX_I8_POSTRA;
1775 NeedsAdditionalReg =
true;
1777 case Mips::ATOMIC_LOAD_UMAX_I16:
1778 AtomicOp = Mips::ATOMIC_LOAD_UMAX_I16_POSTRA;
1779 NeedsAdditionalReg =
true;
1808 int64_t MaskImm = (
Size == 1) ? 255 : 65535;
1849 if (NeedsAdditionalReg) {
1855 MI.eraseFromParent();
1869 assert((
MI.getOpcode() == Mips::ATOMIC_CMP_SWAP_I32 ||
1870 MI.getOpcode() == Mips::ATOMIC_CMP_SWAP_I64) &&
1871 "Unsupported atomic pseudo for EmitAtomicCmpSwap.");
1873 const unsigned Size =
MI.getOpcode() == Mips::ATOMIC_CMP_SWAP_I32 ? 4 : 8;
1881 unsigned AtomicOp =
MI.getOpcode() == Mips::ATOMIC_CMP_SWAP_I32
1882 ? Mips::ATOMIC_CMP_SWAP_I32_POSTRA
1883 : Mips::ATOMIC_CMP_SWAP_I64_POSTRA;
1898 Register OldValCopy =
MRI.createVirtualRegister(
MRI.getRegClass(OldVal));
1899 Register NewValCopy =
MRI.createVirtualRegister(
MRI.getRegClass(NewVal));
1917 MI.eraseFromParent();
1925 "Unsupported size for EmitAtomicCmpSwapPartial.");
1952 unsigned AtomicOp =
MI.getOpcode() == Mips::ATOMIC_CMP_SWAP_I8
1953 ? Mips::ATOMIC_CMP_SWAP_I8_POSTRA
1954 : Mips::ATOMIC_CMP_SWAP_I16_POSTRA;
1995 int64_t MaskImm = (
Size == 1) ? 255 : 65535;
1996 BuildMI(BB,
DL,
TII->get(ArePtrs64bit ? Mips::DADDiu : Mips::ADDiu), MaskLSB2)
1998 BuildMI(BB,
DL,
TII->get(ArePtrs64bit ? Mips::AND64 : Mips::AND), AlignedAddr)
2041 MI.eraseFromParent();
2066 FCC0, Dest, CondRes);
2088 "Floating point operand expected.");
2099 EVT Ty =
Op.getValueType();
2147 EVT Ty =
Op.getValueType();
2190 Args.push_back(Entry);
2195 .setLibCallee(
CallingConv::C, PtrTy, TlsGetAddr, std::move(Args));
2196 std::pair<SDValue, SDValue> CallResult =
LowerCallTo(CLI);
2242 EVT Ty =
Op.getValueType();
2255 EVT Ty =
Op.getValueType();
2284 const Value *SV = cast<SrcValueSDNode>(
Op.getOperand(2))->getValue();
2291 EVT VT =
Node->getValueType(0);
2296 const Value *SV = cast<SrcValueSDNode>(
Node->getOperand(2))->getValue();
2323 unsigned ArgSizeInBytes =
2339 unsigned Adjustment = ArgSlotSizeInBytes - ArgSizeInBytes;
2348 bool HasExtractInsert) {
2349 EVT TyX =
Op.getOperand(0).getValueType();
2350 EVT TyY =
Op.getOperand(1).getValueType();
2367 if (HasExtractInsert) {
2385 if (TyX == MVT::f32)
2395 bool HasExtractInsert) {
2396 unsigned WidthX =
Op.getOperand(0).getValueSizeInBits();
2397 unsigned WidthY =
Op.getOperand(1).getValueSizeInBits();
2406 if (HasExtractInsert) {
2412 if (WidthX > WidthY)
2414 else if (WidthY > WidthX)
2433 if (WidthX > WidthY)
2435 else if (WidthY > WidthX)
2453 bool HasExtractInsert)
const {
2465 Op.getOperand(0), Const1);
2468 if (HasExtractInsert)
2479 if (
Op.getValueType() == MVT::f32)
2493 bool HasExtractInsert)
const {
2504 if (HasExtractInsert)
2526 if (
Op.getConstantOperandVal(0) != 0) {
2528 "return address can be determined only for current frame");
2534 EVT VT =
Op.getValueType();
2547 if (
Op.getConstantOperandVal(0) != 0) {
2549 "return address can be determined only for current frame");
2555 MVT VT =
Op.getSimpleValueType();
2556 unsigned RA =
ABI.
IsN64() ? Mips::RA_64 : Mips::RA;
2582 unsigned OffsetReg =
ABI.
IsN64() ? Mips::V1_64 : Mips::V1;
2583 unsigned AddrReg =
ABI.
IsN64() ? Mips::V0_64 : Mips::V0;
2673 DL, VTList,
Cond, ShiftRightHi,
2689 EVT VT = LD->getValueType(0), MemVT = LD->getMemoryVT();
2690 EVT BasePtrVT =
Ptr.getValueType();
2700 LD->getMemOperand());
2706 EVT MemVT = LD->getMemoryVT();
2712 if ((LD->getAlign().value() >= (MemVT.
getSizeInBits() / 8)) ||
2713 ((MemVT != MVT::i32) && (MemVT != MVT::i64)))
2717 EVT VT =
Op.getValueType();
2721 assert((VT == MVT::i32) || (VT == MVT::i64));
2764 SDValue Ops[] = { SRL, LWR.getValue(1) };
2837 ((MemVT == MVT::i32) || (MemVT == MVT::i64)))
2849 EVT ValTy =
Op->getValueType(0);
2895 static const MCPhysReg IntRegs[] = { Mips::A0, Mips::A1, Mips::A2, Mips::A3 };
2901 static const MCPhysReg FloatVectorIntRegs[] = { Mips::A0, Mips::A2 };
2909 if (LocVT == MVT::i8 || LocVT == MVT::i16 || LocVT == MVT::i32) {
2913 else if (ArgFlags.
isZExt())
2921 if (LocVT == MVT::i8 || LocVT == MVT::i16) {
2925 else if (ArgFlags.
isZExt())
2936 bool AllocateFloatsInIntReg = State.
isVarArg() || ValNo > 1 ||
2939 bool isI64 = (ValVT == MVT::i32 && OrigAlign ==
Align(8));
2943 if (ValVT == MVT::i32 && isVectorFloat) {
2950 if (Reg == Mips::A2)
2959 }
else if (ValVT == MVT::i32 ||
2960 (ValVT == MVT::f32 && AllocateFloatsInIntReg)) {
2964 if (isI64 && (Reg == Mips::A1 || Reg == Mips::A3))
2967 }
else if (ValVT == MVT::f64 && AllocateFloatsInIntReg) {
2971 if (Reg == Mips::A1 || Reg == Mips::A3)
2987 if (ValVT == MVT::f32) {
2995 if (Reg2 == Mips::A1 || Reg2 == Mips::A3)
3014 static const MCPhysReg F64Regs[] = { Mips::D6, Mips::D7 };
3016 return CC_MipsO32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State, F64Regs);
3022 static const MCPhysReg F64Regs[] = { Mips::D12_64, Mips::D14_64 };
3024 return CC_MipsO32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State, F64Regs);
3031#include "MipsGenCallingConv.inc"
3034 return CC_Mips_FixedArg;
3046 const SDLoc &
DL,
bool IsTailCall,
3064 std::deque<std::pair<unsigned, SDValue>> &RegsToPass,
3065 bool IsPICCall,
bool GlobalOrExternal,
bool InternalLinkage,
3078 if (IsPICCall && !InternalLinkage && IsCallReloc) {
3079 unsigned GPReg =
ABI.
IsN64() ? Mips::GP_64 : Mips::GP;
3081 RegsToPass.push_back(std::make_pair(GPReg,
getGlobalReg(CLI.
DAG, Ty)));
3090 for (
auto &R : RegsToPass) {
3097 for (
auto &R : RegsToPass)
3104 assert(Mask &&
"Missing call preserved mask for calling convention");
3108 Function *
F =
G->getGlobal()->getParent()->getFunction(
Sym);
3109 if (
F &&
F->hasFnAttribute(
"__Mips16RetHelper")) {
3122 switch (
MI.getOpcode()) {
3126 case Mips::JALRPseudo:
3128 case Mips::JALR64Pseudo:
3129 case Mips::JALR16_MM:
3130 case Mips::JALRC16_MMR6:
3131 case Mips::TAILCALLREG:
3132 case Mips::TAILCALLREG64:
3133 case Mips::TAILCALLR6REG:
3134 case Mips::TAILCALL64R6REG:
3135 case Mips::TAILCALLREG_MM:
3136 case Mips::TAILCALLREG_MMR6: {
3140 Node->getNumOperands() < 1 ||
3141 Node->getOperand(0).getNumOperands() < 2) {
3147 const SDValue TargetAddr = Node->getOperand(0).getOperand(1);
3150 dyn_cast_or_null<const GlobalAddressSDNode>(TargetAddr)) {
3154 if (!isa<Function>(
G->getGlobal())) {
3155 LLVM_DEBUG(
dbgs() <<
"Not adding R_MIPS_JALR against data symbol "
3156 <<
G->getGlobal()->getName() <<
"\n");
3159 Sym =
G->getGlobal()->getName();
3162 dyn_cast_or_null<const ExternalSymbolSDNode>(TargetAddr)) {
3163 Sym = ES->getSymbol();
3206 dyn_cast_or_null<const ExternalSymbolSDNode>(Callee.getNode());
3238 unsigned ReservedArgArea =
3240 CCInfo.AllocateStack(ReservedArgArea,
Align(1));
3246 unsigned StackSize = CCInfo.getStackSize();
3253 bool InternalLinkage =
false;
3255 IsTailCall = isEligibleForTailCallOptimization(
3258 InternalLinkage =
G->getGlobal()->hasInternalLinkage();
3259 IsTailCall &= (InternalLinkage ||
G->getGlobal()->hasLocalLinkage() ||
3260 G->getGlobal()->hasPrivateLinkage() ||
3261 G->getGlobal()->hasHiddenVisibility() ||
3262 G->getGlobal()->hasProtectedVisibility());
3267 "site marked musttail");
3276 StackSize =
alignTo(StackSize, StackAlignment);
3278 if (!(IsTailCall || MemcpyInByVal))
3285 std::deque<std::pair<unsigned, SDValue>> RegsToPass;
3288 CCInfo.rewindByValRegsInfo();
3291 for (
unsigned i = 0, e = ArgLocs.
size(), OutIdx = 0; i != e; ++i, ++OutIdx) {
3292 SDValue Arg = OutVals[OutIdx];
3296 bool UseUpperBits =
false;
3299 if (
Flags.isByVal()) {
3300 unsigned FirstByValReg, LastByValReg;
3301 unsigned ByValIdx = CCInfo.getInRegsParamsProcessed();
3302 CCInfo.getInRegsParamInfo(ByValIdx, FirstByValReg, LastByValReg);
3305 "ByVal args of size 0 should have been ignored by front-end.");
3306 assert(ByValIdx < CCInfo.getInRegsParamsCount());
3308 "Do not tail-call optimize if there is a byval argument.");
3309 passByValArg(Chain,
DL, RegsToPass, MemOpChains, StackPtr, MFI, DAG, Arg,
3312 CCInfo.nextInRegsParam();
3322 if ((ValVT == MVT::f32 && LocVT == MVT::i32) ||
3323 (ValVT == MVT::f64 && LocVT == MVT::i64) ||
3324 (ValVT == MVT::i64 && LocVT == MVT::f64))
3326 else if (ValVT == MVT::f64 && LocVT == MVT::i32) {
3337 Register LocRegHigh = ArgLocs[++i].getLocReg();
3338 RegsToPass.
push_back(std::make_pair(LocRegLo,
Lo));
3339 RegsToPass.push_back(std::make_pair(LocRegHigh,
Hi));
3348 UseUpperBits =
true;
3354 UseUpperBits =
true;
3360 UseUpperBits =
true;
3368 unsigned ValSizeInBits = Outs[OutIdx].ArgVT.getSizeInBits();
3378 RegsToPass.push_back(std::make_pair(VA.
getLocReg(), Arg));
3399 Chain, Arg,
DL, IsTailCall, DAG));
3404 if (!MemOpChains.
empty())
3412 bool GlobalOrExternal =
false, IsCallReloc =
false;
3421 if (
auto *
N = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3426 }
else if (
auto *
N = dyn_cast<GlobalAddressSDNode>(Callee)) {
3430 if (
auto *
F = dyn_cast<Function>(
N->getGlobal())) {
3431 if (
F->hasFnAttribute(
"long-call"))
3432 UseLongCalls =
true;
3433 else if (
F->hasFnAttribute(
"short-call"))
3434 UseLongCalls =
false;
3448 if (InternalLinkage)
3464 GlobalOrExternal =
true;
3467 const char *
Sym = S->getSymbol();
3483 GlobalOrExternal =
true;
3489 getOpndList(Ops, RegsToPass, IsPIC, GlobalOrExternal, InternalLinkage,
3490 IsCallReloc, CLI, Callee, Chain);
3506 if (!(MemcpyInByVal)) {
3513 return LowerCallResult(Chain, InGlue, CallConv, IsVarArg, Ins,
DL, DAG,
3519SDValue MipsTargetLowering::LowerCallResult(
3530 dyn_cast_or_null<const ExternalSymbolSDNode>(CLI.
Callee.
getNode());
3531 CCInfo.AnalyzeCallResult(Ins, RetCC_Mips, CLI.
RetTy,
3535 for (
unsigned i = 0; i != RVLocs.
size(); ++i) {
3540 RVLocs[i].getLocVT(), InGlue);
3545 unsigned ValSizeInBits =
Ins[i].ArgVT.getSizeInBits();
3646SDValue MipsTargetLowering::LowerFormalArguments(
3657 std::vector<SDValue> OutChains;
3667 if (
Func.hasFnAttribute(
"interrupt") && !
Func.arg_empty())
3669 "Functions with the interrupt attribute cannot have arguments!");
3671 CCInfo.AnalyzeFormalArguments(Ins, CC_Mips_FixedArg);
3673 CCInfo.getInRegsParamsCount() > 0);
3675 unsigned CurArgIdx = 0;
3676 CCInfo.rewindByValRegsInfo();
3678 for (
unsigned i = 0, e = ArgLocs.
size(), InsIdx = 0; i != e; ++i, ++InsIdx) {
3680 if (Ins[InsIdx].isOrigArg()) {
3681 std::advance(FuncArg, Ins[InsIdx].getOrigArgIndex() - CurArgIdx);
3682 CurArgIdx =
Ins[InsIdx].getOrigArgIndex();
3688 if (
Flags.isByVal()) {
3689 assert(Ins[InsIdx].isOrigArg() &&
"Byval arguments cannot be implicit");
3690 unsigned FirstByValReg, LastByValReg;
3691 unsigned ByValIdx = CCInfo.getInRegsParamsProcessed();
3692 CCInfo.getInRegsParamInfo(ByValIdx, FirstByValReg, LastByValReg);
3695 "ByVal args of size 0 should have been ignored by front-end.");
3696 assert(ByValIdx < CCInfo.getInRegsParamsCount());
3697 copyByValRegs(Chain,
DL, OutChains, DAG, Flags, InVals, &*FuncArg,
3698 FirstByValReg, LastByValReg, VA, CCInfo);
3699 CCInfo.nextInRegsParam();
3719 if ((RegVT == MVT::i32 && ValVT == MVT::f32) ||
3720 (RegVT == MVT::i64 && ValVT == MVT::f64) ||
3721 (RegVT == MVT::f64 && ValVT == MVT::i64))
3723 else if (
ABI.
IsO32() && RegVT == MVT::i32 &&
3724 ValVT == MVT::f64) {
3733 ArgValue, ArgValue2);
3752 LocVT,
DL, Chain, FIN,
3754 OutChains.push_back(ArgValue.
getValue(1));
3763 for (
unsigned i = 0, e = ArgLocs.
size(), InsIdx = 0; i != e; ++i, ++InsIdx) {
3765 if (ArgLocs[i].needsCustom()) {
3773 if (Ins[InsIdx].
Flags.isSRet()) {
3787 writeVarArgRegs(OutChains, Chain,
DL, DAG, CCInfo);
3791 if (!OutChains.empty()) {
3792 OutChains.push_back(Chain);
3809 MipsCCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);
3810 return CCInfo.CheckReturn(Outs, RetCC_Mips);
3813bool MipsTargetLowering::shouldSignExtendTypeInLibCall(
EVT Type,
3814 bool IsSigned)
const {
3848 CCInfo.AnalyzeReturn(Outs, RetCC_Mips);
3854 for (
unsigned i = 0; i != RVLocs.
size(); ++i) {
3858 bool UseUpperBits =
false;
3869 UseUpperBits =
true;
3875 UseUpperBits =
true;
3881 UseUpperBits =
true;
3889 unsigned ValSizeInBits = Outs[i].ArgVT.getSizeInBits();
3915 unsigned V0 =
ABI.
IsN64() ? Mips::V0_64 : Mips::V0;
3930 return LowerInterruptReturn(RetOps,
DL, DAG);
3943MipsTargetLowering::getConstraintType(
StringRef Constraint)
const {
3955 if (Constraint.
size() == 1) {
3956 switch (Constraint[0]) {
3970 if (Constraint ==
"ZC")
3980MipsTargetLowering::getSingleConstraintMatchWeight(
3981 AsmOperandInfo &
info,
const char *constraint)
const {
3983 Value *CallOperandVal =
info.CallOperandVal;
3986 if (!CallOperandVal)
3990 switch (*constraint) {
4019 if (isa<ConstantInt>(CallOperandVal))
4034 unsigned long long &Reg) {
4035 if (
C.front() !=
'{' ||
C.back() !=
'}')
4036 return std::make_pair(
false,
false);
4040 I = std::find_if(
B, E, isdigit);
4046 return std::make_pair(
true,
false);
4057 return VT.
bitsLT(MinVT) ? MinVT : VT;
4060std::pair<unsigned, const TargetRegisterClass *> MipsTargetLowering::
4066 unsigned long long Reg;
4071 return std::make_pair(0U,
nullptr);
4073 if ((Prefix ==
"hi" || Prefix ==
"lo")) {
4076 return std::make_pair(0U,
nullptr);
4078 RC =
TRI->getRegClass(Prefix ==
"hi" ?
4079 Mips::HI32RegClassID : Mips::LO32RegClassID);
4080 return std::make_pair(*(RC->
begin()), RC);
4081 }
else if (Prefix.starts_with(
"$msa")) {
4086 return std::make_pair(0U,
nullptr);
4089 .
Case(
"$msair", Mips::MSAIR)
4090 .
Case(
"$msacsr", Mips::MSACSR)
4091 .
Case(
"$msaaccess", Mips::MSAAccess)
4092 .
Case(
"$msasave", Mips::MSASave)
4093 .
Case(
"$msamodify", Mips::MSAModify)
4094 .
Case(
"$msarequest", Mips::MSARequest)
4095 .
Case(
"$msamap", Mips::MSAMap)
4096 .
Case(
"$msaunmap", Mips::MSAUnmap)
4100 return std::make_pair(0U,
nullptr);
4102 RC =
TRI->getRegClass(Mips::MSACtrlRegClassID);
4103 return std::make_pair(Reg, RC);
4107 return std::make_pair(0U,
nullptr);
4109 if (Prefix ==
"$f") {
4112 if (VT == MVT::Other)
4117 if (RC == &Mips::AFGR64RegClass) {
4121 }
else if (Prefix ==
"$fcc")
4122 RC =
TRI->getRegClass(Mips::FCCRegClassID);
4123 else if (Prefix ==
"$w") {
4130 assert(Reg < RC->getNumRegs());
4131 return std::make_pair(*(RC->
begin() + Reg), RC);
4137std::pair<unsigned, const TargetRegisterClass *>
4141 if (Constraint.
size() == 1) {
4142 switch (Constraint[0]) {
4146 if ((VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8 ||
4150 return std::make_pair(0U, &Mips::CPU16RegsRegClass);
4151 return std::make_pair(0U, &Mips::GPR32RegClass);
4155 return std::make_pair(0U, &Mips::GPR32RegClass);
4158 return std::make_pair(0U, &Mips::GPR64RegClass);
4160 return std::make_pair(0U,
nullptr);
4162 if (VT == MVT::v16i8)
4163 return std::make_pair(0U, &Mips::MSA128BRegClass);
4164 else if (VT == MVT::v8i16 || VT == MVT::v8f16)
4165 return std::make_pair(0U, &Mips::MSA128HRegClass);
4166 else if (VT == MVT::v4i32 || VT == MVT::v4f32)
4167 return std::make_pair(0U, &Mips::MSA128WRegClass);
4168 else if (VT == MVT::v2i64 || VT == MVT::v2f64)
4169 return std::make_pair(0U, &Mips::MSA128DRegClass);
4170 else if (VT == MVT::f32)
4171 return std::make_pair(0U, &Mips::FGR32RegClass);
4174 return std::make_pair(0U, &Mips::FGR64RegClass);
4175 return std::make_pair(0U, &Mips::AFGR64RegClass);
4180 return std::make_pair((
unsigned)Mips::T9, &Mips::GPR32RegClass);
4182 return std::make_pair((
unsigned)Mips::T9_64, &Mips::GPR64RegClass);
4184 return std::make_pair(0U,
nullptr);
4187 if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8)
4188 return std::make_pair((
unsigned)Mips::LO0, &Mips::LO32RegClass);
4189 return std::make_pair((
unsigned)Mips::LO0_64, &Mips::LO64RegClass);
4194 return std::make_pair(0U,
nullptr);
4198 if (!Constraint.
empty()) {
4199 std::pair<unsigned, const TargetRegisterClass *>
R;
4200 R = parseRegForInlineAsmConstraint(Constraint, VT);
4211void MipsTargetLowering::LowerAsmOperandForConstraint(
SDValue Op,
4213 std::vector<SDValue> &Ops,
4219 if (Constraint.
size() > 1)
4222 char ConstraintLetter = Constraint[0];
4223 switch (ConstraintLetter) {
4229 int64_t Val =
C->getSExtValue();
4230 if (isInt<16>(Val)) {
4239 int64_t Val =
C->getZExtValue();
4250 if (isUInt<16>(Val)) {
4259 int64_t Val =
C->getSExtValue();
4260 if ((isInt<32>(Val)) && ((Val & 0xffff) == 0)){
4269 int64_t Val =
C->getSExtValue();
4270 if ((Val >= -65535) && (Val <= -1)) {
4279 int64_t Val =
C->getSExtValue();
4280 if ((isInt<15>(Val))) {
4289 int64_t Val =
C->getSExtValue();
4290 if ((Val <= 65535) && (Val >= 1)) {
4299 Ops.push_back(Result);
4306bool MipsTargetLowering::isLegalAddressingMode(
const DataLayout &
DL,
4334EVT MipsTargetLowering::getOptimalMemOpType(
4342bool MipsTargetLowering::isFPImmLegal(
const APFloat &Imm,
EVT VT,
4343 bool ForCodeSize)
const {
4344 if (VT != MVT::f32 && VT != MVT::f64)
4346 if (
Imm.isNegZero())
4348 return Imm.isZero();
4351unsigned MipsTargetLowering::getJumpTableEncoding()
const {
4360bool MipsTargetLowering::useSoftFloat()
const {
4364void MipsTargetLowering::copyByValRegs(
4368 unsigned FirstReg,
unsigned LastReg,
const CCValAssign &VA,
4373 unsigned NumRegs = LastReg - FirstReg;
4374 unsigned RegAreaSize = NumRegs * GPRSizeInBytes;
4375 unsigned FrameObjSize = std::max(
Flags.getByValSize(), RegAreaSize);
4382 (
int)((ByValArgRegs.
size() - FirstReg) * GPRSizeInBytes);
4404 for (
unsigned I = 0;
I < NumRegs; ++
I) {
4405 unsigned ArgReg = ByValArgRegs[FirstReg +
I];
4406 unsigned VReg =
addLiveIn(MF, ArgReg, RC);
4407 unsigned Offset =
I * GPRSizeInBytes;
4412 OutChains.push_back(Store);
4417void MipsTargetLowering::passByValArg(
4419 std::deque<std::pair<unsigned, SDValue>> &RegsToPass,
4424 unsigned ByValSizeInBytes =
Flags.getByValSize();
4425 unsigned OffsetInBytes = 0;
4428 std::min(
Flags.getNonZeroByValAlign(),
Align(RegSizeInBytes));
4431 unsigned NumRegs = LastReg - FirstReg;
4435 bool LeftoverBytes = (NumRegs * RegSizeInBytes > ByValSizeInBytes);
4439 for (;
I < NumRegs - LeftoverBytes; ++
I, OffsetInBytes += RegSizeInBytes) {
4445 unsigned ArgReg = ArgRegs[FirstReg +
I];
4446 RegsToPass.push_back(std::make_pair(ArgReg, LoadVal));
4450 if (ByValSizeInBytes == OffsetInBytes)
4454 if (LeftoverBytes) {
4457 for (
unsigned LoadSizeInBytes = RegSizeInBytes / 2, TotalBytesLoaded = 0;
4458 OffsetInBytes < ByValSizeInBytes; LoadSizeInBytes /= 2) {
4459 unsigned RemainingSizeInBytes = ByValSizeInBytes - OffsetInBytes;
4461 if (RemainingSizeInBytes < LoadSizeInBytes)
4477 Shamt = TotalBytesLoaded * 8;
4479 Shamt = (RegSizeInBytes - (TotalBytesLoaded + LoadSizeInBytes)) * 8;
4489 OffsetInBytes += LoadSizeInBytes;
4490 TotalBytesLoaded += LoadSizeInBytes;
4491 Alignment = std::min(Alignment,
Align(LoadSizeInBytes));
4494 unsigned ArgReg = ArgRegs[FirstReg +
I];
4495 RegsToPass.push_back(std::make_pair(ArgReg, Val));
4501 unsigned MemCpySize = ByValSizeInBytes - OffsetInBytes;
4508 Align(Alignment),
false,
false,
4513void MipsTargetLowering::writeVarArgRegs(std::vector<SDValue> &OutChains,
4534 (
int)(RegSizeInBytes * (ArgRegs.
size() -
Idx));
4546 for (
unsigned I =
Idx;
I < ArgRegs.
size();
4547 ++
I, VaArgOffset += RegSizeInBytes) {
4554 cast<StoreSDNode>(
Store.getNode())->getMemOperand()->setValue(
4556 OutChains.push_back(Store);
4561 Align Alignment)
const {
4564 assert(
Size &&
"Byval argument's size shouldn't be 0.");
4568 unsigned FirstReg = 0;
4569 unsigned NumRegs = 0;
4581 Alignment >=
Align(RegSizeInBytes) &&
4582 "Byval argument's alignment should be a multiple of RegSizeInBytes.");
4590 if ((Alignment > RegSizeInBytes) && (FirstReg % 2)) {
4591 State->
AllocateReg(IntArgRegs[FirstReg], ShadowRegs[FirstReg]);
4597 for (
unsigned I = FirstReg;
Size > 0 && (
I < IntArgRegs.
size());
4598 Size -= RegSizeInBytes, ++
I, ++NumRegs)
4608 unsigned Opc)
const {
4610 "Subtarget already supports SELECT nodes with the use of"
4611 "conditional-move instructions.");
4634 F->insert(It, copy0MBB);
4635 F->insert(It, sinkMBB);
4678 MI.eraseFromParent();
4687 "Subtarget already supports SELECT nodes with the use of"
4688 "conditional-move instructions.");
4711 F->insert(It, copy0MBB);
4712 F->insert(It, sinkMBB);
4754 MI.eraseFromParent();
4767 .
Case(
"$28", Mips::GP_64)
4768 .
Case(
"sp", Mips::SP_64)
4774 .
Case(
"$28", Mips::GP)
4775 .
Case(
"sp", Mips::SP)
4793 unsigned Imm =
MI.getOperand(2).getImm();
4799 Register Temp =
MRI.createVirtualRegister(&Mips::GPR32RegClass);
4808 Register LoadHalf =
MRI.createVirtualRegister(&Mips::GPR32RegClass);
4809 Register LoadFull =
MRI.createVirtualRegister(&Mips::GPR32RegClass);
4810 Register Undef =
MRI.createVirtualRegister(&Mips::GPR32RegClass);
4815 .
addImm(Imm + (IsLittle ? 0 : 3))
4820 .
addImm(Imm + (IsLittle ? 3 : 0))
4825 MI.eraseFromParent();
4839 unsigned Imm =
MI.getOperand(2).getImm();
4846 Register Temp =
MRI.createVirtualRegister(&Mips::GPR64RegClass);
4853 Register Wtemp =
MRI.createVirtualRegister(&Mips::MSA128WRegClass);
4854 Register Lo =
MRI.createVirtualRegister(&Mips::GPR32RegClass);
4855 Register Hi =
MRI.createVirtualRegister(&Mips::GPR32RegClass);
4859 .
addImm(Imm + (IsLittle ? 0 : 4));
4863 .
addImm(Imm + (IsLittle ? 4 : 0));
4873 Register LoHalf =
MRI.createVirtualRegister(&Mips::GPR32RegClass);
4874 Register LoFull =
MRI.createVirtualRegister(&Mips::GPR32RegClass);
4875 Register LoUndef =
MRI.createVirtualRegister(&Mips::GPR32RegClass);
4876 Register HiHalf =
MRI.createVirtualRegister(&Mips::GPR32RegClass);
4877 Register HiFull =
MRI.createVirtualRegister(&Mips::GPR32RegClass);
4878 Register HiUndef =
MRI.createVirtualRegister(&Mips::GPR32RegClass);
4879 Register Wtemp =
MRI.createVirtualRegister(&Mips::MSA128WRegClass);
4884 .
addImm(Imm + (IsLittle ? 0 : 7))
4889 .
addImm(Imm + (IsLittle ? 3 : 4))
4895 .
addImm(Imm + (IsLittle ? 4 : 3))
4900 .
addImm(Imm + (IsLittle ? 7 : 0))
4909 MI.eraseFromParent();
4921 Register StoreVal =
MI.getOperand(0).getReg();
4923 unsigned Imm =
MI.getOperand(2).getImm();
4929 Register BitcastW =
MRI.createVirtualRegister(&Mips::MSA128WRegClass);
4930 Register Tmp =
MRI.createVirtualRegister(&Mips::GPR32RegClass);
4943 Register Tmp =
MRI.createVirtualRegister(&Mips::GPR32RegClass);
4951 .
addImm(Imm + (IsLittle ? 0 : 3));
4955 .
addImm(Imm + (IsLittle ? 3 : 0));
4958 MI.eraseFromParent();
4971 Register StoreVal =
MI.getOperand(0).getReg();
4973 unsigned Imm =
MI.getOperand(2).getImm();
4980 Register BitcastD =
MRI.createVirtualRegister(&Mips::MSA128DRegClass);
4981 Register Lo =
MRI.createVirtualRegister(&Mips::GPR64RegClass);
4994 Register BitcastW =
MRI.createVirtualRegister(&Mips::MSA128WRegClass);
4995 Register Lo =
MRI.createVirtualRegister(&Mips::GPR32RegClass);
4996 Register Hi =
MRI.createVirtualRegister(&Mips::GPR32RegClass);
5011 .
addImm(Imm + (IsLittle ? 0 : 4));
5015 .
addImm(Imm + (IsLittle ? 4 : 0));
5021 Register Lo =
MRI.createVirtualRegister(&Mips::GPR32RegClass);
5022 Register Hi =
MRI.createVirtualRegister(&Mips::GPR32RegClass);
5035 .
addImm(Imm + (IsLittle ? 0 : 3));
5039 .
addImm(Imm + (IsLittle ? 3 : 0));
5043 .
addImm(Imm + (IsLittle ? 4 : 7));
5047 .
addImm(Imm + (IsLittle ? 7 : 4));
5050 MI.eraseFromParent();
unsigned const MachineRegisterInfo * MRI
static SDValue performORCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const AArch64Subtarget *Subtarget, const AArch64TargetLowering &TLI)
static SDValue performANDCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
This file declares a class to represent arbitrary precision floating point values and provide a varie...
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Function Alias Analysis Results
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
#define LLVM_ATTRIBUTE_UNUSED
This file contains the declarations for the subclasses of Constant, which represent the different fla...
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
const HexagonInstrInfo * TII
static MachineBasicBlock * insertDivByZeroTrap(MachineInstr &MI, MachineBasicBlock *MBB)
unsigned const TargetRegisterInfo * TRI
cl::opt< bool > EmitJalrReloc
static bool CC_MipsO32_FP64(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
static bool CC_Mips(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State) LLVM_ATTRIBUTE_UNUSED
static bool CC_MipsO32_FP32(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
static bool CC_MipsO32(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State, ArrayRef< MCPhysReg > F64Regs)
static SDValue performMADD_MSUBCombine(SDNode *ROOTNode, SelectionDAG &CurDAG, const MipsSubtarget &Subtarget)
static bool invertFPCondCodeUser(Mips::CondCode CC)
This function returns true if the floating point conditional branches and conditional moves which use...
static SDValue lowerFP_TO_SINT_STORE(StoreSDNode *SD, SelectionDAG &DAG, bool SingleFloat)
static SDValue performDivRemCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget)
static const MCPhysReg Mips64DPRegs[8]
static SDValue performSHLCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget)
static SDValue lowerUnalignedIntStore(StoreSDNode *SD, SelectionDAG &DAG, bool IsLittle)
static SDValue createStoreLR(unsigned Opc, SelectionDAG &DAG, StoreSDNode *SD, SDValue Chain, unsigned Offset)
static unsigned addLiveIn(MachineFunction &MF, unsigned PReg, const TargetRegisterClass *RC)
static std::pair< bool, bool > parsePhysicalReg(StringRef C, StringRef &Prefix, unsigned long long &Reg)
This is a helper function to parse a physical register string and split it into non-numeric and numer...
static SDValue createLoadLR(unsigned Opc, SelectionDAG &DAG, LoadSDNode *LD, SDValue Chain, SDValue Src, unsigned Offset)
static SDValue lowerFCOPYSIGN64(SDValue Op, SelectionDAG &DAG, bool HasExtractInsert)
static SDValue performADDCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget)
cl::opt< bool > EmitJalrReloc
static SDValue performSUBCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget)
static SDValue createFPCmp(SelectionDAG &DAG, const SDValue &Op)
static SDValue lowerFCOPYSIGN32(SDValue Op, SelectionDAG &DAG, bool HasExtractInsert)
static cl::opt< bool > NoZeroDivCheck("mno-check-zero-division", cl::Hidden, cl::desc("MIPS: Don't trap on integer division by zero."), cl::init(false))
static SDValue performSELECTCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget)
static SDValue performCMovFPCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget)
static SDValue UnpackFromArgumentSlot(SDValue Val, const CCValAssign &VA, EVT ArgVT, const SDLoc &DL, SelectionDAG &DAG)
static Mips::CondCode condCodeToFCC(ISD::CondCode CC)
static SDValue createCMovFP(SelectionDAG &DAG, SDValue Cond, SDValue True, SDValue False, const SDLoc &DL)
Module.h This file contains the declarations for the Module class.
uint64_t IntrinsicInst * II
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
const char LLVMTargetMachineRef TM
const SmallVectorImpl< MachineOperand > & Cond
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
SI optimize exec mask operations pre RA
This file defines the SmallVector class.
static const MCPhysReg IntRegs[32]
This file defines the 'Statistic' class, which is designed to be an easy way to expose various metric...
#define STATISTIC(VARNAME, DESC)
This file implements the StringSwitch template, which mimics a switch() statement whose cases are str...
static const MCPhysReg F32Regs[64]
static bool contains(SmallPtrSetImpl< ConstantExpr * > &Cache, ConstantExpr *Expr, Constant *C)
This class represents an incoming formal argument to a Function.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
size_t size() const
size - Get the array size.
LLVM Basic Block Representation.
static BranchProbability getOne()
CCState - This class holds information needed while lowering arguments and return values.
MachineFunction & getMachineFunction() const
unsigned getFirstUnallocated(ArrayRef< MCPhysReg > Regs) const
getFirstUnallocated - Return the index of the first unallocated register in the set,...
CallingConv::ID getCallingConv() const
MCRegister AllocateReg(MCPhysReg Reg)
AllocateReg - Attempt to allocate one register.
int64_t AllocateStack(unsigned Size, Align Alignment)
AllocateStack - Allocate a chunk of stack space with the specified size and alignment.
uint64_t getStackSize() const
Returns the size of the currently allocated portion of the stack.
void addInRegsParamInfo(unsigned RegBegin, unsigned RegEnd)
void addLoc(const CCValAssign &V)
CCValAssign - Represent assignment of one arg/retval to a location.
Register getLocReg() const
LocInfo getLocInfo() const
bool isUpperBitsInLoc() const
static CCValAssign getMem(unsigned ValNo, MVT ValVT, int64_t Offset, MVT LocVT, LocInfo HTP, bool IsCustom=false)
static CCValAssign getReg(unsigned ValNo, MVT ValVT, unsigned RegNo, MVT LocVT, LocInfo HTP, bool IsCustom=false)
static CCValAssign getCustomReg(unsigned ValNo, MVT ValVT, unsigned RegNo, MVT LocVT, LocInfo HTP)
int64_t getLocMemOffset() const
bool isMustTailCall() const
Tests if this call site must be tail call optimized.
uint64_t getZExtValue() const
int64_t getSExtValue() const
This class represents an Operation in the Expression.
A parsed version of the target data layout string in and methods for querying it.
TypeSize getTypeAllocSize(Type *Ty) const
Returns the offset in bytes between successive objects of the specified type, including alignment pad...
const char * getSymbol() const
This is a fast-path instruction selection class that generates poor code and doesn't support illegal ...
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
bool hasStructRetAttr() const
Determine if the function returns a structure through first or second pointer argument.
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
const GlobalValue * getGlobal() const
bool hasLocalLinkage() const
const GlobalObject * getAliaseeObject() const
bool hasInternalLinkage() const
Class to represent integer types.
This is an important class for using LLVM in a threaded context.
void emitError(uint64_t LocCookie, const Twine &ErrorStr)
emitError - Emit an error message to the currently installed error handler with optional location inf...
This class is used to represent ISD::LOAD nodes.
MCSymbol * getOrCreateSymbol(const Twine &Name)
Lookup the symbol inside with the specified Name.
Wrapper class representing physical registers. Should be passed by value.
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
static auto integer_valuetypes()
TypeSize getSizeInBits() const
Returns the size of the specified MVT in bits.
TypeSize getStoreSize() const
Return the number of bytes overwritten by a store of the specified value type.
static MVT getVectorVT(MVT VT, unsigned NumElements)
bool isFloatingPoint() const
Return true if this is a FP or a vector FP type.
bool isValid() const
Return true if this is a valid simple valuetype.
static MVT getIntegerVT(unsigned BitWidth)
static auto fp_valuetypes()
static auto fp_fixedlen_vector_valuetypes()
void transferSuccessorsAndUpdatePHIs(MachineBasicBlock *FromMBB)
Transfers all the successors, as in transferSuccessors, and update PHI operands in the successor bloc...
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool IsImmutable, bool isAliased=false)
Create a new object at a fixed location on the stack.
void setFrameAddressIsTaken(bool T)
void setHasTailCall(bool V=true)
void setReturnAddressIsTaken(bool s)
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
MCContext & getContext() const
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
Function & getFunction()
Return the LLVM function that this machine code represents.
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Register addLiveIn(MCRegister PReg, const TargetRegisterClass *RC)
addLiveIn - Add the specified physical register as a live-in value and create a corresponding virtual...
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *BB=nullptr, std::optional< UniqueBBID > BBID=std::nullopt)
CreateMachineBasicBlock - Allocate a new MachineBasicBlock.
void insert(iterator MBBI, MachineBasicBlock *MBB)
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
const MachineInstrBuilder & addUse(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register use operand.
const MachineInstrBuilder & addDef(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register definition operand.
Representation of each machine instruction.
const MachineOperand & getOperand(unsigned i) const
@ EK_GPRel64BlockAddress
EK_GPRel64BlockAddress - Each entry is an address of block, encoded with a relocation as gp-relative,...
@ MOVolatile
The memory access is volatile.
Flags getFlags() const
Return the raw flags of the source value,.
MachineOperand class - Representation of each machine instruction operand.
void setSubReg(unsigned subReg)
static MachineOperand CreateMCSymbol(MCSymbol *Sym, unsigned TargetFlags=0)
void setIsKill(bool Val=true)
Register getReg() const
getReg - Returns the register number.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
void addLiveIn(MCRegister Reg, Register vreg=Register())
addLiveIn - Add the specified register as a live-in.
MachineMemOperand * getMemOperand() const
Return a MachineMemOperand object describing the memory reference performed by operation.
const MachinePointerInfo & getPointerInfo() const
const SDValue & getChain() const
EVT getMemoryVT() const
Return the type of the in-memory value.
ArrayRef< MCPhysReg > GetVarArgRegs() const
The registers to use for the variable argument list.
bool ArePtrs64bit() const
unsigned GetCalleeAllocdArgSizeInBytes(CallingConv::ID CC) const
Obtain the size of the area allocated by the callee for arguments.
unsigned GetPtrAddiuOp() const
unsigned GetPtrAndOp() const
ArrayRef< MCPhysReg > GetByValArgRegs() const
The registers to use for byval arguments.
unsigned GetNullPtr() const
bool WasOriginalArgVectorFloat(unsigned ValNo) const
static SpecialCallingConvType getSpecialCallingConvForCallee(const SDNode *Callee, const MipsSubtarget &Subtarget)
Determine the SpecialCallingConvType for the given callee.
MipsFunctionInfo - This class is derived from MachineFunction private Mips target-specific informatio...
void setVarArgsFrameIndex(int Index)
unsigned getSRetReturnReg() const
int getVarArgsFrameIndex() const
MachinePointerInfo callPtrInfo(MachineFunction &MF, const char *ES)
Create a MachinePointerInfo that has an ExternalSymbolPseudoSourceValue object representing a GOT ent...
Register getGlobalBaseReg(MachineFunction &MF)
void setSRetReturnReg(unsigned Reg)
void setFormalArgInfo(unsigned Size, bool HasByval)
static const uint32_t * getMips16RetHelperMask()
bool inMicroMipsMode() const
bool useSoftFloat() const
const MipsInstrInfo * getInstrInfo() const override
bool inMips16Mode() const
bool inAbs2008Mode() const
const MipsRegisterInfo * getRegisterInfo() const override
bool systemSupportsUnalignedAccess() const
Does the system support unaligned memory access.
bool hasExtractInsert() const
Features related to the presence of specific instructions.
bool isSingleFloat() const
bool useLongCalls() const
unsigned getGPRSizeInBytes() const
bool inMips16HardFloat() const
const TargetFrameLowering * getFrameLowering() const override
MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const override
Return the register type for a given MVT, ensuring vectors are treated as a series of gpr sized integ...
bool hasBitTest(SDValue X, SDValue Y) const override
Return true if the target has a bit-test instruction: (X & (1 << Y)) ==/!= 0 This knowledge can be us...
static const MipsTargetLowering * create(const MipsTargetMachine &TM, const MipsSubtarget &STI)
SDValue getAddrGPRel(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG, bool IsN64) const
unsigned getVectorTypeBreakdownForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const override
Break down vectors to the correct number of gpr sized integers.
Register getRegisterByName(const char *RegName, LLT VT, const MachineFunction &MF) const override
Return the register ID of the name passed in.
const char * getTargetNodeName(unsigned Opcode) const override
getTargetNodeName - This method returns the name of a target specific
SDValue getAddrNonPICSym64(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG) const
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override
getSetCCResultType - get the ISD::SETCC result ValueType
SDValue getAddrGlobal(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG, unsigned Flag, SDValue Chain, const MachinePointerInfo &PtrInfo) const
FastISel * createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo) const override
createFastISel - This method returns a target specific FastISel object, or null if the target does no...
MipsTargetLowering(const MipsTargetMachine &TM, const MipsSubtarget &STI)
SDValue getAddrGlobalLargeGOT(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG, unsigned HiFlag, unsigned LoFlag, SDValue Chain, const MachinePointerInfo &PtrInfo) const
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
CCAssignFn * CCAssignFnForReturn() const
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
ReplaceNodeResults - Replace the results of node with an illegal result type with new values built ou...
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
CCAssignFn * CCAssignFnForCall() const
unsigned getNumRegistersForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const override
Return the number of registers for a given MVT, ensuring vectors are treated as a series of gpr sized...
SDValue getAddrNonPIC(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG) const
SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const
void AdjustInstrPostInstrSelection(MachineInstr &MI, SDNode *Node) const override
This method should be implemented by targets that mark instructions with the 'hasPostISelHook' flag.
virtual void getOpndList(SmallVectorImpl< SDValue > &Ops, std::deque< std::pair< unsigned, SDValue > > &RegsToPass, bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage, bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const
This function fills Ops, which is the list of operands that will later be used when a function call n...
EVT getTypeForExtReturn(LLVMContext &Context, EVT VT, ISD::NodeType) const override
Return the type that should be used to zero or sign extend a zeroext/signext integer return value.
bool isCheapToSpeculateCtlz(Type *Ty) const override
Return true if it is cheap to speculate a call to intrinsic ctlz.
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
LowerOperation - Provide custom lowering hooks for some operations.
bool isCheapToSpeculateCttz(Type *Ty) const override
Return true if it is cheap to speculate a call to intrinsic cttz.
bool shouldFoldConstantShiftPairToMask(const SDNode *N, CombineLevel Level) const override
Return true if it is profitable to fold a pair of shifts into a mask.
SDValue getAddrLocal(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG, bool IsN32OrN64) const
SDValue getGlobalReg(SelectionDAG &DAG, EVT Ty) const
const MipsSubtarget & Subtarget
void HandleByVal(CCState *, unsigned &, Align) const override
Target-specific cleanup for formal ByVal parameters.
SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const
bool IsConstantInSmallSection(const DataLayout &DL, const Constant *CN, const TargetMachine &TM) const
Return true if this constant should be placed into small data section.
Wrapper class representing virtual and physical registers.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
uint64_t getAsZExtVal() const
Helper method returns the zero-extended integer value of a ConstantSDNode.
const SDValue & getOperand(unsigned Num) const
EVT getValueType(unsigned ResNo) const
Return the type of a specified result.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
SDNode * getNode() const
get the SDNode which holds the desired result
SDValue getValue(unsigned R) const
EVT getValueType() const
Return the ValueType of the referenced return value.
TypeSize getValueSizeInBits() const
Returns the size of the value in bits.
const SDValue & getOperand(unsigned i) const
unsigned getOpcode() const
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
SDValue getExtLoad(ISD::LoadExtType ExtType, const SDLoc &dl, EVT VT, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, EVT MemVT, MaybeAlign Alignment=MaybeAlign(), MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
SDValue getTargetGlobalAddress(const GlobalValue *GV, const SDLoc &DL, EVT VT, int64_t offset=0, unsigned TargetFlags=0)
SDValue getMergeValues(ArrayRef< SDValue > Ops, const SDLoc &dl)
Create a MERGE_VALUES node from the given operands.
SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
SDValue getMemcpy(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, Align Alignment, bool isVol, bool AlwaysInline, const CallInst *CI, std::optional< bool > OverrideTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo, const AAMDNodes &AAInfo=AAMDNodes(), AAResults *AA=nullptr)
SDValue getSetCC(const SDLoc &DL, EVT VT, SDValue LHS, SDValue RHS, ISD::CondCode Cond, SDValue Chain=SDValue(), bool IsSignaling=false)
Helper function to make it easier to build SetCC's if you just have an ISD::CondCode instead of an SD...
SDValue getLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, MaybeAlign Alignment=MaybeAlign(), MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
Loads are not normal binary operators: their result type is not determined by their operands,...
SDValue getTargetJumpTable(int JTI, EVT VT, unsigned TargetFlags=0)
SDValue getUNDEF(EVT VT)
Return an UNDEF node. UNDEF does not have a useful SDLoc.
SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2, SDValue InGlue, const SDLoc &DL)
Return a new CALLSEQ_END node, which always must have a glue result (to ensure it's not CSE'd).
const DataLayout & getDataLayout() const
SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
Create a ConstantSDNode wrapping a constant value.
SDValue getStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, Align Alignment, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
Helper function to build ISD::STORE nodes.
SDValue getCALLSEQ_START(SDValue Chain, uint64_t InSize, uint64_t OutSize, const SDLoc &DL)
Return a new CALLSEQ_START node, that starts new call frame, in which InSize bytes are set up inside ...
SDValue getRegister(unsigned Reg, EVT VT)
SDValue getExternalSymbol(const char *Sym, EVT VT)
const TargetMachine & getTarget() const
SDValue getCopyToReg(SDValue Chain, const SDLoc &dl, unsigned Reg, SDValue N)
SDValue getIntPtrConstant(uint64_t Val, const SDLoc &DL, bool isTarget=false)
SDValue getValueType(EVT)
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
SDValue getTargetConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isOpaque=false)
SDValue getTargetBlockAddress(const BlockAddress *BA, EVT VT, int64_t Offset=0, unsigned TargetFlags=0)
void ReplaceAllUsesOfValueWith(SDValue From, SDValue To)
Replace any uses of From with To, leaving uses of other values produced by From.getNode() alone.
MachineFunction & getMachineFunction() const
SDValue getCopyFromReg(SDValue Chain, const SDLoc &dl, unsigned Reg, EVT VT)
SDValue getFrameIndex(int FI, EVT VT, bool isTarget=false)
SDValue getRegisterMask(const uint32_t *RegMask)
void addCallSiteInfo(const SDNode *Node, CallSiteInfo &&CallInfo)
Set CallSiteInfo to be associated with Node.
LLVMContext * getContext() const
SDValue getMemIntrinsicNode(unsigned Opcode, const SDLoc &dl, SDVTList VTList, ArrayRef< SDValue > Ops, EVT MemVT, MachinePointerInfo PtrInfo, Align Alignment, MachineMemOperand::Flags Flags=MachineMemOperand::MOLoad|MachineMemOperand::MOStore, LocationSize Size=0, const AAMDNodes &AAInfo=AAMDNodes())
Creates a MemIntrinsicNode that may produce a result and takes a list of operands.
SDValue getTargetExternalSymbol(const char *Sym, EVT VT, unsigned TargetFlags=0)
SDValue getTargetConstantPool(const Constant *C, EVT VT, MaybeAlign Align=std::nullopt, int Offset=0, unsigned TargetFlags=0)
SDValue getEntryNode() const
Return the token chain corresponding to the entry of the function.
std::pair< SDValue, SDValue > SplitScalar(const SDValue &N, const SDLoc &DL, const EVT &LoVT, const EVT &HiVT)
Split the scalar node with EXTRACT_ELEMENT using the provided VTs and return the low/high part.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
This class is used to represent ISD::STORE nodes.
const SDValue & getBasePtr() const
const SDValue & getValue() const
bool isTruncatingStore() const
Return true if the op does a truncation before store.
StringRef - Represent a constant reference to a string, i.e.
constexpr bool empty() const
empty - Check if the string is empty.
constexpr size_t size() const
size - Get the string size.
A switch()-like statement whose cases are string literals.
StringSwitch & Case(StringLiteral S, T Value)
Information about stack frame layout on the target.
unsigned getStackAlignment() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
Align getStackAlign() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
TargetInstrInfo - Interface to description of machine instruction set.
Provides information about what library functions are available for the current target.
void setBooleanVectorContents(BooleanContent Ty)
Specify how the target extends the result of a vector boolean value from a vector of i1 to a wider ty...
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
Indicate that the specified operation does not work with the specified type and indicate what to do a...
virtual const TargetRegisterClass * getRegClassFor(MVT VT, bool isDivergent=false) const
Return the register class that should be used for the specified value type.
void setMinStackArgumentAlignment(Align Alignment)
Set the minimum stack alignment of an argument.
const TargetMachine & getTargetMachine() const
virtual unsigned getNumRegisters(LLVMContext &Context, EVT VT, std::optional< MVT > RegisterVT=std::nullopt) const
Return the number of registers that this ValueType will eventually require.
void setMaxAtomicSizeInBitsSupported(unsigned SizeInBits)
Set the maximum atomic operation size supported by the backend.
void setMinFunctionAlignment(Align Alignment)
Set the target's minimum function alignment.
void setBooleanContents(BooleanContent Ty)
Specify how the target extends the result of integer and floating point boolean values from i1 to a w...
virtual MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
void setTruncStoreAction(MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified truncating store does not work with the specified type and indicate what ...
@ ZeroOrOneBooleanContent
@ ZeroOrNegativeOneBooleanContent
void setStackPointerRegisterToSaveRestore(Register R)
If set to a physical register, this specifies the register that llvm.savestack/llvm....
void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT)
If Opc/OrigVT is specified as being promoted, the promotion code defaults to trying a larger integer/...
void setTargetDAGCombine(ArrayRef< ISD::NodeType > NTs)
Targets should invoke this method for each target independent node that they want to provide a custom...
Align getMinStackArgumentAlignment() const
Return the minimum stack alignment of an argument.
void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified load with extension does not work with the specified type and indicate wh...
std::vector< ArgListEntry > ArgListTy
unsigned MaxStoresPerMemcpy
Specify maximum number of store instructions per memcpy call.
MVT getRegisterType(MVT VT) const
Return the type of registers that this ValueType will eventually require.
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
virtual ConstraintType getConstraintType(StringRef Constraint) const
Given a constraint, return the type of constraint it is for this target.
virtual SDValue LowerToTLSEmulatedModel(const GlobalAddressSDNode *GA, SelectionDAG &DAG) const
Lower TLS global address SDNode for target independent emulated TLS model.
std::pair< SDValue, SDValue > LowerCallTo(CallLoweringInfo &CLI) const
This function lowers an abstract call to a function into an actual call.
bool isPositionIndependent() const
virtual ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &info, const char *constraint) const
Examine constraint string and operand type and determine a weight value.
virtual std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const
Given a physical register constraint (e.g.
bool verifyReturnAddressArgumentIsConstant(SDValue Op, SelectionDAG &DAG) const
virtual void LowerAsmOperandForConstraint(SDValue Op, StringRef Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const
Lower the specified operand into the Ops vector.
virtual unsigned getJumpTableEncoding() const
Return the entry encoding for a jump table in the current function.
virtual void LowerOperationWrapper(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const
This callback is invoked by the type legalizer to legalize nodes with an illegal operand type but leg...
TLSModel::Model getTLSModel(const GlobalValue *GV) const
Returns the TLS model which should be used for the given global variable.
bool useEmulatedTLS() const
Returns true if this target uses emulated TLS.
virtual TargetLoweringObjectFile * getObjFileLowering() const
unsigned NoNaNsFPMath
NoNaNsFPMath - This flag is enabled when the -enable-no-nans-fp-math flag is specified on the command...
iterator begin() const
begin/end - Return all of the registers in this class.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
The instances of the Type class are immutable: once they are created, they are never changed.
bool isVectorTy() const
True if this is an instance of VectorType.
bool isFloatTy() const
Return true if this is 'float', a 32-bit IEEE fp type.
static IntegerType * getIntNTy(LLVMContext &C, unsigned N)
bool isIntegerTy() const
True if this is an instance of IntegerType.
TypeSize getPrimitiveSizeInBits() const LLVM_READONLY
Return the basic size of this type if it is a primitive type.
LLVM Value Representation.
Type * getType() const
All values are typed, get the type of this value.
constexpr ScalarTy getFixedValue() const
self_iterator getIterator()
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
constexpr char Args[]
Key for Kernel::Metadata::mArgs.
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
@ Fast
Attempts to make calls as fast as possible (e.g.
@ C
The default llvm calling convention, compatible with C.
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
@ SETCC
SetCC operator - This evaluates to a true value iff the condition is true.
@ STACKRESTORE
STACKRESTORE has two operands, an input chain and a pointer to restore to it returns an output chain.
@ STACKSAVE
STACKSAVE - STACKSAVE has one operand, an input chain.
@ BSWAP
Byte Swap and Counting operators.
@ VAEND
VAEND, VASTART - VAEND and VASTART have three operands: an input chain, pointer, and a SRCVALUE.
@ ATOMIC_STORE
OUTCHAIN = ATOMIC_STORE(INCHAIN, ptr, val) This corresponds to "store atomic" instruction.
@ ADD
Simple integer binary arithmetic operators.
@ LOAD
LOAD and STORE have token chains as their first operand, then the same operands as an LLVM load/store...
@ ANY_EXTEND
ANY_EXTEND - Used for integer types. The high bits are undefined.
@ FMA
FMA - Perform a * b + c with no intermediate rounding step.
@ ATOMIC_FENCE
OUTCHAIN = ATOMIC_FENCE(INCHAIN, ordering, scope) This corresponds to the fence instruction.
@ SDIVREM
SDIVREM/UDIVREM - Divide two integers and produce both a quotient and remainder result.
@ FP16_TO_FP
FP16_TO_FP, FP_TO_FP16 - These operators are used to perform promotions and truncation for half-preci...
@ BITCAST
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
@ BUILD_PAIR
BUILD_PAIR - This is the opposite of EXTRACT_ELEMENT in some ways.
@ EH_RETURN
OUTCHAIN = EH_RETURN(INCHAIN, OFFSET, HANDLER) - This node represents 'eh_return' gcc dwarf builtin,...
@ SIGN_EXTEND
Conversion operators.
@ FSINCOS
FSINCOS - Compute both fsin and fcos as a single operation.
@ BR_CC
BR_CC - Conditional branch.
@ BR_JT
BR_JT - Jumptable branch.
@ SELECT
Select(COND, TRUEVAL, FALSEVAL).
@ ATOMIC_LOAD
Val, OUTCHAIN = ATOMIC_LOAD(INCHAIN, ptr) This corresponds to "load atomic" instruction.
@ VACOPY
VACOPY - VACOPY has 5 operands: an input chain, a destination pointer, a source pointer,...
@ SHL
Shift and rotation operations.
@ FMINNUM_IEEE
FMINNUM_IEEE/FMAXNUM_IEEE - Perform floating-point minimumNumber or maximumNumber on two values,...
@ ZERO_EXTEND
ZERO_EXTEND - Used for integer types, zeroing the new bits.
@ SELECT_CC
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
@ FMINNUM
FMINNUM/FMAXNUM - Perform floating-point minimum or maximum on two values.
@ DYNAMIC_STACKALLOC
DYNAMIC_STACKALLOC - Allocate some number of bytes on the stack aligned to a specified boundary.
@ SIGN_EXTEND_INREG
SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to sign extend a small value in ...
@ EH_DWARF_CFA
EH_DWARF_CFA - This node represents the pointer to the DWARF Canonical Frame Address (CFA),...
@ FRAMEADDR
FRAMEADDR, RETURNADDR - These nodes represent llvm.frameaddress and llvm.returnaddress on the DAG.
@ FP_TO_SINT
FP_TO_[US]INT - Convert a floating point value to a signed or unsigned integer.
@ AND
Bitwise operators - logical and, logical or, logical xor.
@ TRAP
TRAP - Trapping instruction.
@ TokenFactor
TokenFactor - This node takes multiple tokens as input and produces a single token result.
@ TRUNCATE
TRUNCATE - Completely drop the high bits.
@ VAARG
VAARG - VAARG has four operands: an input chain, a pointer, a SRCVALUE, and the alignment.
@ BRCOND
BRCOND - Conditional branch.
@ SHL_PARTS
SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded integer shift operations.
@ AssertSext
AssertSext, AssertZext - These nodes record if a register contains a value that has already been zero...
@ FCOPYSIGN
FCOPYSIGN(X, Y) - Return the value of X with the sign of Y.
@ CALLSEQ_START
CALLSEQ_START/CALLSEQ_END - These operators mark the beginning and end of a call sequence,...
CondCode getSetCCInverse(CondCode Operation, EVT Type)
Return the operation corresponding to !(X op Y), where 'op' is a valid SetCC operation.
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...
LoadExtType
LoadExtType enum - This enum defines the three variants of LOADEXT (load with extension).
@ Bitcast
Perform the operation on a different, but equivalently sized type.
Flag
These should be considered private to the implementation of the MCInstrDesc class.
@ MO_GOT_CALL
MO_GOT_CALL - Represents the offset into the global offset table at which the address of a call site ...
@ MO_TPREL_HI
MO_TPREL_HI/LO - Represents the hi and low part of the offset from.
@ MO_GOT
MO_GOT - Represents the offset into the global offset table at which the address the relocation entry...
@ MO_JALR
Helper operand used to generate R_MIPS_JALR.
@ MO_GOTTPREL
MO_GOTTPREL - Represents the offset from the thread pointer (Initial.
@ MO_GOT_HI16
MO_GOT_HI16/LO16, MO_CALL_HI16/LO16 - Relocations used for large GOTs.
@ MO_TLSLDM
MO_TLSLDM - Represents the offset into the global offset table at which.
@ MO_TLSGD
MO_TLSGD - Represents the offset into the global offset table at which.
FastISel * createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo)
@ Implicit
Not emitted register (e.g. carry, or temporary result).
@ Define
Register definition.
@ Kill
The last use of a register.
@ EarlyClobber
Register definition happens before uses.
Not(const Pred &P) -> Not< Pred >
Reg
All possible values of the reg field in the ModR/M byte.
initializer< Ty > init(const Ty &Val)
NodeAddr< FuncNode * > Func
This is an optimization pass for GlobalISel generic memory operations.
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
constexpr bool isShiftedMask_64(uint64_t Value)
Return true if the argument contains a non-empty sequence of ones with the remainder zero (64 bit ver...
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
constexpr T divideCeil(U Numerator, V Denominator)
Returns the integer ceil(Numerator / Denominator).
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change.
const MipsTargetLowering * createMips16TargetLowering(const MipsTargetMachine &TM, const MipsSubtarget &STI)
Create MipsTargetLowering objects.
@ Or
Bitwise or logical OR of integers.
unsigned getKillRegState(bool B)
uint64_t alignTo(uint64_t Size, Align A)
Returns a multiple of A needed to store Size bytes.
DWARFExpression::Operation Op
const MipsTargetLowering * createMipsSETargetLowering(const MipsTargetMachine &TM, const MipsSubtarget &STI)
bool getAsUnsignedInteger(StringRef Str, unsigned Radix, unsigned long long &Result)
Helper functions for StringRef::getAsInteger.
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
This struct is a compact representation of a valid (non-zero power of two) alignment.
uint64_t value() const
This is a hole in the type system and should not be abused.
EVT changeVectorElementTypeToInteger() const
Return a vector with the same number of elements as this vector, but with the element type converted ...
bool bitsLT(EVT VT) const
Return true if this has less bits than VT.
TypeSize getSizeInBits() const
Return the size of the specified value type in bits.
bool isPow2VectorType() const
Returns true if the given vector is a power of 2.
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
static EVT getFloatingPointVT(unsigned BitWidth)
Returns the EVT that represents a floating-point type with the given number of bits.
bool isVector() const
Return true if this is a vector value type.
Type * getTypeForEVT(LLVMContext &Context) const
This method returns an LLVM type corresponding to the specified EVT.
bool isRound() const
Return true if the size is a power-of-two number of bytes.
EVT getVectorElementType() const
Given a vector type, return the type of each element.
unsigned getVectorNumElements() const
Given a vector type, return the number of elements it contains.
bool isInteger() const
Return true if this is an integer or a vector integer type.
Align getNonZeroOrigAlign() const
SmallVector< ArgRegPair, 1 > ArgRegPairs
Vector of call argument and its forwarding register.
This class contains a discriminated union of information about pointers in memory operands,...
static MachinePointerInfo getGOT(MachineFunction &MF)
Return a MachinePointerInfo record that refers to a GOT entry.
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
This struct is a compact representation of a valid (power of two) or undefined (0) alignment.
Align valueOrOne() const
For convenience, returns a valid alignment or 1 if undefined.
This represents a list of ValueType's that has been intern'd by a SelectionDAG.
This structure contains all information that is necessary for lowering calls.
SmallVector< ISD::InputArg, 32 > Ins
SmallVector< ISD::OutputArg, 32 > Outs
SmallVector< SDValue, 32 > OutVals
bool isBeforeLegalizeOps() const
