27#define DEBUG_TYPE "msp430-disassembler"
58 return new MSP430Disassembler(STI, Ctx);
67 MSP430::PCB, MSP430::SPB, MSP430::SRB, MSP430::CGB,
68 MSP430::R4B, MSP430::R5B, MSP430::R6B, MSP430::R7B,
69 MSP430::R8B, MSP430::R9B, MSP430::R10B, MSP430::R11B,
70 MSP430::R12B, MSP430::R13B, MSP430::R14B, MSP430::R15B
85 MSP430::PC, MSP430::SP, MSP430::SR, MSP430::CG,
86 MSP430::R4, MSP430::R5, MSP430::R6, MSP430::R7,
87 MSP430::R8, MSP430::R9, MSP430::R10, MSP430::R11,
88 MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15
109#include "MSP430GenDisassemblerTables.inc"
117 case 0x22: Imm = 4;
break;
118 case 0x32: Imm = 8;
break;
119 case 0x03: Imm = 0;
break;
120 case 0x13: Imm = 1;
break;
121 case 0x23: Imm = 2;
break;
122 case 0x33: Imm = -1;
break;
131 unsigned Reg = Bits & 15;
132 unsigned Imm = Bits >> 4;
182 unsigned Rs = fieldFromInstruction(
Insn, 8, 4);
183 unsigned As = fieldFromInstruction(
Insn, 4, 2);
188 unsigned Rs = fieldFromInstruction(
Insn, 0, 4);
189 unsigned As = fieldFromInstruction(
Insn, 4, 2);
194 unsigned Rd = fieldFromInstruction(
Insn, 0, 4);
195 unsigned Ad = fieldFromInstruction(
Insn, 7, 1);
206 assert(0 < Words && Words < 4 &&
"Incorrect number of words");
211 assert(Words < 3 &&
"Incorrect number of words");
212 return Words == 2 ? DecoderTableAlpha32 : DecoderTableAlpha16;
214 assert(Words < 3 &&
"Incorrect number of words");
215 return Words == 2 ? DecoderTableBeta32 : DecoderTableBeta16;
220 assert(Words > 1 &&
"Incorrect number of words");
221 return Words == 2 ? DecoderTableGamma32 : DecoderTableGamma48;
224 assert(Words < 3 &&
"Incorrect number of words");
225 return Words == 2 ? DecoderTableDelta32 : DecoderTableDelta16;
247 if (Bytes.
size() < (Words + 1) * 2) {
249 return DecodeStatus::Fail;
261 if (Bytes.
size() < (Words + 1) * 2) {
263 return DecodeStatus::Fail;
274 Insn, Address,
this, STI);
281 return DecodeStatus::Fail;
301 if (Bytes.
size() < (Words + 1) * 2) {
303 return DecodeStatus::Fail;
312 const uint8_t *DecoderTable = Words == 2 ? DecoderTable32 : DecoderTable16;
321 return DecodeStatus::Fail;
344 unsigned Cond = fieldFromInstruction(
Insn, 10, 3);
345 unsigned Offset = fieldFromInstruction(
Insn, 0, 10);
350 MI.setOpcode(MSP430::JMP);
352 MI.setOpcode(MSP430::JCC);
357 return DecodeStatus::Success;
364 if (Bytes.
size() < 2) {
370 unsigned Opc = fieldFromInstruction(
Insn, 13, 3);
373 return getInstructionII(
MI,
Size, Bytes, Address, CStream);
375 return getInstructionCJ(
MI,
Size, Bytes, Address, CStream);
377 return getInstructionI(
MI,
Size, Bytes, Address, CStream);
SmallVector< AArch64_IMM::ImmInsnModel, 4 > Insn
#define LLVM_EXTERNAL_VISIBILITY
MCDisassembler::DecodeStatus DecodeStatus
static DecodeStatus DecodeCGImm(MCInst &MI, uint64_t Bits, uint64_t Address, const MCDisassembler *Decoder)
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeMSP430Disassembler()
static const unsigned GR16DecoderTable[]
static DecodeStatus DecodeMemOperand(MCInst &MI, uint64_t Bits, uint64_t Address, const MCDisassembler *Decoder)
static AddrMode DecodeSrcAddrModeII(unsigned Insn)
static const uint8_t * getDecoderTable(AddrMode SrcAM, unsigned Words)
static AddrMode DecodeDstAddrMode(unsigned Insn)
static MCDisassembler * createMSP430Disassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
static AddrMode DecodeSrcAddrMode(unsigned Rs, unsigned As)
static AddrMode DecodeSrcAddrModeI(unsigned Insn)
static MSP430CC::CondCodes getCondCode(unsigned Cond)
static const unsigned GR8DecoderTable[]
static DecodeStatus DecodeGR8RegisterClass(MCInst &MI, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeGR16RegisterClass(MCInst &MI, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
const SmallVectorImpl< MachineOperand > & Cond
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
size_t size() const
size - Get the array size.
Context object for machine code objects.
Superclass for all disassemblers.
DecodeStatus
Ternary decode status.
virtual DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address, raw_ostream &CStream) const =0
Returns the disassembly of a single instruction.
Instances of this class represent a single low-level machine instruction.
static MCOperand createReg(unsigned Reg)
static MCOperand createImm(int64_t Val)
Generic base class for all target subtargets.
Target - Wrapper for Target specific information.
This class implements an extremely fast bulk output stream that can only output to a stream.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
uint16_t read16le(const void *P)
This is an optimization pass for GlobalISel generic memory operations.
Target & getTheMSP430Target()
constexpr int32_t SignExtend32(uint32_t X)
Sign-extend the number in the bottom B bits of X to a 32-bit integer.
static void RegisterMCDisassembler(Target &T, Target::MCDisassemblerCtorTy Fn)
RegisterMCDisassembler - Register a MCDisassembler implementation for the given target.