31#define DEBUG_TYPE "avr-disassembler"
42 virtual ~AVRDisassembler() =
default;
53 return new AVRDisassembler(STI, Ctx);
63 AVR::R0, AVR::R1, AVR::R2, AVR::R3, AVR::R4, AVR::R5, AVR::R6,
64 AVR::R7, AVR::R8, AVR::R9, AVR::R10, AVR::R11, AVR::R12, AVR::R13,
65 AVR::R14, AVR::R15, AVR::R16, AVR::R17, AVR::R18, AVR::R19, AVR::R20,
66 AVR::R21, AVR::R22, AVR::R23, AVR::R24, AVR::R25, AVR::R26, AVR::R27,
67 AVR::R28, AVR::R29, AVR::R30, AVR::R31,
140#include "AVRGenDisassemblerTables.inc"
145 addr |= fieldFromInstruction(
Insn, 0, 4);
146 addr |= fieldFromInstruction(
Insn, 9, 2) << 4;
147 unsigned reg = fieldFromInstruction(
Insn, 4, 5);
158 addr |= fieldFromInstruction(
Insn, 0, 4);
159 addr |= fieldFromInstruction(
Insn, 9, 2) << 4;
160 unsigned reg = fieldFromInstruction(
Insn, 4, 5);
170 unsigned addr = fieldFromInstruction(
Insn, 3, 5);
171 unsigned b = fieldFromInstruction(
Insn, 0, 3);
188 unsigned d = fieldFromInstruction(
Insn, 4, 5);
206 unsigned d = fieldFromInstruction(
Insn, 4, 3) + 16;
207 unsigned r = fieldFromInstruction(
Insn, 0, 3) + 16;
220 unsigned r = fieldFromInstruction(
Insn, 4, 4) * 2;
221 unsigned d = fieldFromInstruction(
Insn, 0, 4) * 2;
233 unsigned d = fieldFromInstruction(
Insn, 4, 2) * 2 + 24;
235 k |= fieldFromInstruction(
Insn, 0, 4);
236 k |= fieldFromInstruction(
Insn, 6, 2) << 4;
250 unsigned rd = fieldFromInstruction(
Insn, 4, 4) + 16;
251 unsigned rr = fieldFromInstruction(
Insn, 0, 4) + 16;
281 switch (
Insn & 0xf000) {
292 int16_t
Offset = ((int16_t)((
Insn & 0xfff) << 4)) >> 3;
302 {0x000, AVR::BRLOk}, {0x400, AVR::BRSHk}, {0x001, AVR::BREQk},
303 {0x401, AVR::BRNEk}, {0x002, AVR::BRMIk}, {0x402, AVR::BRPLk},
304 {0x004, AVR::BRLTk}, {0x404, AVR::BRGEk}};
307 int16_t
Offset = ((int16_t)((
Insn & 0x3f8) << 6)) >> 8;
310 auto NotAlias = [&
Insn](
const std::pair<unsigned, unsigned> &
I) {
311 return (
Insn & 0x407) !=
I.first;
317 if (It != brInsts.
end()) {
338 if ((
Insn & 0xf000) == 0x8000) {
339 unsigned RegBase = (
Insn & 0x8) ? AVR::R29R28 : AVR::R31R30;
341 if ((
Insn & 0x200) == 0) {
373 if ((
Insn & 0xfc00) != 0x9000 || (
Insn & 0xf) == 0)
378 switch (
Insn & 0xc) {
380 RegBase = AVR::R27R26;
383 RegBase = AVR::R29R28;
386 RegBase = AVR::R31R30;
393 switch (
Insn & 0x203) {
421 if ((
Insn & 0x200) == 0) {
438 if (Bytes.
size() < 2) {
444 Insn = (Bytes[0] << 0) | (Bytes[1] << 8);
452 if (Bytes.
size() < 4) {
459 (Bytes[0] << 16) | (Bytes[1] << 24) | (Bytes[2] << 0) | (Bytes[3] << 8);
468 return DecoderTable16;
470 return DecoderTable32;
492 if (STI.hasFeature(AVR::FeatureTinyEncoding)) {
493 Result = decodeInstruction(DecoderTableAVRTiny16, Instr,
Insn, Address,
SmallVector< AArch64_IMM::ImmInsnModel, 4 > Insn
static DecodeStatus decodeFRd(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeFLPMX(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
MCDisassembler::DecodeStatus DecodeStatus
static DecodeStatus decodeLoadStore(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeFMUL2RdRr(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeFWRdK(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeGPR8RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeFIOARr(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeCallTarget(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeLD8RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
DecodeStatus(* DecodeFunc)(MCInst &MI, unsigned insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeFIORdA(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeFIOBIT(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus readInstruction16(ArrayRef< uint8_t > Bytes, uint64_t Address, uint64_t &Size, uint32_t &Insn)
static DecodeStatus decodeCondBranch(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static const uint16_t GPRDecoderTable[]
static DecodeStatus decodeFFMULRdRr(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static MCDisassembler * createAVRDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
static DecodeStatus decodeMemri(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus readInstruction32(ArrayRef< uint8_t > Bytes, uint64_t Address, uint64_t &Size, uint32_t &Insn)
static DecodeStatus decodeFMOVWRdRr(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAVRDisassembler()
static const uint8_t * getDecoderTable(uint64_t Size)
static DecodeStatus decodeFBRk(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
#define LLVM_EXTERNAL_VISIBILITY
This file defines the DenseMap class.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
size_t size() const
size - Get the array size.
Context object for machine code objects.
Superclass for all disassemblers.
DecodeStatus
Ternary decode status.
virtual DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address, raw_ostream &CStream) const =0
Returns the disassembly of a single instruction.
Instances of this class represent a single low-level machine instruction.
void addOperand(const MCOperand Op)
void setOpcode(unsigned Op)
static MCOperand createReg(unsigned Reg)
static MCOperand createImm(int64_t Val)
Generic base class for all target subtargets.
Wrapper class representing virtual and physical registers.
Target - Wrapper for Target specific information.
This class implements an extremely fast bulk output stream that can only output to a stream.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
This is an optimization pass for GlobalISel generic memory operations.
Target & getTheAVRTarget()
auto partition_point(R &&Range, Predicate P)
Binary search for the first iterator in a range where a predicate is false.
auto partition(R &&Range, UnaryPredicate P)
Provide wrappers to std::partition which take ranges instead of having to pass begin/end explicitly.
static void RegisterMCDisassembler(Target &T, Target::MCDisassemblerCtorTy Fn)
RegisterMCDisassembler - Register a MCDisassembler implementation for the given target.