LLVM 20.0.0git
AArch64Disassembler.cpp
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1//===- AArch64Disassembler.cpp - Disassembler for AArch64 -----------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9//
10//===----------------------------------------------------------------------===//
11
12#include "AArch64Disassembler.h"
13#include "AArch64ExternalSymbolizer.h"
14#include "MCTargetDesc/AArch64AddressingModes.h"
15#include "MCTargetDesc/AArch64MCTargetDesc.h"
16#include "TargetInfo/AArch64TargetInfo.h"
17#include "Utils/AArch64BaseInfo.h"
18#include "llvm-c/Disassembler.h"
19#include "llvm/MC/MCDecoderOps.h"
20#include "llvm/MC/MCDisassembler/MCRelocationInfo.h"
21#include "llvm/MC/MCInst.h"
22#include "llvm/MC/MCInstrDesc.h"
23#include "llvm/MC/MCRegisterInfo.h"
24#include "llvm/MC/MCSubtargetInfo.h"
25#include "llvm/MC/TargetRegistry.h"
26#include "llvm/Support/Compiler.h"
27#include "llvm/Support/Debug.h"
28#include "llvm/Support/ErrorHandling.h"
29#include <algorithm>
30#include <memory>
31
32using namespace llvm;
33
34#define DEBUG_TYPE "aarch64-disassembler"
35
36// Pull DecodeStatus and its enum values into the global namespace.
37using DecodeStatus = MCDisassembler::DecodeStatus;
38
39// Forward declare these because the autogenerated code will reference them.
40// Definitions are further down.
41template <unsigned RegClassID, unsigned FirstReg, unsigned NumRegsInClass>
42static DecodeStatus DecodeSimpleRegisterClass(MCInst &Inst, unsigned RegNo,
43 uint64_t Address,
44 const MCDisassembler *Decoder);
45static DecodeStatus
46DecodeGPR64x8ClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
47 const MCDisassembler *Decoder);
48static DecodeStatus DecodeZPR2Mul2RegisterClass(MCInst &Inst, unsigned RegNo,
49 uint64_t Address,
50 const void *Decoder);
51static DecodeStatus DecodeZPR4Mul4RegisterClass(MCInst &Inst, unsigned RegNo,
52 uint64_t Address,
53 const void *Decoder);
54template <unsigned NumBitsForTile>
55static DecodeStatus DecodeMatrixTile(MCInst &Inst, unsigned RegNo,
56 uint64_t Address,
57 const MCDisassembler *Decoder);
58static DecodeStatus
59DecodeMatrixTileListRegisterClass(MCInst &Inst, unsigned RegMask,
60 uint64_t Address,
61 const MCDisassembler *Decoder);
62static DecodeStatus DecodePPR2Mul2RegisterClass(MCInst &Inst, unsigned RegNo,
63 uint64_t Address,
64 const void *Decoder);
65
66static DecodeStatus DecodeFixedPointScaleImm32(MCInst &Inst, unsigned Imm,
67 uint64_t Address,
68 const MCDisassembler *Decoder);
69static DecodeStatus DecodeFixedPointScaleImm64(MCInst &Inst, unsigned Imm,
70 uint64_t Address,
71 const MCDisassembler *Decoder);
72static DecodeStatus DecodePCRelLabel16(MCInst &Inst, unsigned Imm,
73 uint64_t Address,
74 const MCDisassembler *Decoder);
75static DecodeStatus DecodePCRelLabel19(MCInst &Inst, unsigned Imm,
76 uint64_t Address,
77 const MCDisassembler *Decoder);
78static DecodeStatus DecodeMemExtend(MCInst &Inst, unsigned Imm,
79 uint64_t Address,
80 const MCDisassembler *Decoder);
81static DecodeStatus DecodeMRSSystemRegister(MCInst &Inst, unsigned Imm,
82 uint64_t Address,
83 const MCDisassembler *Decoder);
84static DecodeStatus DecodeMSRSystemRegister(MCInst &Inst, unsigned Imm,
85 uint64_t Address,
86 const MCDisassembler *Decoder);
87static DecodeStatus
88DecodeThreeAddrSRegInstruction(MCInst &Inst, uint32_t insn, uint64_t Address,
89 const MCDisassembler *Decoder);
90static DecodeStatus DecodeMoveImmInstruction(MCInst &Inst, uint32_t insn,
91 uint64_t Address,
92 const MCDisassembler *Decoder);
93static DecodeStatus
94DecodeUnsignedLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Address,
95 const MCDisassembler *Decoder);
96static DecodeStatus DecodeSignedLdStInstruction(MCInst &Inst, uint32_t insn,
97 uint64_t Address,
98 const MCDisassembler *Decoder);
99static DecodeStatus
100DecodeExclusiveLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Address,
101 const MCDisassembler *Decoder);
102static DecodeStatus DecodePairLdStInstruction(MCInst &Inst, uint32_t insn,
103 uint64_t Address,
104 const MCDisassembler *Decoder);
105static DecodeStatus DecodeAuthLoadInstruction(MCInst &Inst, uint32_t insn,
106 uint64_t Address,
107 const MCDisassembler *Decoder);
108static DecodeStatus DecodeAddSubERegInstruction(MCInst &Inst, uint32_t insn,
109 uint64_t Address,
110 const MCDisassembler *Decoder);
111static DecodeStatus DecodeLogicalImmInstruction(MCInst &Inst, uint32_t insn,
112 uint64_t Address,
113 const MCDisassembler *Decoder);
114static DecodeStatus DecodeModImmInstruction(MCInst &Inst, uint32_t insn,
115 uint64_t Address,
116 const MCDisassembler *Decoder);
117static DecodeStatus DecodeModImmTiedInstruction(MCInst &Inst, uint32_t insn,
118 uint64_t Address,
119 const MCDisassembler *Decoder);
120static DecodeStatus DecodeAdrInstruction(MCInst &Inst, uint32_t insn,
121 uint64_t Address,
122 const MCDisassembler *Decoder);
123static DecodeStatus DecodeAddSubImmShift(MCInst &Inst, uint32_t insn,
124 uint64_t Address,
125 const MCDisassembler *Decoder);
126static DecodeStatus DecodeUnconditionalBranch(MCInst &Inst, uint32_t insn,
127 uint64_t Address,
128 const MCDisassembler *Decoder);
129static DecodeStatus
130DecodeSystemPStateImm0_15Instruction(MCInst &Inst, uint32_t insn,
131 uint64_t Address,
132 const MCDisassembler *Decoder);
133static DecodeStatus
134DecodeSystemPStateImm0_1Instruction(MCInst &Inst, uint32_t insn,
135 uint64_t Address,
136 const MCDisassembler *Decoder);
137static DecodeStatus DecodeTestAndBranch(MCInst &Inst, uint32_t insn,
138 uint64_t Address,
139 const MCDisassembler *Decoder);
140
141static DecodeStatus DecodeFMOVLaneInstruction(MCInst &Inst, unsigned Insn,
142 uint64_t Address,
143 const MCDisassembler *Decoder);
144static DecodeStatus DecodeVecShiftR64Imm(MCInst &Inst, unsigned Imm,
145 uint64_t Addr,
146 const MCDisassembler *Decoder);
147static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst &Inst, unsigned Imm,
148 uint64_t Addr,
149 const MCDisassembler *Decoder);
150static DecodeStatus DecodeVecShiftR32Imm(MCInst &Inst, unsigned Imm,
151 uint64_t Addr,
152 const MCDisassembler *Decoder);
153static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst &Inst, unsigned Imm,
154 uint64_t Addr,
155 const MCDisassembler *Decoder);
156static DecodeStatus DecodeVecShiftR16Imm(MCInst &Inst, unsigned Imm,
157 uint64_t Addr,
158 const MCDisassembler *Decoder);
159static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst &Inst, unsigned Imm,
160 uint64_t Addr,
161 const MCDisassembler *Decoder);
162static DecodeStatus DecodeVecShiftR8Imm(MCInst &Inst, unsigned Imm,
163 uint64_t Addr,
164 const MCDisassembler *Decoder);
165static DecodeStatus DecodeVecShiftL64Imm(MCInst &Inst, unsigned Imm,
166 uint64_t Addr,
167 const MCDisassembler *Decoder);
168static DecodeStatus DecodeVecShiftL32Imm(MCInst &Inst, unsigned Imm,
169 uint64_t Addr,
170 const MCDisassembler *Decoder);
171static DecodeStatus DecodeVecShiftL16Imm(MCInst &Inst, unsigned Imm,
172 uint64_t Addr,
173 const MCDisassembler *Decoder);
174static DecodeStatus DecodeVecShiftL8Imm(MCInst &Inst, unsigned Imm,
175 uint64_t Addr,
176 const MCDisassembler *Decoder);
177static DecodeStatus
178DecodeWSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr,
179 const MCDisassembler *Decoder);
180static DecodeStatus
181DecodeXSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr,
182 const MCDisassembler *Decoder);
183static DecodeStatus DecodeSyspXzrInstruction(MCInst &Inst, uint32_t insn,
184 uint64_t Addr,
185 const MCDisassembler *Decoder);
186static DecodeStatus
187DecodeSVELogicalImmInstruction(MCInst &Inst, uint32_t insn, uint64_t Address,
188 const MCDisassembler *Decoder);
189template <int Bits>
190static DecodeStatus DecodeSImm(MCInst &Inst, uint64_t Imm, uint64_t Address,
191 const MCDisassembler *Decoder);
192template <int ElementWidth>
193static DecodeStatus DecodeImm8OptLsl(MCInst &Inst, unsigned Imm, uint64_t Addr,
194 const MCDisassembler *Decoder);
195static DecodeStatus DecodeSVEIncDecImm(MCInst &Inst, unsigned Imm,
196 uint64_t Addr,
197 const MCDisassembler *Decoder);
198static DecodeStatus DecodeSVCROp(MCInst &Inst, unsigned Imm, uint64_t Address,
199 const MCDisassembler *Decoder);
200static DecodeStatus DecodeCPYMemOpInstruction(MCInst &Inst, uint32_t insn,
201 uint64_t Addr,
202 const MCDisassembler *Decoder);
203static DecodeStatus DecodeSETMemOpInstruction(MCInst &Inst, uint32_t insn,
204 uint64_t Addr,
205 const MCDisassembler *Decoder);
206static DecodeStatus DecodePRFMRegInstruction(MCInst &Inst, uint32_t insn,
207 uint64_t Address,
208 const MCDisassembler *Decoder);
209
210#include "AArch64GenDisassemblerTables.inc"
211#include "AArch64GenInstrInfo.inc"
212
213#define Success MCDisassembler::Success
214#define Fail MCDisassembler::Fail
215#define SoftFail MCDisassembler::SoftFail
216
217static MCDisassembler *createAArch64Disassembler(const Target &T,
218 const MCSubtargetInfo &STI,
219 MCContext &Ctx) {
220
221 return new AArch64Disassembler(STI, Ctx, T.createMCInstrInfo());
222}
223
224DecodeStatus AArch64Disassembler::getInstruction(MCInst &MI, uint64_t &Size,
225 ArrayRef<uint8_t> Bytes,
226 uint64_t Address,
227 raw_ostream &CS) const {
228 CommentStream = &CS;
229
230 Size = 0;
231 // We want to read exactly 4 bytes of data.
232 if (Bytes.size() < 4)
233 return Fail;
234 Size = 4;
235
236 // Encoded as a small-endian 32-bit word in the stream.
237 uint32_t Insn =
238 (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0);
239
240 const uint8_t *Tables[] = {DecoderTable32, DecoderTableFallback32};
241
242 for (const auto *Table : Tables) {
243 DecodeStatus Result =
244 decodeInstruction(Table, MI, Insn, Address, this, STI);
245
246 const MCInstrDesc &Desc = MCII->get(MI.getOpcode());
247
248 // For Scalable Matrix Extension (SME) instructions that have an implicit
249 // operand for the accumulator (ZA) or implicit immediate zero which isn't
250 // encoded, manually insert operand.
251 for (unsigned i = 0; i < Desc.getNumOperands(); i++) {
252 if (Desc.operands()[i].OperandType == MCOI::OPERAND_REGISTER) {
253 switch (Desc.operands()[i].RegClass) {
254 default:
255 break;
256 case AArch64::MPRRegClassID:
257 MI.insert(MI.begin() + i, MCOperand::createReg(AArch64::ZA));
258 break;
259 case AArch64::MPR8RegClassID:
260 MI.insert(MI.begin() + i, MCOperand::createReg(AArch64::ZAB0));
261 break;
262 case AArch64::ZTRRegClassID:
263 MI.insert(MI.begin() + i, MCOperand::createReg(AArch64::ZT0));
264 break;
265 }
266 } else if (Desc.operands()[i].OperandType ==
267 AArch64::OPERAND_IMPLICIT_IMM_0) {
268 MI.insert(MI.begin() + i, MCOperand::createImm(0));
269 }
270 }
271
272 if (MI.getOpcode() == AArch64::LDR_ZA ||
273 MI.getOpcode() == AArch64::STR_ZA) {
274 // Spill and fill instructions have a single immediate used for both
275 // the vector select offset and optional memory offset. Replicate
276 // the decoded immediate.
277 const MCOperand &Imm4Op = MI.getOperand(2);
278 assert(Imm4Op.isImm() && "Unexpected operand type!");
279 MI.addOperand(Imm4Op);
280 }
281
282 if (Result != MCDisassembler::Fail)
283 return Result;
284 }
285
286 return MCDisassembler::Fail;
287}
288
289uint64_t AArch64Disassembler::suggestBytesToSkip(ArrayRef<uint8_t> Bytes,
290 uint64_t Address) const {
291 // AArch64 instructions are always 4 bytes wide, so there's no point
292 // in skipping any smaller number of bytes if an instruction can't
293 // be decoded.
294 return 4;
295}
296
297static MCSymbolizer *
298createAArch64ExternalSymbolizer(const Triple &TT, LLVMOpInfoCallback GetOpInfo,
299 LLVMSymbolLookupCallback SymbolLookUp,
300 void *DisInfo, MCContext *Ctx,
301 std::unique_ptr<MCRelocationInfo> &&RelInfo) {
302 return new AArch64ExternalSymbolizer(*Ctx, std::move(RelInfo), GetOpInfo,
303 SymbolLookUp, DisInfo);
304}
305
306extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAArch64Disassembler() {
307 TargetRegistry::RegisterMCDisassembler(getTheAArch64leTarget(),
308 createAArch64Disassembler);
309 TargetRegistry::RegisterMCDisassembler(getTheAArch64beTarget(),
310 createAArch64Disassembler);
311 TargetRegistry::RegisterMCSymbolizer(getTheAArch64leTarget(),
312 createAArch64ExternalSymbolizer);
313 TargetRegistry::RegisterMCSymbolizer(getTheAArch64beTarget(),
314 createAArch64ExternalSymbolizer);
315 TargetRegistry::RegisterMCDisassembler(getTheAArch64_32Target(),
316 createAArch64Disassembler);
317 TargetRegistry::RegisterMCSymbolizer(getTheAArch64_32Target(),
318 createAArch64ExternalSymbolizer);
319
320 TargetRegistry::RegisterMCDisassembler(getTheARM64Target(),
321 createAArch64Disassembler);
322 TargetRegistry::RegisterMCSymbolizer(getTheARM64Target(),
323 createAArch64ExternalSymbolizer);
324 TargetRegistry::RegisterMCDisassembler(getTheARM64_32Target(),
325 createAArch64Disassembler);
326 TargetRegistry::RegisterMCSymbolizer(getTheARM64_32Target(),
327 createAArch64ExternalSymbolizer);
328}
329
330template <unsigned RegClassID, unsigned FirstReg, unsigned NumRegsInClass>
331static DecodeStatus DecodeSimpleRegisterClass(MCInst &Inst, unsigned RegNo,
332 uint64_t Address,
333 const MCDisassembler *Decoder) {
334 if (RegNo > NumRegsInClass - 1)
335 return Fail;
336
337 unsigned Register =
338 AArch64MCRegisterClasses[RegClassID].getRegister(RegNo + FirstReg);
339 Inst.addOperand(MCOperand::createReg(Register));
340 return Success;
341}
342
343static DecodeStatus
344DecodeGPR64x8ClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
345 const MCDisassembler *Decoder) {
346 if (RegNo > 22)
347 return Fail;
348 if (RegNo & 1)
349 return Fail;
350
351 unsigned Register =
352 AArch64MCRegisterClasses[AArch64::GPR64x8ClassRegClassID].getRegister(
353 RegNo >> 1);
354 Inst.addOperand(MCOperand::createReg(Register));
355 return Success;
356}
357
358static DecodeStatus DecodeZPR2Mul2RegisterClass(MCInst &Inst, unsigned RegNo,
359 uint64_t Address,
360 const void *Decoder) {
361 if (RegNo * 2 > 30)
362 return Fail;
363 unsigned Register =
364 AArch64MCRegisterClasses[AArch64::ZPR2RegClassID].getRegister(RegNo * 2);
365 Inst.addOperand(MCOperand::createReg(Register));
366 return Success;
367}
368
369static DecodeStatus DecodeZPR4Mul4RegisterClass(MCInst &Inst, unsigned RegNo,
370 uint64_t Address,
371 const void *Decoder) {
372 if (RegNo * 4 > 28)
373 return Fail;
374 unsigned Register =
375 AArch64MCRegisterClasses[AArch64::ZPR4RegClassID].getRegister(RegNo * 4);
376 Inst.addOperand(MCOperand::createReg(Register));
377 return Success;
378}
379
380static DecodeStatus
381DecodeMatrixTileListRegisterClass(MCInst &Inst, unsigned RegMask,
382 uint64_t Address,
383 const MCDisassembler *Decoder) {
384 if (RegMask > 0xFF)
385 return Fail;
386 Inst.addOperand(MCOperand::createImm(RegMask));
387 return Success;
388}
389
390static const MCPhysReg MatrixZATileDecoderTable[5][16] = {
391 {AArch64::ZAB0},
392 {AArch64::ZAH0, AArch64::ZAH1},
393 {AArch64::ZAS0, AArch64::ZAS1, AArch64::ZAS2, AArch64::ZAS3},
394 {AArch64::ZAD0, AArch64::ZAD1, AArch64::ZAD2, AArch64::ZAD3, AArch64::ZAD4,
395 AArch64::ZAD5, AArch64::ZAD6, AArch64::ZAD7},
396 {AArch64::ZAQ0, AArch64::ZAQ1, AArch64::ZAQ2, AArch64::ZAQ3, AArch64::ZAQ4,
397 AArch64::ZAQ5, AArch64::ZAQ6, AArch64::ZAQ7, AArch64::ZAQ8, AArch64::ZAQ9,
398 AArch64::ZAQ10, AArch64::ZAQ11, AArch64::ZAQ12, AArch64::ZAQ13,
399 AArch64::ZAQ14, AArch64::ZAQ15}};
400
401template <unsigned NumBitsForTile>
402static DecodeStatus DecodeMatrixTile(MCInst &Inst, unsigned RegNo,
403 uint64_t Address,
404 const MCDisassembler *Decoder) {
405 unsigned LastReg = (1 << NumBitsForTile) - 1;
406 if (RegNo > LastReg)
407 return Fail;
408 Inst.addOperand(
409 MCOperand::createReg(MatrixZATileDecoderTable[NumBitsForTile][RegNo]));
410 return Success;
411}
412
413static DecodeStatus DecodePPR2Mul2RegisterClass(MCInst &Inst, unsigned RegNo,
414 uint64_t Address,
415 const void *Decoder) {
416 if ((RegNo * 2) > 14)
417 return Fail;
418 unsigned Register =
419 AArch64MCRegisterClasses[AArch64::PPR2RegClassID].getRegister(RegNo * 2);
420 Inst.addOperand(MCOperand::createReg(Register));
421 return Success;
422}
423
424static DecodeStatus DecodeFixedPointScaleImm32(MCInst &Inst, unsigned Imm,
425 uint64_t Addr,
426 const MCDisassembler *Decoder) {
427 // scale{5} is asserted as 1 in tblgen.
428 Imm |= 0x20;
429 Inst.addOperand(MCOperand::createImm(64 - Imm));
430 return Success;
431}
432
433static DecodeStatus DecodeFixedPointScaleImm64(MCInst &Inst, unsigned Imm,
434 uint64_t Addr,
435 const MCDisassembler *Decoder) {
436 Inst.addOperand(MCOperand::createImm(64 - Imm));
437 return Success;
438}
439
440static DecodeStatus DecodePCRelLabel16(MCInst &Inst, unsigned Imm,
441 uint64_t Addr,
442 const MCDisassembler *Decoder) {
443 // Immediate is encoded as the top 16-bits of an unsigned 18-bit negative
444 // PC-relative offset.
445 uint64_t ImmVal = Imm;
446 if (ImmVal > (1 << 16))
447 return Fail;
448 ImmVal = -ImmVal;
449 if (!Decoder->tryAddingSymbolicOperand(Inst, (ImmVal << 2), Addr,
450 /*IsBranch=*/false, 0, 0, 4))
451 Inst.addOperand(MCOperand::createImm(ImmVal));
452 return Success;
453}
454
455static DecodeStatus DecodePCRelLabel19(MCInst &Inst, unsigned Imm,
456 uint64_t Addr,
457 const MCDisassembler *Decoder) {
458 int64_t ImmVal = Imm;
459
460 // Sign-extend 19-bit immediate.
461 if (ImmVal & (1 << (19 - 1)))
462 ImmVal |= ~((1LL << 19) - 1);
463
464 if (!Decoder->tryAddingSymbolicOperand(
465 Inst, ImmVal * 4, Addr, Inst.getOpcode() != AArch64::LDRXl, 0, 0, 4))
466 Inst.addOperand(MCOperand::createImm(ImmVal));
467 return Success;
468}
469
470static DecodeStatus DecodeMemExtend(MCInst &Inst, unsigned Imm,
471 uint64_t Address,
472 const MCDisassembler *Decoder) {
473 Inst.addOperand(MCOperand::createImm((Imm >> 1) & 1));
474 Inst.addOperand(MCOperand::createImm(Imm & 1));
475 return Success;
476}
477
478static DecodeStatus DecodeMRSSystemRegister(MCInst &Inst, unsigned Imm,
479 uint64_t Address,
480 const MCDisassembler *Decoder) {
481 Inst.addOperand(MCOperand::createImm(Imm));
482
483 // Every system register in the encoding space is valid with the syntax
484 // S<op0>_<op1>_<Cn>_<Cm>_<op2>, so decoding system registers always succeeds.
485 return Success;
486}
487
488static DecodeStatus DecodeMSRSystemRegister(MCInst &Inst, unsigned Imm,
489 uint64_t Address,
490 const MCDisassembler *Decoder) {
491 Inst.addOperand(MCOperand::createImm(Imm));
492
493 return Success;
494}
495
496static DecodeStatus DecodeFMOVLaneInstruction(MCInst &Inst, unsigned Insn,
497 uint64_t Address,
498 const MCDisassembler *Decoder) {
499 // This decoder exists to add the dummy Lane operand to the MCInst, which must
500 // be 1 in assembly but has no other real manifestation.
501 unsigned Rd = fieldFromInstruction(Insn, 0, 5);
502 unsigned Rn = fieldFromInstruction(Insn, 5, 5);
503 unsigned IsToVec = fieldFromInstruction(Insn, 16, 1);
504
505 if (IsToVec) {
506 DecodeSimpleRegisterClass<AArch64::FPR128RegClassID, 0, 32>(
507 Inst, Rd, Address, Decoder);
508 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(
509 Inst, Rn, Address, Decoder);
510 } else {
511 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(
512 Inst, Rd, Address, Decoder);
513 DecodeSimpleRegisterClass<AArch64::FPR128RegClassID, 0, 32>(
514 Inst, Rn, Address, Decoder);
515 }
516
517 // Add the lane
518 Inst.addOperand(MCOperand::createImm(1));
519
520 return Success;
521}
522
523static DecodeStatus DecodeVecShiftRImm(MCInst &Inst, unsigned Imm,
524 unsigned Add) {
525 Inst.addOperand(MCOperand::createImm(Add - Imm));
526 return Success;
527}
528
529static DecodeStatus DecodeVecShiftLImm(MCInst &Inst, unsigned Imm,
530 unsigned Add) {
531 Inst.addOperand(MCOperand::createImm((Imm + Add) & (Add - 1)));
532 return Success;
533}
534
535static DecodeStatus DecodeVecShiftR64Imm(MCInst &Inst, unsigned Imm,
536 uint64_t Addr,
537 const MCDisassembler *Decoder) {
538 return DecodeVecShiftRImm(Inst, Imm, 64);
539}
540
541static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst &Inst, unsigned Imm,
542 uint64_t Addr,
543 const MCDisassembler *Decoder) {
544 return DecodeVecShiftRImm(Inst, Imm | 0x20, 64);
545}
546
547static DecodeStatus DecodeVecShiftR32Imm(MCInst &Inst, unsigned Imm,
548 uint64_t Addr,
549 const MCDisassembler *Decoder) {
550 return DecodeVecShiftRImm(Inst, Imm, 32);
551}
552
553static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst &Inst, unsigned Imm,
554 uint64_t Addr,
555 const MCDisassembler *Decoder) {
556 return DecodeVecShiftRImm(Inst, Imm | 0x10, 32);
557}
558
559static DecodeStatus DecodeVecShiftR16Imm(MCInst &Inst, unsigned Imm,
560 uint64_t Addr,
561 const MCDisassembler *Decoder) {
562 return DecodeVecShiftRImm(Inst, Imm, 16);
563}
564
565static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst &Inst, unsigned Imm,
566 uint64_t Addr,
567 const MCDisassembler *Decoder) {
568 return DecodeVecShiftRImm(Inst, Imm | 0x8, 16);
569}
570
571static DecodeStatus DecodeVecShiftR8Imm(MCInst &Inst, unsigned Imm,
572 uint64_t Addr,
573 const MCDisassembler *Decoder) {
574 return DecodeVecShiftRImm(Inst, Imm, 8);
575}
576
577static DecodeStatus DecodeVecShiftL64Imm(MCInst &Inst, unsigned Imm,
578 uint64_t Addr,
579 const MCDisassembler *Decoder) {
580 return DecodeVecShiftLImm(Inst, Imm, 64);
581}
582
583static DecodeStatus DecodeVecShiftL32Imm(MCInst &Inst, unsigned Imm,
584 uint64_t Addr,
585 const MCDisassembler *Decoder) {
586 return DecodeVecShiftLImm(Inst, Imm, 32);
587}
588
589static DecodeStatus DecodeVecShiftL16Imm(MCInst &Inst, unsigned Imm,
590 uint64_t Addr,
591 const MCDisassembler *Decoder) {
592 return DecodeVecShiftLImm(Inst, Imm, 16);
593}
594
595static DecodeStatus DecodeVecShiftL8Imm(MCInst &Inst, unsigned Imm,
596 uint64_t Addr,
597 const MCDisassembler *Decoder) {
598 return DecodeVecShiftLImm(Inst, Imm, 8);
599}
600
601static DecodeStatus
602DecodeThreeAddrSRegInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr,
603 const MCDisassembler *Decoder) {
604 unsigned Rd = fieldFromInstruction(insn, 0, 5);
605 unsigned Rn = fieldFromInstruction(insn, 5, 5);
606 unsigned Rm = fieldFromInstruction(insn, 16, 5);
607 unsigned shiftHi = fieldFromInstruction(insn, 22, 2);
608 unsigned shiftLo = fieldFromInstruction(insn, 10, 6);
609 unsigned shift = (shiftHi << 6) | shiftLo;
610 switch (Inst.getOpcode()) {
611 default:
612 return Fail;
613 case AArch64::ADDWrs:
614 case AArch64::ADDSWrs:
615 case AArch64::SUBWrs:
616 case AArch64::SUBSWrs:
617 // if shift == '11' then ReservedValue()
618 if (shiftHi == 0x3)
619 return Fail;
620 [[fallthrough]];
621 case AArch64::ANDWrs:
622 case AArch64::ANDSWrs:
623 case AArch64::BICWrs:
624 case AArch64::BICSWrs:
625 case AArch64::ORRWrs:
626 case AArch64::ORNWrs:
627 case AArch64::EORWrs:
628 case AArch64::EONWrs: {
629 // if sf == '0' and imm6<5> == '1' then ReservedValue()
630 if (shiftLo >> 5 == 1)
631 return Fail;
632 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rd, Addr,
633 Decoder);
634 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rn, Addr,
635 Decoder);
636 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rm, Addr,
637 Decoder);
638 break;
639 }
640 case AArch64::ADDXrs:
641 case AArch64::ADDSXrs:
642 case AArch64::SUBXrs:
643 case AArch64::SUBSXrs:
644 // if shift == '11' then ReservedValue()
645 if (shiftHi == 0x3)
646 return Fail;
647 [[fallthrough]];
648 case AArch64::ANDXrs:
649 case AArch64::ANDSXrs:
650 case AArch64::BICXrs:
651 case AArch64::BICSXrs:
652 case AArch64::ORRXrs:
653 case AArch64::ORNXrs:
654 case AArch64::EORXrs:
655 case AArch64::EONXrs:
656 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rd, Addr,
657 Decoder);
658 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rn, Addr,
659 Decoder);
660 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rm, Addr,
661 Decoder);
662 break;
663 }
664
665 Inst.addOperand(MCOperand::createImm(shift));
666 return Success;
667}
668
669static DecodeStatus DecodeMoveImmInstruction(MCInst &Inst, uint32_t insn,
670 uint64_t Addr,
671 const MCDisassembler *Decoder) {
672 unsigned Rd = fieldFromInstruction(insn, 0, 5);
673 unsigned imm = fieldFromInstruction(insn, 5, 16);
674 unsigned shift = fieldFromInstruction(insn, 21, 2);
675 shift <<= 4;
676 switch (Inst.getOpcode()) {
677 default:
678 return Fail;
679 case AArch64::MOVZWi:
680 case AArch64::MOVNWi:
681 case AArch64::MOVKWi:
682 if (shift & (1U << 5))
683 return Fail;
684 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rd, Addr,
685 Decoder);
686 break;
687 case AArch64::MOVZXi:
688 case AArch64::MOVNXi:
689 case AArch64::MOVKXi:
690 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rd, Addr,
691 Decoder);
692 break;
693 }
694
695 if (Inst.getOpcode() == AArch64::MOVKWi ||
696 Inst.getOpcode() == AArch64::MOVKXi)
697 Inst.addOperand(Inst.getOperand(0));
698
699 Inst.addOperand(MCOperand::createImm(imm));
700 Inst.addOperand(MCOperand::createImm(shift));
701 return Success;
702}
703
704static DecodeStatus
705DecodeUnsignedLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr,
706 const MCDisassembler *Decoder) {
707 unsigned Rt = fieldFromInstruction(insn, 0, 5);
708 unsigned Rn = fieldFromInstruction(insn, 5, 5);
709 unsigned offset = fieldFromInstruction(insn, 10, 12);
710
711 switch (Inst.getOpcode()) {
712 default:
713 return Fail;
714 case AArch64::PRFMui:
715 // Rt is an immediate in prefetch.
716 Inst.addOperand(MCOperand::createImm(Rt));
717 break;
718 case AArch64::STRBBui:
719 case AArch64::LDRBBui:
720 case AArch64::LDRSBWui:
721 case AArch64::STRHHui:
722 case AArch64::LDRHHui:
723 case AArch64::LDRSHWui:
724 case AArch64::STRWui:
725 case AArch64::LDRWui:
726 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rt, Addr,
727 Decoder);
728 break;
729 case AArch64::LDRSBXui:
730 case AArch64::LDRSHXui:
731 case AArch64::LDRSWui:
732 case AArch64::STRXui:
733 case AArch64::LDRXui:
734 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rt, Addr,
735 Decoder);
736 break;
737 case AArch64::LDRQui:
738 case AArch64::STRQui:
739 DecodeSimpleRegisterClass<AArch64::FPR128RegClassID, 0, 32>(Inst, Rt, Addr,
740 Decoder);
741 break;
742 case AArch64::LDRDui:
743 case AArch64::STRDui:
744 DecodeSimpleRegisterClass<AArch64::FPR64RegClassID, 0, 32>(Inst, Rt, Addr,
745 Decoder);
746 break;
747 case AArch64::LDRSui:
748 case AArch64::STRSui:
749 DecodeSimpleRegisterClass<AArch64::FPR32RegClassID, 0, 32>(Inst, Rt, Addr,
750 Decoder);
751 break;
752 case AArch64::LDRHui:
753 case AArch64::STRHui:
754 DecodeSimpleRegisterClass<AArch64::FPR16RegClassID, 0, 32>(Inst, Rt, Addr,
755 Decoder);
756 break;
757 case AArch64::LDRBui:
758 case AArch64::STRBui:
759 DecodeSimpleRegisterClass<AArch64::FPR8RegClassID, 0, 32>(Inst, Rt, Addr,
760 Decoder);
761 break;
762 }
763
764 DecodeSimpleRegisterClass<AArch64::GPR64spRegClassID, 0, 32>(Inst, Rn, Addr,
765 Decoder);
766 if (!Decoder->tryAddingSymbolicOperand(Inst, offset, Addr, Fail, 0, 0, 4))
767 Inst.addOperand(MCOperand::createImm(offset));
768 return Success;
769}
770
771static DecodeStatus DecodeSignedLdStInstruction(MCInst &Inst, uint32_t insn,
772 uint64_t Addr,
773 const MCDisassembler *Decoder) {
774 unsigned Rt = fieldFromInstruction(insn, 0, 5);
775 unsigned Rn = fieldFromInstruction(insn, 5, 5);
776 int64_t offset = fieldFromInstruction(insn, 12, 9);
777
778 // offset is a 9-bit signed immediate, so sign extend it to
779 // fill the unsigned.
780 if (offset & (1 << (9 - 1)))
781 offset |= ~((1LL << 9) - 1);
782
783 // First operand is always the writeback to the address register, if needed.
784 switch (Inst.getOpcode()) {
785 default:
786 break;
787 case AArch64::LDRSBWpre:
788 case AArch64::LDRSHWpre:
789 case AArch64::STRBBpre:
790 case AArch64::LDRBBpre:
791 case AArch64::STRHHpre:
792 case AArch64::LDRHHpre:
793 case AArch64::STRWpre:
794 case AArch64::LDRWpre:
795 case AArch64::LDRSBWpost:
796 case AArch64::LDRSHWpost:
797 case AArch64::STRBBpost:
798 case AArch64::LDRBBpost:
799 case AArch64::STRHHpost:
800 case AArch64::LDRHHpost:
801 case AArch64::STRWpost:
802 case AArch64::LDRWpost:
803 case AArch64::LDRSBXpre:
804 case AArch64::LDRSHXpre:
805 case AArch64::STRXpre:
806 case AArch64::LDRSWpre:
807 case AArch64::LDRXpre:
808 case AArch64::LDRSBXpost:
809 case AArch64::LDRSHXpost:
810 case AArch64::STRXpost:
811 case AArch64::LDRSWpost:
812 case AArch64::LDRXpost:
813 case AArch64::LDRQpre:
814 case AArch64::STRQpre:
815 case AArch64::LDRQpost:
816 case AArch64::STRQpost:
817 case AArch64::LDRDpre:
818 case AArch64::STRDpre:
819 case AArch64::LDRDpost:
820 case AArch64::STRDpost:
821 case AArch64::LDRSpre:
822 case AArch64::STRSpre:
823 case AArch64::LDRSpost:
824 case AArch64::STRSpost:
825 case AArch64::LDRHpre:
826 case AArch64::STRHpre:
827 case AArch64::LDRHpost:
828 case AArch64::STRHpost:
829 case AArch64::LDRBpre:
830 case AArch64::STRBpre:
831 case AArch64::LDRBpost:
832 case AArch64::STRBpost:
833 DecodeSimpleRegisterClass<AArch64::GPR64spRegClassID, 0, 32>(Inst, Rn, Addr,
834 Decoder);
835 break;
836 }
837
838 switch (Inst.getOpcode()) {
839 default:
840 return Fail;
841 case AArch64::PRFUMi:
842 // Rt is an immediate in prefetch.
843 Inst.addOperand(MCOperand::createImm(Rt));
844 break;
845 case AArch64::STURBBi:
846 case AArch64::LDURBBi:
847 case AArch64::LDURSBWi:
848 case AArch64::STURHHi:
849 case AArch64::LDURHHi:
850 case AArch64::LDURSHWi:
851 case AArch64::STURWi:
852 case AArch64::LDURWi:
853 case AArch64::LDTRSBWi:
854 case AArch64::LDTRSHWi:
855 case AArch64::STTRWi:
856 case AArch64::LDTRWi:
857 case AArch64::STTRHi:
858 case AArch64::LDTRHi:
859 case AArch64::LDTRBi:
860 case AArch64::STTRBi:
861 case AArch64::LDRSBWpre:
862 case AArch64::LDRSHWpre:
863 case AArch64::STRBBpre:
864 case AArch64::LDRBBpre:
865 case AArch64::STRHHpre:
866 case AArch64::LDRHHpre:
867 case AArch64::STRWpre:
868 case AArch64::LDRWpre:
869 case AArch64::LDRSBWpost:
870 case AArch64::LDRSHWpost:
871 case AArch64::STRBBpost:
872 case AArch64::LDRBBpost:
873 case AArch64::STRHHpost:
874 case AArch64::LDRHHpost:
875 case AArch64::STRWpost:
876 case AArch64::LDRWpost:
877 case AArch64::STLURBi:
878 case AArch64::STLURHi:
879 case AArch64::STLURWi:
880 case AArch64::LDAPURBi:
881 case AArch64::LDAPURSBWi:
882 case AArch64::LDAPURHi:
883 case AArch64::LDAPURSHWi:
884 case AArch64::LDAPURi:
885 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rt, Addr,
886 Decoder);
887 break;
888 case AArch64::LDURSBXi:
889 case AArch64::LDURSHXi:
890 case AArch64::LDURSWi:
891 case AArch64::STURXi:
892 case AArch64::LDURXi:
893 case AArch64::LDTRSBXi:
894 case AArch64::LDTRSHXi:
895 case AArch64::LDTRSWi:
896 case AArch64::STTRXi:
897 case AArch64::LDTRXi:
898 case AArch64::LDRSBXpre:
899 case AArch64::LDRSHXpre:
900 case AArch64::STRXpre:
901 case AArch64::LDRSWpre:
902 case AArch64::LDRXpre:
903 case AArch64::LDRSBXpost:
904 case AArch64::LDRSHXpost:
905 case AArch64::STRXpost:
906 case AArch64::LDRSWpost:
907 case AArch64::LDRXpost:
908 case AArch64::LDAPURSWi:
909 case AArch64::LDAPURSHXi:
910 case AArch64::LDAPURSBXi:
911 case AArch64::STLURXi:
912 case AArch64::LDAPURXi:
913 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rt, Addr,
914 Decoder);
915 break;
916 case AArch64::LDURQi:
917 case AArch64::STURQi:
918 case AArch64::LDRQpre:
919 case AArch64::STRQpre:
920 case AArch64::LDRQpost:
921 case AArch64::STRQpost:
922 DecodeSimpleRegisterClass<AArch64::FPR128RegClassID, 0, 32>(Inst, Rt, Addr,
923 Decoder);
924 break;
925 case AArch64::LDURDi:
926 case AArch64::STURDi:
927 case AArch64::LDRDpre:
928 case AArch64::STRDpre:
929 case AArch64::LDRDpost:
930 case AArch64::STRDpost:
931 DecodeSimpleRegisterClass<AArch64::FPR64RegClassID, 0, 32>(Inst, Rt, Addr,
932 Decoder);
933 break;
934 case AArch64::LDURSi:
935 case AArch64::STURSi:
936 case AArch64::LDRSpre:
937 case AArch64::STRSpre:
938 case AArch64::LDRSpost:
939 case AArch64::STRSpost:
940 DecodeSimpleRegisterClass<AArch64::FPR32RegClassID, 0, 32>(Inst, Rt, Addr,
941 Decoder);
942 break;
943 case AArch64::LDURHi:
944 case AArch64::STURHi:
945 case AArch64::LDRHpre:
946 case AArch64::STRHpre:
947 case AArch64::LDRHpost:
948 case AArch64::STRHpost:
949 DecodeSimpleRegisterClass<AArch64::FPR16RegClassID, 0, 32>(Inst, Rt, Addr,
950 Decoder);
951 break;
952 case AArch64::LDURBi:
953 case AArch64::STURBi:
954 case AArch64::LDRBpre:
955 case AArch64::STRBpre:
956 case AArch64::LDRBpost:
957 case AArch64::STRBpost:
958 DecodeSimpleRegisterClass<AArch64::FPR8RegClassID, 0, 32>(Inst, Rt, Addr,
959 Decoder);
960 break;
961 }
962
963 DecodeSimpleRegisterClass<AArch64::GPR64spRegClassID, 0, 32>(Inst, Rn, Addr,
964 Decoder);
965 Inst.addOperand(MCOperand::createImm(offset));
966
967 bool IsLoad = fieldFromInstruction(insn, 22, 1);
968 bool IsIndexed = fieldFromInstruction(insn, 10, 2) != 0;
969 bool IsFP = fieldFromInstruction(insn, 26, 1);
970
971 // Cannot write back to a transfer register (but xzr != sp).
972 if (IsLoad && IsIndexed && !IsFP && Rn != 31 && Rt == Rn)
973 return SoftFail;
974
975 return Success;
976}
977
978static DecodeStatus
979DecodeExclusiveLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr,
980 const MCDisassembler *Decoder) {
981 unsigned Rt = fieldFromInstruction(insn, 0, 5);
982 unsigned Rn = fieldFromInstruction(insn, 5, 5);
983 unsigned Rt2 = fieldFromInstruction(insn, 10, 5);
984 unsigned Rs = fieldFromInstruction(insn, 16, 5);
985
986 unsigned Opcode = Inst.getOpcode();
987 switch (Opcode) {
988 default:
989 return Fail;
990 case AArch64::STLXRW:
991 case AArch64::STLXRB:
992 case AArch64::STLXRH:
993 case AArch64::STXRW:
994 case AArch64::STXRB:
995 case AArch64::STXRH:
996 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rs, Addr,
997 Decoder);
998 [[fallthrough]];
999 case AArch64::LDARW:
1000 case AArch64::LDARB:
1001 case AArch64::LDARH:
1002 case AArch64::LDAXRW:
1003 case AArch64::LDAXRB:
1004 case AArch64::LDAXRH:
1005 case AArch64::LDXRW:
1006 case AArch64::LDXRB:
1007 case AArch64::LDXRH:
1008 case AArch64::STLRW:
1009 case AArch64::STLRB:
1010 case AArch64::STLRH:
1011 case AArch64::STLLRW:
1012 case AArch64::STLLRB:
1013 case AArch64::STLLRH:
1014 case AArch64::LDLARW:
1015 case AArch64::LDLARB:
1016 case AArch64::LDLARH:
1017 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rt, Addr,
1018 Decoder);
1019 break;
1020 case AArch64::STLXRX:
1021 case AArch64::STXRX:
1022 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rs, Addr,
1023 Decoder);
1024 [[fallthrough]];
1025 case AArch64::LDARX:
1026 case AArch64::LDAXRX:
1027 case AArch64::LDXRX:
1028 case AArch64::STLRX:
1029 case AArch64::LDLARX:
1030 case AArch64::STLLRX:
1031 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rt, Addr,
1032 Decoder);
1033 break;
1034 case AArch64::STLXPW:
1035 case AArch64::STXPW:
1036 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rs, Addr,
1037 Decoder);
1038 [[fallthrough]];
1039 case AArch64::LDAXPW:
1040 case AArch64::LDXPW:
1041 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rt, Addr,
1042 Decoder);
1043 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rt2, Addr,
1044 Decoder);
1045 break;
1046 case AArch64::STLXPX:
1047 case AArch64::STXPX:
1048 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rs, Addr,
1049 Decoder);
1050 [[fallthrough]];
1051 case AArch64::LDAXPX:
1052 case AArch64::LDXPX:
1053 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rt, Addr,
1054 Decoder);
1055 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rt2, Addr,
1056 Decoder);
1057 break;
1058 }
1059
1060 DecodeSimpleRegisterClass<AArch64::GPR64spRegClassID, 0, 32>(Inst, Rn, Addr,
1061 Decoder);
1062
1063 // You shouldn't load to the same register twice in an instruction...
1064 if ((Opcode == AArch64::LDAXPW || Opcode == AArch64::LDXPW ||
1065 Opcode == AArch64::LDAXPX || Opcode == AArch64::LDXPX) &&
1066 Rt == Rt2)
1067 return SoftFail;
1068
1069 return Success;
1070}
1071
1072static DecodeStatus DecodePairLdStInstruction(MCInst &Inst, uint32_t insn,
1073 uint64_t Addr,
1074 const MCDisassembler *Decoder) {
1075 unsigned Rt = fieldFromInstruction(insn, 0, 5);
1076 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1077 unsigned Rt2 = fieldFromInstruction(insn, 10, 5);
1078 int64_t offset = fieldFromInstruction(insn, 15, 7);
1079 bool IsLoad = fieldFromInstruction(insn, 22, 1);
1080
1081 // offset is a 7-bit signed immediate, so sign extend it to
1082 // fill the unsigned.
1083 if (offset & (1 << (7 - 1)))
1084 offset |= ~((1LL << 7) - 1);
1085
1086 unsigned Opcode = Inst.getOpcode();
1087 bool NeedsDisjointWritebackTransfer = false;
1088
1089 // First operand is always writeback of base register.
1090 switch (Opcode) {
1091 default:
1092 break;
1093 case AArch64::LDPXpost:
1094 case AArch64::STPXpost:
1095 case AArch64::LDPSWpost:
1096 case AArch64::LDPXpre:
1097 case AArch64::STPXpre:
1098 case AArch64::LDPSWpre:
1099 case AArch64::LDPWpost:
1100 case AArch64::STPWpost:
1101 case AArch64::LDPWpre:
1102 case AArch64::STPWpre:
1103 case AArch64::LDPQpost:
1104 case AArch64::STPQpost:
1105 case AArch64::LDPQpre:
1106 case AArch64::STPQpre:
1107 case AArch64::LDPDpost:
1108 case AArch64::STPDpost:
1109 case AArch64::LDPDpre:
1110 case AArch64::STPDpre:
1111 case AArch64::LDPSpost:
1112 case AArch64::STPSpost:
1113 case AArch64::LDPSpre:
1114 case AArch64::STPSpre:
1115 case AArch64::STGPpre:
1116 case AArch64::STGPpost:
1117 DecodeSimpleRegisterClass<AArch64::GPR64spRegClassID, 0, 32>(Inst, Rn, Addr,
1118 Decoder);
1119 break;
1120 }
1121
1122 switch (Opcode) {
1123 default:
1124 return Fail;
1125 case AArch64::LDPXpost:
1126 case AArch64::STPXpost:
1127 case AArch64::LDPSWpost:
1128 case AArch64::LDPXpre:
1129 case AArch64::STPXpre:
1130 case AArch64::LDPSWpre:
1131 case AArch64::STGPpre:
1132 case AArch64::STGPpost:
1133 NeedsDisjointWritebackTransfer = true;
1134 [[fallthrough]];
1135 case AArch64::LDNPXi:
1136 case AArch64::STNPXi:
1137 case AArch64::LDPXi:
1138 case AArch64::STPXi:
1139 case AArch64::LDPSWi:
1140 case AArch64::STGPi:
1141 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rt, Addr,
1142 Decoder);
1143 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rt2, Addr,
1144 Decoder);
1145 break;
1146 case AArch64::LDPWpost:
1147 case AArch64::STPWpost:
1148 case AArch64::LDPWpre:
1149 case AArch64::STPWpre:
1150 NeedsDisjointWritebackTransfer = true;
1151 [[fallthrough]];
1152 case AArch64::LDNPWi:
1153 case AArch64::STNPWi:
1154 case AArch64::LDPWi:
1155 case AArch64::STPWi:
1156 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rt, Addr,
1157 Decoder);
1158 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rt2, Addr,
1159 Decoder);
1160 break;
1161 case AArch64::LDNPQi:
1162 case AArch64::STNPQi:
1163 case AArch64::LDPQpost:
1164 case AArch64::STPQpost:
1165 case AArch64::LDPQi:
1166 case AArch64::STPQi:
1167 case AArch64::LDPQpre:
1168 case AArch64::STPQpre:
1169 DecodeSimpleRegisterClass<AArch64::FPR128RegClassID, 0, 32>(Inst, Rt, Addr,
1170 Decoder);
1171 DecodeSimpleRegisterClass<AArch64::FPR128RegClassID, 0, 32>(Inst, Rt2, Addr,
1172 Decoder);
1173 break;
1174 case AArch64::LDNPDi:
1175 case AArch64::STNPDi:
1176 case AArch64::LDPDpost:
1177 case AArch64::STPDpost:
1178 case AArch64::LDPDi:
1179 case AArch64::STPDi:
1180 case AArch64::LDPDpre:
1181 case AArch64::STPDpre:
1182 DecodeSimpleRegisterClass<AArch64::FPR64RegClassID, 0, 32>(Inst, Rt, Addr,
1183 Decoder);
1184 DecodeSimpleRegisterClass<AArch64::FPR64RegClassID, 0, 32>(Inst, Rt2, Addr,
1185 Decoder);
1186 break;
1187 case AArch64::LDNPSi:
1188 case AArch64::STNPSi:
1189 case AArch64::LDPSpost:
1190 case AArch64::STPSpost:
1191 case AArch64::LDPSi:
1192 case AArch64::STPSi:
1193 case AArch64::LDPSpre:
1194 case AArch64::STPSpre:
1195 DecodeSimpleRegisterClass<AArch64::FPR32RegClassID, 0, 32>(Inst, Rt, Addr,
1196 Decoder);
1197 DecodeSimpleRegisterClass<AArch64::FPR32RegClassID, 0, 32>(Inst, Rt2, Addr,
1198 Decoder);
1199 break;
1200 }
1201
1202 DecodeSimpleRegisterClass<AArch64::GPR64spRegClassID, 0, 32>(Inst, Rn, Addr,
1203 Decoder);
1204 Inst.addOperand(MCOperand::createImm(offset));
1205
1206 // You shouldn't load to the same register twice in an instruction...
1207 if (IsLoad && Rt == Rt2)
1208 return SoftFail;
1209
1210 // ... or do any operation that writes-back to a transfer register. But note
1211 // that "stp xzr, xzr, [sp], #4" is fine because xzr and sp are different.
1212 if (NeedsDisjointWritebackTransfer && Rn != 31 && (Rt == Rn || Rt2 == Rn))
1213 return SoftFail;
1214
1215 return Success;
1216}
1217
1218static DecodeStatus DecodeAuthLoadInstruction(MCInst &Inst, uint32_t insn,
1219 uint64_t Addr,
1220 const MCDisassembler *Decoder) {
1221 unsigned Rt = fieldFromInstruction(insn, 0, 5);
1222 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1223 uint64_t offset = fieldFromInstruction(insn, 22, 1) << 9 |
1224 fieldFromInstruction(insn, 12, 9);
1225 unsigned writeback = fieldFromInstruction(insn, 11, 1);
1226
1227 switch (Inst.getOpcode()) {
1228 default:
1229 return Fail;
1230 case AArch64::LDRAAwriteback:
1231 case AArch64::LDRABwriteback:
1232 DecodeSimpleRegisterClass<AArch64::GPR64spRegClassID, 0, 32>(
1233 Inst, Rn /* writeback register */, Addr, Decoder);
1234 break;
1235 case AArch64::LDRAAindexed:
1236 case AArch64::LDRABindexed:
1237 break;
1238 }
1239
1240 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rt, Addr,
1241 Decoder);
1242 DecodeSimpleRegisterClass<AArch64::GPR64spRegClassID, 0, 32>(Inst, Rn, Addr,
1243 Decoder);
1244 DecodeSImm<10>(Inst, offset, Addr, Decoder);
1245
1246 if (writeback && Rt == Rn && Rn != 31) {
1247 return SoftFail;
1248 }
1249
1250 return Success;
1251}
1252
1253static DecodeStatus DecodeAddSubERegInstruction(MCInst &Inst, uint32_t insn,
1254 uint64_t Addr,
1255 const MCDisassembler *Decoder) {
1256 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1257 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1258 unsigned Rm = fieldFromInstruction(insn, 16, 5);
1259 unsigned extend = fieldFromInstruction(insn, 10, 6);
1260
1261 unsigned shift = extend & 0x7;
1262 if (shift > 4)
1263 return Fail;
1264
1265 switch (Inst.getOpcode()) {
1266 default:
1267 return Fail;
1268 case AArch64::ADDWrx:
1269 case AArch64::SUBWrx:
1270 DecodeSimpleRegisterClass<AArch64::GPR32spRegClassID, 0, 32>(Inst, Rd, Addr,
1271 Decoder);
1272 DecodeSimpleRegisterClass<AArch64::GPR32spRegClassID, 0, 32>(Inst, Rn, Addr,
1273 Decoder);
1274 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rm, Addr,
1275 Decoder);
1276 break;
1277 case AArch64::ADDSWrx:
1278 case AArch64::SUBSWrx:
1279 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rd, Addr,
1280 Decoder);
1281 DecodeSimpleRegisterClass<AArch64::GPR32spRegClassID, 0, 32>(Inst, Rn, Addr,
1282 Decoder);
1283 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rm, Addr,
1284 Decoder);
1285 break;
1286 case AArch64::ADDXrx:
1287 case AArch64::SUBXrx:
1288 DecodeSimpleRegisterClass<AArch64::GPR64spRegClassID, 0, 32>(Inst, Rd, Addr,
1289 Decoder);
1290 DecodeSimpleRegisterClass<AArch64::GPR64spRegClassID, 0, 32>(Inst, Rn, Addr,
1291 Decoder);
1292 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rm, Addr,
1293 Decoder);
1294 break;
1295 case AArch64::ADDSXrx:
1296 case AArch64::SUBSXrx:
1297 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rd, Addr,
1298 Decoder);
1299 DecodeSimpleRegisterClass<AArch64::GPR64spRegClassID, 0, 32>(Inst, Rn, Addr,
1300 Decoder);
1301 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rm, Addr,
1302 Decoder);
1303 break;
1304 case AArch64::ADDXrx64:
1305 case AArch64::SUBXrx64:
1306 DecodeSimpleRegisterClass<AArch64::GPR64spRegClassID, 0, 32>(Inst, Rd, Addr,
1307 Decoder);
1308 DecodeSimpleRegisterClass<AArch64::GPR64spRegClassID, 0, 32>(Inst, Rn, Addr,
1309 Decoder);
1310 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rm, Addr,
1311 Decoder);
1312 break;
1313 case AArch64::SUBSXrx64:
1314 case AArch64::ADDSXrx64:
1315 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rd, Addr,
1316 Decoder);
1317 DecodeSimpleRegisterClass<AArch64::GPR64spRegClassID, 0, 32>(Inst, Rn, Addr,
1318 Decoder);
1319 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rm, Addr,
1320 Decoder);
1321 break;
1322 }
1323
1324 Inst.addOperand(MCOperand::createImm(extend));
1325 return Success;
1326}
1327
1328static DecodeStatus DecodeLogicalImmInstruction(MCInst &Inst, uint32_t insn,
1329 uint64_t Addr,
1330 const MCDisassembler *Decoder) {
1331 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1332 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1333 unsigned Datasize = fieldFromInstruction(insn, 31, 1);
1334 unsigned imm;
1335
1336 if (Datasize) {
1337 if (Inst.getOpcode() == AArch64::ANDSXri)
1338 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rd, Addr,
1339 Decoder);
1340 else
1341 DecodeSimpleRegisterClass<AArch64::GPR64spRegClassID, 0, 32>(
1342 Inst, Rd, Addr, Decoder);
1343 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rn, Addr,
1344 Decoder);
1345 imm = fieldFromInstruction(insn, 10, 13);
1346 if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 64))
1347 return Fail;
1348 } else {
1349 if (Inst.getOpcode() == AArch64::ANDSWri)
1350 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rd, Addr,
1351 Decoder);
1352 else
1353 DecodeSimpleRegisterClass<AArch64::GPR32spRegClassID, 0, 32>(
1354 Inst, Rd, Addr, Decoder);
1355 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rn, Addr,
1356 Decoder);
1357 imm = fieldFromInstruction(insn, 10, 12);
1358 if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 32))
1359 return Fail;
1360 }
1361 Inst.addOperand(MCOperand::createImm(imm));
1362 return Success;
1363}
1364
1365static DecodeStatus DecodeModImmInstruction(MCInst &Inst, uint32_t insn,
1366 uint64_t Addr,
1367 const MCDisassembler *Decoder) {
1368 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1369 unsigned cmode = fieldFromInstruction(insn, 12, 4);
1370 unsigned imm = fieldFromInstruction(insn, 16, 3) << 5;
1371 imm |= fieldFromInstruction(insn, 5, 5);
1372
1373 if (Inst.getOpcode() == AArch64::MOVID)
1374 DecodeSimpleRegisterClass<AArch64::FPR64RegClassID, 0, 32>(Inst, Rd, Addr,
1375 Decoder);
1376 else
1377 DecodeSimpleRegisterClass<AArch64::FPR128RegClassID, 0, 32>(Inst, Rd, Addr,
1378 Decoder);
1379
1380 Inst.addOperand(MCOperand::createImm(imm));
1381
1382 switch (Inst.getOpcode()) {
1383 default:
1384 break;
1385 case AArch64::MOVIv4i16:
1386 case AArch64::MOVIv8i16:
1387 case AArch64::MVNIv4i16:
1388 case AArch64::MVNIv8i16:
1389 case AArch64::MOVIv2i32:
1390 case AArch64::MOVIv4i32:
1391 case AArch64::MVNIv2i32:
1392 case AArch64::MVNIv4i32:
1393 Inst.addOperand(MCOperand::createImm((cmode & 6) << 2));
1394 break;
1395 case AArch64::MOVIv2s_msl:
1396 case AArch64::MOVIv4s_msl:
1397 case AArch64::MVNIv2s_msl:
1398 case AArch64::MVNIv4s_msl:
1399 Inst.addOperand(MCOperand::createImm((cmode & 1) ? 0x110 : 0x108));
1400 break;
1401 }
1402
1403 return Success;
1404}
1405
1406static DecodeStatus DecodeModImmTiedInstruction(MCInst &Inst, uint32_t insn,
1407 uint64_t Addr,
1408 const MCDisassembler *Decoder) {
1409 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1410 unsigned cmode = fieldFromInstruction(insn, 12, 4);
1411 unsigned imm = fieldFromInstruction(insn, 16, 3) << 5;
1412 imm |= fieldFromInstruction(insn, 5, 5);
1413
1414 // Tied operands added twice.
1415 DecodeSimpleRegisterClass<AArch64::FPR128RegClassID, 0, 32>(Inst, Rd, Addr,
1416 Decoder);
1417 DecodeSimpleRegisterClass<AArch64::FPR128RegClassID, 0, 32>(Inst, Rd, Addr,
1418 Decoder);
1419
1420 Inst.addOperand(MCOperand::createImm(imm));
1421 Inst.addOperand(MCOperand::createImm((cmode & 6) << 2));
1422
1423 return Success;
1424}
1425
1426static DecodeStatus DecodeAdrInstruction(MCInst &Inst, uint32_t insn,
1427 uint64_t Addr,
1428 const MCDisassembler *Decoder) {
1429 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1430 int64_t imm = fieldFromInstruction(insn, 5, 19) << 2;
1431 imm |= fieldFromInstruction(insn, 29, 2);
1432
1433 // Sign-extend the 21-bit immediate.
1434 if (imm & (1 << (21 - 1)))
1435 imm |= ~((1LL << 21) - 1);
1436
1437 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rd, Addr,
1438 Decoder);
1439 if (!Decoder->tryAddingSymbolicOperand(Inst, imm, Addr, Fail, 0, 0, 4))
1440 Inst.addOperand(MCOperand::createImm(imm));
1441
1442 return Success;
1443}
1444
1445static DecodeStatus DecodeAddSubImmShift(MCInst &Inst, uint32_t insn,
1446 uint64_t Addr,
1447 const MCDisassembler *Decoder) {
1448 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1449 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1450 unsigned Imm = fieldFromInstruction(insn, 10, 14);
1451 unsigned S = fieldFromInstruction(insn, 29, 1);
1452 unsigned Datasize = fieldFromInstruction(insn, 31, 1);
1453
1454 unsigned ShifterVal = (Imm >> 12) & 3;
1455 unsigned ImmVal = Imm & 0xFFF;
1456
1457 if (ShifterVal != 0 && ShifterVal != 1)
1458 return Fail;
1459
1460 if (Datasize) {
1461 if (Rd == 31 && !S)
1462 DecodeSimpleRegisterClass<AArch64::GPR64spRegClassID, 0, 32>(
1463 Inst, Rd, Addr, Decoder);
1464 else
1465 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rd, Addr,
1466 Decoder);
1467 DecodeSimpleRegisterClass<AArch64::GPR64spRegClassID, 0, 32>(Inst, Rn, Addr,
1468 Decoder);
1469 } else {
1470 if (Rd == 31 && !S)
1471 DecodeSimpleRegisterClass<AArch64::GPR32spRegClassID, 0, 32>(
1472 Inst, Rd, Addr, Decoder);
1473 else
1474 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rd, Addr,
1475 Decoder);
1476 DecodeSimpleRegisterClass<AArch64::GPR32spRegClassID, 0, 32>(Inst, Rn, Addr,
1477 Decoder);
1478 }
1479
1480 if (!Decoder->tryAddingSymbolicOperand(Inst, Imm, Addr, Fail, 0, 0, 4))
1481 Inst.addOperand(MCOperand::createImm(ImmVal));
1482 Inst.addOperand(MCOperand::createImm(12 * ShifterVal));
1483 return Success;
1484}
1485
1486static DecodeStatus DecodeUnconditionalBranch(MCInst &Inst, uint32_t insn,
1487 uint64_t Addr,
1488 const MCDisassembler *Decoder) {
1489 int64_t imm = fieldFromInstruction(insn, 0, 26);
1490
1491 // Sign-extend the 26-bit immediate.
1492 if (imm & (1 << (26 - 1)))
1493 imm |= ~((1LL << 26) - 1);
1494
1495 if (!Decoder->tryAddingSymbolicOperand(Inst, imm * 4, Addr, true, 0, 0, 4))
1496 Inst.addOperand(MCOperand::createImm(imm));
1497
1498 return Success;
1499}
1500
1501static bool isInvalidPState(uint64_t Op1, uint64_t Op2) {
1502 return Op1 == 0b000 && (Op2 == 0b000 || // CFINV
1503 Op2 == 0b001 || // XAFlag
1504 Op2 == 0b010); // AXFlag
1505}
1506
1507static DecodeStatus
1508DecodeSystemPStateImm0_15Instruction(MCInst &Inst, uint32_t insn, uint64_t Addr,
1509 const MCDisassembler *Decoder) {
1510 uint64_t op1 = fieldFromInstruction(insn, 16, 3);
1511 uint64_t op2 = fieldFromInstruction(insn, 5, 3);
1512 uint64_t imm = fieldFromInstruction(insn, 8, 4);
1513 uint64_t pstate_field = (op1 << 3) | op2;
1514
1515 if (isInvalidPState(op1, op2))
1516 return Fail;
1517
1518 Inst.addOperand(MCOperand::createImm(pstate_field));
1519 Inst.addOperand(MCOperand::createImm(imm));
1520
1521 auto PState = AArch64PState::lookupPStateImm0_15ByEncoding(pstate_field);
1522 if (PState &&
1523 PState->haveFeatures(Decoder->getSubtargetInfo().getFeatureBits()))
1524 return Success;
1525 return Fail;
1526}
1527
1528static DecodeStatus
1529DecodeSystemPStateImm0_1Instruction(MCInst &Inst, uint32_t insn, uint64_t Addr,
1530 const MCDisassembler *Decoder) {
1531 uint64_t op1 = fieldFromInstruction(insn, 16, 3);
1532 uint64_t op2 = fieldFromInstruction(insn, 5, 3);
1533 uint64_t crm_high = fieldFromInstruction(insn, 9, 3);
1534 uint64_t imm = fieldFromInstruction(insn, 8, 1);
1535 uint64_t pstate_field = (crm_high << 6) | (op1 << 3) | op2;
1536
1537 if (isInvalidPState(op1, op2))
1538 return Fail;
1539
1540 Inst.addOperand(MCOperand::createImm(pstate_field));
1541 Inst.addOperand(MCOperand::createImm(imm));
1542
1543 auto PState = AArch64PState::lookupPStateImm0_1ByEncoding(pstate_field);
1544 if (PState &&
1545 PState->haveFeatures(Decoder->getSubtargetInfo().getFeatureBits()))
1546 return Success;
1547 return Fail;
1548}
1549
1550static DecodeStatus DecodeTestAndBranch(MCInst &Inst, uint32_t insn,
1551 uint64_t Addr,
1552 const MCDisassembler *Decoder) {
1553 uint64_t Rt = fieldFromInstruction(insn, 0, 5);
1554 uint64_t bit = fieldFromInstruction(insn, 31, 1) << 5;
1555 bit |= fieldFromInstruction(insn, 19, 5);
1556 int64_t dst = fieldFromInstruction(insn, 5, 14);
1557
1558 // Sign-extend 14-bit immediate.
1559 if (dst & (1 << (14 - 1)))
1560 dst |= ~((1LL << 14) - 1);
1561
1562 if (fieldFromInstruction(insn, 31, 1) == 0)
1563 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rt, Addr,
1564 Decoder);
1565 else
1566 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rt, Addr,
1567 Decoder);
1568 Inst.addOperand(MCOperand::createImm(bit));
1569 if (!Decoder->tryAddingSymbolicOperand(Inst, dst * 4, Addr, true, 0, 0, 4))
1570 Inst.addOperand(MCOperand::createImm(dst));
1571
1572 return Success;
1573}
1574
1575static DecodeStatus
1576DecodeGPRSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegClassID,
1577 unsigned RegNo, uint64_t Addr,
1578 const MCDisassembler *Decoder) {
1579 // Register number must be even (see CASP instruction)
1580 if (RegNo & 0x1)
1581 return Fail;
1582
1583 unsigned Reg = AArch64MCRegisterClasses[RegClassID].getRegister(RegNo / 2);
1584 Inst.addOperand(MCOperand::createReg(Reg));
1585 return Success;
1586}
1587
1588static DecodeStatus
1589DecodeWSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr,
1590 const MCDisassembler *Decoder) {
1591 return DecodeGPRSeqPairsClassRegisterClass(
1592 Inst, AArch64::WSeqPairsClassRegClassID, RegNo, Addr, Decoder);
1593}
1594
1595static DecodeStatus
1596DecodeXSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr,
1597 const MCDisassembler *Decoder) {
1598 return DecodeGPRSeqPairsClassRegisterClass(
1599 Inst, AArch64::XSeqPairsClassRegClassID, RegNo, Addr, Decoder);
1600}
1601
1602static DecodeStatus DecodeSyspXzrInstruction(MCInst &Inst, uint32_t insn,
1603 uint64_t Addr,
1604 const MCDisassembler *Decoder) {
1605 unsigned op1 = fieldFromInstruction(insn, 16, 3);
1606 unsigned CRn = fieldFromInstruction(insn, 12, 4);
1607 unsigned CRm = fieldFromInstruction(insn, 8, 4);
1608 unsigned op2 = fieldFromInstruction(insn, 5, 3);
1609 unsigned Rt = fieldFromInstruction(insn, 0, 5);
1610 if (Rt != 0b11111)
1611 return Fail;
1612
1613 Inst.addOperand(MCOperand::createImm(op1));
1614 Inst.addOperand(MCOperand::createImm(CRn));
1615 Inst.addOperand(MCOperand::createImm(CRm));
1616 Inst.addOperand(MCOperand::createImm(op2));
1617 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rt, Addr,
1618 Decoder);
1619
1620 return Success;
1621}
1622
1623static DecodeStatus
1624DecodeSVELogicalImmInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr,
1625 const MCDisassembler *Decoder) {
1626 unsigned Zdn = fieldFromInstruction(insn, 0, 5);
1627 unsigned imm = fieldFromInstruction(insn, 5, 13);
1628 if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 64))
1629 return Fail;
1630
1631 // The same (tied) operand is added twice to the instruction.
1632 DecodeSimpleRegisterClass<AArch64::ZPRRegClassID, 0, 32>(Inst, Zdn, Addr,
1633 Decoder);
1634 if (Inst.getOpcode() != AArch64::DUPM_ZI)
1635 DecodeSimpleRegisterClass<AArch64::ZPRRegClassID, 0, 32>(Inst, Zdn, Addr,
1636 Decoder);
1637 Inst.addOperand(MCOperand::createImm(imm));
1638 return Success;
1639}
1640
1641template <int Bits>
1642static DecodeStatus DecodeSImm(MCInst &Inst, uint64_t Imm, uint64_t Address,
1643 const MCDisassembler *Decoder) {
1644 if (Imm & ~((1LL << Bits) - 1))
1645 return Fail;
1646
1647 // Imm is a signed immediate, so sign extend it.
1648 if (Imm & (1 << (Bits - 1)))
1649 Imm |= ~((1LL << Bits) - 1);
1650
1651 Inst.addOperand(MCOperand::createImm(Imm));
1652 return Success;
1653}
1654
1655// Decode 8-bit signed/unsigned immediate for a given element width.
1656template <int ElementWidth>
1657static DecodeStatus DecodeImm8OptLsl(MCInst &Inst, unsigned Imm, uint64_t Addr,
1658 const MCDisassembler *Decoder) {
1659 unsigned Val = (uint8_t)Imm;
1660 unsigned Shift = (Imm & 0x100) ? 8 : 0;
1661 if (ElementWidth == 8 && Shift)
1662 return Fail;
1663 Inst.addOperand(MCOperand::createImm(Val));
1664 Inst.addOperand(MCOperand::createImm(Shift));
1665 return Success;
1666}
1667
1668// Decode uimm4 ranged from 1-16.
1669static DecodeStatus DecodeSVEIncDecImm(MCInst &Inst, unsigned Imm,
1670 uint64_t Addr,
1671 const MCDisassembler *Decoder) {
1672 Inst.addOperand(MCOperand::createImm(Imm + 1));
1673 return Success;
1674}
1675
1676static DecodeStatus DecodeSVCROp(MCInst &Inst, unsigned Imm, uint64_t Address,
1677 const MCDisassembler *Decoder) {
1678 if (AArch64SVCR::lookupSVCRByEncoding(Imm)) {
1679 Inst.addOperand(MCOperand::createImm(Imm));
1680 return Success;
1681 }
1682 return Fail;
1683}
1684
1685static DecodeStatus DecodeCPYMemOpInstruction(MCInst &Inst, uint32_t insn,
1686 uint64_t Addr,
1687 const MCDisassembler *Decoder) {
1688 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1689 unsigned Rs = fieldFromInstruction(insn, 16, 5);
1690 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1691
1692 // None of the registers may alias: if they do, then the instruction is not
1693 // merely unpredictable but actually entirely unallocated.
1694 if (Rd == Rs || Rs == Rn || Rd == Rn)
1695 return MCDisassembler::Fail;
1696
1697 // All three register operands are written back, so they all appear
1698 // twice in the operand list, once as outputs and once as inputs.
1699 if (!DecodeSimpleRegisterClass<AArch64::GPR64commonRegClassID, 0, 31>(
1700 Inst, Rd, Addr, Decoder) ||
1701 !DecodeSimpleRegisterClass<AArch64::GPR64commonRegClassID, 0, 31>(
1702 Inst, Rs, Addr, Decoder) ||
1703 !DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(
1704 Inst, Rn, Addr, Decoder) ||
1705 !DecodeSimpleRegisterClass<AArch64::GPR64commonRegClassID, 0, 31>(
1706 Inst, Rd, Addr, Decoder) ||
1707 !DecodeSimpleRegisterClass<AArch64::GPR64commonRegClassID, 0, 31>(
1708 Inst, Rs, Addr, Decoder) ||
1709 !DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(
1710 Inst, Rn, Addr, Decoder))
1711 return MCDisassembler::Fail;
1712
1713 return MCDisassembler::Success;
1714}
1715
1716static DecodeStatus DecodeSETMemOpInstruction(MCInst &Inst, uint32_t insn,
1717 uint64_t Addr,
1718 const MCDisassembler *Decoder) {
1719 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1720 unsigned Rm = fieldFromInstruction(insn, 16, 5);
1721 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1722
1723 // None of the registers may alias: if they do, then the instruction is not
1724 // merely unpredictable but actually entirely unallocated.
1725 if (Rd == Rm || Rm == Rn || Rd == Rn)
1726 return MCDisassembler::Fail;
1727
1728 // Rd and Rn (not Rm) register operands are written back, so they appear
1729 // twice in the operand list, once as outputs and once as inputs.
1730 if (!DecodeSimpleRegisterClass<AArch64::GPR64commonRegClassID, 0, 31>(
1731 Inst, Rd, Addr, Decoder) ||
1732 !DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(
1733 Inst, Rn, Addr, Decoder) ||
1734 !DecodeSimpleRegisterClass<AArch64::GPR64commonRegClassID, 0, 31>(
1735 Inst, Rd, Addr, Decoder) ||
1736 !DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(
1737 Inst, Rn, Addr, Decoder) ||
1738 !DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(
1739 Inst, Rm, Addr, Decoder))
1740 return MCDisassembler::Fail;
1741
1742 return MCDisassembler::Success;
1743}
1744
1745static DecodeStatus DecodePRFMRegInstruction(MCInst &Inst, uint32_t insn,
1746 uint64_t Addr,
1747 const MCDisassembler *Decoder) {
1748 // PRFM with Rt = '11xxx' should be decoded as RPRFM.
1749 // Fail to decode and defer to fallback decoder table to decode RPRFM.
1750 unsigned Mask = 0x18;
1751 uint64_t Rt = fieldFromInstruction(insn, 0, 5);
1752 if ((Rt & Mask) == Mask)
1753 return Fail;
1754
1755 uint64_t Rn = fieldFromInstruction(insn, 5, 5);
1756 uint64_t Shift = fieldFromInstruction(insn, 12, 1);
1757 uint64_t Extend = fieldFromInstruction(insn, 15, 1);
1758 uint64_t Rm = fieldFromInstruction(insn, 16, 5);
1759
1760 Inst.addOperand(MCOperand::createImm(Rt));
1761 DecodeSimpleRegisterClass<AArch64::GPR64spRegClassID, 0, 32>(Inst, Rn, Addr,
1762 Decoder);
1763
1764 switch (Inst.getOpcode()) {
1765 default:
1766 return Fail;
1767 case AArch64::PRFMroW:
1768 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rm, Addr,
1769 Decoder);
1770 break;
1771 case AArch64::PRFMroX:
1772 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rm, Addr,
1773 Decoder);
1774 break;
1775 }
1776
1777 DecodeMemExtend(Inst, (Extend << 1) | Shift, Addr, Decoder);
1778
1779 return Success;
1780}
DecodeUnconditionalBranch
static DecodeStatus DecodeUnconditionalBranch(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1486
DecodeVecShiftL64Imm
static DecodeStatus DecodeVecShiftL64Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:577
DecodeVecShiftL32Imm
static DecodeStatus DecodeVecShiftL32Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:583
createAArch64ExternalSymbolizer
static MCSymbolizer * createAArch64ExternalSymbolizer(const Triple &TT, LLVMOpInfoCallback GetOpInfo, LLVMSymbolLookupCallback SymbolLookUp, void *DisInfo, MCContext *Ctx, std::unique_ptr< MCRelocationInfo > &&RelInfo)
Definition: AArch64Disassembler.cpp:298
DecodeCPYMemOpInstruction
static DecodeStatus DecodeCPYMemOpInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1685
DecodeVecShiftR8Imm
static DecodeStatus DecodeVecShiftR8Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:571
DecodeFixedPointScaleImm64
static DecodeStatus DecodeFixedPointScaleImm64(MCInst &Inst, unsigned Imm, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:433
DecodeAddSubERegInstruction
static DecodeStatus DecodeAddSubERegInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1253
DecodeModImmInstruction
static DecodeStatus DecodeModImmInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1365
DecodeLogicalImmInstruction
static DecodeStatus DecodeLogicalImmInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1328
DecodeMoveImmInstruction
static DecodeStatus DecodeMoveImmInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:669
DecodeSystemPStateImm0_1Instruction
static DecodeStatus DecodeSystemPStateImm0_1Instruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1529
createAArch64Disassembler
static MCDisassembler * createAArch64Disassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
Definition: AArch64Disassembler.cpp:217
DecodeGPR64x8ClassRegisterClass
static DecodeStatus DecodeGPR64x8ClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:344
DecodeUnsignedLdStInstruction
static DecodeStatus DecodeUnsignedLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:705
MatrixZATileDecoderTable
static const MCPhysReg MatrixZATileDecoderTable[5][16]
Definition: AArch64Disassembler.cpp:390
DecodeXSeqPairsClassRegisterClass
static DecodeStatus DecodeXSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1596
DecodeZPR2Mul2RegisterClass
static DecodeStatus DecodeZPR2Mul2RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:358
DecodeAuthLoadInstruction
static DecodeStatus DecodeAuthLoadInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1218
DecodeVecShiftL16Imm
static DecodeStatus DecodeVecShiftL16Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:589
DecodePairLdStInstruction
static DecodeStatus DecodePairLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1072
SoftFail
#define SoftFail
Definition: AArch64Disassembler.cpp:215
DecodeMatrixTile
static DecodeStatus DecodeMatrixTile(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:402
DecodeSImm
static DecodeStatus DecodeSImm(MCInst &Inst, uint64_t Imm, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1642
DecodeVecShiftR32ImmNarrow
static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:553
DecodePPR2Mul2RegisterClass
static DecodeStatus DecodePPR2Mul2RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:413
DecodeSystemPStateImm0_15Instruction
static DecodeStatus DecodeSystemPStateImm0_15Instruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1508
DecodeVecShiftL8Imm
static DecodeStatus DecodeVecShiftL8Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:595
DecodePCRelLabel16
static DecodeStatus DecodePCRelLabel16(MCInst &Inst, unsigned Imm, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:440
DecodeSVEIncDecImm
static DecodeStatus DecodeSVEIncDecImm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1669
DecodeFixedPointScaleImm32
static DecodeStatus DecodeFixedPointScaleImm32(MCInst &Inst, unsigned Imm, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:424
DecodeTestAndBranch
static DecodeStatus DecodeTestAndBranch(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1550
DecodeSVELogicalImmInstruction
static DecodeStatus DecodeSVELogicalImmInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1624
DecodeVecShiftRImm
static DecodeStatus DecodeVecShiftRImm(MCInst &Inst, unsigned Imm, unsigned Add)
Definition: AArch64Disassembler.cpp:523
LLVMInitializeAArch64Disassembler
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAArch64Disassembler()
Definition: AArch64Disassembler.cpp:306
DecodeVecShiftR64Imm
static DecodeStatus DecodeVecShiftR64Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:535
DecodeVecShiftLImm
static DecodeStatus DecodeVecShiftLImm(MCInst &Inst, unsigned Imm, unsigned Add)
Definition: AArch64Disassembler.cpp:529
DecodeVecShiftR16ImmNarrow
static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:565
DecodeSVCROp
static DecodeStatus DecodeSVCROp(MCInst &Inst, unsigned Imm, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1676
DecodeWSeqPairsClassRegisterClass
static DecodeStatus DecodeWSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1589
DecodeVecShiftR64ImmNarrow
static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:541
DecodeZPR4Mul4RegisterClass
static DecodeStatus DecodeZPR4Mul4RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:369
DecodeAddSubImmShift
static DecodeStatus DecodeAddSubImmShift(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1445
Fail
#define Fail
Definition: AArch64Disassembler.cpp:214
DecodeMSRSystemRegister
static DecodeStatus DecodeMSRSystemRegister(MCInst &Inst, unsigned Imm, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:488
Success
#define Success
Definition: AArch64Disassembler.cpp:213
DecodeSETMemOpInstruction
static DecodeStatus DecodeSETMemOpInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1716
DecodePCRelLabel19
static DecodeStatus DecodePCRelLabel19(MCInst &Inst, unsigned Imm, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:455
DecodeThreeAddrSRegInstruction
static DecodeStatus DecodeThreeAddrSRegInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:602
DecodeMemExtend
static DecodeStatus DecodeMemExtend(MCInst &Inst, unsigned Imm, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:470
DecodeSignedLdStInstruction
static DecodeStatus DecodeSignedLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:771
DecodeExclusiveLdStInstruction
static DecodeStatus DecodeExclusiveLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:979
DecodeSyspXzrInstruction
static DecodeStatus DecodeSyspXzrInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1602
DecodeFMOVLaneInstruction
static DecodeStatus DecodeFMOVLaneInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:496
isInvalidPState
static bool isInvalidPState(uint64_t Op1, uint64_t Op2)
Definition: AArch64Disassembler.cpp:1501
DecodeSimpleRegisterClass
static DecodeStatus DecodeSimpleRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:331
DecodeMatrixTileListRegisterClass
static DecodeStatus DecodeMatrixTileListRegisterClass(MCInst &Inst, unsigned RegMask, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:381
DecodeAdrInstruction
static DecodeStatus DecodeAdrInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1426
DecodePRFMRegInstruction
static DecodeStatus DecodePRFMRegInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1745
DecodeVecShiftR16Imm
static DecodeStatus DecodeVecShiftR16Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:559
DecodeVecShiftR32Imm
static DecodeStatus DecodeVecShiftR32Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:547
DecodeImm8OptLsl
static DecodeStatus DecodeImm8OptLsl(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1657
DecodeGPRSeqPairsClassRegisterClass
static DecodeStatus DecodeGPRSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegClassID, unsigned RegNo, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1576
DecodeMRSSystemRegister
static DecodeStatus DecodeMRSSystemRegister(MCInst &Inst, unsigned Imm, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:478
DecodeModImmTiedInstruction
static DecodeStatus DecodeModImmTiedInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1406
Insn
SmallVector< AArch64_IMM::ImmInsnModel, 4 > Insn
Definition: AArch64MIPeepholeOpt.cpp:163
LLVM_EXTERNAL_VISIBILITY
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:131
Addr
uint64_t Addr
Definition: ELFObjHandler.cpp:79
Size
uint64_t Size
Definition: ELFObjHandler.cpp:81
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:113
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::AArch64Disassembler::getInstruction
MCDisassembler::DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address, raw_ostream &CStream) const override
Returns the disassembly of a single instruction.
Definition: AArch64Disassembler.cpp:224
llvm::AArch64Disassembler::suggestBytesToSkip
uint64_t suggestBytesToSkip(ArrayRef< uint8_t > Bytes, uint64_t Address) const override
Suggest a distance to skip in a buffer of data to find the next place to look for the start of an ins...
Definition: AArch64Disassembler.cpp:289
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
llvm::ArrayRef::size
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:165
llvm::MCContext
Context object for machine code objects.
Definition: MCContext.h:83
llvm::MCDisassembler
Superclass for all disassemblers.
Definition: MCDisassembler.h:84
llvm::MCDisassembler::tryAddingSymbolicOperand
bool tryAddingSymbolicOperand(MCInst &Inst, int64_t Value, uint64_t Address, bool IsBranch, uint64_t Offset, uint64_t OpSize, uint64_t InstSize) const
Definition: MCDisassembler.cpp:28
llvm::MCDisassembler::getSubtargetInfo
const MCSubtargetInfo & getSubtargetInfo() const
Definition: MCDisassembler.h:217
llvm::MCDisassembler::STI
const MCSubtargetInfo & STI
Definition: MCDisassembler.h:200
llvm::MCDisassembler::CommentStream
raw_ostream * CommentStream
Definition: MCDisassembler.h:224
llvm::MCDisassembler::DecodeStatus
DecodeStatus
Ternary decode status.
Definition: MCDisassembler.h:108
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
llvm::MCInst::getOpcode
unsigned getOpcode() const
Definition: MCInst.h:198
llvm::MCInst::addOperand
void addOperand(const MCOperand Op)
Definition: MCInst.h:210
llvm::MCInst::getOperand
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:206
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:198
llvm::MCOperand
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:36
llvm::MCOperand::createReg
static MCOperand createReg(unsigned Reg)
Definition: MCInst.h:134
llvm::MCOperand::createImm
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:141
llvm::MCOperand::isImm
bool isImm() const
Definition: MCInst.h:62
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition: MCSubtargetInfo.h:76
llvm::MCSubtargetInfo::getFeatureBits
const FeatureBitset & getFeatureBits() const
Definition: MCSubtargetInfo.h:112
llvm::MCSymbolizer
Symbolize and annotate disassembled instructions.
Definition: MCSymbolizer.h:39
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::Target
Target - Wrapper for Target specific information.
Definition: TargetRegistry.h:144
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:52
uint16_t
uint32_t
uint64_t
LLVMSymbolLookupCallback
const char *(* LLVMSymbolLookupCallback)(void *DisInfo, uint64_t ReferenceValue, uint64_t *ReferenceType, uint64_t ReferencePC, const char **ReferenceName)
The type for the symbol lookup function.
Definition: DisassemblerTypes.h:118
LLVMOpInfoCallback
int(* LLVMOpInfoCallback)(void *DisInfo, uint64_t PC, uint64_t Offset, uint64_t OpSize, uint64_t InstSize, int TagType, void *TagBuf)
The type for the operand information call back function.
Definition: DisassemblerTypes.h:48
llvm::AArch64_AM::isValidDecodeLogicalImmediate
static bool isValidDecodeLogicalImmediate(uint64_t val, unsigned regSize)
isValidDecodeLogicalImmediate - Check to see if the logical immediate value in the form "N:immr:imms"...
Definition: AArch64AddressingModes.h:321
llvm::MCOI::OPERAND_REGISTER
@ OPERAND_REGISTER
Definition: MCInstrDesc.h:61
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::getTheAArch64beTarget
Target & getTheAArch64beTarget()
Definition: AArch64TargetInfo.cpp:17
llvm::getTheAArch64leTarget
Target & getTheAArch64leTarget()
Definition: AArch64TargetInfo.cpp:13
llvm::getTheAArch64_32Target
Target & getTheAArch64_32Target()
Definition: AArch64TargetInfo.cpp:21
llvm::getTheARM64_32Target
Target & getTheARM64_32Target()
Definition: AArch64TargetInfo.cpp:29
llvm::RecurKind::Add
@ Add
Sum of integers.
llvm::getTheARM64Target
Target & getTheARM64Target()
Definition: AArch64TargetInfo.cpp:25
llvm::DWARFExpression::Operation::Description
Description of the encoding of one expression Op.
Definition: DWARFExpression.h:66
llvm::TargetRegistry::RegisterMCSymbolizer
static void RegisterMCSymbolizer(Target &T, Target::MCSymbolizerCtorTy Fn)
RegisterMCSymbolizer - Register an MCSymbolizer implementation for the given target.
Definition: TargetRegistry.h:964
llvm::TargetRegistry::RegisterMCDisassembler
static void RegisterMCDisassembler(Target &T, Target::MCDisassemblerCtorTy Fn)
RegisterMCDisassembler - Register a MCDisassembler implementation for the given target.
Definition: TargetRegistry.h:878
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