AMDGPURegBankSelect.cpp File Reference

#include "AMDGPU.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/InitializePasses.h"

Go to the source code of this file.

Macros
#define	DEBUG_TYPE   "amdgpu-regbankselect"
	Assign register banks to all register operands of G_ instructions using machine uniformity analysis.

Functions
	INITIALIZE_PASS_BEGIN (AMDGPURegBankSelect, DEBUG_TYPE, "AMDGPU Register Bank Select", false, false) INITIALIZE_PASS_END(AMDGPURegBankSelect

Variables
	DEBUG_TYPE
AMDGPU Register Bank	Select
AMDGPU Register Bank	false

Macro Definition Documentation

DEBUG_TYPE

#define DEBUG_TYPE   "amdgpu-regbankselect"

Assign register banks to all register operands of G_ instructions using machine uniformity analysis.

Sgpr - uniform values and some lane masks Vgpr - divergent, non S1, values Vcc - divergent S1 values(lane masks) However in some cases G_ instructions with this register bank assignment can't be inst-selected. This is solved in AMDGPURegBankLegalize.

Definition at line 22 of file AMDGPURegBankSelect.cpp.

Function Documentation

INITIALIZE_PASS_BEGIN()

INITIALIZE_PASS_BEGIN	(	AMDGPURegBankSelect	,
		DEBUG_TYPE	,
		"AMDGPU Register Bank Select"	,
		false	,
		false
	)

Variable Documentation

DEBUG_TYPE

DEBUG_TYPE

Definition at line 58 of file AMDGPURegBankSelect.cpp.

false

AMDGPU Register Bank false

Definition at line 59 of file AMDGPURegBankSelect.cpp.

Select

AMDGPU Register Bank Select

Definition at line 59 of file AMDGPURegBankSelect.cpp.

Referenced by llvm::CombinerHelper::applyFoldBinOpIntoSelect(), llvm::InstCombinerImpl::canonicalizeCondSignextOfHighBitExtractToSignextHighBitExtract(), combineAdd(), combineMulSelectConstOne(), combineSelect(), constantFold(), llvm::createMinMaxOp(), llvm::logicalview::LVReader::doLoad(), llvm::VPReductionRecipe::execute(), llvm::TargetLowering::expandFP_TO_INT_SAT(), llvm::TargetLowering::expandVPCTTZElements(), llvm::InstCombinerImpl::foldICmpSelectConstant(), getV_CMPOpcode(), getValueOnFirstIteration(), llvm::SIInstrInfo::insertSelect(), instCombineSVESel(), llvm::TargetLoweringBase::InstructionOpcodeToISD(), llvm::RecurrenceDescriptor::isAnyOfPattern(), isFixedVectorShuffle(), llvm::RecurrenceDescriptor::isMinMaxPattern(), isSignedMinMaxClamp(), LowerBUILD_VECTORvXi1(), lowerDisjointIndicesShuffle(), LowerMLOAD(), llvm::PatternMatch::LogicalOp_match< LHS, RHS, Opcode, Commutable >::match(), llvm::CombinerHelper::matchCastOfSelect(), llvm::CombinerHelper::matchFoldBinOpIntoSelect(), llvm::CombinerHelper::matchSelect(), llvm::CombinerHelper::matchSelectIMinMax(), llvm::LegalizerHelper::narrowScalarSelect(), simplifySwitchOnSelectUsingRanges(), tryToRecognizeTableBasedCttz(), tryWhileWRFromOR(), upgradeMaskedMove(), llvm::InstCombinerImpl::visitCallInst(), llvm::InstCombinerImpl::visitSub(), and llvm::InstCombinerImpl::visitSwitchInst().