SI implementation of the TargetRegisterInfo class. More...

#include "SIRegisterInfo.h"
#include "AMDGPU.h"
#include "AMDGPURegisterBankInfo.h"
#include "GCNSubtarget.h"
#include "MCTargetDesc/AMDGPUInstPrinter.h"
#include "SIMachineFunctionInfo.h"
#include "llvm/CodeGen/LiveIntervals.h"
#include "llvm/CodeGen/LiveRegUnits.h"
#include "llvm/CodeGen/MachineDominators.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/RegisterScavenging.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
#include "AMDGPUGenRegisterInfo.inc"

Classes
struct	llvm::SGPRSpillBuilder
struct	llvm::SGPRSpillBuilder::PerVGPRData

Namespaces
namespace	llvm
	This is an optimization pass for GlobalISel generic memory operations.

Macros
#define	DEBUG_TYPE "amdgpu-si-register-info"
#define	GET_REGINFO_TARGET_DESC

Functions
static void	emitUnsupportedError (const Function &Fn, const MachineInstr &MI, const Twine &ErrMsg)
static bool	isFIPlusImmOrVGPR (const SIRegisterInfo &TRI, const MachineInstr &MI)
static unsigned	getNumSubRegsForSpillOp (const MachineInstr &MI, const SIInstrInfo *TII)
static int	getOffsetMUBUFStore (unsigned Opc)
static int	getOffsetMUBUFLoad (unsigned Opc)
static int	getOffenMUBUFStore (unsigned Opc)
static int	getOffenMUBUFLoad (unsigned Opc)
static MachineInstrBuilder	spillVGPRtoAGPR (const GCNSubtarget &ST, MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, int Index, unsigned Lane, unsigned ValueReg, bool IsKill, bool NeedsCFI)
static bool	buildMUBUFOffsetLoadStore (const GCNSubtarget &ST, MachineFrameInfo &MFI, MachineBasicBlock::iterator MI, int Index, int64_t Offset)
static unsigned	getFlatScratchSpillOpcode (const SIInstrInfo *TII, unsigned LoadStoreOp, unsigned EltSize)
static bool	wrapsAround32 (int64_t LHS, int64_t RHS)
static bool	foldingOffsetChangesCarry (const MachineOperand &OtherOp, int64_t Offset, Register FrameReg)
static bool	isSCCLiveInto (const RegScavenger &RS, const MachineInstr &MI)
static const TargetRegisterClass *	getAnyVGPRClassForBitWidth (unsigned BitWidth)
static const TargetRegisterClass *	getAlignedVGPRClassForBitWidth (unsigned BitWidth)
static const TargetRegisterClass *	getAnyAGPRClassForBitWidth (unsigned BitWidth)
static const TargetRegisterClass *	getAlignedAGPRClassForBitWidth (unsigned BitWidth)
static const TargetRegisterClass *	getAnyVectorSuperClassForBitWidth (unsigned BitWidth)
static const TargetRegisterClass *	getAlignedVectorSuperClassForBitWidth (unsigned BitWidth)

Variables
static cl::opt< bool >	EnableSpillSGPRToVGPR ("amdgpu-spill-sgpr-to-vgpr", cl::desc("Enable spilling SGPRs to VGPRs"), cl::ReallyHidden, cl::init(true))
static cl::opt< bool >	EnableSpillCFISavedRegs ("amdgpu-spill-cfi-saved-regs", cl::desc("Enable spilling the registers required for CFI emission"), cl::ReallyHidden, cl::init(false))
static cl::opt< unsigned >	StressVGPRLimit ("amdgpu-stress-vgpr", cl::Hidden, cl::init(0), cl::desc("Limit VGPRs to N registers by reserving the rest"))
static cl::opt< unsigned >	StressAGPRLimit ("amdgpu-stress-agpr", cl::Hidden, cl::init(0), cl::desc("Limit AGPRs to N registers by reserving the rest"))
static cl::opt< unsigned >	StressSGPRLimit ("amdgpu-stress-sgpr", cl::Hidden, cl::init(0), cl::desc("Limit SGPRs to N registers by reserving the rest"))
static const std::array< unsigned, 17 >	SubRegFromChannelTableWidthMap

Detailed Description

SI implementation of the TargetRegisterInfo class.

Definition in file SIRegisterInfo.cpp.

Macro Definition Documentation

◆ DEBUG_TYPE

#define DEBUG_TYPE "amdgpu-si-register-info"

Definition at line 28 of file SIRegisterInfo.cpp.

◆ GET_REGINFO_TARGET_DESC

#define GET_REGINFO_TARGET_DESC

Definition at line 32 of file SIRegisterInfo.cpp.

Function Documentation

◆ buildMUBUFOffsetLoadStore()

bool buildMUBUFOffsetLoadStore	(	const GCNSubtarget &	ST,
		MachineFrameInfo &	MFI,
		MachineBasicBlock::iterator	MI,
		int	Index,
		int64_t	Offset )

static

Definition at line 1506 of file SIRegisterInfo.cpp.

References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addImm(), llvm::BuildMI(), llvm::MachineInstrBuilder::cloneMemRefs(), DL, llvm::MachineInstrBuilder::getInstr(), getOffsetMUBUFLoad(), getOffsetMUBUFStore(), MBB, MI, llvm::Offset, Opc, Reg, spillVGPRtoAGPR(), and TII.

Referenced by llvm::SIRegisterInfo::eliminateFrameIndex().

◆ emitUnsupportedError()

void emitUnsupportedError	(	const Function &	Fn,
		const MachineInstr &	MI,
		const Twine &	ErrMsg )

static

Definition at line 68 of file SIRegisterInfo.cpp.

References llvm::LLVMContext::diagnose(), llvm::Function::getContext(), and MI.

Referenced by llvm::SGPRSpillBuilder::prepare(), and llvm::SGPRSpillBuilder::readWriteTmpVGPR().

◆ foldingOffsetChangesCarry()

bool foldingOffsetChangesCarry	(	const MachineOperand &	OtherOp,
		int64_t	Offset,
		Register	FrameReg )

static

Definition at line 2544 of file SIRegisterInfo.cpp.

References llvm::MachineOperand::getImm(), llvm::MachineOperand::isImm(), llvm::Register::isValid(), llvm::Offset, and wrapsAround32().

Referenced by llvm::SIRegisterInfo::eliminateFrameIndex().

◆ getAlignedAGPRClassForBitWidth()

const TargetRegisterClass * getAlignedAGPRClassForBitWidth ( unsigned BitWidth )

static

Definition at line 3879 of file SIRegisterInfo.cpp.

References llvm::BitWidth.

Referenced by llvm::SIRegisterInfo::getAGPRClassForBitWidth().

◆ getAlignedVectorSuperClassForBitWidth()

const TargetRegisterClass * getAlignedVectorSuperClassForBitWidth ( unsigned BitWidth )

static

Definition at line 3953 of file SIRegisterInfo.cpp.

References llvm::BitWidth.

Referenced by llvm::SIRegisterInfo::getVectorSuperClassForBitWidth().

◆ getAlignedVGPRClassForBitWidth()

const TargetRegisterClass * getAlignedVGPRClassForBitWidth ( unsigned BitWidth )

static

Definition at line 3769 of file SIRegisterInfo.cpp.

References llvm::BitWidth.

Referenced by llvm::SIRegisterInfo::getVGPRClassForBitWidth().

◆ getAnyAGPRClassForBitWidth()

const TargetRegisterClass * getAnyAGPRClassForBitWidth ( unsigned BitWidth )

static

Definition at line 3847 of file SIRegisterInfo.cpp.

References llvm::BitWidth.

Referenced by llvm::SIRegisterInfo::getAGPRClassForBitWidth().

◆ getAnyVectorSuperClassForBitWidth()

const TargetRegisterClass * getAnyVectorSuperClassForBitWidth ( unsigned BitWidth )

static

Definition at line 3921 of file SIRegisterInfo.cpp.

References llvm::BitWidth.

Referenced by llvm::SIRegisterInfo::getVectorSuperClassForBitWidth().

◆ getAnyVGPRClassForBitWidth()

const TargetRegisterClass * getAnyVGPRClassForBitWidth ( unsigned BitWidth )

static

Definition at line 3737 of file SIRegisterInfo.cpp.

References llvm::BitWidth.

Referenced by llvm::SIRegisterInfo::getVGPRClassForBitWidth().

◆ getFlatScratchSpillOpcode()

unsigned getFlatScratchSpillOpcode	(	const SIInstrInfo *	TII,
		unsigned	LoadStoreOp,
		unsigned	EltSize )

static

Definition at line 1544 of file SIRegisterInfo.cpp.

References llvm::AMDGPU::getFlatScratchInstSTfromSS(), llvm::AMDGPU::getFlatScratchInstSVfromSS(), llvm::AMDGPU::hasNamedOperand(), llvm_unreachable, and TII.

Referenced by llvm::SIRegisterInfo::buildSpillLoadStore().

◆ getNumSubRegsForSpillOp()

unsigned getNumSubRegsForSpillOp	(	const MachineInstr &	MI,
		const SIInstrInfo *	TII )

static

Definition at line 1154 of file SIRegisterInfo.cpp.

References llvm_unreachable, MI, llvm::popcount(), TII, and uint64_t.

Referenced by llvm::SIRegisterInfo::eliminateFrameIndex().

◆ getOffenMUBUFLoad()

int getOffenMUBUFLoad ( unsigned Opc )

static

Definition at line 1424 of file SIRegisterInfo.cpp.

References Opc.

Referenced by llvm::SIRegisterInfo::buildSpillLoadStore().

◆ getOffenMUBUFStore()

int getOffenMUBUFStore ( unsigned Opc )

static

Definition at line 1401 of file SIRegisterInfo.cpp.

References Opc.

Referenced by llvm::SIRegisterInfo::buildSpillLoadStore().

◆ getOffsetMUBUFLoad()

int getOffsetMUBUFLoad ( unsigned Opc )

static

Definition at line 1366 of file SIRegisterInfo.cpp.

References Opc.

Referenced by buildMUBUFOffsetLoadStore().

◆ getOffsetMUBUFStore()

int getOffsetMUBUFStore ( unsigned Opc )

static

Definition at line 1343 of file SIRegisterInfo.cpp.

References Opc.

Referenced by buildMUBUFOffsetLoadStore().

◆ isFIPlusImmOrVGPR()

bool isFIPlusImmOrVGPR	(	const SIRegisterInfo &	TRI,
		const MachineInstr &	MI )

static

Definition at line 872 of file SIRegisterInfo.cpp.

References assert(), llvm::MachineOperand::getReg(), llvm::MachineOperand::isFI(), llvm::MachineOperand::isImm(), llvm::MachineOperand::isReg(), MI, and TRI.

Referenced by llvm::SIRegisterInfo::needsFrameBaseReg().

◆ isSCCLiveInto()

bool isSCCLiveInto	(	const RegScavenger &	RS,
		const MachineInstr &	MI )

static

Definition at line 2551 of file SIRegisterInfo.cpp.

References MI.

Referenced by llvm::SIRegisterInfo::eliminateFrameIndex().

◆ spillVGPRtoAGPR()

MachineInstrBuilder spillVGPRtoAGPR	(	const GCNSubtarget &	ST,
		MachineBasicBlock &	MBB,
		MachineBasicBlock::iterator	MI,
		int	Index,
		unsigned	Lane,
		unsigned	ValueReg,
		bool	IsKill,
		bool	NeedsCFI )

static

◆ wrapsAround32()

bool wrapsAround32	(	int64_t	LHS,
		int64_t	RHS )

static

Definition at line 2536 of file SIRegisterInfo.cpp.

References LHS, RHS, and uint64_t.

Referenced by foldingOffsetChangesCarry().

Variable Documentation

◆ EnableSpillCFISavedRegs

cl::opt< bool > EnableSpillCFISavedRegs("amdgpu-spill-cfi-saved-regs", cl::desc("Enable spilling the registers required for CFI emission"), cl::ReallyHidden, cl::init(false))	(	"amdgpu-spill-cfi-saved-regs"	,
		cl::desc("Enable spilling the registers required for CFI emission")	,
		cl::ReallyHidden	,
		cl::init(false)	)

static

Referenced by llvm::SIRegisterInfo::isCFISavedRegsSpillEnabled().

◆ EnableSpillSGPRToVGPR

cl::opt< bool > EnableSpillSGPRToVGPR("amdgpu-spill-sgpr-to-vgpr", cl::desc("Enable spilling SGPRs to VGPRs"), cl::ReallyHidden, cl::init(true))	(	"amdgpu-spill-sgpr-to-vgpr"	,
		cl::desc("Enable spilling SGPRs to VGPRs")	,
		cl::ReallyHidden	,
		cl::init(true)	)

static

Referenced by llvm::SIRegisterInfo::SIRegisterInfo().

◆ StressAGPRLimit

cl::opt< unsigned > StressAGPRLimit("amdgpu-stress-agpr", cl::Hidden, cl::init(0), cl::desc("Limit AGPRs to N registers by reserving the rest"))	(	"amdgpu-stress-agpr"	,
		cl::Hidden	,
		cl::init(0)	,
		cl::desc("Limit AGPRs to N registers by reserving the rest")	)

static

Referenced by llvm::SIRegisterInfo::getReservedRegs().

◆ StressSGPRLimit

cl::opt< unsigned > StressSGPRLimit("amdgpu-stress-sgpr", cl::Hidden, cl::init(0), cl::desc("Limit SGPRs to N registers by reserving the rest"))	(	"amdgpu-stress-sgpr"	,
		cl::Hidden	,
		cl::init(0)	,
		cl::desc("Limit SGPRs to N registers by reserving the rest")	)

static

Referenced by llvm::SIRegisterInfo::getReservedRegs().

◆ StressVGPRLimit

cl::opt< unsigned > StressVGPRLimit("amdgpu-stress-vgpr", cl::Hidden, cl::init(0), cl::desc("Limit VGPRs to N registers by reserving the rest"))	(	"amdgpu-stress-vgpr"	,
		cl::Hidden	,
		cl::init(0)	,
		cl::desc("Limit VGPRs to N registers by reserving the rest")	)

static

Referenced by llvm::SIRegisterInfo::getReservedRegs().

◆ SubRegFromChannelTableWidthMap

const std::array<unsigned, 17> SubRegFromChannelTableWidthMap

static

Initial value:

= {

0, 1, 2, 3, 4, 5, 6, 7, 8, 0, 0, 0, 0, 0, 0, 0, 9}

Definition at line 65 of file SIRegisterInfo.cpp.

Referenced by llvm::SIRegisterInfo::getSubRegFromChannel(), and llvm::SIRegisterInfo::SIRegisterInfo().

Classes

Namespaces

Macros

Functions

Variables

Detailed Description

Macro Definition Documentation

◆ DEBUG_TYPE

◆ GET_REGINFO_TARGET_DESC

Function Documentation

◆ buildMUBUFOffsetLoadStore()

◆ emitUnsupportedError()

◆ foldingOffsetChangesCarry()

◆ getAlignedAGPRClassForBitWidth()

◆ getAlignedVectorSuperClassForBitWidth()

◆ getAlignedVGPRClassForBitWidth()

◆ getAnyAGPRClassForBitWidth()

◆ getAnyVectorSuperClassForBitWidth()

◆ getAnyVGPRClassForBitWidth()

◆ getFlatScratchSpillOpcode()

◆ getNumSubRegsForSpillOp()

◆ getOffenMUBUFLoad()

◆ getOffenMUBUFStore()

◆ getOffsetMUBUFLoad()

◆ getOffsetMUBUFStore()

◆ isFIPlusImmOrVGPR()

◆ isSCCLiveInto()

◆ spillVGPRtoAGPR()

◆ wrapsAround32()

Variable Documentation

◆ EnableSpillCFISavedRegs

◆ EnableSpillSGPRToVGPR

◆ StressAGPRLimit

◆ StressSGPRLimit

◆ StressVGPRLimit

◆ SubRegFromChannelTableWidthMap