SIRegisterInfo.cpp File Reference

SI implementation of the TargetRegisterInfo class. More...

#include "AMDGPU.h"
#include "AMDGPURegisterBankInfo.h"
#include "GCNSubtarget.h"
#include "MCTargetDesc/AMDGPUInstPrinter.h"
#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
#include "SIMachineFunctionInfo.h"
#include "SIRegisterInfo.h"
#include "llvm/CodeGen/LiveIntervals.h"
#include "llvm/CodeGen/LiveRegUnits.h"
#include "llvm/CodeGen/MachineDominators.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/RegisterScavenging.h"
#include "AMDGPUGenRegisterInfo.inc"

Go to the source code of this file.

Classes
struct	llvm::SGPRSpillBuilder
struct	llvm::SGPRSpillBuilder::PerVGPRData

Namespaces
namespace	llvm
	This is an optimization pass for GlobalISel generic memory operations.

Macros
#define	GET_REGINFO_TARGET_DESC

Functions
static void	emitUnsupportedError (const Function &Fn, const MachineInstr &MI, const Twine &ErrMsg)
static bool	isFIPlusImmOrVGPR (const SIRegisterInfo &TRI, const MachineInstr &MI)
static unsigned	getNumSubRegsForSpillOp (unsigned Op)
static int	getOffsetMUBUFStore (unsigned Opc)
static int	getOffsetMUBUFLoad (unsigned Opc)
static int	getOffenMUBUFStore (unsigned Opc)
static int	getOffenMUBUFLoad (unsigned Opc)
static MachineInstrBuilder	spillVGPRtoAGPR (const GCNSubtarget &ST, MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, int Index, unsigned Lane, unsigned ValueReg, bool IsKill)
static bool	buildMUBUFOffsetLoadStore (const GCNSubtarget &ST, MachineFrameInfo &MFI, MachineBasicBlock::iterator MI, int Index, int64_t Offset)
static unsigned	getFlatScratchSpillOpcode (const SIInstrInfo *TII, unsigned LoadStoreOp, unsigned EltSize)
static const TargetRegisterClass *	getAnyVGPRClassForBitWidth (unsigned BitWidth)
static const TargetRegisterClass *	getAlignedVGPRClassForBitWidth (unsigned BitWidth)
static const TargetRegisterClass *	getAnyAGPRClassForBitWidth (unsigned BitWidth)
static const TargetRegisterClass *	getAlignedAGPRClassForBitWidth (unsigned BitWidth)
static const TargetRegisterClass *	getAnyVectorSuperClassForBitWidth (unsigned BitWidth)
static const TargetRegisterClass *	getAlignedVectorSuperClassForBitWidth (unsigned BitWidth)

Variables
static cl::opt< bool >	EnableSpillSGPRToVGPR ("amdgpu-spill-sgpr-to-vgpr", cl::desc("Enable spilling SGPRs to VGPRs"), cl::ReallyHidden, cl::init(true))
static const std::array< unsigned, 17 >	SubRegFromChannelTableWidthMap

Detailed Description

SI implementation of the TargetRegisterInfo class.

Definition in file SIRegisterInfo.cpp.

Macro Definition Documentation

GET_REGINFO_TARGET_DESC

#define GET_REGINFO_TARGET_DESC

Definition at line 29 of file SIRegisterInfo.cpp.

Function Documentation

buildMUBUFOffsetLoadStore()

static bool buildMUBUFOffsetLoadStore ( const GCNSubtarget &  ST, MachineFrameInfo &  MFI, MachineBasicBlock::iterator  MI, int  Index, int64_t  Offset  )

static

Definition at line 1448 of file SIRegisterInfo.cpp.

References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addImm(), llvm::BuildMI(), llvm::MachineInstrBuilder::cloneMemRefs(), DL, llvm::MachineInstrBuilder::getInstr(), getOffsetMUBUFLoad(), getOffsetMUBUFStore(), MBB, MI, llvm::Offset, spillVGPRtoAGPR(), and TII.

Referenced by llvm::SIRegisterInfo::eliminateFrameIndex().

emitUnsupportedError()

static void emitUnsupportedError ( const Function &  Fn, const MachineInstr &  MI, const Twine &  ErrMsg  )

static

Definition at line 48 of file SIRegisterInfo.cpp.

References llvm::LLVMContext::diagnose(), llvm::Function::getContext(), and MI.

Referenced by llvm::SGPRSpillBuilder::prepare(), and llvm::SGPRSpillBuilder::readWriteTmpVGPR().

getAlignedAGPRClassForBitWidth()

static const TargetRegisterClass * getAlignedAGPRClassForBitWidth ( unsigned  BitWidth )

static

Definition at line 3315 of file SIRegisterInfo.cpp.

References llvm::BitWidth.

Referenced by llvm::SIRegisterInfo::getAGPRClassForBitWidth(), and llvm::SIRegisterInfo::getProperlyAlignedRC().

getAlignedVectorSuperClassForBitWidth()

static const TargetRegisterClass * getAlignedVectorSuperClassForBitWidth ( unsigned  BitWidth )

static

Definition at line 3389 of file SIRegisterInfo.cpp.

References llvm::BitWidth.

Referenced by llvm::SIRegisterInfo::getProperlyAlignedRC(), and llvm::SIRegisterInfo::getVectorSuperClassForBitWidth().

getAlignedVGPRClassForBitWidth()

static const TargetRegisterClass * getAlignedVGPRClassForBitWidth ( unsigned  BitWidth )

static

Definition at line 3239 of file SIRegisterInfo.cpp.

References llvm::BitWidth.

Referenced by llvm::SIRegisterInfo::getProperlyAlignedRC(), and llvm::SIRegisterInfo::getVGPRClassForBitWidth().

getAnyAGPRClassForBitWidth()

static const TargetRegisterClass * getAnyAGPRClassForBitWidth ( unsigned  BitWidth )

static

Definition at line 3283 of file SIRegisterInfo.cpp.

References llvm::BitWidth.

Referenced by llvm::SIRegisterInfo::getAGPRClassForBitWidth().

getAnyVectorSuperClassForBitWidth()

static const TargetRegisterClass * getAnyVectorSuperClassForBitWidth ( unsigned  BitWidth )

static

Definition at line 3357 of file SIRegisterInfo.cpp.

References llvm::BitWidth.

Referenced by llvm::SIRegisterInfo::getVectorSuperClassForBitWidth().

getAnyVGPRClassForBitWidth()

static const TargetRegisterClass * getAnyVGPRClassForBitWidth ( unsigned  BitWidth )

static

Definition at line 3207 of file SIRegisterInfo.cpp.

References llvm::BitWidth.

Referenced by llvm::SIRegisterInfo::getVGPRClassForBitWidth().

getFlatScratchSpillOpcode()

static unsigned getFlatScratchSpillOpcode ( const SIInstrInfo *  TII, unsigned  LoadStoreOp, unsigned  EltSize  )

static

Definition at line 1485 of file SIRegisterInfo.cpp.

References llvm::AMDGPU::getFlatScratchInstSTfromSS(), llvm::AMDGPU::getFlatScratchInstSVfromSS(), llvm::AMDGPU::hasNamedOperand(), llvm_unreachable, and TII.

Referenced by llvm::SIRegisterInfo::buildSpillLoadStore().

getNumSubRegsForSpillOp()

static unsigned getNumSubRegsForSpillOp ( unsigned  Op )

static

Definition at line 1152 of file SIRegisterInfo.cpp.

References llvm_unreachable.

Referenced by llvm::SIRegisterInfo::eliminateFrameIndex().

getOffenMUBUFLoad()

static int getOffenMUBUFLoad ( unsigned  Opc )

static

Definition at line 1370 of file SIRegisterInfo.cpp.

Referenced by llvm::SIRegisterInfo::buildSpillLoadStore().

getOffenMUBUFStore()

static int getOffenMUBUFStore ( unsigned  Opc )

static

Definition at line 1347 of file SIRegisterInfo.cpp.

Referenced by llvm::SIRegisterInfo::buildSpillLoadStore().

getOffsetMUBUFLoad()

static int getOffsetMUBUFLoad ( unsigned  Opc )

static

Definition at line 1312 of file SIRegisterInfo.cpp.

Referenced by buildMUBUFOffsetLoadStore().

getOffsetMUBUFStore()

static int getOffsetMUBUFStore ( unsigned  Opc )

static

Definition at line 1289 of file SIRegisterInfo.cpp.

Referenced by buildMUBUFOffsetLoadStore().

isFIPlusImmOrVGPR()

static bool isFIPlusImmOrVGPR ( const SIRegisterInfo &  TRI, const MachineInstr &  MI  )

static

Definition at line 858 of file SIRegisterInfo.cpp.

References assert(), llvm::MachineOperand::getReg(), llvm::MachineOperand::isFI(), llvm::MachineOperand::isImm(), llvm::MachineOperand::isReg(), MI, and TRI.

Referenced by llvm::SIRegisterInfo::needsFrameBaseReg().

spillVGPRtoAGPR()

static MachineInstrBuilder spillVGPRtoAGPR ( const GCNSubtarget &  ST, MachineBasicBlock &  MBB, MachineBasicBlock::iterator  MI, int  Index, unsigned  Lane, unsigned  ValueReg, bool  IsKill  )

static

Definition at line 1405 of file SIRegisterInfo.cpp.

References llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), DL, llvm::MachineFunction::getInfo(), llvm::getKillRegState(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), llvm::SIMachineFunctionInfo::getVGPRToAGPRSpill(), MBB, MI, MRI, llvm::MachineInstr::ReloadReuse, llvm::MachineInstr::setAsmPrinterFlag(), TII, and TRI.

Referenced by buildMUBUFOffsetLoadStore(), and llvm::SIRegisterInfo::buildSpillLoadStore().

Variable Documentation

EnableSpillSGPRToVGPR

cl::opt< bool > EnableSpillSGPRToVGPR("amdgpu-spill-sgpr-to-vgpr", cl::desc("Enable spilling SGPRs to VGPRs"), cl::ReallyHidden, cl::init(true)) ( "amdgpu-spill-sgpr-to-vgpr"  , cl::desc("Enable spilling SGPRs to VGPRs")  , cl::ReallyHidden  , cl::init(true)    )

static

SubRegFromChannelTableWidthMap

const std::array<unsigned, 17> SubRegFromChannelTableWidthMap

static

Initial value:

= {
    0, 1, 2, 3, 4, 5, 6, 7, 8, 0, 0, 0, 0, 0, 0, 0, 9}

Definition at line 45 of file SIRegisterInfo.cpp.

Referenced by llvm::SIRegisterInfo::getSubRegFromChannel(), and llvm::SIRegisterInfo::SIRegisterInfo().